A self-adapting following capacitive sensor chip circuit
The adaptive following capacitance sensor chip, composed of CDAC and RDAC circuits, solves the problems of low detection accuracy and consistency of capacitance sensors, and achieves high-precision capacitance detection and adaptive adjustment to meet the application needs of different clients.
CN121540191BActive Publication Date: 2026-05-29SHENZHEN JINGYANG ELECTRONICS CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JINGYANG ELECTRONICS CO LTD
- Filing Date
- 2026-01-16
- Publication Date
- 2026-05-29
AI Technical Summary
Technical Problem
Existing capacitive sensors have low detection accuracy and cannot track changes in external load capacitance in real time, leading to consistency issues and affecting user experience.
Method used
An adaptive following capacitance sensor chip, composed of a CDAC circuit, an RDAC circuit, a sample-and-hold circuit, a digital logic circuit, and a comparator circuit, tracks the external load capacitance through the CDAC circuit and adjusts the reference value through the RDAC circuit, achieving accurate detection and adaptive adjustment.
Benefits of technology
It achieves high-precision capacitance detection, tracks changes in external load capacitance in real time, improves product reliability and consistency, and adapts to the application needs of different clients.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN121540191B_ABST
Abstract
An adaptive following capacitive sensor chip circuit, comprising: a CDAC circuit connected to an external load capacitor, a sample and hold circuit and a digital logic circuit respectively, for tracking the external load capacitor to keep consistent with the size of the external load capacitor; a RDAC circuit connected to the digital logic circuit and a comparator circuit group respectively, for generating a reference value that can be automatically adjusted to adapt to different degrees of external triggering action; an input end of the sample and hold circuit is connected between the external load capacitor and the CDAC circuit, and an output end is connected to the comparator circuit group, for controlling the acquisition of the external load capacitor size according to the signal sent by the digital logic circuit to the CDAC circuit, and outputting it to the comparator circuit group for comparison and judgment; the digital logic circuit is connected to the comparator circuit group and the sample and hold circuit, for providing the sample and hold circuit with a control timing signal, and providing the CDAC circuit and the RDAC circuit with an excitation voltage signal according to the output result of the comparator circuit group.
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