Method for optimizing strong connection circuit classification, electronic equipment and storage medium

Abstract

The invention relates to the field of chip verification, in particular to a method for optimizing strong connectivity circuit classification, electronic equipment and a storage medium, and the method comprises the steps: obtaining the ancestor nodes of all external input signals of a strong connectivity circuit SCC, obtaining potential paths from the ancestor nodes to each external input signal, and obtaining the potential paths from the ancestor nodes to the external input signals; all combinational logic circuits in the potential path are used as potential constraint circuits of the strong connection circuit, the strong connection circuit is constrained through the potential constraint circuits, and then solution is carried out through a first constraint solver, so that an accurate classification result is efficiently obtained; and meanwhile, the technical problem of inaccurate classification result caused by external input signals with the same ancestor node is solved.

Description

Technical Field

[0001] This invention relates to the field of chip verification, and in particular to a method for optimizing the classification of strongly connected circuits, an electronic device, and a storage medium. Background Technology

[0002] Chip design typically includes numerous closed-loop circuits, also known as cyclic circuits, which contain feedback paths. These cyclic circuits pose a significant challenge during static timing analysis (STM) because STM assumes the circuit is a combination of combinational and sequential logic without feedback. Cyclic circuits can cause analysis tools to get stuck in infinite loops, thus requiring special handling. Typically, tools identify which paths constitute cyclic circuits and attempt to break the loops to ensure the analysis can terminate. However, different types of cyclic circuits require different approaches. Classifying cyclic circuits is an extremely complex problem, necessitating an efficient and accurate classification method. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention adopts the following technical solution: a method for optimizing the classification of strongly connected circuits, the method comprising:

[0004] P100, obtain the strongly connected circuit SCC in the designed circuit, wherein the SCC is at least one closed-loop circuit composed of N-level combinational logic circuits.

[0005] P200 places all external input signals in the strongly connected circuit SCC into the external input set P.

[0006] P300, obtain the ancestor node of all external input signals in P.

[0007] P400, obtains T paths that start from the ancestor node and end at each external input signal in P, where T is greater than or equal to 0.

[0008] P500 obtains the combinational logic circuits traversed by each path, resulting in the potential constraint circuit set CIC.

[0009] P600, taking all combinational logic circuits in the CIC and SCC as the overall target circuit, establish a target Boolean formula UG to describe the logical consistency of the overall target circuit.

[0010] P700 inputs all independent variable signals in UG and UG=1 into the interface of the first solver for solving, and determines the circuit type of the SCC based on the solution results.

[0011] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0012] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0013] The present invention has at least the following beneficial effects:

[0014] This invention provides a method, electronic device, and storage medium for optimizing the classification of strongly connected circuits (SCCs). By obtaining the ancestor nodes of all external input signals of a strongly connected circuit (SCC) and the potential paths from the ancestor nodes to each external input signal as potential constraint circuits for the SCC, the SCCs are constrained by the potential constraint circuits, thereby efficiently obtaining accurate classification results. At the same time, it solves the technical problem that external input signals with the same ancestor node cause inaccurate classification results. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart illustrating a classification method for strongly connected circuits provided in Embodiment 1 of the present invention;

[0017] Figure 2 This is a schematic diagram of an SCC circuit including two inverters provided in Embodiment 1 of the present invention;

[0018] Figure 3 This is a flowchart of an optimization method for classifying strongly connected circuits according to Embodiment 2 of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1

[0021] Please see Figure 1It illustrates a method for classifying strongly connected circuits, the method comprising the following steps:

[0022] S100, Obtain the strongly connected circuit SCC in the designed circuit, wherein the SCC is at least one closed-loop circuit composed of N-level combinational logic circuits; each of the combinational logic circuits includes an input signal and an output signal.

[0023] In this context, the closed-loop circuit is the circuit where the output signal of the last combinational logic circuit in a multi-level combinational logic circuit returns to the input terminal of the first-level combinational logic circuit. When the output signal of a combinational logic circuit LUT1 is used as the input signal of another combinational logic circuit LUT2, then LUT1 is the upper-level combinational logic circuit, and LUT2 is the lower-level combinational logic circuit.

[0024] In this system, any combinational logic circuit in the SCC can eventually return to that combinational logic circuit through a loop, and each combinational logic circuit can reach all other combinational logic circuits. In other words, each combinational logic circuit in the SCC is in at least one closed-loop circuit.

[0025] Optionally, the method for obtaining the SCC is to obtain the directed graph of the designed circuit, and then use Tarjan's algorithm to find the strongly connected components in the directed graph to obtain the strongly connected circuit SCC.

[0026] S200: Obtain all feedback signals in the SCC and place all feedback signals into the feedback set F; place the external input signals of non-feedback signals in the SCC into the external input set P; wherein, the feedback signal is the signal whose output signal of the current combinational logic circuit is connected to the input terminal of the current combinational logic circuit or other combinational logic circuits in the SCC. That is, the input signals of the combinational logic circuit are divided into two types: one is the feedback signal, and the other is the external input signal of non-feedback signals.

[0027] The feedback signal takes the value of either a first signal value or a second signal value. The external input signal also takes the value of either the first signal value or the second signal value. Optionally, the first signal value can be 0, and the second signal value can be 1.

[0028] Here, the set of independent variable signals is obtained by taking all input and output signals in the union of P and F as independent variable signals. All input signals of each combinational logic circuit are subsets of the set of independent variable signals, and the output signals of each combinational logic circuit are also subsets of the set of independent variable signals.

[0029] S300, using the elements in F and P as independent variable signals, construct a first Boolean formula G to describe the logical consistency of all combinational logic circuits in the SCC.

[0030] The logical consistency of all combinational logic circuits in SCC refers to the relationship between all input signals and feedback signals in SCC satisfying the logical relationship of SCC itself.

[0031] In a preferred embodiment, in S300, G satisfies: G = g1·g2·…g i ·…g N =1; where g i To describe the i-th combinational logic circuit LUT i The logically consistent sub-formula, where i ranges from 1 to N.

[0032] Here, "·" represents logical AND or dot product. Logical AND and dot product yield the same result. Both indicate that G = 1 holds true when all subformulas are simultaneously equal to 1.

[0033] Among them, LUT i Logical consistency refers to LUT i The relationship between the input and output signals satisfies the LUT. i The inherent logical relationship. When logical consistency is satisfied, g i The value is 1.

[0034] It should be noted that LUT i Both the input and output signals of a LUT are elements from the set of independent variable signals. Specifically, a LUT... i The input signal may include external input signal and feedback signal, LUT i The output signal is the feedback signal.

[0035] In a preferred embodiment, the truth table represents the behavior of a combinational logic circuit, where the inputs and outputs always satisfy logical consistency. Therefore, based on this truth table result, a sub-formula for the logical consistency of the combinational logic circuit is constructed in reverse. Thus, S300 further includes g. i Steps to obtain:

[0036] S310, Obtain LUT i Truth table TTa i The TTa i It includes R sets of logical mappings between the input signal values ​​and the output signal values. It can be understood that each combinational logic circuit has a unique truth table.

[0037] As an example, consider a two-bit AND gate. This gate has two input signals and one output signal. The truth table of the AND gate includes four sets of logical mappings: 000, 010, 100, 111. In each mapping, the first two bits represent the signal values ​​of the two input signals, and the last bit represents the signal value of the output signal. For example, in "010", "01" represents the signal values ​​of the two input signals, and "0" represents the signal value of the output signal.

[0038] S320, according to the TTa i Get g i g i Satisfy: g i =sub1+sub2+…sub r +…sub R ;sub r Let r be the logical AND of each input and output signal in the r-th logical mapping relationship, where r ranges from 1 to R.

[0039] Here, "+" stands for logical OR, or plus sign. Since each input can only be given a specific signal value for each combinational logic circuit, there is only one set of valid input signal values ​​in the actual circuit. That is, there is only one true logical mapping relationship with a value of 1. Therefore, logical OR and plus sign have the same result.

[0040] Understandably, due to LUT i It has a unique truth table TTa i Therefore, LUT i Having a unique sub-formula g i g i The input and output signals are both independent variable signals from the set of independent variable signals.

[0041] For each combinational logic circuit in SCC, since the truth table covers all the logical mappings of the inputs and outputs in the current combinational logic circuit, when a specific input is applied to the combinational logic circuit, it has a specific output, g. i In the R sub-items, exactly one of them is true and has a value of 1, that is, g is always equal to 1.

[0042] It should be noted that in g i Each sub-item in the truth table represents the relationship between the independent variable signals, not the relationship between the values ​​after substituting the signal values. Suppose one of the input signals is x1; when its signal value in the truth table is 1, its sub-item... r The independent variable signal in the truth table is itself; when its signal value in the truth table is 0, its value in the sub... r The independent variable signal in the equation is the negation of itself.

[0043] As an example, let's take a two-bit AND gate. This gate has two inputs and one output. Its truth table includes four sets of logical mappings: 000, 010, 100, 111. Assuming x1 and x2 represent the first and second input signals respectively, and y represents the third output signal, the relationship between the input and output signals in this AND gate satisfies: The third term, sub3, is derived from the third term "100" in the truth table. The sub-terms of sub3 are... When the signal values ​​of x1 and x2 are 0 and 1 respectively, and the signal value of y is 0, in To take the negative.

[0044] Other methods that obtain LUTs through truth tables i sub-formula g i The manner in which this method is used also falls within the protection scope of this invention.

[0045] S400, P, F, and G=1 are input into the interface of the first solver for solving. When the external input signal in P takes any signal value, the first solver obtains whether there is a solution for G=1. If there is a solution, the SCC is determined to be a stable circuit; otherwise, the SCC is determined to be an oscillating circuit.

[0046] An oscillating circuit is defined as one that has at least one set of input signals that causes it to oscillate. An oscillating circuit may also have a set of input signals that causes it to be in a stable state. A stable circuit, however, only exists in a stable state and does not have an oscillating state.

[0047] It should be noted that the oscillation state is characterized by: when the SCC receives a definite input signal value, at least one feedback signal has a non-unique signal value, meaning the signal value on the feedback line where the feedback signal is located is uncertain. The steady state is characterized by: when the SCC receives a definite input signal value, the signal values ​​on all feedback lines are definite signal values.

[0048] In other words, when the SCC has the possibility of oscillating, it is an oscillating circuit. If no constraints are placed on the external input signal values, and G=1 has a solution, it means there exists at least one set of input and feedback signal values ​​that makes the SCC logically consistent, i.e., the SCC has a stable state. At this point, it's impossible to distinguish between an oscillating circuit and a stable circuit. To differentiate between them, constraints need to be placed on the external input signal so that for any given external input signal value, a set of feedback signal solutions can be found that makes G=1 true. This ensures the SCC is always in a stable state, and the circuit is a stable circuit. When G=1 has no solution, the SCC is an oscillating circuit.

[0049] It uses a Boolean formula that establishes logical consistency across all combinational logic circuits as the basis for determining circuit types, enabling precise logical classification of circuits. The classification efficiency is improved by determining whether a solution exists in the solver.

[0050] Among them, g i Characterizing combinational logic circuits (LUTs) i Logical consistency, G = g1·g2·…g i ·…g N Characterizes the logical consistency of all combinational logic circuits. If G=1 has a solution, it means there exists at least one set of input and output signal values ​​such that all combinational logic circuits in the SCC satisfy their respective logical consistency sub-formulas, i.e., g1=1, g2=1, ..., g i =1, ...,g N If G = 1 holds true simultaneously, then a stable state exists. If there is no solution when G = 1, it means there is no set of input and output signal values ​​that allows all combinational logic circuits in the SCC to satisfy their respective logical consistency sub-formulas. In other words, there are at least two combinational logic circuits that can never simultaneously satisfy their respective logical consistency sub-formulas. For example, consider the feedback signal between two combinational logic circuits. If the feedback signal has a value of 0 in the previous stage and a value of 1 in the next stage, it's equivalent to having two different signal values ​​on a single feedback line. This indicates that the SCC does not have a stable state and is an oscillating circuit.

[0051] Preferably, the first solver is a solver for Quantized Boolean Formulas (QBF) problems, i.e., a QBF solver. Other solvers capable of solving the problem that there exists a set of feedback signals such that G=1 holds when the external input signal in P is of arbitrary value are also within the scope of protection of this invention.

[0052] As a preferred embodiment, the stabilizing circuit further includes a latching circuit and a pseudo-loopback circuit. The latching circuit has two or more stable states and can maintain its state until a specific input signal is received. A pseudo-loopback circuit is a circuit that physically presents a closed loop but is not logically closed. The logical behavior of a pseudo-loopback circuit is equivalent to that of a typical combinational logic circuit, exhibiting a specific output under the influence of a specific input signal. To further distinguish whether the current stabilizing circuit is a latching circuit or a pseudo-loopback circuit, the method further includes the following steps:

[0053] S500: Iterate through each feedback signal in F. When there is a feedback signal with any signal value for which G is true, the SCC is a latching circuit; otherwise, it is a pseudo-loop circuit.

[0054] In a preferred embodiment, when there exists a feedback signal of any value for which G holds true, the relationship between the external input signal and the feedback signal of the SCC satisfies:

[0055] H(f k )=G(f k =v0)·G′(f k =v1)=1;

[0056] Among them, G(f k =v0) is the k-th feedback signal f in F k When the signal value is configured as the first signal value v0, the first Boolean formula obtained by updating G is G′(f k =v1) is to make f k When the signal value is configured as the second signal value v1, G is updated to obtain the first Boolean constraint formula.

[0057] It should be noted that f k The signal value can be v0 or v1, but f k It is impossible to take two different signal values ​​at the same time, therefore f k When configuring v0 or v1, the signal values ​​are set for different times. When different signal values ​​are configured, the signal values ​​of certain input or feedback signals in the SCC may change. Therefore, f k When v0 and v1 are configured separately, the other signals in the system are distinguished in terms of formal expression, that is, when f k When configured as v0, use G(f) k =v0) means that when f k When configured as v1, use G′(f) k =v1).

[0058] As a preferred embodiment, when traversing to f k When determining the circuit type of the SCC, the steps include:

[0059] S510, obtain f k The corresponding second Boolean formula: H(f) k ) = 1.

[0060] S520, the H(f) k =1, the P and except f k The F input is used to access the interface of the second solver to obtain the second output result; when the second output result has a solution, the SCC is determined to be a latching circuit and the traversal is stopped; otherwise, the next feedback signal is traversed.

[0061] It should be noted that when H(f) k The fact that f = 1 has a solution indicates that in f kSCC can reach a stable state with any signal value, meaning SCC is a latching circuit. If all feedback signals are traversed, H(f) k If ) = 1, there is no solution, indicating that a combination of definite input signals has a definite output. In this case, SCC is a pseudo-loop circuit.

[0062] As an example, to simply illustrate the process of determining the circuit type of SCC using an example that omits external inputs, please refer to [link to relevant documentation]. Figure 2 ,exist Figure 2 The SCC in the diagram includes two inverters: LUT1 and LUT2. The truth tables of the inverters contain two sets of logic mappings: "10" and "01". Assume that the input signal of LUT1 is f1 and its output signal is f2; the input signal of LUT2 is f2 and its output signal is f1. Based on the truth tables of the inverters, write the sub-formulas for LUT1 and LUT2 respectively. The sub-formula for LUT1... LUT2 subformulas First Boolean formula When the iteration reaches f1, the signal values ​​of f1 are 0 and 1 respectively. Substituting the corresponding signal values ​​into G, we get: but By solving the problem, we find that H(f1) = 1 holds true when f2 = 1 and f2′ = 0. That is, when f2 = 1 and f2′ = 0, the SCC circuit has two stable states. Therefore, the SCC circuit is a latching circuit.

[0063] Preferably, the second solver is a solver for the Boolean Satisfiability Problem (SAT), i.e., an SAT solver. Optionally, the second solver can also be an SMT (Satisfiability Modulo Theories) solver. Other solvers capable of solving the Boolean satisfiability problem fall within the scope of protection of this invention.

[0064] In summary, this invention provides a method for classifying strongly connected circuits. It involves obtaining a strongly connected circuit (SCC) including at least one closed loop, acquiring an external input set P composed of the external input signals of the SCC, and a feedback set F composed of feedback signals. Using elements in P and F as independent variables, a first Boolean formula G is constructed to describe the logical consistency of all combinational logic circuits in the SCC. When the external input signals in P take any value, if there exists a set of feedback signals that makes G=1 a solution, then the SCC is determined to be a stable circuit; otherwise, the SCC is determined to be an oscillating circuit. This achieves the goal of efficiently and accurately classifying circuits. Furthermore, by traversing each feedback signal in F, if there exists a feedback signal that holds true for any value, then the SCC is determined to be a latching circuit; otherwise, it is a pseudo-loop circuit. This further achieves the goal of efficiently and accurately classifying circuits. This allows for different processing operations to be performed subsequently for oscillating circuits, latching circuits, and pseudo-loop circuits.

[0065] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0066] Embodiment 1 of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0067] Embodiment 1 of the present invention also provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to cause the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0068] The method provided in Embodiment 1 can classify strongly connected circuits. However, due to the complex physical connections in the circuit, different external input signals may originate from the same ancestor node. If the signal values ​​of two external input signals from the same ancestor node are always the same, this dependency will cause a certain change in the truth table of the combinational logic circuit. The sub-formulas obtained based on the truth table will change, leading to inaccurate solutions in S400, i.e., inaccurate classification results. Furthermore, external input signals with dependencies cannot take arbitrary signal values. For example, if p1 and p2 come from the same ancestor node and their signal values ​​are always the same, then when the signal value of p1 is 0, the signal value of p2 cannot be 1. This will cause inaccurate solutions in S400 for G=1 based on "when the external input signal in P takes any signal value," i.e., inaccurate classification results. To solve the technical problem of inaccurate classification results caused by external input signals with the same ancestor node, this invention provides Embodiment 2.

[0069] Example 2

[0070] Please see the appendix Figure 3 It illustrates a flowchart of a method for optimizing the classification of strongly connected circuits, the method comprising:

[0071] P100, obtain the strongly connected circuit SCC in the designed circuit, wherein the SCC is at least one closed-loop circuit composed of N-level combinational logic circuits.

[0072] The strongly connected circuit SCC in Embodiment 1 is the same as the strongly connected circuit SCC in Embodiment 2, and will not be described again.

[0073] P200 places all external input signals in the strongly connected circuit SCC into the external input set P.

[0074] In this embodiment, the external input signal is the same as that in embodiment one, and will not be described again.

[0075] P300, obtain the ancestor node of all external input signals in P.

[0076] In a preferred embodiment, the step of obtaining the ancestor node in P300 includes: traversing backwards from each external input signal in P, marking each combinational logic circuit traversed; after the traversal is completed, all combinational logic circuits with more than one mark are designated as ancestor nodes. The backward traversal yields all fan-in paths ending at each external input signal in P. Other methods for obtaining ancestor nodes fall within the protection scope of this invention.

[0077] It should be noted that external input signals that do not share a common ancestor node have no dependency relationship and do not require additional latent constraints. However, external inputs that share a common ancestor node have specific dependencies and require additional latent constraints to obtain accurate circuit classification results.

[0078] Optionally, the reverse traversal algorithm is the depth-first search (DFS) algorithm. Other traversal algorithms used for reverse searching of fan-in nodes are all within the protection scope of this invention.

[0079] P400, obtains T paths that start from the ancestor node and end at each external input signal in P, where T is greater than or equal to 0.

[0080] In a preferred embodiment, the step of obtaining the T paths is as follows: performing a forward traversal based on the starting point and the ending point to obtain the T paths. Other methods for obtaining paths between the starting point and the ending point are all within the protection scope of this invention.

[0081] The forward traversal can obtain all paths from ancestor nodes to all external input signals. By first performing a reverse traversal and then a forward traversal, a staged traversal approach is adopted. Ancestor nodes are located first, and then paths are searched around them, improving the targeting of the search, reducing the algorithm's time complexity, and increasing search efficiency.

[0082] P500 obtains the combinational logic circuits traversed by each path, resulting in the potential constraint circuit set CIC.

[0083] It should be noted that CIC includes all combinational logic circuits traversed by the T paths.

[0084] P600, taking all combinational logic circuits in the CIC and SCC as the overall target circuit, establish a target Boolean formula UG to describe the logical consistency of the overall target circuit.

[0085] The overall target circuit's logic consistency refers to the logic consistency of all combinational logic circuits in CIC and SCC.

[0086] In this embodiment, the conditions that the relationships between the various combinational logic circuits in the overall target circuit satisfy are the same as the conditions that the relationships between the various combinational logic circuits in the strongly connected circuit in this embodiment are satisfy. That is, the conditions that UG satisfies are the same as the conditions that G satisfies, and will not be repeated here.

[0087] In a preferred embodiment, the UG satisfies: UG = g1·g2·…g i ·…g N ·ug1·ug2·…ugj ·…ug M =1; where g i To describe the i-th combinational logic circuit LUT in the SCC i The logical consistency sub-formula, where i ranges from 1 to N, and N is the number of combinational logic circuits in the SCC; ug j For the j-th combinational logic circuit LUT in the CIC j The logical consistency sub-formula, where j ranges from 1 to M, and M is the number of combinational logic circuits in the CIC.

[0088] In embodiment one of the present invention, g i The steps for obtaining the same information are also applicable to this second embodiment, and will not be repeated here.

[0089] Among them, ug j The steps to obtain g i The steps to obtain it are the same, so I will not repeat them here.

[0090] Each item in UG is used to describe the logic consistency of a single combinational logic circuit, and the logic consistency of each combinational logic circuit in CIC further constrains external input signals with the same ancestor node in SCC.

[0091] P700 inputs all independent variable signals in UG and UG=1 into the interface of the first solver for solving, and determines the circuit type of the SCC based on the solution results.

[0092] In this context, all independent variable signals in UG are all external input signals and all feedback signals in CIC and SCC.

[0093] Adding a latent constraint circuit to the SCC (Synthesis-Combinational Logic Circuit) allows external input nodes with the same ancestor node in the SCC to be converted into feedback signals for the entire combinational logic circuit, and the input signals of the ancestor nodes to be converted into external input signals. Based on this, the solution obtained by the first solver is more accurate.

[0094] As a preferred embodiment, P700 further includes:

[0095] P710, acquire the external input signal of the overall target circuit to obtain the overall external input signal set.

[0096] The external input signal of the overall target circuit is a signal that comes from the outside and is connected to the input terminal of the combinational logic circuit in the overall target circuit.

[0097] P720, obtain the feedback signal of the overall target circuit, and obtain the overall feedback signal set.

[0098] The feedback signal of the overall target circuit is the signal that the output signal of the current combinational logic circuit in the overall target circuit is connected to the input terminal of the current combinational logic circuit or other combinational logic circuits in the overall target circuit.

[0099] P730, input all independent variable signals in UG and UG=1 into the interface of the first solver, so that the first solver can obtain whether there is a solution for UG=1 when the external input signal in the overall external input signal set takes any signal value; if there is a solution, determine that the SCC is a stable circuit; otherwise, determine that the SCC is an oscillating circuit.

[0100] In a preferred embodiment, the method further includes the following steps:

[0101] P800 iterates through each feedback signal in the overall feedback signal set. When there is a feedback signal that holds true for any signal value, the SCC is a latching circuit; otherwise, it is a pseudo-loop circuit.

[0102] The method for obtaining S500 in Embodiment 1 is applicable to Embodiment 2 and will not be described again.

[0103] In a preferred embodiment, in P200, traversal stops when the current object being traversed in reverse meets any of the following conditions: the current object is a register; the current object is a circuit interface; or the current object is within a preset depth threshold. By configuring the traversal stopping condition, the traversal range can be constrained, the resource consumption of the algorithm can be controlled, and stack overflow or memory exhaustion problems caused by excessive depth can be avoided.

[0104] In a preferred embodiment, the depth threshold is the maximum value of the number of levels traversed through the combinational logic.

[0105] In summary, Embodiment 2 of the present invention provides a method for optimizing the classification of strongly connected circuits. This method obtains the ancestor nodes of all external input signals of a strongly connected circuit (SCC), acquires the potential paths from the ancestor nodes to each external input signal, uses all combinational logic circuits in the potential paths as potential constraint circuits of the strongly connected circuit, constrains the strongly connected circuit through these potential constraint circuits, and then solves the problem using a first constraint solver. This efficiently obtains accurate classification results and solves the technical problem of inaccurate classification results caused by external input signals having the same ancestor node.

[0106] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0107] Embodiment 2 of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0108] Embodiment 2 of the present invention also provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to cause the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0109] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A method of optimizing strongly connected circuit classification, characterized by, The method comprises: P100, obtaining a strongly connected circuit SCC in a designed circuit, the SCC being at least one closed loop circuit composed of N-stage combinational logic circuits; P200, putting all external input signals in the strongly connected circuit SCC into an external input set P; P300, obtaining ancestor nodes of all external input signals in P; P400, obtaining T paths starting from the ancestor nodes and ending at each external input signal in P, T being greater than or equal to 0; P500, obtaining combinational logic circuits passed by each path to obtain a potential constraint circuit set CIC; P600, taking all combinational logic circuits in the SCC and the CIC as an overall target circuit, establishing a target Boolean formula UG for describing logical consistency of the overall target circuit; P700, inputting all independent variable signals in UG and UG=1 into an interface of a first solver to solve, and judging a circuit type of the SCC according to a solving result.

2. The method of claim 1, wherein, The step of obtaining the ancestor nodes in P300 comprises: reverse traversal starting from each external input signal in P, and marking each combinational logic circuit in the traversal; after the traversal, all combinational logic circuits with more than one mark are taken as the ancestor nodes.

3. The method of claim 1, wherein, The step of obtaining the T paths comprises: forward traversal according to the starting point and the ending point to obtain the T paths.

4. The method of claim 1, wherein, The UG satisfies: UG = g1 · g2 ·... g i ·... g N · ug1 · ug2 ·... ug j ·... ug M = 1; wherein g i is a sub-formula describing the logic consistency of the i-th combinational logic circuit LUT i in the SCC, i has a value range of 1 to N, and N is the number of combinational logic circuits in the SCC; ug j is a sub-formula describing the logic consistency of the j-th combinational logic circuit LUT j in the CIC, j has a value range of 1 to M, and M is the number of combinational logic circuits in the CIC.

5. The method of claim 1, wherein, P700 further comprises: P710, obtaining external input signals of the overall target circuit to obtain an overall external input signal set; P720, obtaining feedback signals of the overall target circuit to obtain an overall feedback signal set; P730, inputting all independent variable signals in UG and UG=1 into an interface of a first solver, so that the first solver obtains whether there is a solution when UG=1 when external input signals in the overall external input signal set take arbitrary signal values; when there is a solution, it is determined that the SCC is a stable circuit; otherwise, it is determined that the SCC is an oscillation circuit.

6. The method of claim 5, wherein, The method further comprises the following steps: P800, traversing each feedback signal in the overall feedback signal set, when there is a feedback signal taking an arbitrary signal value, UG is established, the SCC is a latch circuit; otherwise, it is a false loop circuit.

7. The method of claim 2, wherein, The traversal is stopped when the current object in the reverse traversal satisfies any one of the following conditions: the current object is a register; the current object is an interface of a circuit; the current object is at a preset depth threshold.

8. The method of claim 2, wherein, The depth threshold is a threshold of the number of stages of passing through combinational logic. 9.A non-transitory computer-readable storage medium having stored therein at least one instruction or at least one piece of program, characterized in that, The at least one instruction or the at least one program is loaded and executed by a processor to implement the method in any one of claims 1-8.

10. An electronic device, comprising: The processor and the non-transitory computer-readable storage medium in claim 9 are included.

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