Verification optimization method and system for DDR3 data eye pattern training result

Abstract

The invention discloses a verification optimization method and system for a DDR3 data eye pattern training result. According to the method, after single training is completed, firstly, phase adjustment values of a plurality of DQ signals in the same group are obtained, then the discrete degree statistical magnitude of the phase adjustment values is calculated, and an outlier threshold value is determined based on an outlier detection algorithm. And comparing the statistical magnitude with a threshold value, and outputting an evaluation conclusion according to a preset rule. If the result is unreliable, the system automatically adjusts and optimizes training parameters and reinitiates training according to the abnormal mode of the statistical characteristic quantity; if the result is reliable, the configuration is locked immediately. The objective quantitative evaluation of the training result is realized, and the abnormal configuration is effectively identified and eliminated. Through a closed-loop mechanism of automatically adjusting parameters and retraining, manual intervention is greatly reduced, and debugging precision and efficiency are improved.

Description

Technical Field

[0001] This invention belongs to the field of software algorithm technology, and in particular relates to a method and system for verifying and optimizing DDR3 data eye diagram training results. Background Technology

[0002] In today's digital society, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is an indispensable core component of modern computing devices. Its performance directly determines the data processing capabilities and overall efficiency of various systems, from mobile devices to large data centers. To ensure stable collaboration between the memory controller and DDR chips under high-speed operation, DDR training becomes a critical step in the system power-on initialization process. This process automatically calibrates parameters such as timing and voltage to compensate for physical deviations caused by factors such as PCB manufacturing tolerances and signal transmission delays. Without precise training, the system faces the risk of data transmission errors, performance degradation, and even startup failure.

[0003] As a classic memory technology, DDR3's training process is particularly crucial. Training is mainly divided into write training and read training. Read training further includes Gate training and data eye diagram training. This invention focuses on data eye diagram training. The core objective of this training is to adjust the phase relationship between the data strobe signal and the data signal during read operations, ensuring that the DQS sampling point is located at the center of the DQ "eye diagram" with maximum opening and optimal signal quality, thereby maximizing the timing tolerance and accuracy of read data.

[0004] Specifically, DDR3 data eye diagram training is initiated by software-enabled registers in the SOC chip. Once in training mode, the DDR3 controller repeatedly reads fixed-mode data pre-stored in the DDR3 chip mode register and dynamically adjusts the phase between READ DQS and DQ accordingly. The controller searches for the phase boundary between correct and incorrect data reads, ultimately selecting an intermediate value between the two boundaries as the training result.

[0005] However, as DDR3 speeds have increased to 1.6Gbps and even higher, signal integrity issues have become increasingly prominent. The inherent crosstalk and inter-symbol interference in parallel bus architectures, along with inconsistencies in PCB manufacturing, mean that the controller's training algorithm may fail to find the globally optimal solution in complex real-world environments, leading to occasional deviations from ideal training results. This potential risk in mass-produced products seriously threatens the reliability of the final product.

[0006] To improve training accuracy, the industry has conducted numerous studies. One existing technology proposes a stress coding scheme for high-speed parallel buses. This scheme applies stronger signal pressure during training, aiming to force the training algorithm to find an optimal sampling point that maintains a low bit error rate even under harsh conditions. While this method is valuable in DDR IP core design, its advantages are limited in applications such as driver development and product optimization based on standard IP. The main reason is that if stress testing fails, developers find it difficult to quickly pinpoint whether the problem stems from poor read or write training results, making troubleshooting and targeted optimization challenging.

[0007] Another paper proposes a method to find the optimal sampling point by adjusting the DDR3 output impedance and the dynamic termination resistor value at the SOC end, and performing two rounds of read training. The essence of this method is to simulate different signal integrity environments by changing the electrical characteristics of the signal. However, its drawback lies in the limited combination of selectable parameters, covering only a few preset environments. It cannot adequately cope with the diverse PCB characteristics and complex electrical changes caused by random external interference in mass-produced products, thus lacking universality and effectiveness in actual mass production.

[0008] In summary, existing technical solutions primarily focus on optimizing the training process itself from the outset. However, their coverage and adaptability are often insufficient when faced with the complex influencing factors of high-speed signals. Therefore, how to effectively evaluate and ensure the reliability of the results obtained from each power-on training session at the application level has become a pressing technical problem. Currently, there is a lack of a mechanism that can quickly and automatically determine the validity of the results after training is completed, which is precisely the pain point that this invention aims to address. Summary of the Invention

[0009] To address the above technical problems, this invention provides a method and system for verifying and optimizing DDR3 data eye diagram training results.

[0010] The technical solution adopted by this invention to solve its technical problem is:

[0011] A method for verifying and optimizing DDR3 data eye diagram training results, the method comprising the following steps:

[0012] S100: After completing a DDR3 data eye diagram training, obtain the phase adjustment values ​​of multiple data signals DQ within the same group;

[0013] S200: Calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​in this group. The statistical features include the dispersion statistics, and determine the outlier threshold of this group of data based on the outlier detection algorithm.

[0014] S300: Compares the dispersion statistic with the outlier threshold, and outputs the evaluation conclusion of the current training result according to the preset decision rules.

[0015] S400: If the evaluation conclusion is that the training result is unreliable, then adjust the DDR3 training parameters and re-initiate the data eye diagram training based on the abnormal pattern of the statistical features, and return to S100; if the evaluation conclusion indicates that the training result is reliable, then confirm and lock the training result.

[0016] Preferably, the dispersion statistic in S200 is the variance of multiple DQ phase adjustment values ​​within the same group.

[0017] Preferably, the outlier detection algorithm in S200 is the interquartile range (ICM) method, and the outlier threshold is determined based on the ICM method, specifically including:

[0018] S210: Sort the phase adjustment values ​​of multiple DQs within the same group in ascending order x[0] <x[1]<….x[7];

[0019] S220: Calculate its quartile Q1 = (x[2] + x[3]) / 2, tertiary quartile Q3 = (x[6] + x[7]) / 2 and interquartile range IQR = Q3 – Q1;

[0020] S230: Calculate the upper and lower limits of outliers based on the tertiary quotient, quarter quotient, and interquartile range, specifically:

[0021] Outlier limit = Q³ + 1.5 * IQR

[0022] Outlier lower bound = Q1 – 1.5 * IQR

[0023] The outlier threshold is the range from the lower limit to the upper limit of outliers.

[0024] Preferably, S300 includes: determining whether the variance of multiple DQ phase adjustment values ​​within the same group is greater than the upper limit of the outlier threshold; if so, determining that the training result is unreliable.

[0025] Preferably, adjusting the DDR3 training parameters in S400 specifically involves adjusting the sampling start point.

[0026] A system for verifying and optimizing eye diagram training results for DDR3 data includes:

[0027] The phase adjustment value acquisition module is used to obtain the phase adjustment values ​​of multiple data signals DQ in the same group after completing a DDR3 data eye diagram training.

[0028] The statistical feature calculation and outlier threshold determination module is used to calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​of the group. The statistical features include the dispersion statistics, and the outlier threshold of the group of data is determined based on the outlier detection algorithm.

[0029] The training result evaluation module is used to compare the dispersion statistics with the outlier threshold and output the evaluation conclusion of the current training result according to the preset decision rules.

[0030] The verification and optimization module is used to verify the optimization module. If the evaluation conclusion is that the training result is unreliable, it adjusts the DDR3 training parameters based on the abnormal pattern of the statistical features and re-initiates the data eye diagram training, returning to the phase adjustment value acquisition module. If the evaluation conclusion indicates that the training result is reliable, it confirms and locks the training result.

[0031] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of a method for verifying and optimizing DDR3 data eye diagram training results.

[0032] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a method for verifying and optimizing DDR3 data eye diagram training results.

[0033] The aforementioned method and system for verifying and optimizing DDR3 data eye diagram training results significantly improves the reliability and efficiency of DDR3 data eye diagram training through statistical quantization and closed-loop optimization. The method achieves objective quantitative evaluation of training results by calculating the discrete statistics of the DQ phase adjustment value and detecting outliers, effectively identifying and eliminating abnormal configurations, and ensuring system stability from the source. When the results are unreliable, the system can automatically adjust parameters and retrain based on the abnormal pattern, forming an intelligent closed-loop optimization that eliminates the need for manual intervention and improves debugging accuracy. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the DQS and DQ phases of the DDR3 and SOC ends before data eye diagram training in one embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of the DQS and DQ phases at the SOC end after data eye diagram training in one embodiment of the present invention;

[0036] Figure 3 This is a flowchart of a method for verifying and optimizing DDR3 data eye diagram training results in one embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0038] According to JEDEC standard 79-3, during DDR3 (Double Data Rate 3) read operations, the DQS (Data Strobe) and DQ (Data Line) should be aligned. On the DDR3 controller side of the SOC (System on Chip) chip, the DQS undergoes a 90-degree phase shift to obtain accurate DQ data. On the DDR3 side, DQS and DQ are strictly aligned. On the SOC side, DQ and DQS must have a certain phase difference; a quarter-phase, or 90-degree phase difference, is optimal for DQS sampling. From the DQS perspective, the eye diagram of DQ is at its maximum. Although there are strict requirements for PCB (Printed Circuit Board) routing, requiring DQS and DQ lines within the same group to be of strictly equal length, it is difficult to achieve perfect consistency in line length for all DQ and DQ lines within the same group due to additional routing within the SOC chip package and differences in PCB layers.

[0039] The purpose of data eye diagram training is to ensure complete alignment of all DQ lines within the same group, compensating for phase differences between DQ lines and maximizing the accuracy of DQS sampling. "Same group" refers to the number of DQ data lines sampled simultaneously by DQS. Typically, a group of data lines consists of 8 or 4 DQ lines. This invention uses 8 DQ lines as a group (i.e., DQ0 to DQ7) as an example.

[0040] Figure 1 In this context, CLK (Clock) is the clock source for the DDR3 memory subsystem, DQS is the data synchronization signal for the DDR3 driver, and DDR3 DQ represents the data signals from the DDR3 side within the same group. SOC DQn and SOC DQx represent different DQ data lines within the same group received by the SOC side. It can be seen that the phases of the DQ lines within the same group are uneven at the SOC side. After data eye diagram training, the phases of the DQ lines within the same group are kept consistent, such as... Figure 2 As shown, SOC DQ0', SOC DQx', and SOC DQ7' represent different DQ values ​​within the same group after training with the eye diagram.

[0041] Figures 1 to 2The process is the adjustment process of data eye diagram training. Based on the above analysis, the phase adjustment values ​​of each DQ within the same group tend to be consistent. In actual batch production, the phase adjustment value of a certain DQ within the same group may deviate from the normal distribution and differ from the phase adjustment values ​​of other DQs, leading to errors in the data eye diagram training results. Table 1 shows some statistical results of data eye diagram training errors on the same circuit board.

[0042] Table 1. Statistical results of errors in eye diagram training.

[0043]

[0044] In the table, column 2 represents the error in DQ4 of group 0 in a certain training session, column 3 represents the error in DQ6 of group 6 in a certain training session, column 4 represents the error in DQ7 of group 6 in a certain training session, and so on.

[0045] Extensive statistical data indicates that the error rate of the DQ data line is not consistent. The error value is much smaller than the accurate value.

[0046] Table 2 shows examples of all accurate eye diagram training results.

[0047] Table 2 Results of a certain data eye diagram training.

[0048]

[0049] This invention designs an algorithm that provides a standard for judging the correctness of DDR3 data eye diagram training results, solving the problem that errors in DDR3 data eye diagram training results lead to instability in subsequent large-scale applications, resulting in a significant reduction in product reliability.

[0050] In one embodiment, such as Figure 3 As shown, a method for verifying and optimizing DDR3 data eye diagram training results includes the following steps:

[0051] S100: After completing a DDR3 data eye diagram training, obtain the phase adjustment values ​​of multiple data signals DQ within the same group;

[0052] S200: Calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​in this group. The statistical features include the dispersion statistics, and determine the outlier threshold of this group of data based on the outlier detection algorithm.

[0053] S300: Compares the dispersion statistic with the outlier threshold, and outputs the evaluation conclusion of the current training result according to the preset decision rules.

[0054] S400: If the evaluation conclusion is that the training result is unreliable, then adjust the DDR3 training parameters and re-initiate the data eye diagram training based on the abnormal pattern of the statistical features, and return to S100; if the evaluation conclusion indicates that the training result is reliable, then confirm and lock the training result.

[0055] Specifically, the purpose of this invention is to solve the problem of errors occurring during DDR3 data eye diagram training in SOC chip applications, which affects the overall reliability of the product. This invention adds a step after completing DDR3 data eye diagram training: using a designed algorithm to determine the accuracy of the training results. If the result is incorrect, the adjustment parameters of the data eye diagram training are corrected, and the data eye diagram training operation is performed again. The algorithm designed in this invention references the IQR (Interquartile Range) algorithm for detecting outliers, and combines it with a large amount of empirical data from DDR3 data eye diagram training in SOC chips, perfectly eliminating the phenomenon of errors in DDR3 data eye diagram training. This invention analyzes the results of data eye diagram training, feeds back erroneous results to the DDR controller, and further corrects the parameters of the data eye diagram training, fully ensuring the correctness of the data eye diagram training results, requiring no manual intervention, and achieving 100% accuracy.

[0056] In one embodiment, the dispersion statistic in S200 is the variance of multiple DQ phase adjustment values ​​within the same group.

[0057] In one embodiment, the outlier detection algorithm in S200 is the interquartile range (ICM) method. The outlier threshold is determined based on the ICM method, specifically including:

[0058] S210: Sort the phase adjustment values ​​of multiple DQs within the same group in ascending order x[0] <x[1]<….x[7];

[0059] S220: Calculate its quartile Q1 = (x[2] + x[3]) / 2, tertiary quartile Q3 = (x[6] + x[7]) / 2 and interquartile range IQR = Q3 – Q1;

[0060] S230: Calculate the upper and lower limits of outliers based on the tertiary quotient, quarter quotient, and interquartile range, specifically:

[0061] Outlier limit = Q³ + 1.5 * IQR

[0062] Outlier lower bound = Q1 – 1.5 * IQR

[0063] The outlier threshold is the range from the lower limit to the upper limit of outliers.

[0064] Specifically, any value that is less than the lower limit of outliers or greater than the upper limit of outliers is considered an outlier.

[0065] In one embodiment, S300 includes: determining whether the variance of multiple DQ phase adjustment values ​​within the same group is greater than the upper limit of the outlier threshold; if so, determining that the training result is unreliable.

[0066] Specifically, the variance is compared with the upper limit of outliers. If the variance is greater than the upper limit of outliers, it indicates that the data eye diagram training result is incorrect. If only the method of being less than the lower limit of outliers is used as the basis for judging whether the data eye diagram training result is incorrect, misjudgment will occur. Taking column 2 of Table 2 as an example, at this time, Q1 = 0xb6, Q3 = 0xba, IQR = 0x4, and the lower limit of outliers = 0xb0. At this time, the result of DQ0 is less than 0xb0, leading to misjudgment.

[0067] In one embodiment, adjusting the DDR3 training parameters in S400 specifically involves adjusting the sampling start point.

[0068] Specifically, the parameters typically affecting DDR3 eye diagram training include the training step (sampling step size), training capture cnt (number of samples at the same sampling point), and training start point (starting point of sampling). In this invention, the primary adjustment parameter is the starting point of sampling. Based on feedback from actual engineering applications, a starting point of 0x40 covers 80% of application scenarios, and a starting point of 0x80 covers 60%. The desired starting point setting is to cover 100% of application scenarios. For example, setting it to 0x40 at room temperature works normally, but at high temperatures, some DQ training results become abnormal, and the abnormal DQs are inconsistent each time. Setting the starting point in the software code to 0x80 works normally at high temperatures, but abnormal phenomena reappear at low temperatures. Therefore, it is necessary to solve the problem of adaptively adjusting the starting point based on the training results. By adjusting the starting point, the training results can be made reliable while covering 100% of application scenarios.

[0069] The adaptive detection algorithm in this invention is based on variance and outlier theory in statistics, fully considering the discreteness and uniformity of the data eye diagram training results. The adaptive detection algorithm calculates the variance and outlier upper limit, analyzes and judges the results of the data eye diagram training, and feeds back to the software. The software program automatically determines the next step of the DDR3 driver based on whether it meets the accuracy standards of the data eye diagram training. It is completely adaptive, requires no manual intervention, has low computational load, does not affect the normal training process, and is highly feasible. Outlier detection is currently a hot topic in data analysis, data mining, and machine learning. Applying this popular technology to the traditional technical field of DDR driver development achieves a disruptive innovation in traditional problem-solving methods.

[0070] In one embodiment, a verification and optimization system for DDR3 data eye diagram training results is also provided, comprising:

[0071] The phase adjustment value acquisition module is used to obtain the phase adjustment values ​​of multiple data signals DQ in the same group after completing a DDR3 data eye diagram training.

[0072] The statistical feature calculation and outlier threshold determination module is used to calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​of the group. The statistical features include the dispersion statistics, and the outlier threshold of the group of data is determined based on the outlier detection algorithm.

[0073] The training result evaluation module is used to compare the dispersion statistics with the outlier threshold and output the evaluation conclusion of the current training result according to the preset decision rules.

[0074] The verification and optimization module is used to verify the optimization module. If the evaluation conclusion is that the training result is unreliable, it adjusts the DDR3 training parameters based on the abnormal pattern of the statistical features and re-initiates the data eye diagram training, returning to the phase adjustment value acquisition module. If the evaluation conclusion indicates that the training result is reliable, it confirms and locks the training result.

[0075] Specific limitations regarding the verification and optimization system for DDR3 data eye diagram training results can be found in the limitations of the verification and optimization method for DDR3 data eye diagram training results described above, and will not be repeated here. Each module in the aforementioned verification and optimization system for DDR3 data eye diagram training results can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0076] In one embodiment, a computer device is also provided, including a memory and a processor, the memory storing a computer program, characterized in that the processor, when executed, implements the steps of a method for verifying and optimizing DDR3 data eye diagram training results.

[0077] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, it implements the steps of a method for verifying and optimizing DDR3 data eye diagram training results.

[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0079] The present invention provides a detailed description of a method and system for verifying and optimizing DDR3 data eye diagram training results. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely for the purpose of helping to understand the core ideas of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for verifying and optimizing DDR3 data eye diagram training results, characterized in that, The method includes the following steps: S100: After completing a DDR3 data eye diagram training, obtain the phase adjustment values ​​of multiple data signals DQ within the same group; S200: Calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​in this group. The statistical features include the dispersion statistics, and determine the outlier threshold of this group of data based on the outlier detection algorithm. S300: Compares the dispersion statistic with the outlier threshold, and outputs the evaluation conclusion of the current training result according to the preset decision rules. S400: If the evaluation conclusion is that the training result is unreliable, then adjust the DDR3 training parameters and re-initiate the data eye diagram training based on the abnormal pattern of the statistical features, and return to S100; if the evaluation conclusion indicates that the training result is reliable, then confirm and lock the training result.

2. The method according to claim 1, characterized in that, In S200, the dispersion statistic is the variance of multiple DQ phase adjustment values ​​within the same group.

3. The method according to claim 2, characterized in that, The outlier detection algorithm in S200 is the interquartile range (ICM) method. The outlier threshold is determined based on the ICM method, specifically including: S210: Sort the phase adjustment values ​​of multiple DQs within the same group in ascending order x[0] <x[1]<….x[7]; S220: Calculate its quartile Q1 = (x[2] + x[3]) / 2, tertiary quartile Q3 = (x[6] + x[7]) / 2 and interquartile range IQR = Q3 – Q1; S230: Calculate the upper and lower limits of outliers based on the tertiary quotient, quarter quotient, and interquartile range, specifically: Outlier limit = Q³ + 1.5 * IQR Outlier lower bound = Q1 – 1.5 * IQR The outlier threshold is the range from the lower limit to the upper limit of outliers.

4. The method according to claim 3, characterized in that, S300 includes: determining whether the variance of multiple DQ phase adjustment values ​​within the same group is greater than the upper limit of the outlier threshold; if so, the training result is deemed unreliable.

5. The method according to claim 4, characterized in that, In S400, adjusting the DDR3 training parameters specifically involves adjusting the sampling start point.

6. A verification and optimization system for DDR3 data eye diagram training results, characterized in that, include: The phase adjustment value acquisition module is used to obtain the phase adjustment values ​​of multiple data signals DQ in the same group after completing a DDR3 data eye diagram training. The statistical feature calculation and outlier threshold determination module is used to calculate the statistical features that characterize the distribution of the DQ phase adjustment values ​​of the group. The statistical features include the dispersion statistics, and the outlier threshold of the group of data is determined based on the outlier detection algorithm. The training result evaluation module is used to compare the dispersion statistics with the outlier threshold and output the evaluation conclusion of the current training result according to the preset decision rules. The verification and optimization module is used to adjust the DDR3 training parameters and re-initiate data eye diagram training based on the abnormal patterns of statistical features if the evaluation conclusion is that the training result is unreliable, and then return to the phase adjustment value acquisition module; if the evaluation conclusion indicates that the training result is reliable, then the training result is confirmed and locked.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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