Simulation efficient SAR-ADC size design method based on pre-training learning estimation

Abstract

The invention relates to the field of electronic design automation, and provides a simulation efficient SAR-ADC size design method based on pre-training learning estimation. The objective of the invention is to solve the problems of low SAR-ADC size design optimization efficiency and poor expandability caused by high SPICE simulation cost. According to the main scheme, the method comprises the steps that hierarchical decomposition processing based on a directed acyclic graph (DAG) is carried out on system-level indexes, and optimization target indexes distributed to all sub-circuits are obtained; and for the target index, performing Bayesian optimization on the target index by using the pre-trained agent model, namely a) performing reliability evaluation on the output of the agent model by using a verifier based on a boosting principle to obtain a reliability score; b) when the reliability score is higher than a threshold value, skipping SPICE simulation and adopting an agent model to predict a value; c) when the reliability score is lower than a threshold value, triggering SPICE simulation to obtain a real performance value; and carrying out system-level integration processing on the obtained sub-circuit size parameters to obtain an SAR ADC size design scheme meeting system-level indexes.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA), and more specifically, provides a simulation-efficient SAR-ADC (Successive Approximation Register Analog-to-Digital Converter) size design method based on pre-trained learning estimation. Background Technology

[0002] Design of system-level mixed-signal (AMS) circuits, such as Figure 2 The SAR-ADC shown is an extremely complex and labor-intensive task that relies heavily on expert experience. Traditional design processes require designers to manually decompose top-level performance metrics (such as resolution and sampling rate) into lower-level metrics for each sub-circuit module, followed by extensive iterative adjustments and costly circuit-level simulations (such as SPICE) for verification. This process is not only extremely time-consuming but also highly dependent on the designer's individual skills.

[0003] To improve design efficiency, the industry has begun exploring AI-driven automated design methods. Bayesian optimization (BO), as an effective global optimization technique, has shown great potential in analog circuit-scale design. BO approximates expensive simulation functions by constructing a surrogate model and intelligently selects the next evaluation point using an acquisition function, thus achieving a balance between exploration and exploitation.

[0004] However, existing methods still have significant bottlenecks:

[0005] 1. High cost of online simulation: The standard business logic (BO) process requires one or more high-fidelity online circuit simulations in each iteration. For complex circuits such as SAR-ADC that require long-term transient simulation, the cost is high and the scalability is severely restricted.

[0006] 2. Redundant computation in hierarchical design: To handle complex systems, existing technologies have proposed hierarchical design frameworks that decompose system-level metrics into sub-circuits and optimize each sub-circuit individually (e.g., gate-voltage bootstrap switches, comparators, preamplifiers). However, during the iterative process of top-level optimization, the metrics allocated to sub-circuits constantly change, requiring multiple re-runs of the optimization (BO) process for similar metrics, resulting in a significant waste of simulation resources.

[0007] 3. Limitations of Traditional Surrogate Models: Surrogate models commonly used in Business Architecture (BO), such as Gaussian Process (GP) and Tree-based Parzen Estimators (TPE), perform well on small-scale problems but face difficulties when pre-training on large-scale historical data. The computational complexity of GP models is typically quadratic with the number of data points, making it difficult to seamlessly utilize the large amounts of historical "size-performance" data accumulated over multiple design iterations.

[0008] Therefore, there is an urgent need in this field for a new automated circuit size design method that can efficiently utilize historical data, significantly reduce simulation overhead, and has good scalability. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the aforementioned background technology and provide a simulation-efficient SAR-ADC size design method based on pre-trained learning estimation. This method introduces an innovative hybrid simulation strategy and an advanced Bayesian optimization model, aiming to significantly reduce reliance on expensive SPICE simulations, accelerate design convergence, and achieve efficient reuse of historical design data.

[0010] To achieve the above objectives, the present invention employs the following technical means:

[0011] This invention provides a simulation-efficient SAR-ADC size design method based on pre-trained learning estimation, the method comprising the following steps:

[0012] Step 1: Perform hierarchical decomposition of system-level indicators based on directed acyclic graphs (DAGs) to obtain the optimization target indicators allocated to each sub-circuit.

[0013] Step 2: For the sub-circuit optimization target index obtained in Step 1, perform Bayesian optimization processing using a pre-trained surrogate model, where:

[0014] a) Use a boosting-based validator to evaluate the reliability of the proxy model output and obtain a reliability score;

[0015] b) When the reliability score is higher than the threshold, skip the SPICE simulation and use the surrogate model prediction;

[0016] c) When the reliability score is below the threshold, trigger SPICE simulation to obtain the actual performance value;

[0017] Step 3: Perform system-level integration processing on the sub-circuit size parameters obtained in Step 2 to obtain a SAR ADC size design scheme that meets system-level specifications.

[0018] In the above scheme, step 1 includes the following steps:

[0019] Step 1.1: Divide the SAR-ADC into multiple sub-circuit modules that require individual optimization. The sub-circuit modules include a bootstrap switch, a comparator, a preamplifier, a capacitive digital-to-analog converter (CDAC), and SAR logic.

[0020] Step 1.2: Construct a Directed Acyclic Graph (DAG) to represent the logical dependencies between system-level performance metrics, sub-circuit performance metrics, physical or empirical relationships, intermediate variables, or derived constraints;

[0021] Step 1.3: According to the topological order of the DAG, iteratively calculate the optimization target of each sub-circuit module, ensuring that the optimization target is set before using all operands; wherein, the system-level performance indicators include resolution N and sampling frequency, and the sub-circuit performance indicators include the effective number of bits of the gate bootstrap switch ENOB and the propagation delay of the comparator;

[0022] Step 1.4: After setting the size design parameters of a sub-circuit module, read its output parameters and use the output parameters to calculate the optimization target of subsequent sub-circuit modules; wherein, the output parameters include the on-resistance of the gate bootstrap switch. The optimization objectives for the subsequent sub-circuit modules include the comparator's comparison time and propagation delay;

[0023] Step 1.5: Obtain the dimensional design schemes for all sub-circuit modules and ensure that all constraints are met.

[0024] In the above scheme, step 2 includes the following steps:

[0025] Step 2.1: Construct an efficient proxy simulator (proxy model), wherein the proxy simulator is a neural network model. ),in:

[0026] Represents a vector of sub-circuit size parameters;

[0027] These are the trainable parameters of the model;

[0028] Predictions generated by the proxy model;

[0029] Step 2.2: Build a reliable proxy validator based on boosting , Generate a reliability score, indicating the trustworthiness of the agent's output. :

[0030]

[0031] in:

[0032] These are the trainable parameters for the validator;

[0033] The validator is trained by minimizing the asymmetric reliability loss function:

[0034]

[0035] Indicates reliability score;

[0036] To predict residuals;

[0037] if Otherwise ,in To underestimate the penalty coefficient, To overestimate the penalty coefficient;

[0038] α is a scaling factor;

[0039] Weights for high-risk samples;

[0040] Step 2.3: Implement a simulation skipping mechanism in the Bayesian optimization iteration:

[0041] Step 2.3.1: For candidate points Calculate reliability score

[0042] Step 2.3.2: If , For a predefined threshold, and satisfying the indicator constraints Then skip SPICE simulation and directly use ;

[0043] Step 2.3.2: Otherwise, perform SPICE simulation. And update the validator parameter ϕ.

[0044] In the above scheme, step 2.1, which involves constructing an efficient agent simulator, employs a boosting-based training paradigm, including the following operations:

[0045] The model is pre-trained by minimizing the basic loss function:

[0046]

[0047] in:

[0048] It is the first The first sample Predicted values ​​of dimensional performance indicators, These are the corresponding actual values ​​from the SPICE simulation. It controls the weights of each output dimension.

[0049] The above scheme also provides another implementation method for step 2, in which a pre-trained neural network model based on a Bayesian neural network (BNN) is used to replace the optimization strategy of the GP model during the Bayesian optimization process, including the following operations:

[0050] Step 2.1.1: Train the neural network model This makes its last hidden layer output a feature vector. D is the dimension of the feature vector:

[0051] Step 2.1.2: In the feature vector Perform Bayesian linear regression on the above:

[0052]

[0053] Represents the circuit performance prediction vector;

[0054] This represents the regression weight vector, which follows a normal distribution. ;

[0055] The observed noise represents a normal distribution. ;

[0056] This indicates that it follows a probability distribution. It is the identity matrix. Represents a multivariate normal distribution;

[0057] α and For hyperparameters;

[0058] Step 2.1.3: Adjust the hyperparameters α and β by maximizing the logarithmic marginal likelihood. :

[0059]

[0060] in:

[0061] N represents the number of training samples. This represents the weighted posterior mean vector. Let represent the posterior covariance matrix.

[0062] Step 2.1.4: Using a pre-trained surrogate model, during the Bayesian optimization process, select the next simulation point by means of a collection function (such as expected improvement (EI), upper confidence bound (UCB), etc.) to guide the optimization iteration.

[0063] In the above scheme, step 3 includes the following steps:

[0064] Step 3.1: Read the size design scheme of each sub-circuit obtained in Step 2. The size design scheme includes the transistor size parameter set of the gate bootstrap switch, comparator and preamplifier, as well as the values ​​of other resistors and capacitors in the circuit.

[0065] Step 3.2: Integrate the aforementioned size design scheme into the complete SAR-ADC circuit for system-level verification, wherein:

[0066] The system-level verification evaluates overall performance metrics through SPICE simulation.

[0067] The overall performance metrics include the number of effective bits (ENOB) and the sampling frequency;

[0068] Step 3.3: Determine if system-level constraints are met: If all constraints are met, output the final size design scheme; If constraints are not met, return to Step 1 to adjust the system-level index decomposition scheme and re-trigger the sub-circuit optimization process.

[0069] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects:

[0070] This invention provides a simulation-efficient SAR-ADC size design method based on pre-trained learning estimation, solving a key problem in SAR-ADC size design in the field of electronic design automation (EDA) through innovative technical means. Specific beneficial effects are as follows:

[0071] 1. This invention solves the problem of redundant calculations caused by dynamic changes in system-level indicators in hierarchical design by using the hierarchical decomposition processing technique based on directed acyclic graphs (DAGs) in step 1, thereby optimizing the design process and reducing the waste of computing resources. Specifically, the topological order of the DAG ensures that the optimization target of the sub-circuit is set before the operands are available (as in steps 1.3 and 1.4), and utilizes output parameters (such as the on-resistance of the gate bootstrap switch) to optimize the design process. Dynamically calculating the targets of subsequent modules (such as the propagation delay of comparators) avoids the redundant operation of repeatedly performing sub-circuit optimization due to minor adjustments in indicators, which is common in traditional methods, and significantly improves design efficiency.

[0072] 2. This invention, through the technical means of employing a pre-trained surrogate model to perform Bayesian optimization processing in step 2, combined with a boosting-based reliable surrogate validator and a simulation skipping mechanism, solves the limitations of high online simulation costs and the inability of surrogate models to handle large-scale historical data in traditional Bayesian optimization, achieving a significant reduction in simulation dependence and an improvement in optimization efficiency. Specifically, due to the pre-trained surrogate model (such as a neural network model) Efficiently utilize historical data (step 2.1) and pass the validator. Generate reliability score To assess the reliability of the prediction (step 2.2), the SPICE simulation is skipped when the score is higher than the threshold (step 2.3.2), otherwise a real simulation is triggered. This reduces unnecessary simulation calls and ensures the reliability of the optimization process, overcoming the computational bottleneck of traditional Gaussian processes (GP) or tree-structured Parzen estimators (TPE).

[0073] 3. This invention solves the problem of sub-circuit size integration failing to meet system-level constraints by employing the system-level integration processing technique in step 3, achieving the effect of efficiently obtaining a reliable and convergent size design scheme. Specifically, because the overall performance indicators (such as the effective number of bits ENOB and sampling frequency) are evaluated through SPICE simulation in system-level verification, and the decomposition scheme is adjusted back to step 1 (step 3.3) when constraints are not met, closed-loop optimization of the design is achieved, avoiding local optima and ensuring the feasibility and robustness of the final scheme.

[0074] In summary, through the synergistic effect of the above-mentioned technical means, this invention significantly improves the efficiency and reliability of SAR-ADC size design, while reducing resource consumption, and provides a scalable solution for the design of complex mixed-signal circuits. Attached Figure Description

[0075] Figure 1 This is a simplified flowchart of the present invention;

[0076] Figure 2 This is a system-level SAR-ADC circuit diagram;

[0077] Figure 3 The diagram shows the schematic of the circuit under test. In the diagram, a is the gate bootstrap switch, b is the preamplifier, and c is the comparator.

[0078] Figure 4 This represents the distribution of data points filtered by a reliable proxy validator. Detailed Implementation

[0079] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0080] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0081] This invention provides a simulation-efficient SAR-ADC size design method based on pre-trained learning estimation, the method comprising the following steps:

[0082] Step 1: Perform hierarchical decomposition of system-level indicators based on directed acyclic graphs (DAGs) to obtain the optimization target indicators allocated to each sub-circuit.

[0083] Step 2: For the sub-circuit optimization target index obtained in Step 1, perform Bayesian optimization processing using a pre-trained surrogate model, where:

[0084] a) Use a boosting-based validator to evaluate the reliability of the proxy model output and obtain a reliability score;

[0085] b) When the reliability score is higher than the threshold, skip the SPICE simulation and use the surrogate model prediction;

[0086] c) When the reliability score is below the threshold, trigger SPICE simulation to obtain the actual performance value;

[0087] Step 3: Perform system-level integration processing on the sub-circuit size parameters obtained in Step 2 to obtain a SAR ADC size design scheme that meets system-level specifications.

[0088] In the above scheme, step 1 includes the following steps:

[0089] Step 1.1: Divide the SAR-ADC into multiple sub-circuit modules that require individual optimization. The sub-circuit modules include a bootstrap switch, a comparator, a preamplifier, a capacitive digital-to-analog converter (CDAC), and SAR logic.

[0090] Step 1.2: Construct a Directed Acyclic Graph (DAG) to represent the logical dependencies between system-level performance metrics, sub-circuit performance metrics, physical or empirical relationships, intermediate variables, or derived constraints;

[0091] Step 1.3: According to the topological order of the DAG, iteratively calculate the optimization target of each sub-circuit module, ensuring that the optimization target is set before using all operands; wherein, the system-level performance indicators include resolution N and sampling frequency, and the sub-circuit performance indicators include the effective number of bits of the gate bootstrap switch ENOB and the propagation delay of the comparator;

[0092] Step 1.4: After setting the size design parameters of a sub-circuit module, read its output parameters and use the output parameters to calculate the optimization target of subsequent sub-circuit modules; wherein, the output parameters include the on-resistance of the gate bootstrap switch. The optimization objectives for the subsequent sub-circuit modules include the comparator's comparison time and propagation delay;

[0093] Step 1.5: Obtain the dimensional design schemes for all sub-circuit modules and ensure that all constraints are met.

[0094] In the above scheme, step 2 includes the following steps:

[0095] Step 2.1: Construct an efficient proxy simulator, which is a neural network model. ),in:

[0096] Represents a vector of sub-circuit size parameters;

[0097] These are the trainable parameters of the model;

[0098] Predictions generated by the proxy model;

[0099] Step 2.2: Build a reliable proxy validator based on boosting , Generate a reliability score, indicating the trustworthiness of the agent's output. :

[0100]

[0101] in:

[0102] For trainable parameters of the validator,

[0103] The validator is trained by minimizing the asymmetric reliability loss function:

[0104]

[0105] Indicates reliability score;

[0106] To predict residuals;

[0107] if Otherwise ,in To underestimate the penalty coefficient, To overestimate the penalty coefficient;

[0108] α is a scaling factor;

[0109] Weights for high-risk samples;

[0110] Step 2.3: Implement a simulation skipping mechanism in the Bayesian optimization iteration:

[0111] Step 2.3.1: For candidate points Calculate reliability score

[0112] Step 2.3.2: If , For a predefined threshold, and satisfying the indicator constraints Then skip SPICE simulation and directly use ;

[0113] Step 2.3.2: Otherwise, perform SPICE simulation. And update the validator parameter ϕ.

[0114] In the above scheme, step 2.1, which involves constructing an efficient agent simulator, employs a boosting-based training paradigm, including the following operations:

[0115] The model is pre-trained by minimizing the basic loss function:

[0116]

[0117] in:

[0118] It is the first The first sample Predicted values ​​of dimensional performance indicators, These are the corresponding actual values ​​from the SPICE simulation. It controls the weights of each output dimension.

[0119] The above scheme also provides another implementation method for step 2, in which a pre-trainable model based on a Bayesian neural network (BNN) is used instead of the GP model optimization strategy during the Bayesian optimization process, including the following operations:

[0120] Step 2.1.1: Train the neural network model This makes its last hidden layer output a feature vector. D is the dimension of the feature vector:

[0121] Step 2.1.2: In the feature vector Perform Bayesian linear regression on the above:

[0122]

[0123] Represents the circuit performance prediction vector;

[0124] This represents the regression weight vector, which follows a normal distribution.

[0125] The observed noise represents a normal distribution. ,

[0126] This indicates that it follows a probability distribution. It is the identity matrix. Represents a multivariate normal distribution;

[0127] α and For hyperparameters;

[0128] Step 2.1.3: Adjust the hyperparameters α and β by maximizing the logarithmic marginal likelihood. :

[0129]

[0130] in:

[0131] N represents the number of training samples. This represents the weighted posterior mean vector. Let represent the posterior covariance matrix.

[0132] In the above scheme, step 3 includes the following steps:

[0133] Step 2.1.4: Using a pre-trained surrogate model, during the Bayesian optimization process, select the next simulation point by means of acquisition functions (such as Expected Improvement (EI), Upper Confidence Bound (UCB), etc.) to guide the optimization iteration. Step 3.1: Read the size design schemes of each sub-circuit obtained in Step 2. The size design schemes include the transistor size parameter sets of the gate bootstrap switch, comparator, and preamplifier, as well as the values ​​of other resistors and capacitors in the circuit.

[0134] Step 3.2: Integrate the aforementioned size design scheme into the complete SAR-ADC circuit for system-level verification, wherein:

[0135] The system-level verification evaluates overall performance metrics through SPICE simulation.

[0136] The overall performance metrics include the number of effective bits (ENOB) and the sampling frequency;

[0137] Step 3.3: Determine if system-level constraints are met: If all constraints are met, output the final size design scheme; If constraints are not met, return to Step 1 to adjust the system-level index decomposition scheme and re-trigger the sub-circuit optimization process.

[0138] experiment

[0139] Experimental setup:

[0140] On TSMC's 28nm CMOS process, we targeted three analog sub-circuits ( Figure 3 Experiments were conducted. Transistor-level simulations were performed using Cadence Spectre.

[0141] As shown in Table 1, we constructed historical datasets for each sub-circuit by combining Sobol sequence sampling in the parameter space with a subset of suboptimal historical data. Each dataset covers a wide range of size configurations and corresponding performance metrics obtained through SPICE simulations. These datasets were used to train the surrogate model and surrogate simulator, and to initialize the BO process through pre-training.

[0142] Table 1: Performance Evaluation of High-Efficiency Agent Emulator

[0143] Model training

[0144] All performance metrics were normalized before training. This applies to gate bootstrap switching circuits and... For all operational amplifier (OPAMP) metrics except those of the standard OPAMP, we apply the Yeo–Johnson transform; the remaining metrics are standardized using mean-variance (Z-score).

[0145] BNN proxy model configuration

[0146] In our BNN-based optimization method, we employ a multilayer perceptron (MLP) with three hidden layers (50 units per layer, tanh activation function), where the last hidden layer serves as the feature basis for Bayesian linear regression. Training is performed using a batch size of 16 and a learning rate of 1×10⁻⁶. −4Inputs and outputs are standardized using mean-variance (Z-score) to ensure training stability.

[0147] Design space and simulation constraints

[0148] Each circuit is dimensionally designed using design parameters defined by the Process Design Kit (PDK). Specifically, the transistor parameter constraints are as follows: transistor length L∈[30nm,1μm], transistor width W∈[100nm,10μm], and transistor index (Number of fingers). .

[0149] Table 1 reports the performance metrics of the high-efficiency agent simulator, demonstrating its high prediction accuracy. Figure 4 The results show trusted and untrusted samples identified by the reliable proxy verifier, demonstrating a clear separation between the two groups. These results demonstrate the effectiveness and reliability of the proxy simulator and the proxy verifier.

[0150] Sub-circuit optimization results: Next, we evaluate the optimization results of the three sub-circuits.

[0151] a) Bootstrap Circuit: This is a relatively simple task, and all methods converged successfully. Introducing surrogate model filtering (SIMPLE) significantly reduced the number of simulation calls: for GP, the number of simulations decreased from 82 to 25.66 (a reduction of 56.34); for TPE, it decreased from 67.66 to 34.48 (a reduction of 33.18). Although the number of BO rounds increased slightly due to bias introduced by surrogate model feedback (e.g., from 82 rounds to 95.33 rounds for GP), this was expected and acceptable. We achieved the lowest number of simulations, from 39.45 to 15.70 (a reduction of 24.75), demonstrating excellent sample efficiency in this low-dimensional, single-objective task.

[0152] Table 2: Statistics of Gate Bootstrap Switch Optimization Results

[0153]

[0154] Comparator

[0155] This module is the most challenging. The objective delay constraint is extremely stringent; none of the 1000 Sobol sampling points collected before optimization satisfy it, indicating that the feasible region is extremely sparse. The classic Gaussian process (GP) fails to converge even after more than 500 simulations. The surrogate model-enhanced Gaussian process (GP) reduces the simulation cost to approximately 140 calls, but still fails to find a feasible design. The tree-structured Parzen estimator (TPE) + SIMPLE performs better, reducing the number of simulation calls from 98.83 to 80.23 (a reduction of 18.60), although the number of Bayesian optimization (BO) rounds increases. Our method based on a Bayesian neural network (BNN) consistently converges across multiple runs, achieving the lowest simulation cost by reducing the number of simulations from 16.6 to 3.2 (a reduction of 13.4) and the number of Bayesian optimization (BO) rounds from 16.6 to 3.2.

[0156] Further analysis revealed that in a specific region of the parameter space, the delay metric exhibits a strictly monotonic relationship with all transistor size variables, and the spec threshold lies near the boundary of this region. While tree-structured Parzen estimators (TPEs) and Gaussian processes (GPs) tend to focus their searches on the central region of the parameter space (YL Li, Rudner, and Wilson 2024), our BNN-based method—due to its global acquisition—is able to efficiently explore boundary solutions. This structure-aware capability enables faster identification of feasible points under extremely sparse conditions.

[0157] Table 3: Comparator Results

[0158]

[0159] Operational amplifier (OPAMP)

[0160] We designed two target specification sets: Target A (Spec A, medium difficulty) and Target B (Spec B, stringent, difficult to achieve). This reflects that in system-level SAR-ADC optimization, the operational amplifier (OPAMP) specification is backpropagated from the preceding modules and can vary significantly between different runs.

[0161] In objective A, all methods converged. The tree-structured Parzen estimator (TPE) + SIMPLE achieved the best results (1.6 simulations), while our Bayesian neural network (BNN)-based method required 126 simulations and showed no advantage.

[0162] In objective B, the tree-structured Parzen estimator (TPE) + SIMPLE still converges (reduced from 144 simulations to 68), but our BNN-based approach deteriorates drastically (415 Bayesian optimization (BO) steps). Two main reasons explain this: (1) Although the Bayesian neural network (BNN) model predicts multiple objectives, it still uses scalar-valued acquisition functions (such as EI, UCB) and fails to take advantage of multi-objective trade-offs; (2) Objective B is far beyond the distribution range of the pre-training data, leading to overconfidence in invalid regions and impairing exploration. Notably, due to this mismatch, the pre-trained model performs worse than the cold-start approach.

[0163] Timing efficiency

[0164] The sampling delay of the Gaussian process (GP) grows rapidly; after approximately 40 iterations, its Bayesian optimization (BO) overhead exceeds the SPICE time. In contrast, Bayesian neural networks (BNNs) and tree-structured Parzen estimators (TPEs) remain efficient, with BNNs benefiting from batch inference and TPEs having negligible overhead.

[0165] Table 4: Operational Amplifier Design Results

[0166] Table 5: Complete flow results for each circuit module (including Bayesian optimization rounds / simulation rounds)

[0167]

[0168] Table 5 reports the complete SAR-ADC optimization results across the three stages: gate bootstrap, comparator, and preamplifier / operational amplifier (OPAMP).

[0169] We compared GP+SIMPLE, TPE+SIMPLE, BNN+SIMPLE, and a hybrid strategy (BEST) that best performs by applying modules, with the baseline TPE (original) as a control.

[0170] Simulation cost. The hybrid strategy (BEST) achieved the lowest overall simulation rounds: 15.7 (gate bootstrap switch, BNN+SIMPLE), 3.03 (comparator, BNN+SIMPLE), and 44 (operational amplifier, TPE+SIMPLE), significantly outperforming any single method.

[0171] Convergence speed. BNN+ achieves the fastest Bayesian optimization (BO) convergence on gate bootstrap switches and comparators, while TPE+SIMPLE remains effective and stable for more complex operational amplifier (OPAMP) modules.

[0172] System-level performance: The hybrid strategy achieved a final effective bit count (ENOB) of 11.43, comparable to the original tree-structured Parzen estimator (TPE) (11.49) and superior to GP+SIMPLE, confirming that reducing simulation costs using this method does not compromise ADC performance.

[0173] The inefficiency of Gaussian processes (GP). GP+SIMPLE performs poorly, especially on the operational amplifier (OPAMP) (>483 Bayesian optimization (BO) rounds) and comparator (>500 Bayesian optimization (BO) rounds), often failing to converge within the number of attempts limit. The inability of the Gaussian process (GP) to satisfy the comparator delay specification further propagates tighter constraints to the operational amplifier (OPAMP), exacerbating its inefficiency.

[0174] In summary, the strategy of assigning optimizers by module (hybrid strategy BEST: each module adopts the optimal method) significantly reduces simulation and optimization overhead while maintaining high ADC performance, verifying the effectiveness of the hybrid process in hierarchical AMS design.

Claims

1. A simulation efficient SAR-ADC size design method based on pre-training learning estimation, characterized in that, The method comprises the following steps: Step 1: perform hierarchical decomposition processing on the system-level indicators based on a directed acyclic graph (DAG), to obtain optimization target indicators assigned to each sub-circuit; Step 2: perform Bayesian optimization processing on the sub-circuit optimization target indicators obtained in step 1 using a pre-trained surrogate model, wherein: a) use a verifier based on the boosting principle to evaluate the reliability of the surrogate model output to obtain a reliability score; b) when the reliability score is higher than a threshold, skip the SPICE simulation and use the surrogate model prediction value; c) when the reliability score is lower than the threshold, trigger the SPICE simulation to obtain the real performance value; Step 3: perform system-level integration processing on the sub-circuit size parameters obtained in step 2, to obtain a SAR ADC size design scheme that satisfies the system-level indicators.

2. The method of claim 1, wherein, The step 1 comprises the following steps: Step 1.1: divide the SAR-ADC into a plurality of sub-circuit modules that need to be optimized separately, the sub-circuit modules including a gate bootstrap switch, a comparator, a preamplifier, a capacitive digital-to-analog converter (CDAC), and a SAR logic; Step 1.2: construct a directed acyclic graph (DAG) to represent the logical dependency relationship between the system-level performance indicators, the sub-circuit performance indicators, the physical or empirical relationships, the intermediate variables, or the derived constraints; Step 1.3: iteratively calculate the optimization target of each sub-circuit module in the topological order of the DAG, to ensure that the optimization target is set before all operands are used; wherein the system-level performance indicators include resolution N and sampling frequency, and the sub-circuit performance indicators include effective number of bits (ENOB) of the gate bootstrap switch and propagation delay of the comparator; Step 1.4: After setting the size design parameter of a sub-circuit module, reading its output parameter, and using the output parameter to calculate the optimization target of the subsequent sub-circuit module; wherein the output parameter includes the on-resistance of the gate bootstrap switch , and the optimization target of the subsequent sub-circuit module includes the comparison time of the comparator and the propagation delay; Step 1.5: obtain the size design scheme of all sub-circuit modules and ensure that all constraint conditions are met.

3. The method of claim 1, wherein, The step 2 comprises the following steps: Step 2.1 : Building a high-performance proxy simulator, the proxy simulator being a neural network model ), wherein: represent a sub-circuit size parameter vector; are model trainable parameters; predictions generated for the proxy model; Step 2.2: Building a boosting-based reliable agent validator , producing a reliability score indicating the trustworthiness of the agent output : Wherein: To validate the verifier trainable parameters, The verifier is trained by minimizing an asymmetric reliability loss function: represents a reliability score; to predict the residual; If , otherwise wherein is an underestimation penalty coefficient, is an overestimation penalty coefficient; α is a scaling factor; Weight for high risk samples; Step 2.3: perform a simulation skipping mechanism in the Bayesian optimization iteration: Step 2.3.1: On candidate points Computing reliability score Step 2.3.2: If , is a predefined threshold and the indicator constraint is satisfied, then skip the SPICE simulation and directly adopt ; Step 2.3.2: Otherwise perform SPICE simulation and update the verifier parameter f.

4. The method of claim 3, wherein, In constructing the efficient surrogate simulator in step 2.1, an integrated learning principle-based training paradigm is used to construct an efficient surrogate simulator, including the following operations: The model is pre-trained by minimizing a base loss function: Wherein: is the th sample th performance indicator prediction value, represents the true value, here the spice simulation value, is the weight controlling each output dimension.

5. The method of claim 3, wherein, In constructing the efficient surrogate simulator in step 2.1, a neural network model is used, and a pre-trained neural network model based on a Bayesian neural network (BNN) is used in the optimization step, including the following operations: Step 2.1.1 : Training the neural network model ) to make its last hidden layer output feature vector D is the dimension of the feature vector: Step 2.1.2: Perform Bayesian linear regression on the feature vectors on the feature vectors representing a circuit performance prediction vector; represents the regression weight vector, subject to a normal distribution represents an observation noise, subject to a normal distribution , denotes a compliance probability distribution, is the identity matrix, denotes a multivariate normal distribution; a and are hyperparameters; Step 2.1.3: Adjusting the hyperparameters a and b by maximizing the log marginal likelihood : Wherein: N denotes the number of training samples, denotes the posterior mean vector of the weights, denotes the posterior covariance matrix; Step 2.1.4: use the pre-trained neural network model to guide the optimization iteration by selecting the next simulation point through function selection in the Bayesian optimization process.

6. The method of claim 1, wherein, The step 3 comprises the following steps: Step 3.1: read the size design scheme of each sub-circuit obtained in step 2, the size design scheme including a transistor size parameter set of the gate bootstrap switch, the comparator, and the preamplifier, and the values of other resistors and capacitors in the circuit; Step 3.2: integrate the size design scheme into the complete SAR-ADC circuit for system-level verification, wherein: the system-level verification evaluates overall performance indicators through SPICE simulation; the overall performance indicators include effective number of bits and sampling frequency; Step 3.3: determine whether the system-level constraint conditions are met: if all constraint conditions are met, output the final size design scheme; if the constraint conditions are not met, return to step 1 to adjust the system-level indicator decomposition scheme, and retrigger the sub-circuit optimization process.

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