Fault detection system and method and storage medium
By performing fault analysis on the original upper and lower PWM signals of the servo driver and using hardware logic circuits for real-time monitoring, the problem of not being able to identify PWM signal anomalies in advance in the existing technology is solved, and the high robustness and safety of the servo system are achieved.
Patent Information
- Application Number
- CN202511570684.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-17
AI Technical Summary
Existing fault detection methods are mostly post-event detection methods, which cannot identify PWM signal abnormalities within microseconds, resulting in insufficient robustness and safety of servo systems.
Fault analysis is performed by generating raw upper and lower PWM signals, and real-time monitoring is conducted using hardware logic circuits to generate control signals to prevent faults, including the detection of shoot-through, signal loss, and abnormal duty cycle.
This enables protection before a fault occurs, improving the robustness and security of the system, and enhancing the maintainability and response speed of the equipment.
Smart Images
Figure CN121546974A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of fault detection technology, specifically to a fault detection system, method, and storage medium. Background Technology
[0002] Servo drives are core components in modern industrial automation. They control the switching on and off of power switching devices (such as IGBTs and MOSFETs) by outputting PWM signals, thereby driving servo motors to achieve precise motion control. The accuracy and reliability of the PWM signal are directly related to the safety and performance of the entire servo system.
[0003] In practical applications, due to electromagnetic interference, hardware aging, software malfunctions, overheating, and other reasons, the original PWM signal generated by the servo driver may experience various faults, such as: Shoot-through fault: The upper and lower switches of the same bridge arm are accidentally triggered and conduct simultaneously, causing a short circuit in the DC bus, generating a huge short-circuit current, which can easily burn out power devices.
[0004] Drive signal loss: The drive signal of one or more switching transistors is lost unexpectedly, resulting in the motor running with a single phase, torque fluctuation, and even damage to the motor and mechanical equipment.
[0005] Abnormal duty cycle: Abnormal control software may cause the output PWM duty cycle to exceed the safe range, resulting in overcurrent or bus voltage surge.
[0006] Existing fault detection methods mostly focus on current sampling feedback or bus voltage detection. However, these methods are "post-incident" detections, meaning that protection actions can only be initiated after a fault current or voltage has already occurred, resulting in a lag in response. Sometimes, this is insufficient to prevent device damage within microseconds. Furthermore, some minor signal anomalies may not be immediately reflected in the current or voltage, but long-term operation can reduce system reliability.
[0007] Therefore, there is an urgent need for a technology that can detect the PWM signal itself "before" or "during" at the front end, so as to identify and block abnormal signals before they are actually applied to power devices, thereby achieving a higher level of active protection. Summary of the Invention
[0008] The technical problem to be solved by the present invention is to provide a fault detection system, method and storage medium to address the shortcomings of the prior art.
[0009] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: a fault detection system, comprising a main controller, a fault analysis module, and a power drive module. The main controller is used to generate the original upper-path PWM signal and the original lower-path PWM signal; The fault analysis module is used to perform fault analysis on the original upper PWM signal and the original lower PWM signal, and generate control signals based on the analysis results; The power drive module is used to control the servo motor according to the control signal.
[0010] Another technical solution of the present invention to solve the above-mentioned technical problems is as follows: A fault detection method, comprising the following steps: Generate the original upper-path PWM signal and the original lower-path PWM signal; Fault analysis is performed on the original upper-path PWM signal and the original lower-path PWM signal, and control signals are generated based on the analysis results; The servo motor is controlled according to the control signal.
[0011] The beneficial effects of this invention are: by generating original upper-path PWM signals and original lower-path PWM signals, performing fault analysis on the original upper-path PWM signals and original lower-path PWM signals, and generating control signals based on the analysis results, and controlling the servo motor based on the control signals, true protection is achieved before an accident occurs, and it is not affected by the main controller software failure, which greatly improves the robustness and safety of the system, realizes the detection of multiple faults, and also improves the maintainability of the equipment. Attached Figure Description
[0012] Figure 1 This is a block diagram of a fault detection system provided in an embodiment of the present invention; Figure 2 This is a structural block diagram of a fault detection system provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a fault analysis module in a fault detection system provided in an embodiment of the present invention; Figure 4 This is a timing diagram for through-fault detection of a fault detection system provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating a fault detection method provided in an embodiment of the present invention. Detailed Implementation
[0013] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.
[0014] Figure 1 This is a block diagram of a fault detection system provided in an embodiment of the present invention.
[0015] like Figure 1As shown, a fault detection system includes a main controller, a fault analysis module, and a power drive module. The main controller is used to generate the original upper-path PWM signal and the original lower-path PWM signal; The fault analysis module is used to perform fault analysis on the original upper PWM signal and the original lower PWM signal, and generate control signals based on the analysis results; The power drive module is used to control the servo motor according to the control signal.
[0016] It should be understood that the raw PWM signals (i.e., the raw upper PWM signal and the raw lower PWM signal) generated by the servo drive master controller (such as DSP, FPGA) (i.e., the master controller) are acquired in real time.
[0017] In the above embodiments, by generating original upper-path PWM signals and original lower-path PWM signals, fault analysis is performed on the original upper-path PWM signals and original lower-path PWM signals, and control signals are generated based on the analysis results. The servo motor is controlled based on the control signals, which realizes true protection before the accident occurs and is not affected by the main controller software failure. This greatly improves the robustness and safety of the system, realizes the detection of multiple faults, and also improves the maintainability of the equipment.
[0018] Optionally, as an embodiment of the present invention, such as Figure 1 and 2 As shown, the fault analysis module includes a fault detection submodule and a protection execution submodule; The fault detection submodule is used to perform fault detection on the original upper PWM signal and the original lower PWM signal to obtain multiple original fault signals; The protection execution submodule is used to merge all the original fault signals through an OR gate to obtain the target fault signal; Determine whether the target fault signal is a preset fault signal. If yes, generate a fault emergency shutdown signal and use the fault emergency shutdown signal as a control signal. If no, generate a PWM enhancement signal and use the PWM enhancement signal as the control signal.
[0019] It should be understood that the protection execution module (i.e., the protection execution submodule) takes immediate action upon detecting a fault, blocking the PWM output and reporting the fault.
[0020] It should be understood that the acquired raw PWM signals (i.e., the raw upper PWM signal and the raw lower PWM signal) are input to the hardware logic circuit (such as CPLD, FPGA or dedicated ASIC) (i.e., the fault detection submodule).
[0021] Specifically, upon receiving a fault signal (any fault) from the hardware logic diagnostic module, all PWM outputs are immediately blocked, causing the driver chip to stop outputting drive signals, thereby protecting the power devices.
[0022] It should be understood that a multi-input OR gate is used to combine all fault flags (straight-through, missing, abnormal duty cycle, etc.) (i.e., the original fault signals) into a single overall fault signal (i.e., the target fault signal).
[0023] It should be understood that all generated fault flag signals are logically ORed to generate a total fault emergency shutdown (Fault) signal (i.e., the target fault signal).
[0024] Specifically, this overall fault signal (i.e., the target fault signal) is directly connected to the enable / block pin (such as nENABLE, nFAULT, etc.) of the driver chip (i.e., the power drive module). When the fault signal is valid (i.e., the target fault signal is the preset fault signal), the driver chip (i.e., the power drive module) will immediately shut down all outputs.
[0025] Specifically, the detailed workflow of the protection execution module (i.e., the protection execution submodule) is as follows: Input comes from multiple fault flags (straight-through, missing, abnormal duty cycle, etc.) (i.e., raw fault signals); These fault flags (i.e., the original fault signals) are combined into a single overall fault signal (i.e., the target fault signal) through an OR gate. Connect the fault signal (i.e., the target fault signal) directly to the blocking pin (active low or active high, depending on the specifications of the driver chip) of the driver chip (i.e., the power drive module).
[0026] In the above embodiments, fault analysis is performed on the original upper PWM signal and the original lower PWM signal, and control signals are generated based on the analysis results. This achieves true protection before an accident occurs and is not affected by the main controller software crash, greatly improving the robustness and safety of the system. It also enables the detection of multiple faults and improves the maintainability of the equipment.
[0027] Optionally, as an embodiment of the present invention, such as Figures 1 to 4 As shown, the fault detection submodule includes a pass-through fault detection unit, a signal loss fault detection unit, and a duty cycle anomaly detection unit; The pass-through fault detection unit is used to perform logical operations on the original upper-path PWM signal and the original lower-path PWM signal through an AND gate to obtain the pass-through fault detection level. Determine whether the through-fault detection level is a preset level. If yes, generate a through-fault flag signal and use the through-fault flag signal as the original fault signal; otherwise, generate a through-normal signal and use the through-normal signal as the original fault signal. The signal loss fault detection unit is used to detect the original upper-path PWM signal or the original lower-path PWM signal through a watchdog timer within a preset time, and determine whether any detection result is a preset signal loss fault result. If so, a signal loss fault flag signal is generated and the signal loss fault flag signal is used as the original fault signal; if not, a signal not lost signal is generated and the signal not lost signal is used as the original fault signal. The duty cycle anomaly detection unit is used to compare the original upper-path PWM signal with a preset window signal or the original lower-path PWM signal with the preset window signal using a window comparator, and determine whether the original upper-path PWM signal is greater than the preset window signal or whether the original lower-path PWM signal is greater than the preset window signal. If so, a duty cycle anomaly fault flag is generated and used as the original fault signal; if not, a duty cycle normal signal is generated and used as the original fault signal.
[0028] It should be understood that the hardware logic diagnostic module (i.e., the fault detection submodule) is responsible for performing real-time analysis on the input raw PWM signals (i.e., the raw upper PWM signal and the raw lower PWM signal) to detect faults such as shoot-through, loss, and abnormal duty cycle.
[0029] Specifically, a logical AND operation is performed on the upper and lower PWM signals of the same bridge arm (i.e., the original upper PWM signal and the original lower PWM signal); if the result of the AND operation is high at any time (i.e., the preset level), a shoot-through fault flag signal is immediately generated.
[0030] It should be understood that the function of the shoot-through fault diagnosis unit (i.e., the shoot-through fault detection unit) is to detect whether the drive signals of the upper and lower switches of the same bridge arm (i.e., the original upper PWM signal and the original lower PWM signal) are simultaneously high (i.e., shoot-through state).
[0031] Specifically, the upper and lower PWM signals of each bridge arm (i.e., the original upper PWM signal and the original lower PWM signal) are connected to the two inputs of an AND gate. Once the AND gate outputs a high level, it indicates that a shoot-through fault has occurred. Since shoot-through is extremely dangerous and needs to be dealt with immediately, this detection must be parallel and real-time.
[0032] It should be understood that each PWM signal (i.e., the original upper PWM signal and the original lower PWM signal) is monitored at regular intervals; if a low level or high level is detected on any PWM signal (i.e., the original upper PWM signal or the original lower PWM signal) that lasts for more than a preset time T_loss (e.g., more than 2 PWM cycles) (i.e., the preset signal loss fault result), it is determined that the signal is lost and a signal loss fault flag (i.e., the signal loss fault flag signal) is generated.
[0033] It should be understood that the function of the signal loss diagnostic unit (i.e., the signal loss fault detection unit) is to detect whether any PWM signal (i.e., the original upper PWM signal or the original lower PWM signal) remains at a fixed level (high or low) for a long time without change (i.e., the preset signal loss fault result), which indicates that the signal is lost or stuck.
[0034] Specifically, a timer (or counter) (i.e., a watchdog timer) is used to monitor the edges of each PWM signal (i.e., the original upper or lower PWM signal). For example, if no edge change is detected within a preset time T_loss, it is considered a signal loss. This preset time is typically set slightly longer than twice the PWM period (ensuring at least one rising and one falling edge). The timer is reset and restarted after each detected edge (rising or falling). If the timer overflows, a fault signal (i.e., a signal loss fault flag) is generated.
[0035] It should be understood that each PWM signal (i.e., the original upper PWM signal and the original lower PWM signal) is compared with a standard window signal (i.e., the preset window signal) generated by the maximum and minimum values of the safe duty cycle; if the effective pulse width of the PWM signal exceeds the window range (i.e., the preset window signal), a duty cycle abnormality fault flag is generated.
[0036] It should be understood that the duty cycle anomaly diagnostic unit (i.e., duty cycle anomaly detection unit) functions to detect whether the duty cycle of each PWM signal (i.e., the original upper PWM signal and the original lower PWM signal) exceeds the allowable safe range (e.g., maximum duty cycle and minimum duty cycle).
[0037] It should be understood that a counter is used to measure the duration of the high level within each cycle and compare it with preset upper and lower limits (i.e., preset window signals).
[0038] Specifically, the detailed workflow of the hardware logic diagnostic module (i.e., the fault detection submodule) is as follows: Input multiple raw PWM signals (e.g., 6 channels, corresponding to the upper and lower arms of the three-phase bridge) (i.e., raw upper PWM signal and raw lower PWM signal); Shoot-through diagnostics: The upper and lower signals of each bridge arm (i.e., the original upper PWM signal and the original lower PWM signal) are fed into an AND gate. The output of the AND gate is latched by a flip-flop (optional) and used as a shoot-through fault indicator.
[0039] Signal loss diagnosis: Each PWM signal (i.e., the original upper PWM signal and the original lower PWM signal) is connected to an edge detection circuit. The output of the edge detection circuit is used to reset a timer. If the timer is full (overflows), a signal loss fault flag is generated.
[0040] Duty cycle diagnosis: The high-level time of each PWM signal (i.e., the original upper PWM signal and the original lower PWM signal) is measured digitally (e.g., using a high-speed counter) and compared with the upper and lower limits stored in the register. If it exceeds the range, a duty cycle abnormality fault flag is generated.
[0041] In the above embodiments, fault detection is performed on the original upper PWM signal and the original lower PWM signal to obtain multiple original fault signals, which greatly improves the robustness and safety of the system, realizes the detection of multiple faults, and also improves the maintainability of the equipment.
[0042] Optionally, as an embodiment of the present invention, the power drive module is used for: If the control signal is a fault emergency shutdown signal, then the servo motor is controlled to shut down; If the control signal is a PWM enhancement signal, then the original upper PWM signal and the original lower PWM signal are enhanced, and the enhanced result is sent to the servo motor.
[0043] It should be understood that once the overall fault emergency shutdown signal is valid (i.e., fault emergency shutdown signal), the output of all PWM channels is immediately blocked by the hardware circuit (i.e., the power drive module), forcing them to a safe state (usually a shutdown state).
[0044] Specifically, a power driver chip (such as TI's DRV830x, ADI's ADuM422x, and Infineon's 1ED series) (i.e., a power driver module) is a "signal amplifier" and "electrical isolator." It receives a weak PWM signal from the main controller (typically at 3.3V or 5V levels, with milliamp-level current) and then converts it into a strong signal sufficient to quickly and reliably drive power switching devices (requiring ±15V levels, with ampere-level peak current).
[0045] In the above embodiments, the servo motor is controlled according to the control signal, which realizes the detection of various faults and improves the maintainability of the equipment.
[0046] Optionally, as an embodiment of the present invention, the protection execution submodule is further configured to: If the target fault signal is a preset fault signal, an error interrupt signal is generated and sent to the main controller.
[0047] It should be understood that the fault signal is latched into a status register as an edge-triggered signal and generates an interrupt signal (i.e., an error interrupt signal) to the main controller.
[0048] Specifically, a fault signal (i.e., the target fault signal) will also trigger an interrupt generation circuit (e.g., a D flip-flop latches the fault state and generates an edge signal) to send an interrupt request (i.e., an error interrupt signal) to the main controller so that the main controller can record the fault and perform subsequent processing.
[0049] Specifically, in the interrupt service routine, the main controller reads the value of the status register through a parallel bus or a serial bus (such as SPI) to determine the specific fault type and fault channel, and then performs operations such as fault logging and system shutdown.
[0050] In the above embodiments, if the target fault signal is a preset fault signal, an error interrupt signal is generated and sent to the main controller, thereby realizing the detection of multiple faults and improving the maintainability of the equipment.
[0051] Alternatively, as another embodiment of the present invention, the purpose of the present invention is to overcome the shortcomings of the prior art and provide a servo drive PWM fault monitoring method and device with fast response speed, high reliability, and the ability to monitor the PWM signal status in real time and take protective measures immediately when a fault occurs.
[0052] Optionally, as another embodiment of the present invention, the present invention further includes software processing and recording, the steps of which are as follows: The main controller responds to the interrupt, reads the fault status register, accurately identifies the fault type and channel, executes the corresponding software protection algorithm (such as shutdown, free coasting, etc.), and stores the fault information in non-volatile memory for subsequent diagnosis and maintenance.
[0053] Optionally, as another embodiment of the present invention, the present invention further includes: Signal acquisition module: Connected to the PWM output pin of the main controller, used to receive the raw PWM signal.
[0054] Hardware logic diagnostic module: Composed of programmable logic devices, including: The direct-through fault diagnosis unit has multiple built-in logic AND gates, corresponding to each H-bridge arm; The signal loss diagnostic unit has multiple built-in timers / counters; Duty cycle limiting diagnostic unit with built-in comparator or window function generator.
[0055] Fault Synthesis Logic Module: Composed of OR gate circuits, used to summarize all fault flags.
[0056] Protection execution module: Includes the enable or block pin control circuit of the driver chip, which can instantly block the output of the driver chip when the fault signal is valid.
[0057] Interrupt generation module: Used to send interrupt signals to the main controller.
[0058] Status register module: used to latch the current fault status for query by the main controller.
[0059] Alternatively, as another embodiment of the present invention, the beneficial effects of the present invention are as follows: 1. Real-time performance and forward-looking capability: Parallel diagnostics are performed using hardware logic circuits, with response times ranging from nanoseconds to microseconds, which is much faster than software scanning or current sampling methods, achieving true "prevention" protection.
[0060] 2. High reliability: The hardware circuit is not affected by the main controller software crash. Even if the main program crashes, the hardware protection mechanism remains effective, greatly improving the robustness and security of the system.
[0061] 3. Comprehensive diagnostics: It integrates monitoring of various common PWM faults such as shoot-through, loss, and abnormal duty cycle, providing comprehensive functionality.
[0062] 4. Facilitates diagnosis: Hardware latches fault status and reports it to the main controller, which facilitates fault recording, analysis and remote diagnosis by the system, improving the maintainability of the equipment.
[0063] Optionally, as another embodiment of the present invention, the fault analysis module of the present invention is located between the servo driver main controller and the power drive chip. The six (or more) raw PWM signals (PWM1H, PWM1L, PWM2H, ...) generated by the main controller are simultaneously sent to the hardware logic diagnostic module (implemented by a CPLD) and the driver chip.
[0064] Inside the CPLD, the signal is processed in three paths: For shoot-through diagnostics, PWM1H and PWM1L are fed into a two-input AND gate. Under normal circumstances, one of them is always low, and the AND gate output is always low; once a shoot-through occurs, both are high, the AND gate output is high, and the fault is triggered.
[0065] For signal loss diagnosis, each PWM signal is connected to a watchdog timer. This timer is reset on each rising or falling edge of the PWM signal. If the signal remains constant at a high or low level, the timer will overflow, generating a fault flag.
[0066] For duty cycle diagnosis, a reference signal corresponding to a safe maximum duty cycle (e.g., 90%) and a minimum duty cycle (e.g., 0.1%) preset by the main controller is compared with the input PWM signal to determine whether the pulse width exceeds the limit.
[0067] All fault flags are fed into an OR gate, the output of which is connected to the blocking pin of the driver chip (e.g., the nITRIP pin of an IR driver chip). Once any fault occurs, the fault signal becomes active, immediately forcing the driver chip to shut down the gate drive outputs of all IGBTs.
[0068] Simultaneously, the fault signal also triggers the interrupt logic inside the CPLD, sending a signal to the external interrupt pin of the main controller. The main controller enters the interrupt service routine, reads the fault status register inside the CPLD via SPI or parallel bus, thereby determining which bridge arm has experienced what type of fault, updates the fault code, and executes the safety shutdown procedure.
[0069] Optionally, as another embodiment of the present invention, the PWM frequency is set to 10kHz (period 100μs), and the signal loss detection time T_loss is set to 200μs (2 cycles). When a certain PWM signal remains high for more than 200μs due to a fault, the signal loss diagnosis unit immediately sets a fault flag. After passing through an OR gate, this flag blocks the driver chip within tens of nanoseconds, protecting the power devices. The main controller responds to the interrupt within microseconds, reads the status, and records the "A-phase upper bridge arm signal loss" fault.
[0070] Figure 5 This is a flowchart illustrating a fault detection method provided in an embodiment of the present invention.
[0071] Alternatively, as another embodiment of the present invention, such as Figure 5 As shown, a fault detection method includes the following steps: S1: Generate the original upper-path PWM signal and the original lower-path PWM signal; S2: Perform fault analysis on the original upper-path PWM signal and the original lower-path PWM signal, and generate control signals based on the analysis results; S3: Control the servo motor according to the control signal.
[0072] Optionally, as an embodiment of the present invention, the process of performing fault analysis on the original upper-path PWM signal and the original lower-path PWM signal, and generating a control signal based on the analysis results, includes: Fault detection is performed on the original upper-path PWM signal and the original lower-path PWM signal to obtain multiple original fault signals; The target fault signal is obtained by merging all the original fault signals using an OR gate; Determine whether the target fault signal is a preset fault signal. If yes, generate a fault emergency shutdown signal and use the fault emergency shutdown signal as a control signal. If no, generate a PWM enhancement signal and use the PWM enhancement signal as the control signal.
[0073] Optionally, as an embodiment of the present invention, the process of performing fault detection on the original upper-path PWM signal and the original lower-path PWM signal to obtain multiple original fault signals includes: By performing logical operations on the original upper-path PWM signal and the original lower-path PWM signal using an AND gate, the shoot-through fault detection level is obtained. Determine whether the through-fault detection level is a preset level. If yes, generate a through-fault flag signal and use the through-fault flag signal as the original fault signal; otherwise, generate a through-normal signal and use the through-normal signal as the original fault signal. Within a preset time period, the original upper-path PWM signal or the original lower-path PWM signal is detected by a watchdog timer. It is determined whether either detection result is a preset signal loss fault result. If so, a signal loss fault flag signal is generated and used as the original fault signal. If not, a signal not lost signal is generated and used as the original fault signal. The original upper-path PWM signal is compared with a preset window signal using a window comparator, or the original lower-path PWM signal is compared with the preset window signal to determine whether the original upper-path PWM signal is greater than the preset window signal, or whether the original lower-path PWM signal is greater than the preset window signal. If so, a duty cycle abnormality fault flag is generated and used as the original fault signal; otherwise, a duty cycle normal signal is generated and used as the original fault signal.
[0074] Optionally, another embodiment of the present invention provides a fault detection system, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the fault detection method described above. This system can be a computer or similar system.
[0075] Optionally, another embodiment of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the fault detection method described above.
[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0077] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0078] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0079] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.
[0080] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. This is understood to mean that the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0082] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A fault detection system, characterized in that, include: Main controller, fault analysis module, and power drive module, The main controller is used to generate the original upper-path PWM signal and the original lower-path PWM signal; The fault analysis module is used to perform fault analysis on the original upper PWM signal and the original lower PWM signal, and generate control signals based on the analysis results; The power drive module is used to control the servo motor according to the control signal.
2. The fault detection system according to claim 1, characterized in that, The fault analysis module includes a fault detection submodule and a protection execution submodule; The fault detection submodule is used to perform fault detection on the original upper PWM signal and the original lower PWM signal to obtain multiple original fault signals; The protection execution submodule is used to merge all the original fault signals through an OR gate to obtain the target fault signal; Determine whether the target fault signal is a preset fault signal. If yes, generate a fault emergency shutdown signal and use the fault emergency shutdown signal as a control signal. If no, generate a PWM enhancement signal and use the PWM enhancement signal as the control signal.
3. The fault detection system according to claim 2, characterized in that, The fault detection submodule includes a pass-through fault detection unit, a signal loss fault detection unit, and a duty cycle anomaly detection unit. The pass-through fault detection unit is used to perform logical operations on the original upper-path PWM signal and the original lower-path PWM signal through an AND gate to obtain the pass-through fault detection level. Determine whether the through-fault detection level is a preset level. If yes, generate a through-fault flag signal and use the through-fault flag signal as the original fault signal; otherwise, generate a through-normal signal and use the through-normal signal as the original fault signal. The signal loss fault detection unit is used to detect the original upper-path PWM signal or the original lower-path PWM signal through a watchdog timer within a preset time, and determine whether any detection result is a preset signal loss fault result. If so, a signal loss fault flag signal is generated and the signal loss fault flag signal is used as the original fault signal; if not, a signal not lost signal is generated and the signal not lost signal is used as the original fault signal. The duty cycle anomaly detection unit is used to compare the original upper-path PWM signal with a preset window signal or the original lower-path PWM signal with the preset window signal using a window comparator, and determine whether the original upper-path PWM signal is greater than the preset window signal or whether the original lower-path PWM signal is greater than the preset window signal. If so, a duty cycle anomaly fault flag is generated and used as the original fault signal; if not, a duty cycle normal signal is generated and used as the original fault signal.
4. The fault detection system according to claim 2, characterized in that, The power drive module is used for: If the control signal is a fault emergency shutdown signal, then the servo motor is controlled to shut down; If the control signal is a PWM enhancement signal, then the original upper PWM signal and the original lower PWM signal are enhanced, and the enhanced result is sent to the servo motor.
5. The fault detection system according to claim 2, characterized in that, The protection execution submodule is also used for: If the target fault signal is a preset fault signal, an error interrupt signal is generated and sent to the main controller.
6. A fault detection method, characterized in that, Includes the following steps: Generate the original upper-path PWM signal and the original lower-path PWM signal; Fault analysis is performed on the original upper-path PWM signal and the original lower-path PWM signal, and control signals are generated based on the analysis results; The servo motor is controlled according to the control signal.
7. The fault detection method according to claim 6, characterized in that, The process of performing fault analysis on the original upper-path PWM signal and the original lower-path PWM signal, and generating control signals based on the analysis results, includes: Fault detection is performed on the original upper-path PWM signal and the original lower-path PWM signal to obtain multiple original fault signals; The target fault signal is obtained by merging all the original fault signals using an OR gate; Determine whether the target fault signal is a preset fault signal. If yes, generate a fault emergency shutdown signal and use the fault emergency shutdown signal as a control signal. If no, generate a PWM enhancement signal and use the PWM enhancement signal as the control signal.
8. The fault detection method according to claim 7, characterized in that, The process of performing fault detection on the original upper-channel PWM signal and the original lower-channel PWM signal to obtain multiple original fault signals includes: By performing logical operations on the original upper-path PWM signal and the original lower-path PWM signal using an AND gate, the shoot-through fault detection level is obtained. Determine whether the through-fault detection level is a preset level. If yes, generate a through-fault flag signal and use the through-fault flag signal as the original fault signal; otherwise, generate a through-normal signal and use the through-normal signal as the original fault signal. Within a preset time period, the original upper-path PWM signal or the original lower-path PWM signal is detected by a watchdog timer. It is determined whether either detection result is a preset signal loss fault result. If so, a signal loss fault flag signal is generated and used as the original fault signal. If not, a signal not lost signal is generated and used as the original fault signal. The original upper-path PWM signal is compared with a preset window signal using a window comparator, or the original lower-path PWM signal is compared with the preset window signal to determine whether the original upper-path PWM signal is greater than the preset window signal, or whether the original lower-path PWM signal is greater than the preset window signal. If so, a duty cycle abnormality fault flag is generated and used as the original fault signal; otherwise, a duty cycle normal signal is generated and used as the original fault signal.
9. A fault detection system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the fault detection method as described in claims 6 to 8.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the fault detection method as described in claims 6 to 8.