Multi-channel sampling circuit and multi-channel sampling method

Abstract

The invention relates to a multi-channel sampling circuit and a multi-channel sampling method.The circuit comprises a controller, a comparator, a first capacitor array and a second capacitor array, the first capacitor array comprises a first reset switch, first capacitors and first sampling switches in one-to-one correspondence with the first capacitors, and the second capacitor array comprises a second reset switch and second sampling switches in one-to-one correspondence with the second capacitors; the second capacitor array comprises a second reset switch, second capacitors and second sampling switches in one-to-one correspondence with the second capacitors, a capacitor top plate of the first capacitor is connected with the first reset switch and the input end of the comparator, and a capacitor bottom plate of the first capacitor is connected with the first sampling switch; a capacitor top plate of the second capacitor is connected with the second reset switch and the input end of the comparator, a capacitor bottom plate of the second capacitor is connected with the second sampling switch, the output end of the comparator is connected with the controller, and the controller is used for controlling the first reset switch, the second reset switch, the first sampling switch and the second sampling switch. The technical problems of high circuit complexity, large chip area and high chip power consumption in the prior art can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal sampling, in particular to a multi-channel sampling circuit and a multi-channel sampling method. BACKGROUND

[0002] In the field of precision analog-to-digital conversion, the successive approximation register (SAR) architecture can achieve high energy-efficient conversion by virtue of the switched-capacitor DAC and binary search mechanism, and becomes the core element of a multi-channel acquisition system. The key processes include a sampling period (input signal is stored in a capacitor array) and a conversion period (digital code is output by successive comparison). In the face of multi-channel signal processing requirements, the technical problem of multiplexing multiple input channels by a single ADC core needs to be solved.

[0003] Existing solutions mainly adopt two paths: one is to use a front-end analog multiplexer (MUX) in series with a shared ADC core. This method relies on independent sample-and-hold circuits to drive the capacitor array, resulting in the need for a high-bandwidth amplifier for each channel, which significantly increases power consumption and chip area; at the same time, charge injection and signal crosstalk during analog switch switching will degrade the isolation between multiple channels, and high-frequency switching will also disturb the stability of the reference voltage network. The second is to configure an independent ADC core (including a dedicated capacitor DAC and a comparator) for each channel. This solution avoids interference between channels, but the repeated layout of the capacitor array causes the chip area to multiply with the number of channels and the resolution, especially the large-size capacitor units required for high-precision conversion, which becomes an area problem; the coexistence of multiple comparators and calibration circuits also leads to linear growth of static power consumption, making it difficult to meet the needs of low-power scenarios. SUMMARY

[0004] In view of the above, it is necessary to provide a multi-channel sampling circuit and a multi-channel sampling method, which can reduce the technical problems of high circuit complexity, large chip area and high chip power consumption in the prior art.

[0005] The present application first provides a multi-channel sampling circuit, which comprises a controller, a comparator, a first capacitor array and a second capacitor array. The first capacitor array comprises a first reset switch, a plurality of first capacitors and a plurality of first sampling switches corresponding to the first capacitors one by one. The second capacitor array comprises a second reset switch, a plurality of second capacitors and a plurality of second sampling switches corresponding to the second capacitors one by one. The top plate of the first capacitor is connected to the first reset switch and one input terminal of the comparator, and the bottom plate of the first capacitor is connected to the first sampling switch. The top plate of the second capacitor is connected to the second reset switch and the other input terminal of the comparator, and the bottom plate of the second capacitor is connected to the second sampling switch. The output terminal of the comparator is connected to the controller, and the controller is used to control the first reset switch, the second reset switch, the first sampling switch and the second sampling switch.

[0006] In the multi-channel sampling circuit of this application, a capacitor array structure design (with a reset switch and comparator connected to the top plate and a sampling switch connected to the bottom plate) securely stores the input signal in the capacitors during the sampling phase, avoiding charge injection noise introduced by switch switching. The reset switch can reset the top plate potential to a reference potential (such as common-mode voltage), ensuring consistent initial states for each conversion. This allows for subsequent processing of different channels through successive approximation, eliminating the need for independent comparators or driver amplifiers, reducing power consumption, and improving signal isolation. This enables independent sampling and conversion of multi-channel signals using the same comparator, reducing hardware complexity and chip area.

[0007] In some embodiments, the controller is configured to: control a first sampling switch and a second sampling switch based on a sampling signal to sample the sampling signal onto a first capacitor array and a second capacitor array, respectively; control a first reset switch and a second reset switch based on a reset signal to reset the top plates of the first capacitor and the second capacitor to reference potentials; control a first sampling switch based on a first coupling signal to couple the sampling signal onto the top plate of the first capacitor; control a first reset switch and a first sampling switch based on a reset signal to reset the top plates of the first capacitor and the bottom plates of the first capacitor to reference potentials; and control a second sampling switch based on a second coupling signal to couple the sampling signal onto the top plate of the second capacitor; wherein the sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal, the sampling signal, the first coupling signal, and the second coupling signal have the same pulse width, the first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

[0008] In some embodiments, the controller is further configured to: after coupling the sampling signal to the top plate of the first capacitor, control the first sampling switch to convert the sampling signal into at least one of a reference potential, the maximum value of the reference potential, and the minimum value of the reference potential in a successive approximation manner.

[0009] In some embodiments, the controller is further configured to: after coupling the sampling signal to the top plate of the second capacitor, control the second sampling switch to convert the sampling signal into at least one of a reference potential, the maximum value of the reference potential, and the minimum value of the reference potential in a successive approximation manner.

[0010] In some embodiments, there are multiple first capacitor arrays and multiple second capacitor arrays with the same number as the first capacitor arrays.

[0011] In some embodiments, the first capacitor and / or the second capacitor include a virtual capacitor, which is used to increase the resolution of the sampled signal.

[0012] In some embodiments, the controller is configured to: control the first sampling switch and the second sampling switch based on the sampling signal to sample the sampling signal to the plurality of first capacitor arrays and the plurality of second capacitor arrays respectively; control the first reset switch and the second reset switch based on the reset signal to reset the capacitor top plates of the plurality of first capacitors and the capacitor top plates of the plurality of second capacitors to the reference potential; control the first sampling switch of one of the plurality of first capacitor arrays based on the first coupling signal to couple the sampling signal to the capacitor top plate of the first capacitor accordingly; control the first reset switch and the first sampling switch based on the reset signal to reset the capacitor top plate of the first capacitor and the capacitor bottom plate of the first capacitor to the reference potential accordingly; control the first reset switch and the first sampling switch based on the plurality of first coupling signals and the reset signal in sequence to complete the coupling of the sampling signal to the capacitor top plates of the remaining first capacitor arrays and the reset of the capacitor top plates and the capacitor bottom plates accordingly; control the second sampling switch of one of the plurality of second capacitor arrays based on the second coupling signal to couple the sampling signal to the capacitor top plate of the second capacitor accordingly; control the second reset switch and the second sampling switch based on the reset signal to reset the capacitor top plate of the second capacitor and the capacitor bottom plate of the second capacitor to the reference potential accordingly; control the second reset switch and the second sampling switch based on the plurality of second coupling signals and the reset signal in sequence to complete the coupling of the sampling signal to the capacitor top plates of the remaining second capacitor arrays and the reset of the capacitor top plates and the capacitor bottom plates accordingly; wherein the period of the sampling signal, the first coupling signal and the second coupling signal is the same and is a preset multiple of the period of the reset signal, the pulse width of the sampling signal, the first coupling signal and the second coupling signal is the same, the first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

[0013] In some embodiments, after the sampling signal is coupled to the capacitor top plate of the first capacitor, the first sampling switch is controlled by a successive approximation method to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the decay value of the maximum value of the reference potential, and the decay value of the minimum value of the reference potential, wherein the decay value is related to the number of the first capacitor array and the second capacitor array.

[0014] In some embodiments, after the sampling signal is coupled to the capacitor top plate of the second capacitor, the second sampling switch is controlled by a successive approximation method to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the decay value of the maximum value of the reference potential, and the decay value of the minimum value of the reference potential, wherein the decay value is related to the number of the second capacitor array and the second capacitor array.

[0015] In some embodiments, the controller is configured to: control the first sampling switch and the second sampling switch based on the sampling signal to sample the sampling signal to the plurality of first capacitor arrays and the plurality of second capacitor arrays respectively; control the first reset switch and the second reset switch based on the reset signal to reset the capacitor top plates of the plurality of first capacitors and the capacitor top plates of the plurality of second capacitors to the reference potential; control the first sampling switch of one of the plurality of first capacitor arrays and the second sampling switch of one of the plurality of second capacitor arrays based on the coupling signal to couple the sampling signal to the capacitor top plate of the first capacitor and to the capacitor top plate of the second capacitor respectively; control the first reset switch, the first sampling switch and the second sampling switch based on the reset signal to reset the capacitor top plate of the first capacitor and the capacitor bottom plate of the first capacitor to the reference potential and to reset the capacitor top plate of the second capacitor and the capacitor bottom plate of the second capacitor to the reference potential respectively; and control the first reset switch and the first sampling switch based on the plurality of coupling signals and the reset signal in turn to complete the coupling of the sampling signal to the capacitor top plates of the remaining first capacitor arrays and the reset of the capacitor top plates and the capacitor bottom plates respectively; wherein the period of the sampling signal and the coupling signal is the same and is a preset multiple of the period of the reset signal, the pulse width of the sampling signal and the coupling signal is the same, and the coupling signal lags behind the sampling signal by n or n+2 pulse widths.

[0016] In some embodiments, after the sampling signal is coupled to the capacitor top plates of the first capacitors and the capacitor top plates of the second capacitors, the first sampling switch and the second sampling switch are controlled in turn to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the decay value of the maximum value of the reference potential and the decay value of the minimum value of the reference potential by a successive approximation method, wherein the decay value is related to the number of the first capacitor arrays and the second capacitor arrays.

[0017] The application also provides a multi-channel sampling method, which is executed by the multi-channel sampling circuit of any one of the above embodiments of the application, and the method comprises: controlling the first sampling switch and the second sampling switch based on a sampling signal, so as to sample the sampling signal to the first capacitor array and the second capacitor array respectively; controlling the first reset switch and the second reset switch based on a reset signal, so as to reset the capacitor top plate of the first capacitor and the capacitor top plate of the second capacitor to a reference potential; controlling the first sampling switch based on a first coupling signal, so as to couple the sampling signal to the capacitor top plate of the first capacitor; controlling the first reset switch and the first sampling switch based on the reset signal, so as to reset the capacitor top plate of the first capacitor and the capacitor bottom plate of the first capacitor to the reference potential; and controlling the second sampling switch based on a second coupling signal, so as to couple the sampling signal to the capacitor top plate of the second capacitor; wherein the period of the sampling signal, the first coupling signal and the second coupling signal is the same and is a preset multiple of the period of the reset signal, the pulse width of the sampling signal, the first coupling signal and the second coupling signal is the same, the first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a circuit diagram of a multi-channel sampling circuit according to an embodiment of the application.

[0019] Figure 2 FIG. 2 is a pulse waveform diagram of control signals according to the embodiment of the application.

[0020] Figure 3 FIG. 3 is a schematic diagram of a part of a signal sampling process of the multi-channel sampling circuit according to the embodiment of the application.

[0021] Figure 4 FIG. 4 is a schematic diagram of a conversion result of a first sampling channel according to the embodiment of the application.

[0022] Figure 5 FIG. 5 is a schematic diagram of another part of a signal sampling process of the multi-channel sampling circuit according to the embodiment of the application.

[0023] Figure 6 FIG. 6 is a schematic diagram of a conversion result of a second sampling channel according to the embodiment of the application.

[0024] Figure 7 FIG. 7 is a schematic diagram of a conversion result of a first sampling channel of 3 bits by a successive approximation method according to the embodiment of the application.

[0025] Figure 8 FIG. 8 is a circuit diagram of a multi-channel sampling circuit according to another embodiment of the application.

[0026] Figure 9 FIG. 9 is a signal attenuation diagram of the multi-channel sampling circuit according to the embodiment of the application.

[0027] Figure 10 is a pulse waveform diagram of the control signal of Embodiment Two of the present application.

[0028] Figure 11 is a diagram of a partial signal sampling process of the multi-channel sampling circuit of Embodiment Two of the present application.

[0029] Figure 12 is a diagram of another partial signal sampling process of the multi-channel sampling circuit of Embodiment Two of the present application.

[0030] Figure 13 is a flow chart of the multi-channel sampling method of the present application.

[0031] Main element symbol explanation 1, multi-channel sampling circuit; 11, controller; 12, comparator; 13, first capacitor array; 14, second capacitor array; 131, first reset switch; 132, first capacitor; 133, first sampling switch; 141, second reset switch; 142, second capacitor; 143, second sampling switch.

[0032] The following detailed description will further describe the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] In the description of the embodiments of the present application, the words "exemplary", "or", "for example" are used to mean example, illustration, or description. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or having more advantages than other embodiments or design solutions. Rather, the use of "exemplary", "or", "for example" is intended to present the relevant concept in a specific manner.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It should be understood that, in the present application, unless otherwise specified, " / " means or. For example, A / B can mean A or B. "And / or" in the present application is only a description of the relationship between the associated objects, which means that there can be three relationships. For example, A and / or B can mean: A alone, A and B together, B alone. "At least one" means one or more. "Multiple" means two or more. For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c, a, b and c seven cases.

[0035] In addition, it should be noted that the terms "first", "second" in the specification and claims of the present application and the drawings are used to distinguish similar objects, and are not used to describe a specific order or sequence. The method disclosed in the embodiments of the present application or the method shown in the flowchart includes one or more steps for implementing the method, and the execution order of the multiple steps can be interchanged with each other without departing from the scope of the claims, and some steps can also be deleted.

[0036] In the field of analog-to-digital conversion, successive approximation converter has become the mainstream architecture in medium and high precision applications due to its simple structure and outstanding energy efficiency. Its core working principle includes two stages of sampling and conversion: in the sampling stage, the input signal is captured on the internal capacitor digital-to-analog converter array through the switching network; in the conversion stage, the binary search algorithm is used to drive the switching to make the comparison voltage generated by the capacitor array gradually approach the sampled input value, and finally output the corresponding digital code. With the increasing demand for multi-channel signal acquisition of the system, how to efficiently realize multi-channel multiplexing on a single SAR-ADC becomes a key problem.

[0037] There are mainly two directions in the prior art to realize multi-channel input. One is to configure independent sampling and holding circuits and analog multiplexers (MUXs) at the front end of each analog input channel, and then select the signals to be connected to the shared single-channel ADC core for conversion. This scheme has a direct structure, but has significant limitations: the pre-sampling circuit of each channel usually needs a high-bandwidth amplifier to drive the capacitive load (especially the switched-capacitor DAC network), which significantly increases the overall area and power consumption of the system; the crosstalk and charge injection effects introduced by the analog switch during switching will reduce the isolation between the multi-channel signals; high-frequency multi-channel switching will also exacerbate the load fluctuation of the reference voltage network, affecting the conversion linearity.

[0038] The second is to integrate multiple complete SAR-ADC cores (such as an independent capacitor DAC and comparator for each channel) in a single chip, and only share the digital control logic between channels. Although it can work in parallel, has good channel isolation and low delay, the repeated configuration of a large number of capacitor arrays leads to a multiple increase in chip area, especially when implementing high resolution (such as >14 bits), the area cost of large-size capacitor units is more prominent. In addition, each ADC core needs to be configured with a dedicated comparator and calibration circuit, and the static power consumption increases synchronously with the number of channels, which directly conflicts with the demand for low power consumption of portable devices.

[0039] Therefore, the embodiments of the present application provide a multi-channel sampling circuit and a multi-channel sampling method, which can reduce the technical problems of high circuit complexity, large chip area and high chip power consumption in the prior art. Some embodiments will be described below with reference to the accompanying drawings. In the case of no conflict, the embodiments described below and the features in the embodiments can be combined with each other.

[0040] Example 1 Figure 1 This is a circuit diagram of the multi-channel sampling circuit 1 according to Embodiment 1 of this application. The dashed lines with arrows indicate signal control; VIN1 is the voltage of the first sampling channel corresponding to the first capacitor array 13; VIN2 is the voltage of the second sampling channel corresponding to the second capacitor array 14; and VCM is the reference potential.

[0041] Please see Figure 1 This application first provides a multi-channel sampling circuit 1. The multi-channel sampling circuit 1 may include a controller 11 (also called "SAR controller 11"), a comparator 12, a first capacitor array 13, and a second capacitor array 14. The first capacitor array 13 includes a first reset switch 131, a plurality of first capacitors 132, and a plurality of first sampling switches 133 corresponding one-to-one with the first capacitors 132. The second capacitor array 14 includes a second reset switch 141, a plurality of second capacitors 142, and a plurality of second sampling switches 143 corresponding one-to-one with the second capacitors 142. The top plate of capacitor 132 is connected to the first reset switch 131 and one input terminal of comparator 12. The bottom plate of capacitor 132 is connected to the first sampling switch 133. The top plate of capacitor 142 is connected to the second reset switch 141 and the other input terminal of comparator 12. The bottom plate of capacitor 142 is connected to the second sampling switch 143. The output terminal of comparator 12 is connected to controller 11. Controller 11 is used to control the first reset switch 131, the second reset switch 141, the first sampling switch 133, and the second sampling switch 143.

[0042] Here, "one-to-one correspondence" can mean that the quantity is consistent and one capacitor can be connected to one sampling switch. "Capacitor bottom plate" can refer to the plate through which the sampling signal first passes, i.e., the plate connected to the sampling switch, and "capacitor top plate" can refer to the plate through which the sampling signal last passes, i.e., the plate connected to comparator 12. Additionally, it can be understood that... Figure 1 The number of the first capacitor 132, the second capacitor 142, the first sampling switch 133, or the second sampling switch 143 is 3 for the sake of easy illustration, but in reality there can be more.

[0043] In some embodiments, the input of comparator 12 can be inverted via controller 11. Specifically, the top plate of the first capacitor 132 can be connected to either the first reset switch 131 and the non-inverting input of comparator 12, or vice versa. Similarly, the top plate of the second capacitor 142 can be connected to either the second reset switch 141 and the non-inverting input of comparator 12, or vice versa. Furthermore, when the top plate of the first capacitor 132 is connected to the non-inverting input of comparator 12, the top plate of the second capacitor 142 is connected to the inverting input of comparator 12; conversely, when the top plate of the first capacitor 132 is connected to the inverting input of comparator 12, the top plate of the second capacitor 142 is connected to the non-inverting input of comparator 12.

[0044] In the multi-channel sampling circuit 1 of this application, through the structural design of a capacitor array (the top plate connects to the reset switch and comparator 12, and the bottom plate connects to the sampling switch), the input signal is safely stored in the capacitors during the sampling stage, avoiding charge injection noise introduced by switch switching. The reset switch can reset the top plate potential to the reference potential (such as common-mode voltage), ensuring that the initial state of each conversion is consistent. This allows subsequent processing of different channels by successive approximation without the need for a separate comparator 12 or driver amplifier, reducing power consumption and improving signal isolation. Thus, independent sampling and conversion of multi-channel signals can be achieved by sharing the same comparator 12, reducing hardware complexity and chip area.

[0045] Figure 2 This is a schematic diagram of the pulse waveform of the control signal in Embodiment 1 of this application. Figure 3 This is a schematic diagram of a portion of the signal sampling process of the multi-channel sampling circuit 1 in Embodiment 1 of this application. Figure 4 This is a schematic diagram of the conversion result of the first sampling channel in Embodiment 1 of this application. Figure 5 This is a schematic diagram of another part of the signal sampling process of the multi-channel sampling circuit 1 in this application embodiment. Figure 6 This is a schematic diagram of the conversion result of the second sampling channel in Embodiment 1 of this application. Wherein, CK_GS is the sampling signal, CK_RST is the reset signal, CK_H1 is the first coupling signal, CK_H2 is the second coupling signal, MSB is the most significant bit, MSB-1 is the next significant bit, LSB is the least significant bit, Cd is the virtual bit, VRP is the maximum value of the reference potential, VRN is the minimum value of the reference potential, and VREF is VCM.

[0046] In some embodiments, please refer to Figures 2 to 6The controller 11 can be configured to: control the first sampling switch 133 and the second sampling switch 143 based on the sampling signal to sample the sampling signal onto the first capacitor array 13 and the second capacitor array 14, respectively; control the first reset switch 131 and the second reset switch 141 based on the reset signal to reset the top plates of the first capacitor 132 and the second capacitor 142 to reference potentials; and control the first sampling switch 133 based on the first coupling signal to couple the sampling signal onto the top plate of the first capacitor 132 (i.e., the first sampling switch 133) Figure 3 (As shown). Furthermore, the controller 11 can also be configured to: control the first reset switch 131 and the first sampling switch 133 based on a reset signal to reset the top plate and bottom plate of the first capacitor 132 to a reference potential; and control the second sampling switch 143 based on a second coupling signal to couple the sampling signal to the top plate of the second capacitor 142 (i.e.,...). Figure 6 (As shown).

[0047] Continue to refer to Figure 2 As shown, the sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal, the first coupling signal, and the second coupling signal have the same pulse width. The first coupling signal lags behind the sampling signal by n (n is a positive integer, such as n can be equal to 1) pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

[0048] In the embodiments of this application, a strict delay design of the signals (such as a larger lag in the second signal) allows the second array to be started only after the first capacitor array 13 has completed its operation. For example, the reset phase is completed before coupling, reducing errors caused by charge sharing. Timing control can reduce overshoot or noise accumulation during multi-channel switching and enhance conversion stability. This ensures precise synchronization and time isolation of multi-channel operation and reduces crosstalk between signals.

[0049] Figure 7 This is a schematic diagram showing the result of converting the 3-bit first sampling channel of Embodiment 1 of this application through a successive approximation method.

[0050] In some embodiments, the controller 11 is further configured to: after coupling the sampling signal to the top plate of the first capacitor 132, control the first sampling switch 133 to convert the sampling signal into at least one of a reference potential, the maximum value of the reference potential, and the minimum value of the reference potential in a successive approximation manner (i.e., ... Figure 4(As shown). In this case, by switching the base plate voltage (e.g., connecting to ground or positive / negative reference voltage) via a sampling switch, the top plate potential is changed, causing comparator 12 to compare its difference with the reference potential (e.g., VCM). The successive approximation algorithm iteratively adjusts the switch state, gradually approximating the analog value to the digital code, simplifying the conversion process and reducing dynamic power consumption. This allows for efficient signal digitization without additional comparator 12 hardware.

[0051] Specifically, please refer to Figure 7 Taking the first 3-bit sampling channel as an example, the conversion results through successive approximation can be: VRP\VRP\VCM, VRP\VRN\VCM, VRN\VRN\VCM, and VRN\VRP\VCM. Virtual bits do not need to be converted.

[0052] In some embodiments, the controller 11 is further configured to: after coupling the sampling signal to the top plate of the second capacitor 142, control the second sampling switch 143 to convert the sampling signal into at least one of a reference potential, the maximum value of the reference potential, and the minimum value of the reference potential in a successive approximation manner (i.e., Figure 6 (As shown). In this case, based on the voltage switching of the sampling switch, a variable potential is generated on the top plate for comparator 12 to make decisions. By reusing the same comparator 12 and approximation logic, resource conflicts between channels are reduced, and the overall system efficiency is improved. This ensures symmetrical processing of the second channel and maintains the consistency of multi-channel performance.

[0053] It is understandable that the conversion method for the second sampling channel is similar to that for the first sampling channel, so please refer to [the relevant documentation]. Figure 7 Similarly, taking 3 bits as an example, the result of successive approximation conversion can also be: VRP\VRP\VCM, VRP\VRN\VCM, VRN\VRN\VCM, and VRN\VRP\VCM. Virtual bits do not need to be converted.

[0054] Example 2 Figure 8 This is a circuit diagram of the multi-channel sampling circuit 1 according to Embodiment 2 of this application. The difference between Embodiment 2 and Embodiment 1 is as follows: There are multiple first capacitor arrays 13 and multiple second capacitor arrays 14, with the same number as the first capacitor arrays 13. Multiple first capacitor arrays 13 can share a first reset switch 131, and multiple second capacitor arrays 14 can share a second reset switch 141. For example, as shown in Figure 000, there can be two first capacitor arrays 13, namely first capacitor array 13a and first capacitor array 13b, which can share the first reset switch 131. Similarly, there can be two second capacitor arrays 14, namely second capacitor array 14a and second capacitor array 14b, which can share the second reset switch 141. In this case, by managing multiple channels in array groups, each group can independently store and convert signals while sharing the resources of the controller 11. The matching of the number of arrays optimizes timing scheduling, ensures the scalability of parallel processing, and reduces area overhead. That is, more channel inputs can be supported through array multiplexing without multiplying the comparators 12 or switch networks.

[0055] Furthermore, it is understandable. Figure 8 The number of the first capacitor array 13 and the second capacitor array 14 is shown as two for ease of illustration, but in reality, there can be more. Specifically, the first sampling channel corresponds to the first capacitor array 13a, the second sampling channel corresponds to the first capacitor array 13b, the third sampling channel corresponds to the second capacitor array 14a, and the fourth sampling channel corresponds to the second capacitor array 14b.

[0056] Figure 9 This is a schematic diagram of signal attenuation in the multi-channel sampling circuit 1 of Embodiment 2 of this application.

[0057] In some embodiments, the first capacitor 132 and / or the second capacitor 142 include virtual capacitors, which are used to increase the resolution of the sampled signal. In this case, the virtual capacitors serve as auxiliary units, enhancing the dynamic range of the capacitor array through binary weighting; during the sampling phase, the virtual capacitors balance the charge distribution, reducing nonlinear distortion and thus improving the overall accuracy of the SAR conversion. This can improve the accuracy and linearity of signal sampling and compensate for capacitor matching errors.

[0058] Specifically, please refer to Figure 9 Due to the charge sharing effect, the input voltage VIN will decay to VIN / 2 (i.e., VRP×3 / 4-VRP / 4), which causes the effective search range of the MSB array to decay to (VRP-VRN) / 2 accordingly. In order to overcome the problem caused by the signal range decay, the virtual capacitor (Cd) is switched from the common mode voltage VCM to VRP×3 / 4 or VRP×1 / 4 to obtain an additional 1 bit of precision.

[0059] Figure 10This is a schematic diagram of the pulse waveform of the control signal in Embodiment 2 of this application. Figure 11 This is a schematic diagram of a portion of the signal sampling process of the multi-channel sampling circuit 1 in Embodiment 2 of this application. Wherein, CK_GS is the sampling signal, CK_RST is the reset signal, CK_H1 is the first first coupling signal, CK_H2 is the second first coupling signal, CK_H3 is the first second coupling signal, and CK_H4 is the second second coupling signal.

[0060] In the embodiments of this application, the signal sampling process of Embodiment 2 can be the same as or similar to that of Embodiment 1. For example, the sampling process of Embodiment 1 can be referred to for the four sampling channels (VIN1 to VIN4), and further reference can be made to [the relevant documentation]. Figure 11 The sampling and conversion are performed sequentially through multiple first coupling signals and multiple second coupling signals. That is, controller 11 can be configured as follows: Based on the sampling signal, the first sampling switch 133 and the second sampling switch 143 are controlled to sample the sampling signal onto multiple first capacitor arrays 13 and multiple second capacitor arrays 14, respectively; based on the reset signal, the first reset switch 131 and the second reset switch 141 are controlled to reset the top plates of multiple first capacitors 132 and multiple second capacitors 142 to reference potentials; based on the first coupling signal, the first sampling switch 133 of one of the multiple first capacitor arrays 13 is controlled to couple the sampling signal to the top plate of the first capacitor 132 accordingly; based on the reset signal, the first reset switch 131 and the first sampling switch 133 are controlled accordingly to reset the top plate of the first capacitor 132 and the bottom plate of the first capacitor 132 to reference potentials; and so on, based on the multiple first coupling signals and the reset signal, the first sampling switch 133 is controlled to sample the sampling signal onto the top plate of the first capacitor 132, respectively, onto the top plate of the first capacitor 132 and the bottom plate of the first capacitor 132, respectively, onto reference potentials; and so on, based on the multiple first coupling signals and the reset signal, the first sampling switch 133 is controlled to sample the sampling signal onto the top plate of the first capacitor 132 and the bottom plate of the first capacitor 132, respectively, ... The system controls a first reset switch 131 and a first sampling switch 133 to correspondingly couple the sampling signals of the top plates of the remaining first capacitor array 13 and reset the top and bottom plates of the capacitors. Based on a second coupling signal, it controls a second sampling switch 143 of one of the multiple second capacitor arrays 14 to correspondingly couple the sampling signal to the top plate of the second capacitor 142. Based on a reset signal, it controls a second reset switch 141 and a second sampling switch 143 to reset the top and bottom plates of the second capacitor 142 to reference potentials. Sequentially, based on multiple second coupling signals and a reset signal, it controls a second reset switch 141 and a second sampling switch 143 to correspondingly couple the sampling signals of the top plates of the remaining second capacitor array 14 and reset the top and bottom plates of the capacitors.

[0061] Please refer to Figure 10The sampling signal, the first coupling signal (such as CK_H1, CK_H2) and the second coupling signal (such as CK_H3, CK_H4) have the same period and are a preset multiple of the period of the reset signal. The sampling signal, the first coupling signal and the second coupling signal have the same pulse width. The first coupling signal lags the sampling signal by n (n is a positive integer) pulse widths, and the second coupling signal lags the sampling signal by n+2 pulse widths.

[0062] By using inter-array coupling and step-by-step reset operations (e.g., processing the second capacitor array 14 after the first capacitor array 13 is completed), and utilizing time lag to ensure complete charge reset before initiating the next operation, this sequence control can reduce signal coupling when multiple arrays are active simultaneously, improving isolation and conversion reliability. This maximizes the isolation of multi-channel operations and reduces the risk of cross-interference.

[0063] In some embodiments, similarly referring to Embodiment 1 above, after the sampling signal is coupled to the top plate of the first capacitor 132, the first sampling switch 133 is controlled in a successive approximation manner to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, an attenuated value of the maximum value of the reference potential, and an attenuated value of the minimum value of the reference potential, wherein the attenuation value is related to the number of the first capacitor array 13 and the second capacitor array 14. In this case, when the number of arrays increases, the single sampling amplitude may be overloaded; by adjusting the conversion range by an adjustable attenuation factor (such as scaling the reference voltage), the input of the comparator 12 is kept in the effective range, reducing saturation error and ensuring resolution consistency. This allows for signal amplitude scaling in multi-array systems while maintaining conversion accuracy.

[0064] In some embodiments, similarly referring to Embodiment 1 above, after the sampling signal is coupled to the top plate of the second capacitor 142, the second sampling switch 143 is controlled in a successive approximation manner to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, an attenuated value of the maximum value of the reference potential, and an attenuated value of the minimum value of the reference potential, wherein the attenuation value is related to the number of the second capacitor array 14. In this case, the attenuation value corresponds to the array configuration, optimizes the dynamic range, and ensures the uniformity of multi-channel results. This ensures that the signal processing of the second array matches the system scaling, reducing the accuracy loss caused by the increase in the number of arrays.

[0065] Figure 12This is a schematic diagram of another sampling process of a portion of the signals in the multi-channel sampling circuit 1 of Embodiment 2 of this application. Wherein, CK_GS is the sampling signal, CK_RST is the reset signal, CK_H1 is the first coupling signal, and CK_H2 is the second coupling signal. VIN1 and VIP1 are a pair of differential channels that undergo sampling conversion via the first coupling signal, and VIN2 and VIP2 are another pair of differential channels that undergo sampling conversion via the second coupling signal.

[0066] In the embodiments of this application, the signal sampling process of Embodiment 2 can be the same as or similar to that of Embodiment 1. For example, the four sampling channels (VIN1, VIP1, VIN2, and VIP2) can be sampled and converted sequentially through the first coupling signal and the second coupling signal, referring to the sampling process of Embodiment 1 described above. Please refer to... Figure 12 The first coupling signal controls VIN1 and VIP1 simultaneously, and the second coupling signal controls VIN2 and VIP2 simultaneously. That is, controller 11 can be configured as follows: Based on the sampling signal, the first sampling switch 133 and the second sampling switch 143 are controlled to sample the sampling signal onto multiple first capacitor arrays 13 and multiple second capacitor arrays 14, respectively; based on the reset signal, the first reset switch 131 and the second reset switch 141 are controlled to reset the top plates of the multiple first capacitors 132 and the multiple second capacitors 142 to reference potentials; based on the coupling signal, the first sampling switch 133 of one of the multiple first capacitor arrays 13 and the second sampling switch 143 of one of the multiple second capacitor arrays 14 are controlled to couple the sampling signal to the voltage of the first capacitor 132 accordingly. The capacitor top plate and the capacitor top plate that couples the sampling signal to the second capacitor 142 accordingly; based on the reset signal, the first reset switch 131, the first sampling switch 133 and the second sampling switch 143 are controlled accordingly to reset the capacitor top plate and the capacitor bottom plate of the first capacitor 132 to the reference potential and to reset the capacitor top plate and the capacitor bottom plate of the second capacitor 142 to the reference potential; based on multiple coupling signals and the reset signal, the first reset switch 131 and the first sampling switch 133 are controlled accordingly to complete the sampling signal coupling of the capacitor top plate of the remaining first capacitor array 13 and the reset of the capacitor top plate and the capacitor bottom plate.

[0067] Please refer to Figure 10The sampling signal and the coupling signal (first coupling signal and second coupling signal) have the same period, which is a preset multiple of the period of the reset signal. The pulse widths of the sampling signal and the coupling signal are the same, and the coupling signal lags the sampling signal by n or n+2 pulse widths. In this case, some parallel logic (such as simultaneously activating the sampling switch) is executed by sharing the coupling signal, followed by serialized reset. This hybrid mode balances parallel efficiency and timing constraints (signal lag design) and reduces multi-channel conflicts. This can improve processing speed and reduce the total conversion time while maintaining isolation.

[0068] In some embodiments, similarly, after coupling the sampled signal to the top plates of the first capacitor 132 and the second capacitor 142, the first sampling switch 133 and the second sampling switch 143 are controlled accordingly in a successive approximation manner to convert the sampled signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, an attenuated value of the maximum value of the reference potential, and an attenuated value of the minimum value of the reference potential, wherein the attenuation value is related to the number of the first capacitor array 13 and the second capacitor array 14. In this case, the attenuation value is adapted to the system scale, reducing the input overload of the comparator 12, maintaining resolution, and thus compensating for signal scaling related to the number of arrays in partially parallel operation, thereby improving accuracy.

[0069] Figure 13 This is a flowchart of a multi-channel sampling method according to an embodiment of this application.

[0070] This application also provides a multi-channel sampling method, executed by the multi-channel sampling circuit of any of the above embodiments of this application. Please refer to [link to relevant documentation]. Figure 13 The methods may include: Step S100: Control the first sampling switch and the second sampling switch based on the sampling signal to sample the sampling signal onto the first capacitor array and the second capacitor array respectively.

[0071] Step S200: Control the first reset switch and the second reset switch based on the reset signal to reset the top plates of the first capacitor and the second capacitor to the reference potential.

[0072] Step S300: Control the first sampling switch based on the first coupling signal to couple the sampling signal to the top plate of the first capacitor.

[0073] Step S400: Control the first reset switch and the first sampling switch based on the reset signal to reset the top plate and bottom plate of the first capacitor to the reference potential.

[0074] Step S500: Control the second sampling switch based on the second coupling signal to couple the sampling signal to the top plate of the second capacitor.

[0075] The sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal, the first coupling signal, and the second coupling signal have the same pulse width. The first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

[0076] The multi-channel sampling method of this application can perform operations step by step based on timing logic (such as hysteresis delay), ensuring strict isolation between the sampling, reset and coupling stages and reducing the impact of switching transients; this method can enhance the robustness of the entire SAR process and does not require complex analog circuits to support multi-channel management.

[0077] In addition, the sampling method of this application embodiment may also include more control processes, and you can refer to the configuration content of the controller in the above embodiment 1 and embodiment 2.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A multi-channel sampling circuit, characterized in that, The system includes a controller, a comparator, a first capacitor array, and a second capacitor array. The first capacitor array includes a first reset switch, multiple first capacitors, and multiple first sampling switches corresponding to each of the first capacitors. The second capacitor array includes a second reset switch, multiple second capacitors, and multiple second sampling switches corresponding to each of the second capacitors. The top plate of each first capacitor is connected to the first reset switch and one input terminal of the comparator, and the bottom plate of the first capacitor is connected to the first sampling switch. The top plate of each second capacitor is connected to the second reset switch and the other input terminal of the comparator, and the bottom plate of the second capacitor is connected to the second sampling switch. The output terminal of the comparator is connected to the controller, which controls the first reset switch, the second reset switch, the first sampling switch, and the second sampling switch.

2. The multi-channel sampling circuit according to claim 1, characterized in that, The controller is configured as follows: The first sampling switch and the second sampling switch are controlled based on the sampling signal to sample the sampling signal onto the first capacitor array and the second capacitor array, respectively. The first reset switch and the second reset switch are controlled based on the reset signal to reset the top plates of the first capacitor and the second capacitor to the reference potential. The first sampling switch is controlled based on the first coupling signal to couple the sampling signal to the top plate of the first capacitor; Based on the reset signal, the first reset switch and the first sampling switch are controlled to reset the top plate and the bottom plate of the first capacitor to the reference potential. The second sampling switch is controlled based on the second coupling signal to couple the sampling signal to the top plate of the second capacitor; The sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal, the first coupling signal, and the second coupling signal have the same pulse width. The first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

3. The multi-channel sampling circuit according to claim 2, characterized in that, The controller is also configured to: After the sampling signal is coupled to the top plate of the first capacitor, the first sampling switch is controlled in a successive approximation manner to convert the sampling signal into at least one of the reference potential, the maximum value of the reference potential, and the minimum value of the reference potential.

4. The multi-channel sampling circuit according to claim 2, characterized in that, The controller is also configured to: After the sampling signal is coupled to the top plate of the second capacitor, the second sampling switch is controlled in a successive approximation manner to convert the sampling signal into at least one of the reference potential, the maximum value of the reference potential, and the minimum value of the reference potential.

5. The multi-channel sampling circuit according to claim 1, characterized in that, There are multiple first capacitor arrays and multiple second capacitor arrays, with the same number as the first capacitor arrays.

6. The multi-channel sampling circuit according to claim 5, characterized in that, The first capacitor and / or the second capacitor include a virtual capacitor, which is used to increase the resolution of the sampled signal.

7. The multi-channel sampling circuit according to claim 6, characterized in that, The controller is configured as follows: The first sampling switch and the second sampling switch are controlled based on the sampling signal to sample the sampling signal onto multiple first capacitor arrays and multiple second capacitor arrays, respectively. The first reset switch and the second reset switch are controlled based on the reset signal to reset the top plates of the first capacitors and the top plates of the second capacitors to the reference potential. The first sampling switch of one of the first capacitor arrays in the plurality of first capacitor arrays is controlled based on the first coupling signal to couple the sampling signal to the top plate of the first capacitor accordingly; Based on the reset signal, the first reset switch and the first sampling switch are controlled accordingly to reset the top plate and the bottom plate of the first capacitor to the reference potential. The first reset switch and the first sampling switch are controlled sequentially based on the multiple first coupling signals and the reset signal, so as to complete the sampling signal coupling of the capacitor top plate of the remaining first capacitor array and the reset of the capacitor top plate and capacitor bottom plate accordingly; The second sampling switch of one of the multiple second capacitor arrays is controlled based on the second coupling signal to couple the sampling signal to the top plate of the second capacitor accordingly; Based on the reset signal, the second reset switch and the second sampling switch are controlled accordingly to reset the top plate and the bottom plate of the second capacitor to the reference potential. The second reset switch and the second sampling switch are controlled sequentially based on the multiple second coupling signals and the reset signal, so as to complete the sampling signal coupling of the capacitor top plate of the remaining second capacitor array and the reset of the capacitor top plate and capacitor bottom plate accordingly; The sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal, the first coupling signal, and the second coupling signal have the same pulse width. The first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

8. The multi-channel sampling circuit according to claim 7, characterized in that, After the sampling signal is coupled to the top plate of the first capacitor, the first sampling switch is controlled to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the attenuation value of the maximum value of the reference potential, and the attenuation value of the minimum value of the reference potential in a successive approximation manner, wherein the attenuation value is related to the number of the first capacitor array and the second capacitor array.

9. The multi-channel sampling circuit according to claim 7, characterized in that, After the sampling signal is coupled to the top plate of the second capacitor, the second sampling switch is controlled in a successive approximation manner to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the attenuation value of the maximum value of the reference potential, and the attenuation value of the minimum value of the reference potential, wherein the attenuation value is related to the second capacitor array and the number of the second capacitor array.

10. The multi-channel sampling circuit according to claim 6, characterized in that, The controller is configured as follows: The first sampling switch and the second sampling switch are controlled based on the sampling signal to sample the sampling signal onto multiple first capacitor arrays and multiple second capacitor arrays, respectively. The first reset switch and the second reset switch are controlled based on the reset signal to reset the top plates of the first capacitors and the top plates of the second capacitors to the reference potential. Based on the coupling signal, control the first sampling switch of one of the first capacitor arrays and the second sampling switch of one of the second capacitor arrays to couple the sampling signal to the top plate of the first capacitor and the top plate of the second capacitor respectively. Based on the reset signal, the first reset switch, the first sampling switch, and the second sampling switch are controlled accordingly to reset the top plate and bottom plate of the first capacitor to the reference potential and the top plate and bottom plate of the second capacitor to the reference potential. The first reset switch and the first sampling switch are controlled sequentially based on the multiple coupling signals and the reset signal, so as to complete the sampling signal coupling of the top plate of the remaining first capacitor array and the reset of the top plate and bottom plate of the capacitor. The sampling signal and the coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal and the coupling signal have the same pulse width, and the coupling signal lags the sampling signal by n or n+2 pulse widths.

11. The multi-channel sampling circuit according to claim 10, characterized in that, After the sampling signal is coupled to the top plates of the first capacitor and the second capacitor, the first sampling switch and the second sampling switch are controlled in a successive approximation manner to convert the sampling signal into at least one of the maximum value of the reference potential, the minimum value of the reference potential, the attenuation value of the maximum value of the reference potential, and the attenuation value of the minimum value of the reference potential, wherein the attenuation value is related to the number of the first capacitor array and the second capacitor array.

12. A multi-channel sampling method, executed by the multi-channel sampling circuit according to any one of claims 1 to 11, characterized in that, include: The first sampling switch and the second sampling switch are controlled based on the sampling signal to sample the sampling signal onto the first capacitor array and the second capacitor array, respectively. The first and second reset switches are controlled based on the reset signal to reset the top plates of the first capacitor and the second capacitor to the reference potential. The first sampling switch is controlled based on the first coupling signal to couple the sampling signal to the top plate of the first capacitor; Based on the reset signal, the first reset switch and the first sampling switch are controlled to reset the top plate and the bottom plate of the first capacitor to the reference potential. The second sampling switch is controlled based on the second coupling signal to couple the sampling signal to the top plate of the second capacitor; The sampling signal, the first coupling signal, and the second coupling signal have the same period and are multiples of the period of the reset signal. The sampling signal, the first coupling signal, and the second coupling signal have the same pulse width. The first coupling signal lags behind the sampling signal by n pulse widths, and the second coupling signal lags behind the sampling signal by n+2 pulse widths.

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