Power MOS device and preparation method thereof

Abstract

The invention discloses a power MOS device and a preparation method thereof, and relates to the technical field of power devices, and the power MOS device comprises an N-type drift layer; the P-type regions are arranged on the two sides of the N-type drift layer; the N-type buffer layer is arranged on the back surface of the N-type drift layer; the substrate is arranged on the back surface of the N-type buffer layer; the drain electrode is arranged on the back surface of the substrate; the P-type well region is arranged on the front surface of the N-type drift layer; the plurality of P + source regions and the plurality of N + source regions are alternately arranged in the P-type well region in the horizontal direction; the two non-adjacent grooves penetrate through the N + source region and the P-type well region in the vertical direction; the insulating medium layers are arranged on the inner walls of the grooves; the gate metal layers are arranged in the grooves; and the source metal layer is arranged on the front surfaces of the P + source region and the N + source region. According to the invention, the two grooves are arranged in the device, so that the current distribution in the formed current channel is uniform, the electric field distribution is concentrated, and the reliability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of power device technology, and in particular to a power MOS device and its fabrication method. Background Technology

[0002] In the field of semiconductor technology, SiCVDMOS devices have been widely used in high breakdown voltage, high temperature and high power electronic devices due to their wide bandgap and high voltage withstand capability.

[0003] However, due to the high critical breakdown electric field strength of SiC material, the voltage per unit thickness increases, resulting in a greater electric field strength inside the device. Furthermore, the structure of SiC VDMOS devices is relatively complex, and the internal electric field distribution is easily affected by various factors. Uneven electric field distribution may lead to excessively high local electric field strength, thereby causing local breakdown, reducing the breakdown voltage and lifespan of the device, and thus affecting the reliability of power MOS devices. Summary of the Invention

[0004] The main objective of this invention is to propose a power MOS device and its fabrication method, aiming to solve the problem that the uneven electric field distribution of existing power MOS devices affects device reliability.

[0005] To achieve the above objectives, embodiments of this application propose a power MOS device, the power MOS device comprising: N-type drift layer; P-type regions are disposed on both sides of the N-type drift layer; An N-type buffer layer is disposed on the back side of the N-type drift layer; A substrate is disposed on the back side of the N-type buffer layer; The drain electrode is disposed on the back side of the substrate; A P-type well region is disposed on the front side of the N-type drift layer; Multiple P+ source regions and multiple N+ source regions are alternately arranged in the horizontal direction inside the P-type well region; Two non-adjacent grooves penetrate the N+ source region and the P-type well region in the vertical direction; An insulating dielectric layer is disposed on the inner wall of each of the grooves; A gate metal layer is disposed in each of the grooves; A source metal layer is disposed on the front side of the P+ source region and the N+ source region.

[0006] In one feasible embodiment, the P-type well region is divided by the groove into: a first P-type well region and a second P-type well region; The first P-type well region is located between each of the grooves; The second P-type well region is located on the side of each groove away from the first P-type well region.

[0007] In one feasible embodiment, the power MOS device further includes: The first P-type shielding layer is disposed on the bottom outer side of each of the grooves and is adjacent to the N-type drift layer; A second P-type shielding layer is disposed between the first P-type well region and the N-type drift layer.

[0008] In one feasible embodiment, the P+ source region includes a first P+ source region and a second P+ source region; The first P+ source region is located on the front side of the first P-type well region; The second P+ source region is located on the front side of the second P-type well region.

[0009] In one feasible embodiment, the source metal layer includes a first source metal layer and a second source metal layer; The first source metal layer is disposed on the front side of the first P+ source region; The second source metal layer is disposed on the front side of the second P+ source region.

[0010] In one feasible embodiment, the doping concentration of the substrate is 2~8e18cm. -3 ; And / or, the doping concentration of the N-type buffer layer is 6~10e17cm. -3 ; And / or, the doping concentration of the N-type drift layer is 1~5e17cm. -3 ; And / or, the doping concentration of the P-type region is 6~10e17cm. -3 ; And / or, the doping concentration of the P-type shielding layer is 6~8e17cm. -3 ; And / or, the doping concentration of the P-type well region is 1~5e16cm. -3 ; And / or, the doping concentration of the P+ source region is 1~5e18cm. -3 ; And / or, the doping concentration of the N+ source region is 2~8e18cm. -3 .

[0011] In one feasible embodiment, the thickness of the substrate is 1 μm; And / or, the thickness of the N-type buffer layer is 500 nm; And / or, the width of the N-type drift layer is 1 μm and the thickness is 30~50 μm; And / or, the width of the P-type region is 2 μm and the thickness is 25~45 μm; And / or, the width of the N+ source region is 500 nm and the thickness is 600 nm; And / or, the maximum width of the insulating dielectric layer is 600 nm and the maximum thickness is 2.1 μm; And / or, the thickness of the source metal layer is 300 nm; And / or, the gate metal layer has a width of 500 nm and a thickness of 2 μm; And / or, the width of the first P-type shielding layer is 600 nm and the thickness is 500 nm; And / or, the width of the second P-type shielding layer is 600 nm and the thickness is 300 nm; And / or, the width of the first P-type well region is 3 μm and the thickness is 1.0~1.6 μm; And / or, the width of the second P-type well region is 0.5~3μm; And / or, the width of the first P+ source region is 2 μm and the thickness is 600 nm; And / or, the width of the second P+ source region is 0.5~2μm and the thickness is 600~900nm; And / or, the width of the first source metal layer is 3 μm; And / or, the width of the second source metal layer is 2 μm.

[0012] In one feasible embodiment, the material of the source metal layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt; The material of the drain electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0013] This application also provides a method for fabricating a power MOS device, the method comprising the following steps: A substrate is provided, and an N-type buffer layer is formed on the front side of the substrate; A first N-type drift layer is formed on the front side of the N-type buffer layer; A first barrier layer pattern is defined on the front side of the first N-type drift layer, ions are injected based on the first barrier layer pattern to form a P-type region, and the first barrier layer pattern is removed. A second N-type drift layer is formed covering the first N-type drift layer; Ions are implanted into the front side of the second N-type drift layer to form a P-type well region; A second barrier layer pattern is defined on the front side of the second N-type drift layer, ions are injected based on the second barrier layer pattern to form an N+ source region, and the second barrier layer pattern is removed. A third barrier layer pattern is defined on the front side of the second N-type drift layer, ions are injected based on the third barrier layer pattern to form a P+ source region, and the third barrier layer pattern is removed. A fourth barrier layer pattern is defined on the front side of the second N-type drift layer, and the N+ source region and the P-type well region are etched based on the fourth barrier layer pattern to form a groove; The inner wall of the groove is oxidized to form an insulating dielectric layer, and the fourth barrier layer pattern is removed; A fifth barrier layer pattern is defined on the front side of the second N-type drift layer, a gate metal layer is deposited based on the fifth barrier layer pattern, and the fifth barrier layer pattern is removed. A sixth barrier layer pattern is defined on the front side of the second N-type drift layer. The P+ source region and the N+ source region are etched based on the sixth barrier layer pattern, and a source metal layer is deposited to form the sixth barrier layer pattern. The sixth barrier layer pattern is then removed.

[0014] In one feasible embodiment, the step of implanting ions on the front side of the second N-type drift layer to form a P-type well region further includes: A seventh barrier layer pattern is defined on the front side of the second drift layer, ions are injected based on the seventh barrier layer pattern to form a P-type shielding layer, and the seventh barrier layer pattern is removed.

[0015] The power MOS device proposed in this application includes: an N-type drift layer; P-type regions disposed on both sides of the N-type drift layer; an N-type buffer layer disposed on the back side of the N-type drift layer; a substrate disposed on the back side of the N-type buffer layer; a drain disposed on the back side of the substrate; a P-type well region disposed on the front side of the N-type drift layer; multiple P+ source regions and multiple N+ source regions alternately disposed horizontally inside the P-type well region; two non-adjacent grooves penetrating the N+ source region and the P-type well region vertically; an insulating dielectric layer disposed on the inner wall of each groove; a gate metal layer disposed in each groove; and a source metal layer disposed on the front side of the P+ source region and the N+ source region. Although power MOS devices have high voltage withstand performance, the uneven electric field distribution caused by the structure can affect the reliability of the device. To effectively solve this problem, this application embodiment constructs two grooves in the device. When a forward bias voltage higher than the threshold voltage is applied to the gate metal layer, the electric field will form a conductive channel on the vertical sidewall of the adjacent P-type well region. This avoids current congestion at surface corners, allowing electrons from various N+ source regions to flow smoothly into the N-type drift layer, preventing excessive local current. Furthermore, the groove provides multiple parallel low-resistance paths to disperse the current, optimizing the current distribution inside the device and ultimately improving the reliability of the power MOS device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the power MOS device provided in this application; Figure 2 This is a schematic diagram of the method for fabricating the power MOS device provided in this application; Figure 3 A schematic diagram of the structure of forming an N-type buffer layer on a substrate provided in this application; Figure 4 A schematic diagram of the structure for forming an N-type drift layer in an N-type buffer layer provided in this application; Figure 5 This is a schematic diagram of the structure used to prepare the P-type region provided in this application; Figure 6 A schematic diagram of the structure provided in this application, showing an N-type drift layer covering a P-type region; Figure 7 This is a schematic diagram of the structure forming the P-type shielding layer provided in this application; Figure 8 This is a schematic diagram of the structure of the P-type well region provided in this application; Figure 9 This application provides a schematic diagram of the structure forming the N+ source region; Figure 10 This application provides a schematic diagram of the structure that forms the P+ source region. Figure 11 A schematic diagram of the structure forming the groove provided in this application; Figure 12 This application provides a schematic diagram of the structure forming the insulating dielectric layer; Figure 13 This is a schematic diagram of the structure for forming the gate metal layer provided in this application; Figure 14 The structural schematic diagram for forming the source metal layer provided in this application Figure 1 ; Figure 15 The structural schematic diagram for forming the source metal layer provided in this application Figure 2 .

[0018] Explanation of icon numbers: 10. N-type drift layer; 10a. First N-type drift layer; 10b. Second N-type drift layer; 101. First barrier layer pattern; 102. Second barrier layer pattern; 103. Third barrier layer pattern; 104. Fourth barrier layer pattern; 105. Fifth barrier layer pattern; 106. Sixth barrier layer pattern; 107. Seventh barrier layer pattern; 11. P-type region; 12. P-type well region; 121. First P-type well region; 122. Second P-type well region ; 13. P+ source region; 131. First P+ source region; 132. Second P+ source region; 14. N+ source region; 15. Trench; 20. N-type buffer layer; 30. Substrate; 40. Drain; 50. Source metal layer; 51. First source metal layer; 52. Second source metal layer; 53. Source trench; 60. Insulating dielectric layer; 70. Gate metal layer; 80. P-type shielding layer; 81. First P-type shielding layer; 82. Second P-type shielding layer.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0023] This invention proposes a power MOS device. (Refer to...) Figure 1 In one embodiment of this application, the power MOS device includes: The structure includes an N-type drift layer 10, a P-type region 11, a P-type well region 12, a P+ source region 13, an N+ source region 14, an N-type buffer layer 20, a substrate 30, a drain 40, a source metal layer 50, an insulating dielectric layer 60, and a gate metal layer 70.

[0024] N-type drift layer 10.

[0025] In one feasible embodiment, the N-type drift layer 10 is a crucial component of the power MOS device, primarily responsible for withstanding the high voltage across the device. It is typically composed of a lightly doped semiconductor material, a design that allows the N-type drift layer 10 to maintain stable electrical performance under high voltage conditions. By precisely controlling the doping concentration and thickness of the N-type drift layer 10, the breakdown voltage of the device can be effectively adjusted, thereby meeting the withstand voltage requirements of different application scenarios.

[0026] P-type region 11 is located on both sides of N-type drift layer 10.

[0027] In one feasible embodiment, P-type regions 11 are provided on both sides of the N-type drift layer 10, forming a columnar structure perpendicular to the N-type drift layer 10, which forms a superjunction with the N-type drift layer 10. Through the principle of charge balance, a transverse electric field is generated in the off state, which improves the withstand voltage and reduces the on-resistance.

[0028] The N-type buffer layer 20 is disposed on the back side of the N-type drift layer 10.

[0029] In one feasible embodiment, the N-type buffer layer 20 forms a buffer structure with a gradually varying doping concentration, thereby improving the quality at the device interface and suppressing reliability issues caused by interface defects in high-voltage applications.

[0030] Optionally, the front and back sides mentioned in the embodiments of this application are two opposite directions, used to indicate the physical orientation of the device and the relative position of the functional layers.

[0031] Optionally, the front side can be the surface corresponding to the first direction of the power MOS device, while the back side can be the opposite of the front side, i.e., the surface away from the first direction.

[0032] Substrate 30 is disposed on the back side of N-type buffer layer 20.

[0033] In one feasible embodiment, the substrate 30 is the core structural element of the power MOS device. It is typically composed of a highly doped semiconductor material, which endows the substrate 30 with superior physical and electrical properties. Physically, the substrate 30 provides robust support for the device, ensuring its structural stability and mechanical strength during complex manufacturing processes and long-term use. Electrically, the substrate 30 plays a crucial isolating role, effectively preventing leakage current and suppressing parasitic effects, thereby ensuring the device's electrical performance remains undisturbed.

[0034] Drain 40 is disposed on the back side of substrate 30.

[0035] In one feasible embodiment, the drain 40 is one of the three main electrodes of the power MOS device. During operation, the drain 40 is typically connected to a high potential and is the end from which current flows out of the device. In power applications, the drain withstands high voltage and current, thus requiring good electrical and thermal performance.

[0036] Optionally, the material of the drain electrode 40 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0037] P-type well region 12 is disposed on the front side of N-type drift layer 10.

[0038] In one feasible embodiment, the P-type well region 12 is P-type doped, meaning it is doped with a trivalent impurity element (such as boron), resulting in a large number of holes as majority carriers in this region. The main function of the P-type well region 12 is to adjust the electrical performance of the device, such as influencing the threshold voltage and channel characteristics. The P-type well region 12 can also form a specific electric field distribution together with other regions, improving the device's breakdown voltage and switching characteristics.

[0039] In one feasible embodiment, the P-type well region 12 is divided by a groove into: a first P-type well region 121 and a second P-type well region 122; The first P-type well region 121 is located between the grooves; The second P-type well region 122 is located on the side of each groove away from the first P-type well region 121.

[0040] In a feasible embodiment, the first P-type well region 121 is located between the grooves and is the main area for forming conductive channels. It can effectively form the gate control structure of the device and form a straight conductive structure from the source to the drain 40 to achieve low resistance control of the device. The second P-type well region 122 is located on the side of each groove away from the first P-type well region 121. It plays an auxiliary role in adjusting the electric field and current distribution. It isolates the cells between the gate and source and can effectively protect the gate metal layer 70 of the device from being broken down by the drain voltage 40.

[0041] Multiple P+ source regions 13 and multiple N+ source regions 14 are alternately arranged in the horizontal direction inside the P-type well region 12.

[0042] In a feasible embodiment, the P+ source region 13 is disposed inside the P-type well region 12, where P+ indicates that the region is highly P-type doped. The P+ source region 13 forms a good ohmic contact with the source metal layer 50, facilitating current inflow and outflow. The N+ source region is disposed between the P+ source region 13 and the insulating dielectric layer 60.

[0043] In a feasible embodiment, the N+ source region 14 is disposed inside the P-type well region 12. N+ indicates that this region is highly N-type doped, containing a large number of free electrons as majority carriers. When the power MOS device is turned on, these electrons participate in the conduction process as the main current carriers. When a suitable voltage is applied to the gate to form a channel, electrons from the N+ source region enter the N-type drift layer 10 through the channel, thereby forming a current path from the source metal layer 50 to the drain 40, realizing the device's conduction function. The N+ source region and the source metal layer 50 can form a good ohmic contact. Ohmic contact can reduce the contact resistance between the source metal layer 50 and the semiconductor region, reducing energy loss during current conduction and improving device efficiency. Lower contact resistance also reduces the heat generated by the device when operating at high current, contributing to improved device reliability and stability.

[0044] In one feasible implementation, the P+ source region 13 includes a first P+ source region 131 and a second P+ source region 132; The first P+ source region 131 is located on the front side of the first P-type well region 121; The second P+ source region 132 is located on the front side of the second P-type well region 122.

[0045] Optionally, the first P+ source region 131 is located on the front side of the first P-type well region 121 and closely cooperates with the first P-type well region 121 to participate in the conduction of channel current; the second P+ source region 132 is located on the front side of the second P-type well region 122 and also plays the role of current conduction and ohmic contact.

[0046] Two non-adjacent grooves penetrate the N+ source region and the P-type well region in the vertical direction.

[0047] In one feasible implementation, a groove is formed in the middle of the device by etching, thereby creating a current path from the source metal layer to the N-type drift region inside the device, which can improve the heat dissipation performance of the device or achieve electrical isolation between different regions.

[0048] An insulating dielectric layer 60 is disposed on the inner wall of each groove.

[0049] The insulating dielectric layer 60 is typically an insulating material. Its main function is to isolate the gate metal layer 70 from the semiconductor region, preventing short circuits between the gate metal layer 70 and the source metal layer 50 and drain 40. Simultaneously, when an appropriate voltage is applied to the gate metal layer 70, the gate voltage can effectively regulate the formation of the channel.

[0050] Optionally, the grooves are symmetrically distributed in the device to form four symmetrical current paths, optimize the electric field balance, and avoid local electric field concentration.

[0051] A gate metal layer 70 is disposed in each groove.

[0052] In one feasible embodiment, the gate metal layer 70 is the core control component of the power MOS device, capable of controlling the device's on and off states by applying a voltage. For example, when the gate voltage reaches a threshold voltage, a conductive channel is formed on the semiconductor surface around the gate, allowing current to flow from the source to the drain 40. The change in gate voltage determines the device's switching speed and dynamic characteristics.

[0053] A source metal layer 50 is disposed on the front side of the P+ source region 13 and the N+ source region 14.

[0054] In one feasible embodiment, the source metal layer 50 is the current-out terminal of the power MOS device, typically composed of highly doped N-type or P-type semiconductor material, the doping type of which is closely related to the conductivity type of the device. In an N-channel power MOS device, the source metal layer 50 serves as the electron injection terminal, responsible for injecting electrons into the channel layer, thereby realizing the current transfer from the source to the drain 40; while in a P-channel power MOS device, the source metal layer 50 serves as the hole injection terminal, realizing current conduction by injecting holes. The highly doped characteristics of the source metal layer 50 not only ensure low contact resistance, thereby reducing the conduction loss of the device, but also improve the overall performance of the device by optimizing electrical characteristics.

[0055] In one feasible implementation, the source metal layer 50 includes a first source metal layer 51 and a second source metal layer 52; The first source metal layer 51 is disposed on the front side of the first P+ source region 131; The second source metal layer 52 is disposed on the front side of the second P+ source region 132.

[0056] Optionally, the first source metal layer 51 is disposed on the front side of the first P+ source region 131, and the second source metal layer 52 is disposed on the front side of the second P+ source region 132, forming a good electrical connection with the corresponding P+ source region 13.

[0057] In one feasible implementation, the power MOS device further includes: The first P-type shielding layer 81 is disposed between the first P-type well region 121 and the N-type drift layer 10; The second P-type shielding layer 82 is disposed on the bottom outer side of each groove and is adjacent to the N-type drift layer 10.

[0058] In one feasible embodiment, the P-type shielding layer 80 can suppress electric field concentration at the corner between the device gate metal layer 70 and the insulating dielectric layer 60, improving device reliability, and shielding the capacitance from the device gate metal layer 70 to the drain 40, thereby improving the switching speed of the device and reducing the drive loss of the device. Specifically, the first P-type shielding layer 81 can control the consistency of the conductive path of the device, shield the influence of the electric field in the N-type drift layer 10 on the first P-type well region 121, reduce leakage current and improve the stability of the device; the second P-type shielding layer 82 helps to optimize the electric field distribution of the device and improve the withstand voltage capability of the device.

[0059] Optionally, the first P-type shielding layer 81 is located in the center of the device, which controls the symmetry of the conductive channel of the device, can average the current inside the device, and avoid current concentration.

[0060] In one feasible implementation, the N+ source region 14 and the P+ source region 13 are arranged horizontally adjacent to each other, wherein the N+ source region 14 is in contact with the source metal layer 50, and the P+ source region 13 is in contact with the source metal layer 50.

[0061] Optionally, the P+ source region 13 and N+ source region 14 are arranged adjacent to each other in the horizontal direction, which will affect the electric field distribution and carrier concentration distribution of the P-type well region 12. This change in distribution can have a certain impact on the formation and characteristics of the channel, such as fine-tuning parameters like the threshold voltage and on-resistance of the channel, thereby optimizing the performance of the device.

[0062] The second embodiment of this application provides a method for fabricating a power MOS device, referring to... Figure 2 This includes the following steps: Step S101: Provide a substrate 30 and form an N-type buffer layer 20 on the front side of the substrate 30; In one feasible embodiment, refer to Figure 3 A substrate 30 is provided, and an N-type buffer layer 20 is formed on the front epitaxial layer of the substrate 30.

[0063] Optionally, the substrate 30 is N-type doped, and the material of the substrate 30 is doped silicon carbide.

[0064] Optionally, the thickness of the substrate 30 is 1 μm.

[0065] Optionally, the doping concentration of the substrate 30 is 2~8e18cm. -3 .

[0066] Optionally, the doping concentration of the substrate 30 can be 2e18cm. -3 3e18cm -3 4e18cm -3 5e18cm -3 6e18cm -3 7e18cm -3 8e18cm -3 Within this doping concentration range, a low-resistance ohmic contact can be formed between the substrate 30 and the drain 40, reducing the overall on-resistance of the device.

[0067] Optionally, the N-type buffer layer 20 is made of doped silicon carbide.

[0068] Optionally, the thickness of the N-type buffer layer 20 is 500 nm.

[0069] Optionally, the doping concentration of the N-type buffer layer 20 is 6-10e17cm. -3 .

[0070] Optionally, the doping concentration of the N-type buffer layer 20 can be 6e17cm. -3 7e17cm -3 8e17cm -3 9e17cm -3 10e17cm -3 wait.

[0071] Step S102, refer to Figure 4 A first N-type drift layer 10a is formed on the front side of the N-type buffer layer 20.

[0072] Step S103: Define a first barrier layer pattern 101 on the front side of the first N-type drift layer 10a, implant ions based on the first barrier layer pattern 101 to form a P-type region 11, and remove the first barrier layer pattern. In one feasible embodiment, refer to Figure 5 In the formation of the first N-type drift layer 10, photoresist is coated and a mask is set. The photoresist is then etched to obtain a first barrier layer pattern 101, forming two regions exposing the N-type drift layer 10 for subsequent ion implantation. These regions are located on both sides of the first N-type drift layer 10a. Ions are then implanted into the exposed regions of the first N-type drift layer 10a to form a P-type region 11. The P-type region 11 and the first N-type drift layer 10a form a PN junction structure.

[0073] Optionally, the width of the P-type region 11 is 2 μm and the thickness is 25~45 μm.

[0074] Optionally, the thickness of the P-type region 11 can be 25μm, 30μm, 35μm, 40μm, 45μm, etc. Within the above thickness range, it can be ensured that the device forms a PN junction structure and that the P-type region 11 plays a good isolation role.

[0075] Optionally, the doping concentration of the p-type region 11 is 6~10e17cm. -3 .

[0076] Optionally, the doping concentration of the p-type region 11 can be 6e17cm. -3 7e17cm -3 8e17cm -3 9e17cm -3 10e17cm -3 The aforementioned doping concentrations can ensure the lateral and longitudinal diffusion relationship of the space charge region of the PN junction of the device, realize the superstructure of the device, and ensure the isolation between devices, thereby ensuring that the device has both breakdown voltage, low on-resistance and high reliability.

[0077] Optionally, as the gate positive voltage increases, holes on the surface of the P-type region 11 are continuously repelled, leading to a sharp decrease in the hole concentration in this region, forming a depletion layer. This depletion layer contains almost no mobile charge carriers. When the gate voltage continues to increase beyond a certain value, enough electrons accumulate on the surface of the P-type region 11, causing the conductivity type of this region to change from P-type to N-type, forming an inversion layer. This inversion layer then becomes the current path connecting the N-type drift layer 10 and the source metal layer 50.

[0078] Step S104, refer to Figure 6 This forms a second N-type drift layer 10b covering the first N-type drift region 10a; In one feasible embodiment, epitaxially growing a second N-type drift layer 10b can optimize the electric field distribution in the longitudinal direction.

[0079] Optionally, the N-type drift layer 10 includes a first N-type drift layer 10a and a second N-type drift layer 10b.

[0080] Optionally, the N-type drift layer 10 is made of doped silicon carbide.

[0081] Optionally, the N-type drift layer 10 has a width of 1 μm and a thickness of 30~50 μm.

[0082] Optionally, the thickness of the N-type drift layer 10 can be 30μm, 35μm, 40μm, 45μm, 50μm, etc.

[0083] Optionally, the doping concentration of the N-type drift layer 10 is 1~5e17cm. -3 .

[0084] Optionally, the doping concentration of the N-type drift layer 10 can be 1e17cm. -3 2e17cm -3 3e17cm -3 4e17cm -3 5e17cm -3 wait.

[0085] Step A10: Define a seventh barrier layer pattern 107 on the front side of the second drift layer, inject ions based on the seventh barrier layer pattern 107 to form a P-type shielding layer 80, and remove the seventh barrier layer pattern 107.

[0086] In one feasible embodiment, refer to Figure 7 Photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. The seventh barrier layer pattern 107 is obtained by etching the photoresist, forming two regions that expose the second N-type drift layer 10b, located between the P-type regions 11 and spaced apart within the N-type drift layer 10. Ions are implanted into the exposed regions to form a P-type shielding layer 80.

[0087] Optionally, the material of the P-type shielding layer 80 is doped silicon carbide.

[0088] Optionally, the doping concentration of the P-type shielding layer 80 is 6-8e17cm. -3 .

[0089] Optionally, the doping concentration of the P-type shielding layer can be 6e17cm. -3 6.5e17cm -3 7e17cm -3 7.5e17cm -3 8e17cm -3 wait.

[0090] Step S105: Ions are implanted on the front side of the second N-type drift layer 10b to form a P-type trap region 12; In one feasible embodiment, refer to Figure 8 By injecting ions and allowing them to diffuse within the second N-type drift layer 10b, a P-type well region 12 is formed.

[0091] Optionally, the doping concentration of the P-type well region 12 is 1-5e16cm. -3 .

[0092] Optionally, the doping concentration of the P-type well region 12 is 1e16cm. -3 2e16cm -3 3e16cm -3 4e16cm -3 5e16cm -3 wait.

[0093] Step S106: Define a second barrier layer pattern 102 on the front side of the second N-type drift layer 10b, inject ions based on the second barrier layer pattern 102 to form an N+ source region, and remove the second barrier layer pattern 102. Step S107: Define a third barrier layer pattern 103 on the front side of the second N-type drift layer 10b, inject ions based on the third barrier layer pattern 103 to form a P+ source region 13, and remove the third barrier layer pattern 103. In one feasible embodiment, refer to Figure 9 Photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. The second barrier layer pattern 102 is obtained by etching the photoresist, forming an area that exposes the second N-type drift layer 10b for ion implantation to form an N+ source region 14. The exposed area is located in the P-type well region. Ions are implanted into the exposed area corresponding to the second barrier layer pattern 102 to form an N+ source region, and then the second barrier layer pattern 102 is removed.

[0094] In one feasible embodiment, refer to Figure 10 Photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. The photoresist is then etched to obtain the third barrier layer pattern 103, forming an area exposing the second N-type drift layer 10b for ion implantation to form a P+ source region 13. The exposed area is located within the P-type well region. Ions are implanted into the exposed area corresponding to the third barrier layer pattern 103 to form the P+ source region, and then the second barrier layer pattern 103 is removed.

[0095] Alternatively, the N-type doping process requires the implantation of phosphorus or arsenic ions.

[0096] Optionally, the ions required for the P-type doping process are boron.

[0097] Optionally, the doping concentration of the P+ source region 13 is 1-5e18cm. -3 .

[0098] Optionally, the doping concentration of the P+ source region 13 can be 1e18cm. -3 2e18cm -3 3e18cm -3 4e18cm -3 5e18cm -3 wait.

[0099] Optionally, the doping concentration of the N+ source region 14 is 2~8e18cm. -3 .

[0100] Optionally, the doping concentration of the N+ source region 14 can be 2e18cm. -3 3e18cm -3 4e18cm -35e18cm -3 6e18cm -3 7e18cm -3 8e18cm -3 wait.

[0101] Optionally, the N+ source region 14 has a width of 500 nm and a thickness of 600 nm.

[0102] In step S108, a fourth barrier layer pattern 104 is defined on the front side of the second drift layer, and the N+ source region 14 and the P-type well region 12 are etched based on the fourth barrier layer pattern 104 to form a groove. Step S109: Oxidize the inner wall of the groove to form an insulating dielectric layer 60, and remove the fourth barrier layer pattern 104; In one feasible embodiment, refer to Figure 11 Photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. The fourth barrier layer pattern 104 is obtained by etching the photoresist to form the groove 15. The exposed second N-type drift layer 10b corresponding to the fourth barrier layer pattern 104 is etched using an etching process to form the groove 15. The groove vertically penetrates the N+ source region 13 and the P-type well region 12.

[0103] Optionally, the two grooves 15 are symmetrically distributed in the device, which can make the electric field distribution more uniform and improve the reliability of the device.

[0104] Optionally, the insulating dielectric layer 60 has a maximum width of 600 nm and a maximum thickness of 2.1 μm.

[0105] Optionally, the bottom thickness of the insulating dielectric layer 60 is 100 nm, and the sidewall width is 50 nm.

[0106] Optionally, the width of the first P-type shielding layer 81 is 600 nm and the thickness is 300 nm.

[0107] Optionally, the width of the first P-type shielding layer 82 is 1 μm and the thickness is 1.5 μm.

[0108] Optionally, the width of the N-type drift layer 10 between the P-type region 11 and the second P-type shielding layer 82 is 1 μm.

[0109] Optionally, the width of the N-type drift layer 10 between the first P-type shielding layer 81 and the second P-type shielding layer 82 is 600 nm.

[0110] Optionally, by setting the width and doping concentration of each layer, the impedance in the four conductive channels formed between the P-type region 11, the P-type shielding layer 80, and the N-type drift layer 10 can be made equal, thus constructing a symmetrical current path, averaging the current inside the device, avoiding current concentration, and thereby improving the reliability of the device.

[0111] Optionally, the width of the first P-type well region 121 is 3 μm and the thickness is 1.0~1.6 μm.

[0112] Optionally, the width of the second P-type well region is 0.5~3μm.

[0113] Optionally, the width of the second P-type well region 122 is 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm and 3.0 μm.

[0114] Optionally, the width of the first P+ source region 131 is 2 μm and the thickness is 600 nm.

[0115] Optionally, the width of the second P+ source region 132 is 0.5~2μm and the thickness is 600~900nm.

[0116] Optionally, the two grooves are spaced apart in the N-type drift layer 10. This dual-groove arrangement allows current to flow more efficiently from the source to the drain 40, reducing resistance during current flow and significantly lowering the on-resistance. Lower on-resistance means less power consumption when the device is turned on, improving device efficiency and reducing energy loss. The presence of the dual grooves allows for a more uniform electric field distribution within the device, preventing electric field concentration in certain areas and improving the overall breakdown voltage. Furthermore, the dual-groove design can optimize the device structure, reduce parasitic capacitance, and accelerate capacitor charging and discharging, thereby improving the device's switching speed.

[0117] In one feasible embodiment, refer to Figure 12 After the groove 15 is formed, the inner wall of the groove 15 is oxidized. Oxidation refers to exposing the device to a high-temperature environment containing oxygen, causing the silicon on the surface of the inner wall of the groove to react chemically with oxygen to generate dielectric materials such as silicon dioxide, which serve as the insulating dielectric layer 60. Then, the fourth barrier layer pattern 104 is removed.

[0118] Step S110: Define a fifth barrier layer pattern 105 on the front side of the second N-type drift layer, deposit a gate metal layer 70 based on the fifth barrier layer pattern 105, and remove the fifth barrier layer pattern 105. Step S111: Define a sixth barrier layer pattern 106 on the front side of the second N-type drift layer, etch the P+ source region 13 and N+ source region 14 based on the sixth barrier layer pattern 106, and deposit the source metal layer 50, then remove the sixth barrier layer pattern 106.

[0119] In one feasible embodiment, refer to Figure 13A photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. After etching the photoresist, a fifth barrier layer pattern 105 is obtained, which is used to form the gate metal layer 70. The gate metal layer 70 is deposited in the region of the exposed second N-type drift layer 10b corresponding to the fifth barrier layer pattern 105. The gate metal layer 70 is located in two grooves and is surrounded by an insulating dielectric layer 60.

[0120] Optionally, the gate metal layer 70 has a width of 500 nm and a thickness of 2 μm.

[0121] In one feasible embodiment, refer to Figure 14 Photoresist is coated and a mask is set on the front side of the second N-type drift layer 10b. After etching the photoresist, the sixth barrier layer pattern 106 is obtained. The exposed N+ source region 14 and P+ source region 13 corresponding to the fifth barrier layer pattern 105 are etched to form the source trench 53, which is used to deposit the source metal layer 50.

[0122] In one feasible embodiment, refer to Figure 15 A source metal layer 50 is deposited within the source trench 53. The source metal layer 50 is the source of electron injection and, together with the gate metal layer 70 and the drain 40, constitutes the basic structure of the device. The device is turned on by the electron flow between the source metal layer 50 and the drain 40.

[0123] Optionally, the width of the first source metal layer 51 is 3 μm.

[0124] Optionally, the width of the second source metal layer 52 is 2 μm.

[0125] Optionally, the source metal layer 50 may be made of at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0126] The above are merely exemplary embodiments of the present invention and do not limit the scope of the patent of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.

Claims

1. A power MOS device, characterized by, The power MOS device comprises: an N-type drift layer; a P-type region disposed on both sides of the N-type drift layer; an N-type buffer layer disposed on the back of the N-type drift layer; a substrate disposed on the back of the N-type buffer layer; a drain disposed on the back of the substrate; a P-type well region disposed on the front of the N-type drift layer; a plurality of P+ source regions and a plurality of N+ source regions disposed alternately in the horizontal direction inside the P-type well region; two non-adjacent grooves penetrating the N+ source regions and the P-type well region in the vertical direction; an insulating medium layer disposed on the inner wall of each groove; a gate metal layer disposed in each groove; a source metal layer disposed on the front of the P+ source regions and the N+ source regions.

2. The power MOS device of claim 1, wherein, The P-type well region is divided by the grooves into a first P-type well region and a second P-type well region; The first P-type well region is located between each groove; The second P-type well region is located on the side of each groove away from the first P-type well region.

3. The power MOS device of claim 2, wherein, The power MOS device further comprises: a first P-type shielding layer disposed between the first P-type well region and the N-type drift layer; a second P-type shielding layer disposed on the outside of the bottom of each groove and adjacent to the N-type drift layer.

4. The power MOS device of claim 3, wherein, The P+ source regions comprise first P+ source regions and second P+ source regions; The first P+ source regions are located on the front of the first P-type well region; The second P+ source regions are located on the front of the second P-type well region.

5. The power MOS device of claim 4, wherein, The source metal layer comprises first source metal layers and second source metal layers; The first source metal layers are disposed on the front of the first P+ source regions; The second source metal layers are disposed on the front of the second P+ source regions.

6. The power MOS device of claim 5, wherein, The doping concentration of the substrate is 2-8e18cm -3 ; And / or, the N-type buffer layer has a doping concentration of 6-10e17cm-3 -3 ; And / or, the doping concentration of the N-type drift layer is 1-5e17cm -3 ; and / or, the P-type region has a doping concentration of 6-10e17 cm-3 -3 ; And / or, the doping concentration of the P-type shielding layer is 6~8e17cm -3 ; And / or, the P-type well region has a doping concentration of 1-5e16 cm -3 ; and / or, a doping concentration of the P+ source region is 1-5e18cm -3 ; And / or, the N+ source region has a doping concentration of 2-8e18cm -3 .

7. The power MOS device of claim 5, wherein, The thickness of the substrate is 1 μm; and / or, the thickness of the N-type buffer layer is 500 nm; and / or, the width of the N-type drift layer is 1 μm and the thickness is 30-50 μm; and / or, the width of the P-type region is 2 μm and the thickness is 25-45 μm; and / or, the width of the N+ source region is 500 nm and the thickness is 600 nm; and / or, the maximum width of the insulating medium layer is 600 nm and the maximum thickness is 2.1 μm; and / or, the thickness of the source metal layer is 300 nm; and / or, the width of the gate metal layer is 500 nm and the thickness is 2 μm; and / or, the width of the first P-type shielding layer is 600 nm and the thickness is 500 nm; and / or, the width of the second P-type shielding layer is 600 nm and the thickness is 300 nm; and / or, the width of the first P-type well region is 3 μm and the thickness is 1.0-1.6 μm; and / or, the width of the second P-type well region is 0.5-3 μm; and / or, the width of the first P+ source region is 2 μm and the thickness is 600 nm; and / or, the width of the second P+ source region is 0.5-2 μm and the thickness is 600-900 nm; and / or, the width of the first source metal layer is 3 μm; and / or, the width of the second source metal layer is 2 μm.

8. The power MOS device of claim 1, wherein, The material of the source metal layer comprises at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt. The material of the drain electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

9. A method of fabricating a power MOS device as claimed in any one of claims 1 to 8, characterized in that, The preparation method comprises the steps of: providing a substrate, forming an N-type buffer layer on the front surface of the substrate; forming a first N-type drift layer on the front surface of the N-type buffer layer; defining a first barrier layer pattern on the front surface of the first N-type drift layer, implanting ions based on the first barrier layer pattern to form a P-type region, and removing the first barrier layer pattern; forming a second N-type drift layer covering the first N-type drift layer; implanting ions on the front surface of the second N-type drift layer to form a P-type well region; defining a second barrier layer pattern on the front surface of the second N-type drift layer, implanting ions based on the second barrier layer pattern to form an N+ source region, and removing the second barrier layer pattern; defining a third barrier layer pattern on the front surface of the second N-type drift layer, implanting ions based on the third barrier layer pattern to form a P+ source region, and removing the third barrier layer pattern; defining a fourth barrier layer pattern on the front surface of the second N-type drift layer, etching the N+ source region and the P-type well region based on the fourth barrier layer pattern to form a recess; oxidizing the inner wall of the recess to form an insulating medium layer, and removing the fourth barrier layer pattern; defining a fifth barrier layer pattern on the front surface of the second N-type drift layer, depositing a gate metal layer based on the fifth barrier layer pattern, and removing the fifth barrier layer pattern; defining a sixth barrier layer pattern on the front surface of the second N-type drift layer, etching the P+ source region and the N+ source region based on the sixth barrier layer pattern, and depositing a source metal layer, and removing the sixth barrier layer pattern.

10. The production method according to claim 9, wherein Before the step of implanting ions on the front surface of the second N-type drift layer to form a P-type well region, the method further comprises the steps of: defining a seventh barrier layer pattern on the front surface of the second N-type drift layer, implanting ions based on the seventh barrier layer pattern to form a P-type shielding layer, and removing the seventh barrier layer pattern.

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