IGBT layout optimization method based on heat dissipation performance analysis, platform and medium

Abstract

The invention discloses an IGBT layout optimization method, platform and medium based on heat dissipation performance analysis, and relates to the technical field of semiconductor devices.The method comprises the steps that IGBT device layout information is collected, and a heat conduction model is established; the method comprises the following steps: mining a plurality of application scenes to carry out multi-scene coupling heat dissipation performance detection to obtain a coupling heat dissipation coefficient, carrying out multi-scene optimization on a layout scheme based on the coefficient to obtain a first layout adjustment space, carrying out multilateral risk optimization on the space to obtain a plurality of layout optimization guide domains, and carrying out global guide breeding optimization based on the guide domains to obtain a second layout adjustment space. And an IGBT layout scheme is obtained. According to the IGBT device layout method, the technical problems of uneven device heat dissipation, high fault risk and poor adaptability caused by the fact that the multi-scene heat dissipation performance and the layout induction risk are not fully considered in the existing IGBT device layout are solved, and the technical effects of improving the heat dissipation performance and the adaptability of the IGBT under multiple working conditions and reducing the overheating fault risk are achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to an IGBT layout optimization method, platform, and dielectric based on heat dissipation performance analysis. Background Technology

[0002] In modern power electronics technology, IGBTs (Insulated Gate Bipolar Transistors) are widely used in high-efficiency power control systems, such as motor drives, frequency converters, and inverters. Due to the high power density and high-frequency operating characteristics of IGBT devices, they generate a significant amount of heat during operation. If heat dissipation is ineffective, it can lead to performance degradation and even failure. Therefore, optimizing IGBT layout design and improving heat dissipation performance has become a key issue in enhancing the reliability and efficiency of power electronic systems. Existing layout optimization methods mainly rely on static thermal simulation and simple heat dissipation path analysis, failing to fully consider the variable factors in actual application scenarios. With the emergence of diverse application scenarios and different usage conditions, traditional single layout schemes often struggle to meet various requirements. Summary of the Invention

[0003] This application provides an IGBT layout optimization method, platform, and dielectric based on thermal performance analysis, which is used to solve the technical problems of uneven heat dissipation, high failure risk, and poor adaptability of existing IGBT device layouts that do not fully consider the thermal performance and layout-induced risks in multiple scenarios.

[0004] The first aspect of this application provides an IGBT layout optimization method based on heat dissipation performance analysis. The method includes: collecting IGBT layout information of a target device, generating a current layout scheme, and performing thermal characteristic modeling of the target device based on the current layout scheme to obtain a device heat conduction model; mining application scenarios based on the device model characteristics of the target device to obtain D certain application scenarios, where D is a positive integer greater than 1; performing multi-scenario coupled heat dissipation performance testing on the device heat conduction model based on the D certain application scenarios to obtain a current coupled heat dissipation coefficient; performing multi-scenario coupled optimization on the current layout scheme based on the current coupled heat dissipation coefficient and the D certain application scenarios to obtain a first layout adjustment space; performing multilateral risk optimization on the first layout adjustment space through a layout-induced risk prediction model to obtain multiple layout optimization guidance domains; and performing global guided propagation optimization on the first layout adjustment space based on the layout-induced risk prediction model and the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

[0005] A second aspect of this application provides an IGBT layout optimization platform based on heat dissipation performance analysis. The platform includes: a thermal characteristic modeling module, used to collect IGBT layout information of a target device, generate a current layout scheme, and perform thermal characteristic modeling of the target device based on the current layout scheme to obtain a device heat conduction model; an application scenario mining module, used to mine application scenarios based on the device model characteristics of the target device to obtain D certain application scenarios, where D is a positive integer greater than 1; a heat dissipation performance detection module, used to perform multi-scenario coupled heat dissipation performance detection on the device heat conduction model based on the D certain application scenarios to obtain a current coupled heat dissipation coefficient; a multi-scenario coupled optimization module, used to perform multi-scenario coupled optimization on the current layout scheme based on the current coupled heat dissipation coefficient and the D certain application scenarios to obtain a first layout adjustment space; a multilateral risk optimization module, used to perform multilateral risk optimization on the first layout adjustment space through a layout-induced risk prediction model to obtain multiple layout optimization guidance domains; and a global guided propagation optimization module, used to perform global guided propagation optimization on the first layout adjustment space based on the layout-induced risk prediction model and the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

[0006] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of the first aspect.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages: This application provides an IGBT layout optimization method, platform, and dielectric based on heat dissipation performance analysis, which relates to the field of semiconductor device technology. By using thermal characteristic modeling and multi-scenario coupled heat dissipation performance detection, it explores multiple application scenarios to evaluate heat dissipation performance and performs multi-scenario coupled optimization. Combined with a layout-induced risk prediction model, it performs multilateral risk optimization on IGBT device layout schemes to generate the optimal layout scheme. This solves the technical problem that existing IGBT device layouts do not fully consider multi-scenario heat dissipation performance and layout-induced risks, resulting in uneven device heat dissipation, high failure risk, and poor adaptability. It achieves the technical effect of improving the heat dissipation performance and adaptability of IGBTs under multiple operating conditions and reducing the risk of overheating failures through multi-scenario coupled heat dissipation performance detection and multi-risk constraint optimization. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic flowchart of an IGBT layout optimization method based on heat dissipation performance analysis provided in an embodiment of this application; Figure 2 A schematic diagram of the IGBT layout optimization platform structure based on heat dissipation performance analysis provided in this application embodiment.

[0010] Figure labeling: Thermal characteristic modeling module 11, application scenario mining module 12, heat dissipation performance detection module 13, multi-scenario coupling optimization module 14, multilateral risk optimization module 15, global guided reproduction optimization module 16. Detailed Implementation

[0011] This application provides an IGBT layout optimization method, platform, and dielectric based on thermal performance analysis, which is used to solve the technical problems of uneven heat dissipation, high failure risk, and poor adaptability of existing IGBT device layouts that do not fully consider the thermal performance and layout-induced risks in multiple scenarios.

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0013] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0014] Example 1, as Figure 1 As shown, this application provides an IGBT layout optimization method based on heat dissipation performance analysis, the method including: P10: Collect the IGBT layout information of the target device, generate the current layout scheme, and perform thermal characteristic modeling of the target device based on the current layout scheme to obtain the device heat conduction model.

[0015] Furthermore, step P10 in this embodiment of the application also includes: P11: Reconstruct the basic features of the target device to obtain a three-dimensional model of the device; P12: Reconstruct the three-dimensional model according to the current layout scheme to obtain an IGBT layout model; P13: Enhance the model parameters of the three-dimensional model of the device according to the IGBT layout model to generate a thermal conduction model of the device.

[0016] It should be understood that by collecting the IGBT layout information of the target device, the current layout scheme is generated, and the thermal characteristic model of the target device is performed based on the scheme to obtain the device's thermal conduction model.

[0017] First, a basic feature reconstruction is performed on the target device to obtain its 3D model. For example, a high-precision 3D scanning device is used to perform a comprehensive scan of the target IGBT device, ensuring accurate acquisition of its external contours, internal structure, and all key feature points. The scan data is then imported into computer-aided design software, where its modeling capabilities are used to reconstruct the device's 3D model. During this process, special attention must be paid to the model's geometric accuracy to ensure it accurately reflects the device's actual physical structure. Furthermore, the basic feature reconstruction not only focuses on the device's shape but also considers its thermal conductivity, material properties, etc., to ensure that subsequent thermal conduction simulations closely approximate real-world usage. The generated 3D model should possess sufficient accuracy to ensure the reliability of the thermal conduction simulation.

[0018] Next, a 3D reconstruction is performed based on the current layout scheme to obtain the IGBT layout model. This involves a more detailed 3D reconstruction of the target device based on the current layout. The layout scheme includes not only the geometric configuration of the device itself, but also factors such as the distance between the device and other components, electrical connections, heat dissipation paths, and the device's mounting method. By taking these factors into account, an accurate layout model reflecting the actual application state of the device is created. This model needs to consider both the device's mounting space and heat dissipation requirements in the actual circuit, thereby ensuring the simulation results are operable in various application scenarios.

[0019] Finally, based on the generated IGBT layout model, the 3D model of the device is enhanced with improved parameters. This process requires incorporating key environmental factors and the device's operating state into the model for more precise enhancement. Enhancements include, but are not limited to, the distribution of heat sources, heat conduction paths, heat exchange efficiency between different materials, and the thermal impact of the device under actual current operation. These parameter enhancements more realistically simulate the thermal characteristics of the device under different operating environments, enabling the generated heat conduction model to not only provide temperature distribution maps but also reveal the heat transfer mechanisms within the device and its surrounding environment, providing a theoretical basis for subsequent heat dissipation performance evaluation and layout optimization.

[0020] P20: Based on the device model characteristics of the target device, application scenarios are mined to obtain D certain application scenarios, where D is a positive integer greater than 1.

[0021] Furthermore, step P20 in this embodiment of the application also includes: P21: Record and collect application scenarios based on the target device to obtain a first historical application scenario library; P22: Record and collect application scenarios based on the device model characteristics to obtain a second historical application scenario library; P23: Extract a first historical application scenario from the first historical application scenario library, and perform trigger frequency statistics on the first historical application scenario based on the first historical application scenario library to obtain a first scenario local trigger degree; P24: Perform trigger frequency statistics on the first historical application scenario based on the second historical application scenario library to obtain a first scenario global trigger degree; P25: Calculate the average of the first scenario local trigger degree and the first scenario global trigger degree to obtain a first scenario confidence level; P26: If the first scenario confidence level is greater than or equal to a predetermined scenario confidence level, record the first historical application scenario as a first confident application scenario, and add the first confident application scenario to the D confident application scenarios.

[0022] Optionally, application scenario mining is performed based on the device model characteristics of the target device to obtain D definite application scenarios, where D is a positive integer greater than 1. First, application scenario records are collected for the target device to obtain a first historical application scenario library. Specific operations include collecting records of various application scenarios involved in the actual use of the target device. These records can be obtained through various channels such as user feedback, product usage reports, and after-sales maintenance records. The collected application scenario records will be organized and stored in the first historical application scenario library, which contains information such as the device's operating conditions, operating modes, and environmental factors in different applications.

[0023] Next, application scenario records are collected based on the characteristics of the device models to obtain a second historical application scenario library. This step requires further collection of application scenario records related to specific device models. These records may come from application scenario predictions during the product design phase, market research reports, and user feedback for specific models. Through the collection of these records, the second historical application scenario library will contain application scenario data closely related to device models, providing more specific references for subsequent analysis.

[0024] Next, first historical application scenarios are extracted from the first historical application scenario library, and trigger frequency statistics are performed on these scenarios based on the library to obtain the local triggering degree of the first scenario. Specifically, this involves extracting specific application scenario instances, such as the first historical application scenario, from the library and counting the frequency of each instance in the library. This frequency represents the prevalence of the application scenario in the actual use of the target device, i.e., the local triggering degree of the first scenario. For example, if an application scenario appears 100 times in the first historical application scenario library, and the total number of application scenario records in the library is 1000, then the local triggering degree of that application scenario is 10%.

[0025] Subsequently, the trigger frequency of the first historical application scenario is statistically analyzed based on the second historical application scenario library to obtain the global trigger rate of the first scenario. This step requires statistically analyzing the occurrence frequency of the first historical application scenario in the broader second historical application scenario library. This frequency reflects the prevalence of the application scenario in a specific device model, i.e., the global trigger rate of the first scenario. For example, if an application scenario appears 50 times in the second historical application scenario library, while the total number of application scenario records in the library is 500, then the global trigger rate of that application scenario is 10%.

[0026] Next, the mean values ​​of the local triggering degree and the global triggering degree of the first scenario are calculated to obtain the confidence level of the first scenario. By calculating the mean, bias can be eliminated to a certain extent, ensuring the comprehensiveness and accuracy of the evaluation results. This confidence level comprehensively considers the commonality of the application scenario in actual use and its prevalence in a specific model, providing a quantitative basis for judging the reliability of the application scenario.

[0027] Finally, if the confidence level of the first scenario is greater than or equal to the predetermined confidence level, the first historical application scenario is recorded as the first confident application scenario and added to the list of D confident application scenarios. The predetermined confidence level is a pre-set scenario confidence threshold, such as 50%. If the calculated confidence level of the first scenario reaches or exceeds this threshold, the application scenario is considered reliable and marked as the first confident application scenario. Subsequently, this confident application scenario is added to the final list of D confident application scenarios for subsequent thermal performance testing and optimization. This operation ensures that the scenario selection process is both statistically rigorous and can exclude some low-confidence scenarios, thereby selecting application scenarios that have a significant impact on the optimization of the thermal performance of the target device.

[0028] P30: Based on the D confirmed application scenarios, perform multi-scenario coupled heat dissipation performance testing on the thermal conduction model of the device to obtain the current coupled heat dissipation coefficient.

[0029] Furthermore, step P30 in this embodiment of the application also includes: P31: Based on the D confirmed application scenarios, perform heat dissipation simulation on the device's heat conduction model to obtain D scenario heat dissipation simulation data; P32: Using scenario heat dissipation monitoring records as input data and scenario heat dissipation performance evaluation records as output data, perform supervised training on a fully connected neural network to obtain a heat dissipation performance evaluation network; P33: Input the D scenario heat dissipation simulation data into the heat dissipation performance evaluation network to obtain D scenario heat dissipation performance coefficients; P34: Evaluate the importance of heat dissipation performance based on the D confirmed application scenarios to obtain a scenario heat dissipation importance evaluation set, and configure weights for the D confirmed application scenarios based on the scenario heat dissipation importance evaluation set to obtain D scenario heat dissipation weights; P35: Perform weighted fusion of the D scenario heat dissipation performance coefficients based on the D scenario heat dissipation weights to generate the current coupled heat dissipation coefficient.

[0030] Specifically, based on D known application scenarios, the thermal conduction model of the target device is tested for multi-scenario coupled heat dissipation performance to obtain the current coupled heat dissipation coefficient.

[0031] First, based on D confirmed application scenarios, heat dissipation simulations are performed on the device's thermal conduction model to obtain heat dissipation simulation data for each scenario. Specifically, parameters for each confirmed application scenario, such as operating temperature, load conditions, and ambient temperature, need to be input into the device's thermal conduction model. Then, professional thermal simulation software, such as ANSYS Fluent or COMSOL Multiphysics, is used to perform detailed heat dissipation simulations for each application scenario. During the simulation, key parameters such as temperature distribution, heat flow path, and thermal resistance are recorded to generate heat dissipation simulation data for each application scenario.

[0032] Next, using scene heat dissipation monitoring records as input data and scene heat dissipation performance evaluation records as output data, a fully connected neural network is trained under supervision to obtain a heat dissipation performance evaluation network. For this purpose, historical scene heat dissipation monitoring records need to be collected, including actual measured temperature data, heat flow data, etc. Simultaneously, corresponding scene heat dissipation performance evaluation records are collected; these records are typically derived from expert evaluations or actual test results. Then, using the scene heat dissipation monitoring records as input data and the scene heat dissipation performance evaluation records as output data, the fully connected neural network (FCNN) is trained under supervision until the network's prediction error reaches a predetermined threshold. After training, the heat dissipation performance evaluation network is obtained.

[0033] Subsequently, the heat dissipation simulation data for D scenarios are input into the previously trained heat dissipation performance evaluation network. The network will calculate the heat dissipation performance coefficient for each scenario based on the input data. These heat dissipation performance coefficients are a quantitative description of the heat dissipation performance in each scenario, reflecting the heat dissipation efficiency in each application scenario and providing important data on heat conduction and heat dissipation effects in that scenario.

[0034] Then, the importance of heat dissipation performance is evaluated based on D confirmed application scenarios to obtain a scenario heat dissipation importance evaluation set. This process first evaluates the importance of heat dissipation performance for each application scenario through expert assessment, market research, or actual application data, generating a scenario heat dissipation importance evaluation set, where each application scenario corresponds to a heat dissipation importance value. Then, the sum of the heat dissipation importance values ​​for the D scenarios is calculated, and the heat dissipation importance value for each application scenario is normalized to calculate its heat dissipation weight, thus obtaining the heat dissipation weights for the D scenarios. The specific formula is: Scenario heat dissipation weight = Scenario heat dissipation importance / Sum of the heat dissipation importance values ​​for the D scenarios.

[0035] Finally, the thermal performance coefficients of the D scenarios are weighted and fused according to their respective thermal weights to generate the current coupled thermal performance coefficient. Specifically, the thermal performance coefficient of each scenario is multiplied by its corresponding thermal weight to obtain a weighted thermal performance coefficient. Then, all weighted thermal performance coefficients are summed to obtain the current coupled thermal performance coefficient. The specific formula is: Current coupled thermal performance coefficient = ∑(Scenario thermal weight × Scenario thermal performance coefficient). This coupled thermal performance coefficient is a comprehensive evaluation result of thermal performance under multiple scenarios, reflecting the overall thermal performance of the target device in different application scenarios. This coefficient can effectively evaluate the thermal performance of the device and provide a quantitative basis for subsequent layout optimization.

[0036] P40: Based on the current coupling heat dissipation coefficient, perform multi-scenario coupling optimization on the current layout scheme according to the D certain application scenarios to obtain the first layout adjustment space.

[0037] Furthermore, step P40 in this embodiment of the application also includes: P41: If the current coupling heat dissipation coefficient is less than the coupling heat dissipation threshold, adjust the current layout scheme to obtain a layout adjustment scheme set; P42: Extract the nth layout adjustment scheme according to the layout adjustment scheme set, where n is a positive integer; P43: Perform thermal characteristic modeling of the target device according to the nth layout adjustment scheme to obtain the nth layout heat conduction model; P44: Perform multi-scenario coupling heat dissipation performance testing on the nth layout heat conduction model according to the D certain application scenarios to obtain the nth coupling heat dissipation coefficient; P45: If the nth coupling heat dissipation coefficient is greater than or equal to the coupling heat dissipation threshold, add the nth layout adjustment scheme to the first layout adjustment space.

[0038] It should be understood that, based on the current coupling heat dissipation coefficient, multi-scenario coupling optimization is performed on the current layout scheme according to D certain application scenarios to obtain the first layout adjustment space. First, it is necessary to determine whether the current coupling heat dissipation coefficient is less than the coupling heat dissipation threshold. The coupling heat dissipation threshold is preset according to the heat dissipation requirements of the devices and the application scenario, and is used to evaluate whether the heat dissipation performance meets the standards. If the current coupling heat dissipation coefficient is less than the coupling heat dissipation threshold, it means that the heat dissipation performance of the current layout scheme does not meet the design requirements and needs adjustment. Optimization algorithms (such as genetic algorithms, simulated annealing algorithms, etc.) are used to adjust the current layout scheme. The adjustments include changing the relative positions of IGBT devices, adjusting the layout of heat dissipation channels, optimizing heat conduction paths, etc., generating a series of layout adjustment schemes, and selectively choosing the most promising schemes to form a layout adjustment scheme set. The layout parameters of each scheme should be recorded in detail for subsequent evaluation and comparison. Conversely, if the current coupling heat dissipation coefficient is not less than the coupling heat dissipation threshold, it means that the current layout scheme meets the heat dissipation requirements and no further optimization is needed.

[0039] Next, the nth layout adjustment scheme is selected from the set of schemes. The selection process can be sequential or random, depending on the optimization algorithm design. Detailed parameters of the nth layout adjustment scheme are recorded, including the device's location and the layout of heat dissipation channels, for subsequent thermal characteristic modeling. Then, thermal characteristic modeling of the target device is performed based on the nth layout adjustment scheme. For example, the parameters of the nth layout adjustment scheme are input into professional thermal simulation software, such as ANSYS Fluent or COMSOL Multiphysics. In the software, parameters such as the device's material properties, boundary conditions, and initial temperature are set, and the heat conduction process of the device under this layout scheme is simulated. The simulation results are recorded, including key parameters such as temperature distribution, heat flow path, and thermal resistance, generating the nth layout heat conduction model.

[0040] Next, the multi-scenario coupled heat dissipation performance of the nth layout heat conduction model is tested based on D confirmed application scenarios. For example, the parameters of the D confirmed application scenarios are input into the nth layout heat conduction model one by one. The parameters for each application scenario include operating temperature, load conditions, ambient temperature, etc. Heat dissipation simulation is performed for each application scenario using thermal simulation software. Heat dissipation performance parameters for each application scenario are recorded, such as maximum temperature, average temperature, and heat flux density. Based on these parameters, the heat dissipation performance coefficient for each application scenario is calculated using the calculation method described in step P30 above. Finally, the heat dissipation performance coefficients of the D application scenarios are combined to obtain the nth coupled heat dissipation coefficient. A weighted average method can be used for the specific calculation, assigning different weights according to the importance of each application scenario.

[0041] Finally, the nth coupling heat dissipation coefficient is compared with the coupling heat dissipation threshold. If the nth coupling heat dissipation coefficient is greater than or equal to the coupling heat dissipation threshold, it indicates that the heat dissipation performance of the layout adjustment scheme meets the requirements. At this time, the nth layout adjustment scheme is added to the first layout adjustment space. The first layout adjustment space is a set containing all layout adjustment schemes that meet the heat dissipation performance requirements. These schemes have undergone coupling heat dissipation performance testing in multiple scenarios, possess good heat dissipation performance, and are suitable for different application scenarios. If the nth coupling heat dissipation coefficient is less than the coupling heat dissipation threshold, the layout adjustment scheme set is returned, the next layout adjustment scheme is selected, and the above process is repeated until a layout scheme that meets the requirements is found.

[0042] P50: By using a layout-induced risk prediction model, the first layout adjustment space is optimized through multilateral risk search to obtain multiple layout optimization guidance domains.

[0043] Furthermore, step P50 in this embodiment of the application also includes: P51: Activate the layout-induced risk prediction model, which includes multiple layout-induced risk indicators, including layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk; P52: Based on the device basic information of the target device, perform multi-dimensional induced risk prediction for each layout adjustment scheme within the first layout adjustment space according to the layout-induced risk prediction model, and obtain an induced risk prediction map; P53: Based on the induced risk prediction map, adjust the first layout adjustment space according to the layout-induced failure risk threshold. 1. Optimize the induced failure risk to obtain a first layout optimization guidance domain; P54: Based on the induced risk prediction map, optimize the induced aging risk of the first layout adjustment space according to the layout induced aging risk threshold to obtain a second layout optimization guidance domain; P55: Based on the induced risk prediction map, optimize the induced performance risk of the first layout adjustment space according to the layout induced performance risk threshold to obtain a third layout optimization guidance domain; P56: Merge the first layout optimization guidance domain, the second layout optimization guidance domain, and the third layout optimization guidance domain into the plurality of layout optimization guidance domains.

[0044] Optionally, a layout-induced risk prediction model is used to perform multilateral risk optimization on the first layout adjustment space to obtain multiple layout optimization guidance domains. First, the layout-induced risk prediction model is activated. This model includes multiple indicators of layout-induced risk, specifically covering layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk. Layout-induced failure risk primarily assesses whether the layout scheme may lead to device failures, such as short circuits, poor contact, or electrical overload. Layout-induced aging risk assesses whether the layout may accelerate device aging, especially material aging caused by factors such as temperature changes and current load. Layout-induced performance risk includes electrical and mechanical performance risks, reflecting potential problems such as current transmission, power loss, mechanical strength, vibration, and stress distribution.

[0045] Next, based on the basic information of the target device, a layout-induced risk prediction model is used to perform multi-dimensional induced risk prediction for each layout adjustment scheme within the first layout adjustment space. Specifically, basic information of the target device is collected, including its material properties, dimensions, and operating conditions, and this information is input into the layout-induced risk prediction model. Then, based on this data and the risk prediction model, each layout adjustment scheme is evaluated, and its corresponding layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk are calculated. The evaluation results are presented in the form of an induced risk prediction map, with each layout adjustment scheme corresponding to three risk coefficients, representing the layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk, respectively.

[0046] Subsequently, based on the induced risk prediction map, the first layout adjustment space is optimized for induced failure risk according to the layout-induced failure risk threshold. The layout-induced failure risk threshold can be predetermined based on the device's reliability requirements. During this process, the failure risk of each layout adjustment scheme is evaluated. If the failure risk of a scheme is lower than the preset threshold, it is considered a valid scheme and added to the first layout optimization guidance domain. This ensures that the finally selected layout scheme will not generate excessively high failure risks in practical applications.

[0047] Next, based on the induced risk prediction map, the first layout adjustment space is optimized for induced aging risk according to the layout-induced aging risk threshold. The layout-induced aging risk threshold is predetermined based on the expected lifespan and aging characteristics of the device. By evaluating the aging risk coefficient of each layout adjustment scheme in the induced risk prediction map, layout adjustment schemes with aging risk coefficients lower than or equal to the layout-induced aging risk threshold are selected, forming the second layout optimization guidance domain. This method ensures that the selected layout scheme will not experience performance degradation or failure due to excessively rapid aging during long-term use.

[0048] Then, based on the induced risk prediction map, the first layout adjustment space is optimized for induced performance risk according to the layout-induced performance risk threshold. The layout-induced performance risk threshold is predetermined based on the electrical and mechanical performance requirements of the device. By evaluating the performance risk coefficient of each layout adjustment scheme in the induced risk prediction map, layout adjustment schemes with performance risk coefficients lower than or equal to the performance risk threshold are selected, forming the third layout optimization guidance domain. This process ensures that the selected layout can maintain good electrical and mechanical performance under different application conditions, avoiding excessive stress and uneven current distribution.

[0049] Finally, the first, second, and third layout optimization guidance domains are merged to form multiple layout optimization guidance domains. These guidance domains contain layout adjustment schemes that perform well in terms of failure risk, aging risk, and performance risk, and can provide specific guidance for subsequent layout optimization, enabling the selected layout scheme to maintain high reliability and performance in multiple scenarios.

[0050] P60: Based on the layout-induced risk prediction model, the first layout adjustment space is globally guided to reproduce and optimize according to the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

[0051] Furthermore, step P60 in this embodiment of the application also includes: P61: Based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the first layout optimization guidance domain to obtain the second layout adjustment space; P62: Based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the second layout optimization guidance domain to obtain the third layout adjustment space; P63: Based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the third layout optimization guidance domain to obtain the fourth layout adjustment space; P64: The second layout adjustment space, the third layout adjustment space, and the fourth layout adjustment space are merged to obtain the fifth layout adjustment space; P65: The layout-induced global risk analysis model is obtained by weighting multiple indicators of layout-induced risk; P66: The fifth layout adjustment space is optimized to minimize the global risk of layout-induced risk according to the layout-induced global risk analysis model to generate the IGBT layout optimization result.

[0052] Specifically, based on the layout-induced risk prediction model, the system analyzes multiple layout optimization guidance domains to perform global guidance and breeding optimization, and continuously optimizes the layout space to generate the optimal layout scheme.

[0053] First, based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the first layout optimization guidance domain. Specifically, representative layout adjustment schemes are selected from the first layout optimization guidance domain as initial schemes for guided propagation. Using a genetic algorithm or similar optimization algorithm, these initial schemes are propagated and mutated to generate new layout adjustment schemes. These new schemes can further explore better layout possibilities while maintaining the characteristics of the original optimization guidance domain, forming a second layout adjustment space.

[0054] Next, based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the second layout optimization guidance domain. For example, representative layout adjustment schemes are selected from the second layout optimization guidance domain as initial schemes for guided propagation. Similarly, using a genetic algorithm or similar optimization algorithm, these initial schemes are propagated and mutated to generate new layout adjustment schemes. These new schemes can further explore better layout possibilities, forming a third layout adjustment space.

[0055] Subsequently, based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the third layout optimization guidance domain. Specifically, representative layout adjustment schemes are selected from the third layout optimization guidance domain as initial schemes for guided propagation. Using a genetic algorithm or similar optimization algorithm, these initial schemes are propagated and mutated to generate new layout adjustment schemes. These new schemes can further explore better layout possibilities, forming a fourth layout adjustment space.

[0056] Next, the second, third, and fourth layout adjustment spaces are merged, meaning all layout adjustment schemes from the three spaces are summarized to form a comprehensive fifth layout adjustment space. This space contains optimized layout schemes under different risk indicators, providing a rich pool of candidate solutions for subsequent global risk assessments.

[0057] Then, a layout-induced global risk analysis model is obtained by weighting multiple indicators of layout-induced risk. The weight configuration can be adjusted according to the actual application requirements and design goals of the device. For example, if the device has high reliability requirements, the weight of failure risk can be set higher. Based on these weights, a layout-induced global risk analysis model is constructed, which can be represented as a function, for example: Global Risk = w1 × Failure Risk + w2 × Aging Risk + w3 × Performance Risk, where w1, w2, and w3 are the weights of failure risk, aging risk, and performance risk, respectively.

[0058] Finally, the layout-induced global risk is minimized in the fifth layout adjustment space based on the layout-induced global risk analysis model. Specifically, each layout adjustment scheme in the fifth layout adjustment space is input into the layout-induced global risk analysis model, and the global risk value of each scheme is calculated. Optimization algorithms, such as genetic algorithms and simulated annealing algorithms, are used to find the layout scheme with the minimum global risk in the fifth layout adjustment space, generating the IGBT layout optimization result. This result minimizes the global risk by comprehensively considering failure risk, aging risk, and performance risk. By minimizing the risk, the final generated layout scheme not only meets the performance requirements but also provides higher stability and reliability in practical applications.

[0059] Furthermore, step P61 in the embodiments of this application also includes: P61-1: Perform difference analysis on the first layout adjustment space based on the first layout optimization guidance domain to obtain a layout adjustment difference feature set; P61-2: Based on the layout adjustment difference feature set, guide the first layout adjustment space to mutate to obtain a first layout mutation group; P61-3: Perform multi-scenario coupled heat dissipation performance analysis and optimization on the first layout mutation group based on the D certain application scenarios to obtain a second layout mutation group; P61-4: Based on the layout-induced failure risk threshold, layout-induced aging risk threshold, and layout-induced performance risk threshold, perform multi-risk constraint joint optimization on the second layout mutation group according to the layout-induced risk prediction model to generate the second layout adjustment space.

[0060] Optionally, the process of generating the second layout adjustment space can be further refined to optimize the layout adjustment space more precisely. First, the first layout adjustment space is analyzed for differences based on the first layout optimization guiding domain. Specifically, by calculating the differences between different layout schemes, key features affecting layout performance, such as heat dissipation efficiency, electrical performance, and mechanical strength, are extracted. These difference features are then summarized to form a layout adjustment difference feature set, providing a basis for subsequent mutation operations.

[0061] Next, based on the layout adjustment difference feature set, the first layout adjustment space is guided to mutate. That is, using the difference feature set as guidance, the corresponding difference features of the layout schemes within the first layout adjustment space are mutated to generate a new layout group. Mutation operations can include position adjustments, size changes, and changes in connection methods. Through mutation operations in the genetic algorithm, a new set of layout adjustment schemes is generated, forming the first layout mutation group. These mutation schemes, while maintaining the characteristics of the original layout adjustment space, introduce new changes, allowing for the exploration of better layout possibilities.

[0062] Next, based on D certain application scenarios, the first layout variant group undergoes multi-scenario coupled heat dissipation performance analysis and optimization. First, for each layout adjustment scheme in the first layout variant group, heat dissipation performance simulation is performed based on D certain application scenarios. Thermal simulation software (such as ANSYS Fluent or COMSOL Multiphysics) can be used to perform detailed heat dissipation performance analysis for each scheme, and the coupled heat dissipation coefficient for each scheme under D application scenarios is calculated to evaluate whether its heat dissipation performance meets the coupled heat dissipation threshold requirement. Layout adjustment schemes with a coupled heat dissipation coefficient greater than or equal to the coupled heat dissipation threshold are selected to form the second layout variant group.

[0063] Finally, based on the layout-induced failure risk threshold, layout-induced aging risk threshold, and layout-induced performance risk threshold, the second layout variant group is jointly optimized by multiple risk constraints according to the layout-induced risk prediction model. In other words, these layout variant schemes need to simultaneously satisfy the above risk thresholds.

[0064] For example, for each layout adjustment scheme in the second layout variant group, a layout-induced risk prediction model is used for risk assessment. The assessment includes layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk. Next, based on preset failure risk thresholds, aging risk thresholds, and performance risk thresholds, layout adjustment schemes that simultaneously meet the following conditions are selected: layout-induced failure risk is less than the failure risk threshold, layout-induced aging risk is less than the aging risk threshold, and layout-induced performance risk is less than the performance risk threshold. Finally, layout adjustment schemes that meet the above conditions are summarized to form the second layout adjustment space. The generated second layout adjustment space contains layout schemes that satisfy all risk constraints, providing a more feasible and stable adjustment space for subsequent layout optimization, ensuring the reliability and stability of the optimization results.

[0065] In summary, the embodiments of this application have at least the following technical effects: This application optimizes IGBT layout schemes through multi-scenario coupled heat dissipation performance testing, thereby effectively improving the heat dissipation capacity of the devices; based on a layout-induced risk prediction model, it reduces the failure risk caused by improper layout, ensuring stable operation of the devices under high loads; by optimizing the layout scheme, it reduces material aging caused by factors such as temperature fluctuations, extending the service life of IGBT devices; by combining electrical and mechanical performance analysis, it optimizes the layout, reducing performance degradation caused by unreasonable layout; by considering optimization of multiple application scenarios, it ensures that the layout scheme adapts to different working environments, improving the overall stability of the system; and by comprehensively controlling risks and optimizing heat dissipation performance, it ensures the reliability of the devices in long-term operation, avoiding overheating and failure.

[0066] The technology achieves the effect of improving the heat dissipation performance and adaptability of IGBTs under multiple operating conditions and reducing the risk of overheating failure by coupling heat dissipation performance testing in multiple scenarios and optimizing multiple risk constraints.

[0067] Example 2, based on the same inventive concept as the IGBT layout optimization method based on heat dissipation performance analysis in the foregoing examples, such as... Figure 2 As shown, this application provides an IGBT layout optimization platform based on heat dissipation performance analysis. The platform and method embodiments in this application are based on the same inventive concept. The platform includes: The thermal characteristic modeling module 11 is used to collect the IGBT layout information of the target device, generate the current layout scheme, and perform thermal characteristic modeling of the target device based on the current layout scheme to obtain the device heat conduction model.

[0068] The application scenario mining module 12 is used to mine application scenarios based on the device model characteristics of the target device to obtain D certain application scenarios, where D is a positive integer greater than 1.

[0069] The heat dissipation performance detection module 13 is used to perform multi-scenario coupled heat dissipation performance detection on the thermal conduction model of the device according to the D certain application scenarios, and obtain the current coupled heat dissipation coefficient.

[0070] The multi-scenario coupling optimization module 14 is used to perform multi-scenario coupling optimization on the current layout scheme based on the current coupling heat dissipation coefficient and according to the D certain application scenarios to obtain the first layout adjustment space.

[0071] The multilateral risk optimization module 15 is used to perform multilateral risk optimization on the first layout adjustment space through the layout-induced risk prediction model to obtain multiple layout optimization guidance domains.

[0072] The global guided breeding optimization module 16 is used to perform global guided breeding optimization on the first layout adjustment space based on the layout-induced risk prediction model and according to the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

[0073] Furthermore, the thermal characteristic modeling module 11 is also used to perform the following steps: Application scenario records are collected based on the target device to obtain a first historical application scenario library; application scenario records are collected based on the device model characteristics to obtain a second historical application scenario library; a first historical application scenario is extracted from the first historical application scenario library, and the trigger frequency of the first historical application scenario is statistically analyzed based on the first historical application scenario library to obtain a first scenario local trigger degree; the trigger frequency of the first historical application scenario is statistically analyzed based on the second historical application scenario library to obtain a first scenario global trigger degree; the average of the first scenario local trigger degree and the first scenario global trigger degree is calculated to obtain a first scenario confidence degree; if the first scenario confidence degree is greater than or equal to a predetermined scenario confidence degree, the first historical application scenario is recorded as a first confident application scenario, and the first confident application scenario is added to the D confident application scenarios.

[0074] Furthermore, the application scenario mining module 12 is also used to perform the following steps: Based on the D confirmed application scenarios, heat dissipation simulations are performed on the device's heat conduction model to obtain D scenario heat dissipation simulation data. Using scenario heat dissipation monitoring records as input data and scenario heat dissipation performance evaluation records as output data, a fully connected neural network is trained under supervision to obtain a heat dissipation performance evaluation network. The D scenario heat dissipation simulation data are input into the heat dissipation performance evaluation network to obtain D scenario heat dissipation performance coefficients. The importance of heat dissipation performance is evaluated based on the D confirmed application scenarios to obtain a scenario heat dissipation importance evaluation set. Weights are then configured for the D confirmed application scenarios based on the scenario heat dissipation importance evaluation set to obtain D scenario heat dissipation weights. The D scenario heat dissipation performance coefficients are then weighted and fused based on the D scenario heat dissipation weights to generate the current coupled heat dissipation coefficient.

[0075] Furthermore, the heat dissipation performance detection module 13 is also used to perform the following steps: If the current coupling heat dissipation coefficient is less than the coupling heat dissipation threshold, adjust the current layout scheme to obtain a layout adjustment scheme set; extract the nth layout adjustment scheme based on the layout adjustment scheme set, where n is a positive integer; perform thermal characteristic modeling of the target device based on the nth layout adjustment scheme to obtain the nth layout heat conduction model; perform multi-scenario coupling heat dissipation performance testing on the nth layout heat conduction model based on the D certain application scenarios to obtain the nth coupling heat dissipation coefficient; if the nth coupling heat dissipation coefficient is greater than or equal to the coupling heat dissipation threshold, add the nth layout adjustment scheme to the first layout adjustment space.

[0076] Furthermore, the multi-scene coupling optimization module 14 is also used to perform the following steps: Activate the layout-induced risk prediction model, which includes multiple layout-induced risk indicators, including layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk. Based on the device basic information of the target device, perform multi-dimensional induced risk prediction for each layout adjustment scheme within the first layout adjustment space according to the layout-induced risk prediction model to obtain an induced risk prediction map. Based on the induced risk prediction map, optimize the induced failure risk of the first layout adjustment space according to the layout-induced failure risk threshold to obtain a first layout optimization guidance domain. Based on the induced risk prediction map, optimize the induced aging risk of the first layout adjustment space according to the layout-induced aging risk threshold to obtain a second layout optimization guidance domain. Based on the induced risk prediction map, optimize the induced performance risk of the first layout adjustment space according to the layout-induced performance risk threshold to obtain a third layout optimization guidance domain. Incorporate the first layout optimization guidance domain, the second layout optimization guidance domain, and the third layout optimization guidance domain into the plurality of layout optimization guidance domains.

[0077] Furthermore, the multilateral risk optimization module 15 is also used to perform the following steps: Based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the first layout optimization guidance domain to obtain a second layout adjustment space; based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the second layout optimization guidance domain to obtain a third layout adjustment space; based on the layout-induced risk prediction model, the first layout adjustment space is guided to undergo propagation optimization according to the third layout optimization guidance domain to obtain a fourth layout adjustment space; the second layout adjustment space, the third layout adjustment space, and the fourth layout adjustment space are merged to obtain a fifth layout adjustment space; a layout-induced global risk analysis model is obtained by weighting multiple indicators of layout-induced risk; the fifth layout adjustment space is optimized to minimize the layout-induced global risk according to the layout-induced global risk analysis model to generate the IGBT layout optimization result.

[0078] Furthermore, the global guided reproduction optimization module 16 is also used to perform the following steps: The first layout adjustment space is analyzed for differences based on the first layout optimization guidance domain to obtain a layout adjustment difference feature set; based on the layout adjustment difference feature set, the first layout adjustment space is guided to mutate to obtain a first layout mutation group; the first layout mutation group is analyzed and optimized for multi-scenario coupled heat dissipation performance based on the D certain application scenarios to obtain a second layout mutation group; based on the layout-induced failure risk threshold, the layout-induced aging risk threshold, and the layout-induced performance risk threshold, the second layout mutation group is jointly optimized for multiple risk constraints based on the layout-induced risk prediction model to generate the second layout adjustment space.

[0079] Furthermore, the global guided reproduction optimization module 16 is also used to perform the following steps: Based on the target device, a basic feature reconstruction is performed to obtain a three-dimensional model of the device; based on the current layout scheme, a three-dimensional reconstruction is performed to obtain an IGBT layout model; based on the IGBT layout model, the model parameters of the three-dimensional model of the device are enhanced to generate a thermal conduction model of the device.

[0080] In Example 3, based on the same inventive concept as the IGBT layout optimization method based on heat dissipation performance analysis in the foregoing examples, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method as described in Example 1.

[0081] Through the foregoing detailed description of the IGBT layout optimization method based on heat dissipation performance analysis, those skilled in the art will clearly understand that this application provides an IGBT layout optimization platform based on heat dissipation performance analysis. Therefore, for the sake of brevity, further details are omitted here. As the platform disclosed in the embodiments corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be found in the method section.

[0082] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0083] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0084] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0085] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. An IGBT layout optimization method based on heat dissipation performance analysis, characterized in that, include: Collect IGBT layout information of the target device, generate the current layout scheme, and perform thermal characteristic modeling of the target device based on the current layout scheme to obtain the device heat conduction model; Application scenarios are mined based on the device model characteristics of the target device to obtain D certain application scenarios, where D is a positive integer greater than 1; Based on the D confirmed application scenarios, the thermal conduction model of the device is tested for multi-scenario coupled heat dissipation performance to obtain the current coupled heat dissipation coefficient. Based on the current coupling heat dissipation coefficient, the current layout scheme is optimized for multi-scenario coupling according to the D certain application scenarios to obtain the first layout adjustment space; By using a layout-induced risk prediction model, the first layout adjustment space is optimized through multilateral risk search to obtain multiple layout optimization guidance domains. Based on the layout-induced risk prediction model, the first layout adjustment space is globally guided and optimized according to the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

2. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, Based on the device model characteristics of the target device, application scenarios are mined to obtain D definite application scenarios, including: Based on the target device, application scenarios are recorded and collected to obtain a first historical application scenario library; Based on the characteristics of the device model, application scenarios are recorded and collected to obtain a second historical application scenario library; The first historical application scenario is extracted from the first historical application scenario library, and the trigger frequency of the first historical application scenario is statistically analyzed based on the first historical application scenario library to obtain the local triggering degree of the first scenario. Based on the second historical application scenario library, the trigger frequency of the first historical application scenario is statistically analyzed to obtain the global triggering degree of the first scenario; The confidence level of the first scene is obtained by averaging the local triggering degree and the global triggering degree of the first scene. If the confidence level of the first scenario is greater than or equal to the confidence level of the predetermined scenario, the first historical application scenario is recorded as the first confident application scenario, and the first confident application scenario is added to the D confident application scenarios.

3. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, Based on the D confirmed application scenarios, the thermal conduction model of the device is tested for multi-scenario coupled heat dissipation performance to obtain the current coupled heat dissipation coefficient, including: Based on the D known application scenarios, heat dissipation simulations were performed on the thermal conduction model of the device to obtain heat dissipation simulation data for the D scenarios. Using scene heat dissipation monitoring records as input data and scene heat dissipation performance evaluation records as output data, a fully connected neural network is trained under supervision to obtain a heat dissipation performance evaluation network. The heat dissipation simulation data of the D scenarios are input into the heat dissipation performance evaluation network to obtain the heat dissipation performance coefficients of the D scenarios. The importance of heat dissipation performance is evaluated based on the D confirmed application scenarios to obtain a scenario heat dissipation importance evaluation set. The D confirmed application scenarios are then weighted according to the scenario heat dissipation importance evaluation set to obtain D scenario heat dissipation weights. The current coupled heat dissipation coefficient is generated by weighting and fusing the heat dissipation performance coefficients of the D scenes according to the heat dissipation weights of the D scenes.

4. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, Based on the current coupled heat dissipation coefficient, the current layout scheme is optimized for multi-scenario coupling according to the D certain application scenarios to obtain a first layout adjustment space, including: If the current coupling heat dissipation coefficient is less than the coupling heat dissipation threshold, adjust the current layout scheme to obtain a set of layout adjustment schemes; Extract the nth layout adjustment scheme from the set of layout adjustment schemes, where n is a positive integer; Based on the nth layout adjustment scheme, perform thermal characteristic modeling of the target device to obtain the nth layout heat conduction model; Based on the D confirmed application scenarios, the nth layout heat conduction model is tested for multi-scenario coupled heat dissipation performance to obtain the nth coupled heat dissipation coefficient. If the nth coupling heat dissipation coefficient is greater than or equal to the coupling heat dissipation threshold, the nth layout adjustment scheme is added to the first layout adjustment space.

5. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, By using a layout-induced risk prediction model to perform multilateral risk optimization on the first layout adjustment space, multiple layout optimization guidance domains are obtained, including: Activate the layout-induced risk prediction model, which includes multiple layout-induced risk indicators, including layout-induced failure risk, layout-induced aging risk, and layout-induced performance risk. Based on the device basic information of the target device, the multi-dimensional induced risk prediction is performed on each layout adjustment scheme in the first layout adjustment space according to the layout induced risk prediction model to obtain the induced risk prediction map. Based on the induced risk prediction map, the first layout adjustment space is optimized for induced failure risk according to the layout induced failure risk threshold to obtain the first layout optimization guidance domain. Based on the induced risk prediction map, the first layout adjustment space is optimized for induced aging risk according to the layout induced aging risk threshold to obtain the second layout optimization guidance domain. Based on the induced risk prediction map, the first layout adjustment space is optimized for induced performance risk according to the layout induced performance risk threshold to obtain the third layout optimization guidance domain. The first layout optimization guide domain, the second layout optimization guide domain, and the third layout optimization guide domain are incorporated into the plurality of layout optimization guide domains.

6. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, Based on the aforementioned layout-induced risk prediction model, the first layout adjustment space is globally guided and optimized according to the multiple layout optimization guidance domains to obtain IGBT layout optimization results, including: Based on the layout-induced risk prediction model, the first layout adjustment space is guided to reproduce and optimize according to the first layout optimization guidance domain to obtain the second layout adjustment space. Based on the layout-induced risk prediction model, the first layout adjustment space is guided to reproduce and optimize according to the second layout optimization guidance domain to obtain the third layout adjustment space. Based on the layout-induced risk prediction model, the first layout adjustment space is guided to reproduce and optimize according to the third layout optimization guidance domain to obtain the fourth layout adjustment space. The second layout adjustment space, the third layout adjustment space, and the fourth layout adjustment space are merged to obtain the fifth layout adjustment space; By assigning weights to multiple indicators of layout-induced risk, a global risk analysis model for layout-induced risk is obtained. Based on the layout-induced global risk analysis model, the fifth layout adjustment space is optimized to minimize the layout-induced global risk, and the IGBT layout optimization result is generated.

7. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 6, characterized in that, Based on the layout-induced risk prediction model, the first layout adjustment space is guided and optimized according to the first layout optimization guidance domain to obtain the second layout adjustment space, including: Based on the first layout optimization guidance domain, the first layout adjustment space is analyzed for differences to obtain a layout adjustment difference feature set; Based on the layout adjustment difference feature set, the first layout adjustment space is guided to mutate to obtain the first layout mutation group; Based on the D known application scenarios, the first layout variant group is analyzed and optimized for multi-scenario coupled heat dissipation performance to obtain the second layout variant group. Based on the layout-induced failure risk threshold, the layout-induced aging risk threshold, and the layout-induced performance risk threshold, the second layout variant group is jointly optimized under multiple risk constraints according to the layout-induced risk prediction model to generate the second layout adjustment space.

8. The IGBT layout optimization method based on heat dissipation performance analysis as described in claim 1, characterized in that, Based on the current layout scheme, thermal characteristic modeling of the target device is performed to obtain the device's heat conduction model, including: Based on the target device, the basic features are reconstructed to obtain a three-dimensional model of the device; Perform 3D reconstruction based on the current layout scheme to obtain the IGBT layout model; The device's three-dimensional model is enhanced with model parameters based on the IGBT layout model to generate the device's thermal conduction model.

9. An IGBT layout optimization platform based on heat dissipation performance analysis, characterized in that, The platform is used to execute the IGBT layout optimization method based on thermal performance analysis as described in any one of claims 1 to 8, and the platform comprises: The thermal characteristic modeling module is used to collect the IGBT layout information of the target device, generate the current layout scheme, and perform thermal characteristic modeling of the target device based on the current layout scheme to obtain the device heat conduction model. The application scenario mining module is used to mine application scenarios based on the device model characteristics of the target device to obtain D certain application scenarios, where D is a positive integer greater than 1. The heat dissipation performance detection module is used to perform multi-scenario coupled heat dissipation performance detection on the heat conduction model of the device according to the D certain application scenarios, and obtain the current coupled heat dissipation coefficient. A multi-scenario coupling optimization module is used to perform multi-scenario coupling optimization on the current layout scheme based on the current coupling heat dissipation coefficient and according to the D certain application scenarios to obtain a first layout adjustment space. The multilateral risk optimization module is used to perform multilateral risk optimization on the first layout adjustment space through the layout-induced risk prediction model to obtain multiple layout optimization guidance domains. The global guided breeding optimization module is used to perform global guided breeding optimization on the first layout adjustment space based on the layout-induced risk prediction model and according to the multiple layout optimization guidance domains to obtain IGBT layout optimization results.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the IGBT layout optimization method based on thermal performance analysis as described in any one of claims 1 to 8.

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