High-low side power tube driving circuit directly charged by input voltage and step-down converter of high-low side power tube driving circuit

Abstract

The invention discloses a high-low side power tube driving circuit directly charged by input voltage and a buck converter thereof, the high-low side power tube driving circuit comprises an enable circuit, a voltage clamping circuit, a level selection circuit and a driving circuit, the enable circuit is used for outputting a first enable signal and a level selection signal according to a high side power tube control signal, and the voltage clamping circuit is used for clamping the level selection signal; or outputting a second enable signal and a level selection signal according to the low-side power tube control signal; the voltage clamping circuit is used for generating a first floating level or a second floating level; the level selection circuit is used for selecting the first floating level or the internal power supply level as the power supply level according to the level selection signal, or selecting the second floating level or the internal power supply level as the power supply level according to the level selection signal; the driving circuit is used for charging the high-side power tube or the low-side power tube through a power supply level. While the load requirement on the internal linear voltage regulator is reduced, enough power tube driving capability can be maintained, and the linear voltage regulator can be widely applied to the technical field of circuit design.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and in particular to a high- and low-side power transistor drive circuit that directly charges the input voltage and its buck converter. Background Technology

[0002] A wide-input-range buck converter (Buck) with an integrated internal power supply module requires a high input voltage, but the power transistor drive circuit still needs a low-voltage power supply. Driving the power transistor consumes a significant amount of current; if the drive circuit is powered solely by the internal power supply level, the internal power supply module needs to have a higher load-carrying capacity, increasing the design complexity of the internal power supply module and potentially requiring the use of large external capacitors. Summary of the Invention

[0003] To solve the above-mentioned technical problems, the purpose of this application is to provide a high- and low-side power transistor drive circuit and its buck converter that can directly charge the input voltage, while maintaining sufficient power transistor drive capability.

[0004] To achieve the above objectives, one aspect of this application provides a high- and low-side power transistor drive circuit for direct charging with input voltage, comprising: The enable circuit is used to input the internal power supply level, input voltage, high-side power transistor control signal or low-side power transistor control signal, and then output a first enable signal and a level selection signal according to the high-side power transistor control signal, or output a second enable signal and a level selection signal according to the low-side power transistor control signal. A voltage clamping circuit, connected to the output of the enable circuit, is used to generate a first floating level based on the input voltage and the first enable signal, or to generate a second floating level based on the input voltage and the second enable signal; A level selection circuit, connected to the output terminal of the voltage clamping circuit, is used to select either the first floating level or the internal power supply level as the power supply level according to the level selection signal, or to select either the second floating level or the internal power supply level as the power supply level according to the level selection signal. A driving circuit, connected to the output of the level selection circuit, is used to charge the high-side power transistor or the low-side power transistor through the power supply level.

[0005] In some embodiments, the level selection signal includes a first level selection signal, and the enable circuit includes: A first delay unit and a first NAND gate, wherein the first input terminal of the first NAND gate is connected to the high-side power transistor control signal through the first delay unit, and the second input terminal of the first NAND gate is connected to the high-side power transistor control signal, for outputting the first level selection signal according to the high-side power transistor control signal; A first level shifting circuit is connected to the output of the first NAND gate and is used to output the first enable signal according to the internal power supply level, the input voltage and the first level selection signal.

[0006] In some embodiments, the level selection signal includes a first level selection signal and a second level selection signal, and the enable circuit includes: The second delay unit and the second NAND gate, the first input terminal of the second NAND gate is connected to the low-side power transistor control signal through the second delay unit, and the second input terminal of the second NAND gate is connected to the low-side power transistor control signal, for outputting a control signal according to the low-side power transistor control signal; An AND gate, wherein the first input terminal of the AND gate is connected to the low-side power transistor control signal, and the second input terminal of the AND gate is connected between the second delay unit and the second NAND gate, for outputting the first level selection signal according to the low-side power transistor control signal; The NOT gate, whose input is connected to the output of the AND gate, is used to output the second level selection signal according to the first level selection signal; The second level shift circuit is connected to the output of the second NAND gate and is used to output the second enable signal according to the internal power supply level, the input voltage and the control signal.

[0007] In some embodiments, the voltage clamping circuit includes: A power transistor and a diode are provided, wherein the gate of the power transistor is connected to the output terminal of the enable circuit, the drain of the power transistor is connected to the input voltage, the source of the power transistor is connected to the negative terminal of the diode, and the positive terminal of the diode is grounded. The power transistor is used to generate the first floating level according to the input voltage and the first enable signal, or to generate the second floating level according to the input voltage and the second enable signal.

[0008] In some embodiments, the level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: A first transistor and a second transistor, wherein the gate of the first transistor is connected to the first level selection signal, the drain of the first transistor is connected to the voltage clamping circuit, the gate of the second transistor is connected to the second level selection signal, and the drain of the second transistor is connected to the internal power supply level, for selecting either the first floating level or the internal power supply level as the power supply level according to the first level selection signal and the second level selection signal.

[0009] In some embodiments, the level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: A third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the first level selection signal, the drain of the third transistor is connected to the voltage clamping circuit, the gate of the fourth transistor is connected to the second level selection signal, and the drain of the fourth transistor is connected to the internal power supply level, for selecting the second floating level or the internal power supply level as the power supply level according to the first level selection signal and the second level selection signal.

[0010] In some embodiments, the driving circuit includes: The third level shifting circuit is connected to the output of the level selection circuit and is used to charge the high-side power transistor through the power supply level.

[0011] In some embodiments, the driving circuit includes: An inverter chain, connected to the output of the level selection circuit, is used to charge the low-side power transistor through the power supply level.

[0012] To achieve the above objectives, another aspect of the embodiments of this application proposes a buck converter, including a high-side power transistor, a low-side power transistor, and a high- and low-side power transistor driving circuit as described above, wherein the gate of the high-side power transistor and the gate of the low-side power transistor are both connected to the output terminal of the high- and low-side power transistor driving circuit.

[0013] In some embodiments, the buck converter further includes an internal power supply module, a voltage reference module, an error amplifier, a compensation network, a comparator, an inductor current detection module, a conduction time generation module, a zero-crossing detection module, and a dead-time logic module. The output of the dead-time logic module is connected to the input of the high-side and low-side power transistor drive circuit and is used to output the high-side power transistor control signal and the low-side power transistor control signal.

[0014] The beneficial effects of this application are as follows: This application provides a high-side and low-side power transistor drive circuit and its buck converter that directly charges based on input voltage. The circuit includes an enable circuit, a voltage clamping circuit, a level selection circuit, and a drive circuit. The enable circuit outputs a first enable signal and a level selection signal based on the high-side power transistor control signal, or outputs a second enable signal and a level selection signal based on the low-side power transistor control signal. The voltage clamping circuit generates a first floating level based on the input voltage and the first enable signal, or generates a second floating level based on the input voltage and the second enable signal. The level selection circuit selects either the first floating level or the internal power supply level as the power supply level based on the level selection signal, or selects either the second floating level or the internal power supply level as the power supply level based on the level selection signal. The drive circuit charges the high-side or low-side power transistor. Based on the enable signal and the level selection signal, the drive circuit consumes current to charge the gate of the high-side or low-side power transistor. The current is provided by the input voltage through the voltage clamping circuit or by the internal power supply level output from the internal power supply module. This reduces the load requirements on the internal linear regulator while maintaining sufficient power transistor driving capability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a block diagram of a high- and low-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application; Figure 2 A block diagram of the high- and low-side power transistor drive circuit for direct charging provided in one embodiment of this application during the charging stage; Figure 3 A block diagram of the high- and low-side power transistor drive circuit for direct input charging provided in an embodiment of this application, in a holding state; Figure 4 A circuit schematic diagram of a high-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application; Figure 5 A waveform diagram of the high-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application; Figure 6 A circuit schematic of a low-side power transistor drive circuit that directly charges the input voltage according to one embodiment of this application; Figure 7A waveform diagram of the low-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application; Figure 8 This is a circuit schematic diagram of a level shifting circuit provided in one embodiment of this application; Figure 9 This is a waveform diagram of the operation of a level shifting circuit provided in one embodiment of this application; Figure 10 A circuit diagram of an ultra-low power buck converter with wide input and wide load using high-side and low-side power transistor drive circuits provided in one embodiment of this application; Figure 11 This is a waveform diagram of a buck converter under heavy load according to an embodiment of this application. Figure 12 The waveform diagram of the buck converter under heavy load provided in another embodiment of this application; Figure 13 The figure shows the simulation results of the energy conversion efficiency of a buck converter provided in one embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0018] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0019] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0020] A wide-input-range buck converter (Buck) with an integrated internal power supply module requires a high input voltage, but the power transistor drive circuit still needs a low-voltage power supply. Driving the power transistor consumes a significant amount of current; if the drive circuit is powered solely by the internal power supply level, the internal power supply module needs to have a higher load-carrying capacity, increasing the design complexity of the internal power supply module and potentially requiring the use of large external capacitors. Existing technologies have the following shortcomings: First, the input voltage of a wide-input buck converter is high, requiring high-voltage MOSFETs for both the high-side and low-side power transistors. While the drain-to-source voltage of a high-voltage MOSFET is high, the gate-to-source voltage remains low, necessitating a low-voltage power supply for the corresponding drive circuit.

[0021] Secondly, integrating an internal power supply module into a wide-input buck converter can avoid the need for additional low-voltage inputs. The drive circuits for large-area power transistors consume significant current. If the internal power supply module is used directly, and its load-carrying capacity and transient response are insufficient, the current consumed by the power transistors will affect the voltage regulation of the internal power supply level, thus impacting the normal operation of the converter.

[0022] In view of this, this application proposes a high-side and low-side power transistor drive circuit for direct input voltage charging, including an enable circuit, a voltage clamping circuit, a level selection circuit, and a drive circuit. The enable circuit outputs a first enable signal and a level selection signal based on the high-side power transistor control signal, or outputs a second enable signal and a level selection signal based on the low-side power transistor control signal. The voltage clamping circuit generates a first floating level based on the input voltage and the first enable signal, or generates a second floating level based on the input voltage and the second enable signal. The level selection circuit selects either the first floating level or the internal power supply level as the power supply level based on the level selection signal, or selects either the second floating level or the internal power supply level as the power supply level based on the level selection signal. The drive circuit charges the high-side or low-side power transistor. This application charges the gate of the high-side or low-side power transistor by consuming current through the drive circuit based on the enable signal and the level selection signal. The current is provided by the input voltage through the voltage clamping circuit or by the internal power supply level output by the internal power supply module. This reduces the load requirements on the internal linear regulator while maintaining sufficient power transistor driving capability.

[0023] Reference Figure 1 , Figure 1 This is a structural block diagram of a high- and low-side power transistor driving circuit for direct input voltage charging according to an embodiment of this application. The embodiment of this application proposes a high- and low-side power transistor driving circuit for direct input voltage charging, comprising: The enable circuit is used to input the internal power supply level, input voltage, high-side power transistor control signal or low-side power transistor control signal, and then output a first enable signal and a level selection signal according to the high-side power transistor control signal, or output a second enable signal and a level selection signal according to the low-side power transistor control signal. A voltage clamping circuit, connected to the output of an enable circuit, is used to generate a first floating level based on the input voltage and a first enable signal, or to generate a second floating level based on the input voltage and a second enable signal. The level selection circuit is connected to the output of the voltage clamping circuit and is used to select either the first floating level or the internal power supply level as the power supply level according to the level selection signal, or to select either the second floating level or the internal power supply level as the power supply level according to the level selection signal. The driving circuit, connected to the output of the level selection circuit, is used to charge the high-side power transistor or the low-side power transistor by the power supply level.

[0024] It should be noted that, as Figure 2 The diagram shows the structural framework of a high-side and low-side power transistor drive circuit for direct input charging according to an embodiment of this application during the charging phase. The conduction loss of the power transistor is proportional to its on-resistance, and the drive loss is proportional to its gate capacitance. To minimize the conduction and on-resistance of the power transistor, it has a large area, and the corresponding power transistor drive circuit also needs sufficient gate drive capability. If the drive circuit is powered by the level (i.e., the internal power supply level) VDD generated by the internal power supply module, the large current required for the power transistor gate charging acts as a heavy load, deteriorating the voltage regulation of the internal power supply level VDD. This deterioration is even more severe when the internal linear regulator has no external capacitor. Therefore, the high-side and low-side power transistor drive circuit proposed in this embodiment enables a floating level Float generated by the input voltage VIN and the voltage clamping circuit through the enable signal EN during the charging phase of the high-side and low-side power transistors, i.e., the turn-on phase of the low-side NMOS power transistor and the turn-off phase of the high-side PMOS power transistor. The floating level Float is then used as the power supply level of the drive circuit through the level selection signals SF and SF.

[0025] like Figure 3 The diagram shows a structural framework of a high- and low-side power transistor drive circuit for direct input charging according to an embodiment of this application in a holding state. When the gate voltage of the power transistor is charged to a level close to the internal supply level VDD, the supply level of the drive circuit switches to the internal supply level VDD, and during the holding phase of the gate signal, the gate signal is held by the internal supply level VDD. The enable signal EN and the level switching signal SF are generated by the high- and low-side power transistor control signals VHS / LS generated by the dead-time logic after passing through the logic circuit, avoiding the current loss caused by the floating level Float being constantly on.

[0026] Reference Figure 4 , Figure 4 The circuit schematic of the high-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application is further illustrated in the optional implementation, where the level selection signal includes a first level selection signal, and the enable circuit includes: The first delay unit and the first NAND gate, the first input terminal of the first NAND gate is connected to the high-side power transistor control signal through the first delay unit, and the second input terminal of the first NAND gate is connected to the high-side power transistor control signal, for outputting a first level selection signal according to the high-side power transistor control signal; The first level shifting circuit is connected to the output of the first NAND gate and is used to output a first enable signal based on the internal power supply level, the input voltage, and the first level selection signal.

[0027] Reference Figure 4 As a further optional implementation, the voltage clamping circuit includes: The power transistor and diode are used to generate a first floating level based on the input voltage and a first enable signal, or a second floating level based on the input voltage and a second enable signal.

[0028] Reference Figure 4 As a further optional implementation, the level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: A first transistor and a second transistor, wherein the gate of the first transistor is connected to a first level selection signal and the drain of the first transistor is connected to a voltage clamping circuit, the gate of the second transistor is connected to a second level selection signal and the drain of the second transistor is connected to an internal power supply level, for selecting a first floating level or an internal power supply level as the power supply level according to the first level selection signal and the second level selection signal.

[0029] Reference Figure 4 As an optional implementation, the driving circuit includes: The third level shifting circuit is connected to the output of the level selection circuit and is used to charge the high-side power transistor through the power supply level.

[0030] In some alternative embodiments, such as Figure 5The diagram shows the operating waveform of a high-side power transistor drive circuit for direct input voltage charging according to an embodiment of this application. VGP is the drive signal for the high-side power transistor, which generates a high-side power transistor control signal VHS through a dead-time logic module. The high-side power transistor control signal VHS passes through a first delay unit and a first NAND gate to generate a first level conversion signal SF. The first level conversion signal SF passes through an NOT gate to obtain an inverse second level conversion signal !SF. The first level conversion signal SF is converted into a first enable signal EN for the power transistor MP1 by a first level shift circuit LS. The voltage range of the first enable signal EN is between the input voltage VIN and the input voltage VIN minus the internal power supply level VDD (VIN-VDD). When the first enable signal EN is low and the second level conversion signal !SF is high, it is the charging stage of the gate of the high-side power transistor MP. The first level conversion signal SF turns on the first transistor M1, and the input voltage VIN is clamped to the first floating level Float by diode D1 through the power transistor MP1, supplying power to the third level shift circuit LS2. At this time, the drive circuit consumes current to charge the gate of the high-side power transistor. The current is provided by the input voltage VIN through the voltage clamping circuit and does not require the internal power supply level VDD. When the first level conversion signal SF is high, the second transistor M2 is turned on, and the internal power supply level VDD supplies power to the third level shift circuit LS2. At this time, the drive circuit does not consume additional current.

[0031] It is understandable that diode D1 can be implemented using a Zener diode, a general diode, a transistor, or a MOSFET connected to a diode.

[0032] Reference Figure 6 , Figure 6 The circuit schematic of a low-side power transistor drive circuit for direct charging of input voltage provided in one embodiment of this application is shown below. Further, as an optional implementation, the level selection signal includes a first level selection signal and a second level selection signal, and the enable circuit includes: The second delay unit and the second NAND gate, the first input terminal of the second NAND gate is connected to the low-side power transistor control signal through the second delay unit, and the second input terminal of the second NAND gate is connected to the low-side power transistor control signal, for outputting a control signal according to the low-side power transistor control signal; The AND gate has its first input connected to the low-side power transistor control signal, and its second input connected between the second delay unit and the second NAND gate, for outputting a first level selection signal according to the low-side power transistor control signal. The NOT gate connects its input to the AND gate's output to select a second-level signal based on a first-level selection signal. The second level shift circuit is connected to the output of the second NAND gate and is used to output a second enable signal based on the internal power supply level, input voltage, and control signal.

[0033] Reference Figure 6 As a further optional implementation, the voltage clamping circuit includes: The power transistor and diode are used to generate a first floating level based on the input voltage and a first enable signal, or a second floating level based on the input voltage and a second enable signal.

[0034] Reference Figure 6 As a further optional implementation, the level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: The third transistor and the fourth transistor have their gates connected to a first level selection signal and their drains connected to a voltage clamping circuit. The gate of the fourth transistor is connected to a second level selection signal and its drain is connected to an internal power supply level. This allows them to select either a second floating level or an internal power supply level as the power supply level based on the first and second level selection signals.

[0035] Reference Figure 6 As an optional implementation, the driving circuit includes: An inverter chain, connected to the output of a level selection circuit, is used to charge the low-side power transistor using the power supply level.

[0036] In some alternative embodiments, such as Figure 7The diagram shows the operating waveforms of a low-side power transistor drive circuit that directly charges the input voltage according to an embodiment of this application. The low-side power transistor control signal VLS generated by the dead-time logic module is processed by the second delay unit and the second NAND gate to generate a control signal EF and a first level selection signal SF. The first level selection signal SF is processed by the NOT gate to generate a second level selection signal ! SF. The control signal EF is converted into a second enable signal EN by the second level shift circuit LS. When the level of the second enable signal EN is VIN-VDD, that is, when the logic is low, it is the charging stage of the low-side power transistor gate. At this time, the first level selection signal SF turns on the third transistor M3. The input voltage VIN passes through the power transistor MP2 and is regulated to the second floating level Float by the diode D2, supplying power to the inverter chain driving the power transistor. The drive circuit consumes current to charge the gate of the low-side power transistor. When the logic of the second level selection signal ! SF is low, the fourth transistor M4 is turned on, and the internal power supply level VDD supplies power to the inverter chain, maintaining the high potential of the low-side power transistor gate. At this time, the low-side power transistor gate potential is the internal power supply level VDD, and the drive circuit does not consume additional current. When the second level selection signal SF is high and the second enable signal EN is high, the inverter chain is not powered and the drive circuit does not consume additional current.

[0037] It is understandable that diode D1 can be implemented using a Zener diode, a general diode, a transistor, or a MOSFET connected to a diode.

[0038] Furthermore, the enabling circuit includes a first level shifting circuit or a second level shifting circuit, and the driving circuit includes a third level shifting circuit. The first level shifting circuit, the second level shifting circuit, and the third level shifting circuit all have the same circuit structure, such as... Figure 8 The diagram shown is a circuit schematic of a level shifting circuit provided in one embodiment of this application. Figure 9 The diagram shows the operating waveform of a level shifting circuit provided in one embodiment of this application. VLG is a low-voltage logic signal, which generates the VGL signal through an inverter chain. When the VGL signal changes, for example, the VGL signal decreases from the VDD level to the VSS level, or increases from the VSS level to the VDD level, the value of capacitor C1 is set to be much larger than the gate capacitance CP of the PMOS transistor MP. Through charge sharing between capacitors C1 and CP, the signal VG decreases from the VIN level to the VIN-VDD level, or increases from the VIN-VDD level to the VIN level. Transistors M1 and M2 are cross-coupled, and capacitor C2 and Zener diode D1 are added to maintain the stability of the signal VG.

[0039] The above describes the structure and working principle of a high- and low-side power transistor drive circuit for direct charging with input voltage according to an embodiment of this application. It can be understood that, compared with existing power transistor drive circuits, the high- and low-side power transistor drive circuit proposed in this application can provide drive signals in the low voltage range, reduce the load design requirements of the internal power supply module, eliminate the need for an external filter capacitor, and has no static power consumption.

[0040] Reference Figure 10 , Figure 10 This is a circuit diagram of an ultra-low power buck converter with wide input and wide load using a high-side and low-side power transistor driving circuit according to an embodiment of this application. The embodiment of this application provides a buck converter including a high-side power transistor, a low-side power transistor, and the aforementioned high-side and low-side power transistor driving circuit. The gates of both the high-side and low-side power transistors are connected to the output terminal of the high-side and low-side power transistor driving circuit.

[0041] Reference Figure 10 As an optional implementation, the buck converter also includes an internal power supply module, a voltage reference module, an error amplifier, a compensation network, a comparator, an inductor current detection module, a conduction time generation module, a zero-crossing detection module, and a dead-time logic module. The output of the dead-time logic module is connected to the input of the high-side and low-side power transistor drive circuits and is used to output the high-side power transistor control signal and the low-side power transistor control signal.

[0042] Specifically, the ultra-low power buck converter with wide input and wide load using the above-mentioned high and low side power transistor drive circuit includes an internal power supply module, a voltage reference module, an error amplifier and corresponding compensation network, a comparator, an inductor current detection module, a conduction time generation module, a zero-crossing detection module, a dead time logic module, a direct input charging drive circuit, and a power stage, etc.

[0043] The comparator employs a conduction time control method. The inductor current detection module converts the inductor current value into an induced voltage VSEN. Through the coupling structure of resistor RF and capacitor CF, the high-frequency component of the induced voltage VSEN from the inductor current detection module is superimposed with the low-frequency component of the output voltage VOUT to form VFB. In CCM mode (Continuous Conduction Mode), VFB is the ramp voltage of the induced voltage VSEN, and VEA is a relatively stable small ripple signal. When VFB drops below VEA, the comparator outputs a signal to the conduction time generation circuit to enable the conduction time. In DCM mode (Discontinuous Conduction Mode), VFB stabilizes to the output voltage VOUT after the inductor current reaches zero, and the VEA ripple increases. When VEA rises above VFB, the comparator outputs a signal to the conduction time generation circuit. After receiving the signal, the conduction time generation circuit generates a corresponding conduction time signal SON based on the relationship between the input voltage VIN and the output voltage VOUT. This signal, after passing through dead-time logic, is converted into control signals for the high-side power transistor MP and the low-side power transistor MN. These signals, VGP and VGN, are then generated by the drive circuit to drive the power transistors. When the inductor current is zero, the zero-crossing detection module outputs a signal SZCD, which, after passing through dead-time logic and the drive circuit, turns off the low-side power transistor MN. This buck converter has a wide input voltage range. The high-side and low-side power transistor drive circuits in this embodiment can provide drive signals within a low voltage range, while reducing the load design requirements of the internal power supply module and eliminating the need for an external filter capacitor. Furthermore, the drive circuit has no static power consumption, meeting the requirement of low static power consumption for this buck converter.

[0044] To further verify the low-power characteristics of the buck converter proposed in this application, the effects of this application embodiment are further explained below with reference to experiments.

[0045] like Figure 11 The diagram shown is a waveform of a buck converter under heavy load according to an embodiment of this application. Figure 11 The five curves from top to bottom represent the high-side power transistor drive signal VGP, the low-side power transistor drive signal VGN, the inductor current, the switching node voltage VSM, and the output voltage VOUT. The waveforms at this point show that the gate voltage of the high-side power transistor transitions between the input voltage VIN and the input voltage VIN minus the internal supply level VDD (VIN-VDD), while the gate voltage of the low-side power transistor transitions between 0 and the internal supply level VDD. The inductor current and the switching node voltage VSM are normal, indicating that the converter is operating normally in the inductor continuously on mode.

[0046] like Figure 12The diagram shown is a waveform of a buck converter under heavy load according to another embodiment of this application. Figure 12 In the waveform diagram, VGP is the high-side power transistor drive signal, VGN is the low-side power transistor drive signal, VDD is the internal power supply level, IVIN-HD and IVIN-LD are the currents flowing from the input voltage VIN into the high-side and low-side drive circuits, respectively, and IVDD-HD and IVDD-LD are the currents flowing from the power supply level VDD into the high-side and low-side drive circuits, respectively. As can be seen from the waveform diagram, during the charging phase of the high-side and low-side power transistors, the high input current of the drive circuit comes from the input voltage VIN. The load current of VDD is low, maintaining normal voltage regulation. Outside the charging phase, the current from the input voltage VIN is cut off, consuming no additional current.

[0047] like Figure 13 The figure shown is a simulation result of the energy conversion efficiency of a buck converter provided in one embodiment of this application. This embodiment simulates the energy conversion efficiency of four different input voltages under a wide load range: a square curve represents an input voltage of 12V and an output voltage of 1.8V; a circular curve represents an input voltage of 12V and an output voltage of 3V; an equilateral triangle curve represents an input voltage of 8V and an output voltage of 1.8V; an inverted triangle curve represents an input voltage of 8V and an output voltage of 3V; a diamond curve represents an input voltage of 4V and an output voltage of 3V; and a slanted triangle curve represents an input voltage of 3.3V and an output voltage of 2.5V. Based on the efficiency change under varying load currents, it can be observed that the buck converter using the high-side and low-side power transistor drive circuit of this embodiment maintains a stable efficiency curve under different loads. Under light load currents, the buck converter maintains a high conversion efficiency. Only under extremely light load currents does the efficiency curve of the buck converter decrease. Therefore, the high-side and low-side power transistor drive circuit of this embodiment does not introduce new power consumption and can support the design requirements of the buck converter in terms of ultra-low power consumption.

[0048] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0050] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A high- and low-side power transistor drive circuit for direct charging with input voltage, characterized in that, include: The enable circuit is used to input the internal power supply level, input voltage, high-side power transistor control signal or low-side power transistor control signal, and then output a first enable signal and a level selection signal according to the high-side power transistor control signal, or output a second enable signal and a level selection signal according to the low-side power transistor control signal. A voltage clamping circuit, connected to the output of the enable circuit, is used to generate a first floating level based on the input voltage and the first enable signal, or to generate a second floating level based on the input voltage and the second enable signal; A level selection circuit, connected to the output terminal of the voltage clamping circuit, is used to select either the first floating level or the internal power supply level as the power supply level according to the level selection signal, or to select either the second floating level or the internal power supply level as the power supply level according to the level selection signal. A driving circuit, connected to the output of the level selection circuit, is used to charge the high-side power transistor or the low-side power transistor through the power supply level.

2. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The level selection signal includes a first level selection signal, and the enable circuit includes: A first delay unit and a first NAND gate, wherein the first input terminal of the first NAND gate is connected to the high-side power transistor control signal through the first delay unit, and the second input terminal of the first NAND gate is connected to the high-side power transistor control signal, for outputting the first level selection signal according to the high-side power transistor control signal; A first level shifting circuit is connected to the output of the first NAND gate and is used to output the first enable signal according to the internal power supply level, the input voltage and the first level selection signal.

3. The high-side and low-side power transistor driving circuit according to claim 1, characterized in that, The level selection signal includes a first level selection signal and a second level selection signal, and the enable circuit includes: The second delay unit and the second NAND gate, the first input terminal of the second NAND gate is connected to the low-side power transistor control signal through the second delay unit, and the second input terminal of the second NAND gate is connected to the low-side power transistor control signal, for outputting a control signal according to the low-side power transistor control signal; An AND gate, wherein the first input terminal of the AND gate is connected to the low-side power transistor control signal, and the second input terminal of the AND gate is connected between the second delay unit and the second NAND gate, for outputting the first level selection signal according to the low-side power transistor control signal; The NOT gate, whose input is connected to the output of the AND gate, is used to output the second level selection signal according to the first level selection signal; The second level shift circuit is connected to the output of the second NAND gate and is used to output the second enable signal according to the internal power supply level, the input voltage and the control signal.

4. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The voltage clamping circuit includes: A power transistor and a diode are provided, wherein the gate of the power transistor is connected to the output terminal of the enable circuit, the drain of the power transistor is connected to the input voltage, the source of the power transistor is connected to the negative terminal of the diode, and the positive terminal of the diode is grounded. The power transistor is used to generate the first floating level according to the input voltage and the first enable signal, or to generate the second floating level according to the input voltage and the second enable signal.

5. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: A first transistor and a second transistor, wherein the gate of the first transistor is connected to the first level selection signal, the drain of the first transistor is connected to the voltage clamping circuit, the gate of the second transistor is connected to the second level selection signal, and the drain of the second transistor is connected to the internal power supply level, for selecting either the first floating level or the internal power supply level as the power supply level according to the first level selection signal and the second level selection signal.

6. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The level selection signal includes a first level selection signal and a second level selection signal, and the level selection circuit includes: A third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the first level selection signal, the drain of the third transistor is connected to the voltage clamping circuit, the gate of the fourth transistor is connected to the second level selection signal, and the drain of the fourth transistor is connected to the internal power supply level, for selecting the second floating level or the internal power supply level as the power supply level according to the first level selection signal and the second level selection signal.

7. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The driving circuit includes: The third level shifting circuit is connected to the output of the level selection circuit and is used to charge the high-side power transistor through the power supply level.

8. The high-side and low-side power transistor drive circuit according to claim 1, characterized in that, The driving circuit includes: An inverter chain, connected to the output of the level selection circuit, is used to charge the low-side power transistor through the power supply level.

9. A buck converter, characterized in that, It includes a high-side power transistor, a low-side power transistor, and a high-low-side power transistor driving circuit as described in any one of claims 1 to 8, wherein the gate of the high-side power transistor and the gate of the low-side power transistor are both connected to the output terminal of the high-low-side power transistor driving circuit.

10. The buck converter according to claim 9, characterized in that, The buck converter also includes an internal power supply module, a voltage reference module, an error amplifier, a compensation network, a comparator, an inductor current detection module, a conduction time generation module, a zero-crossing detection module, and a dead-time logic module. The output of the dead-time logic module is connected to the input of the high-side and low-side power transistor drive circuit, and is used to output the high-side power transistor control signal and the low-side power transistor control signal.

Images