A method and apparatus for manufacturing an orthogonal backplate

Abstract

This invention relates to the field of PCB manufacturing technology, specifically to an orthogonal backplane manufacturing method and apparatus. By acquiring the expansion and contraction data of the sub-board and matching and pressing it accordingly, and combining this with printing copper paste at the connection holes to form a connection structure, this invention effectively solves the problem of interlayer alignment deviation in traditional methods. It not only improves the interlayer alignment accuracy and reduces the deviation caused by the accumulation of expansion and contraction, but also improves the backplane manufacturing yield and signal transmission performance.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a method and apparatus for manufacturing an orthogonal backplane. Background Technology

[0002] In the fields of high-speed communication and data center equipment, orthogonal backplanes have been proposed and applied as a key interconnect component to meet the ever-increasing demand for data transmission. This technology, by employing a backplane-less architecture, can effectively reduce losses and reflections in the signal transmission path, thereby achieving higher transmission rates, lower signal attenuation, and significant advantages such as reduced system failure rates and enhanced scalability.

[0003] However, to achieve the aforementioned performance, orthogonal backplanes impose extremely stringent physical requirements: they typically have a very high number of layers (e.g., 78, 84, or even 112 layers), a very large board thickness (e.g., 15mm, 18mm, or 24mm), and a very high aspect ratio (reaching 75:1 or higher), while requiring interlayer alignment accuracy to be controlled within an extremely narrow tolerance range of ≤3mil. If such highly complex and high-precision printed circuit boards are processed using traditional mechanical drilling combined with electroplating, problems such as limited drilling accuracy, difficulty in guaranteeing hole wall quality, and large cumulative alignment errors can easily lead to incomplete metallization of vias, decreased signal transmission performance, and even interlayer misalignment, making the circuit unreliable and severely restricting the manufacturability and reliability of this high-performance backplane.

[0004] Therefore, existing manufacturing processes are no longer sufficient to meet the comprehensive requirements of such high-end orthogonal backplanes in terms of electrical performance, structural precision, and mass production consistency. A new high-precision and high-reliability processing method is urgently needed to solve the above-mentioned technical bottlenecks. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide an orthogonal backplane manufacturing method and apparatus to solve the problem that in the prior art, incomplete metallization of vias, degraded signal transmission performance, and even misalignment between layers can easily lead to unreliable circuit conduction, which seriously restricts the manufacturability and reliability of the high-performance backplane.

[0006] According to one aspect of the present invention, a method for manufacturing an orthogonal backplate is provided, the method comprising:

[0007] Obtain a PCB sub-board, wherein the PCB sub-board includes at least a first sub-board and a second sub-board, the first sub-board having a first connecting outer layer and the second sub-board having a second connecting outer layer;

[0008] A first dielectric layer is fabricated in the first connection outer layer and / or the second connection outer layer;

[0009] First positioning holes are made in the first sub-board and the second sub-board respectively, and the expansion and contraction data of the first sub-board and the second sub-board are obtained according to the first positioning holes;

[0010] A second dielectric layer is fabricated outside the first dielectric layer;

[0011] A first connection hole is formed in the first dielectric layer and the second dielectric layer. The first connection hole penetrates the first dielectric layer and the second dielectric layer, and the position of the first connection hole matches the pad of the first sub-board and / or the second sub-board.

[0012] A first copper paste structure is formed by printing copper paste at the first connecting hole;

[0013] The first sub-board and the second sub-board are matched according to the expansion and contraction data, and the matched first sub-board and the second sub-board are stacked and pressed together through the first positioning hole to form a PCB motherboard, so that the pads of the first sub-board are connected to the pads of the second sub-board through the first copper paste structure.

[0014] In some optional embodiments, obtaining the PCB sub-board specifically includes: sequentially producing the PCB sub-board through a core board cutting process, an inner layer patterning process, a sub-board lamination process, a sub-board drilling process, a sub-board electroplating process, a sub-board outer layer patterning process, a sub-board solder mask process, a sub-board electroless gold plating process, and a sub-board electrical testing process.

[0015] In some optional embodiments, the step of fabricating a first dielectric layer on the first and / or second connection outer layers specifically includes:

[0016] The first dielectric layer is formed by pressing and curing PP film in the first and second connecting outer layers respectively;

[0017] Alternatively, a first dielectric layer is formed by pressing and curing a PP film on the first connecting outer layer, and air compression is performed on the second connecting outer layer.

[0018] In some optional embodiments, first positioning holes are respectively formed in the first sub-board and the second sub-board, and expansion and contraction data of the first sub-board and the second sub-board are obtained according to the first positioning holes, specifically including:

[0019] Obtain the preset standard drawings of the first sub-board and the second sub-board, wherein corner points are set at the four corners of the standard drawings;

[0020] Connect the diagonally opposite corner points with a first connecting line, and the intersection of the two first connecting lines shall be used as the standard center point;

[0021] The adjacent corner points are connected by a second connecting line. The center point coordinates of the second connecting line are the positioning coordinates, and any positioning coordinate is added to a preset offset to form a foolproof coordinate.

[0022] First positioning holes are made on the first sub-plate and the second sub-plate according to the positioning coordinates and the error-proof coordinates;

[0023] Obtain the actual coordinates of the first positioning hole, and after compensating for the preset offset of the error-proof coordinates, connect the non-adjacent actual coordinates through the third connecting line, and take the intersection of the two third connecting lines as the actual center point; calculate the expansion and contraction data based on the difference between the actual center point and the standard center point.

[0024] In some optional embodiments, a second dielectric layer is fabricated outside the first dielectric layer, specifically including:

[0025] The first and second sub-boards are subjected to browning treatment;

[0026] A second dielectric layer is formed in the first connecting outer layer and / or the second connecting outer layer by fast-pressed PP film and PET film, respectively, and the second dielectric layer is located outside the first dielectric layer.

[0027] In some optional embodiments, a first connection hole is formed in the first dielectric layer and the second dielectric layer. The first connection hole penetrates the first dielectric layer and the second dielectric layer, and the position of the first connection hole matches the pads of the first sub-board and / or the second sub-board. Specifically, this includes:

[0028] A first connection hole is formed in the first dielectric layer and the second dielectric layer by laser engraving, wherein the diameter of the connection is less than or equal to the pad diameter of the first sub-board or the pad diameter of the second sub-board.

[0029] In some optional embodiments, copper paste is printed at the first connecting hole to form a first copper paste structure, specifically including:

[0030] Copper paste is screen-printed onto the first connection hole using a vacuum plugging device;

[0031] The first sub-board and / or the second sub-board are baked to solidify the copper paste to form a first copper paste structure, and the PET film of the second dielectric layer is removed.

[0032] In some optional implementations, the first sub-board and the second sub-board are matched according to expansion and contraction data, and the matched first sub-board and the second sub-board are stacked and pressed together through the first positioning hole to form a PCB motherboard, specifically including:

[0033] Obtain expansion and contraction data of multiple first sub-boards and multiple second sub-boards, and group the first sub-boards and second sub-boards whose expansion and contraction data are within the same preset range as a group;

[0034] After the first and second sub-boards in the same group are positioned and stacked along the first positioning hole, they are pressed and sintered to form the PCB motherboard.

[0035] In some optional embodiments, when the PCB sub-board further includes a third sub-board, the second sub-board is further provided with a third connecting outer layer, and the third sub-board is provided with a fourth connecting outer layer, and further includes:

[0036] A third dielectric layer is fabricated in the third and / or fourth connection outer layers;

[0037] A second positioning hole is made in the third sub-board, and the expansion and contraction data of the third sub-board are obtained according to the second positioning hole;

[0038] A fourth dielectric layer is fabricated in the third and / or fourth connection outer layers;

[0039] A second connection hole is formed in the third dielectric layer and the fourth dielectric layer. The second connection hole penetrates the third dielectric layer and the fourth dielectric layer, and the position of the second connection hole matches the pad of the second sub-board and / or the third sub-board.

[0040] A second copper paste structure is formed by printing copper paste at the second connecting hole;

[0041] The first sub-board, the second sub-board, and the third sub-board are matched according to the expansion and contraction data and stacked and pressed together through the first positioning hole and the second positioning hole to form a PCB motherboard.

[0042] In some alternative embodiments, prior to fabricating the first dielectric layer on the first and / or second interconnect outer layers, the method further includes:

[0043] The preset crimping holes of the PCB sub-board are treated with semi-resin plugging.

[0044] After completing the semi-resin plugging process, excess resin around the pre-set crimping holes is cleaned using a laser.

[0045] In some alternative embodiments, the present invention also provides an orthogonal backplate manufacturing apparatus, including the orthogonal backplate manufacturing method described above.

[0046] The orthogonal backplane manufacturing method and apparatus of the present invention have the following advantages: The present invention obtains the expansion and contraction data of the sub-board and matches and presses it accordingly, and combines it with printing copper paste at the connection hole to form a connection structure, which effectively solves the problem of interlayer alignment deviation in the traditional method. It not only improves the interlayer alignment accuracy and reduces the deviation caused by the accumulation of expansion and contraction, but also improves the backplane manufacturing yield and signal transmission performance.

[0047] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0048] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0049] Figure 1 A flowchart illustrating the orthogonal backplate fabrication method of Embodiment 1 provided by the present invention is shown;

[0050] Figure 2 A flowchart illustrating step 130 of Embodiment 1 provided by the present invention is shown;

[0051] Figure 3 A flowchart illustrating step 140 of Embodiment 1 provided by the present invention is shown;

[0052] Figure 4 A flowchart illustrating step 160 of Embodiment 1 provided by the present invention is shown;

[0053] Figure 5 A flowchart illustrating step 170 of Embodiment 1 provided by the present invention is shown;

[0054] Figure 6 A flowchart illustrating the orthogonal backplate fabrication method of Embodiment 2 provided by the present invention is shown;

[0055] Figure 7 A flowchart illustrating the process after step 170 in Embodiment 3 provided by the present invention is shown;

[0056] Figure 8 This diagram illustrates a structural schematic of a first dielectric layer and a second dielectric layer being laminated onto a PCB sub-board, according to an embodiment of the present invention.

[0057] Figure 9 This diagram illustrates a structural schematic of pressing a first daughter board and a second daughter board together to form a PCB mother board, according to an embodiment of the present invention.

[0058] Figure 10 This diagram illustrates a structure of a PCB motherboard formed by pressing a first daughter board, a second daughter board, and a third daughter board together, according to an embodiment of the present invention.

[0059] Figure 11 This invention provides a schematic diagram of the structure of the first or second positioning hole on a PCB sub-board according to an embodiment of the present invention.

[0060] Figure 12 This diagram illustrates the calculation of PCB sub-board expansion and contraction data according to an embodiment of the present invention.

[0061] Figure label:

[0062] 1. PCB motherboard; 10. First daughterboard; 11. First connecting outer layer; 12. First dielectric layer; 13. Second dielectric layer; 14. PP film; 15. PET film; 20. Second daughterboard; 30. Third daughterboard; 40. First copper paste structure; 51. Upper pressure plate; 52. Lower pressure plate; S1, actual center point; S2, standard center point. Detailed Implementation

[0063] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0064] Example 1:

[0065] Figure 1 This paper illustrates a first embodiment of the orthogonal backplane fabrication method of the present invention, which addresses the problem that existing technologies easily lead to incomplete metallization of vias, degraded signal transmission performance, and even misalignment between layers, resulting in unreliable circuit conduction and severely restricting the manufacturability and reliability of high-performance backplanes. The method includes:

[0066] 110. Obtain a PCB sub-board, wherein the PCB sub-board includes at least a first sub-board and a second sub-board. The first sub-board has a first connecting outer layer, and the second sub-board has a second connecting outer layer. In step 110, the PCB sub-board refers to an independent printed circuit board unit constituting the final PCB motherboard. It undergoes multiple processes during manufacturing and is ultimately formed into a multi-layer structure through stacking and lamination. The first and second sub-boards are specific examples of PCB sub-boards, each carrying a specific circuit function and achieving electrical interconnection through subsequent connection processes. The first and second connecting outer layers refer to the outermost conductive layers of the first and second sub-boards, respectively, used for connection with other layers or external components. Obtain the PCB sub-board. This PCB sub-board is the basic unit constituting the final PCB motherboard, and it includes at least a first sub-board and a second sub-board. The first and second sub-boards each have a connecting outer layer, namely the first connecting outer layer and the second connecting outer layer, which are the interfaces for subsequent inter-layer connections. These sub-boards can be obtained in a variety of ways, such as by being provided by a specialized PCB manufacturing plant, or through a series of basic PCB manufacturing processes, such as material preparation, pattern transfer, etching, and lamination.

[0067] 120. A first dielectric layer is formed on the first and / or second connecting outer layers. In step 120, the first dielectric layer is an insulating layer formed on the connecting outer layers to provide interlayer insulation and structural support. These dielectric layers are typically made of PP film or similar materials. The first dielectric layer is formed on the first and / or second connecting outer layers. This dielectric layer is used to provide electrical insulation and structural support. The dielectric layer can be formed by curing a PP film onto the first and / or second connecting outer layers and then curing it by heating and pressurizing. Alternatively, it can be formed by coating a liquid resin material and then curing it.

[0068] Step 130 involves fabricating first positioning holes on the first and second sub-boards, and obtaining expansion and contraction data for the first and second sub-boards based on these holes. In step 130, the first positioning holes are holes fabricated on the PCB sub-boards for precise alignment. Their positions and dimensions are designed to ensure alignment accuracy when multiple PCB sub-boards are stacked and laminated. Expansion and contraction data refers to the dimensional changes in the PCB sub-boards during manufacturing due to material properties, temperature variations, process stress, and other factors. Obtaining and utilizing this data is crucial for achieving high-precision interlayer alignment. First positioning holes are fabricated on the first and second sub-boards, and expansion and contraction data for the first and second sub-boards are obtained based on these holes. The fabrication of the first positioning holes can be completed using mechanical drilling equipment to ensure hole position accuracy. Expansion and contraction data can be obtained by measuring the dimensional changes of specific marker points on the sub-boards at different process stages. For example, the distance between the first positioning holes can be precisely measured using optical measuring equipment and compared with the design value to determine the expansion and contraction amount.

[0069] 140. A second dielectric layer is formed outside the first dielectric layer; in step 140, the second dielectric layer is an insulating layer formed on the connecting outer layer to provide interlayer insulation and structural support. These dielectric layers are typically made of PP film or similar materials. The second dielectric layer is formed outside the first dielectric layer. This second dielectric layer also serves to provide electrical insulation and structural support, and is typically located outside the first dielectric layer. The second dielectric layer can be formed using methods similar to those used to form the first dielectric layer, for example, by laminating a PP film or coating with a cured resin.

[0070] 150. First connecting holes are formed in the first dielectric layer and the second dielectric layer. The first connecting holes penetrate the first dielectric layer and the second dielectric layer, and their positions match the pads on the first sub-board and / or the second sub-board. In step 150, the first connecting holes are through holes formed on the dielectric layer to establish electrical connections between different layers. These holes are typically formed by drilling or laser processing and subsequently metallized. Pads are conductive areas on a PCB sub-board used to connect electronic components or make electrical connections with other layers, and are typically circular or square metal areas. First connecting holes are formed in the first dielectric layer and the second dielectric layer. These first connecting holes penetrate the first dielectric layer and the second dielectric layer, and their positions match the pads on the first sub-board and / or the second sub-board to ensure subsequent electrical connections. The first connecting holes can be formed by mechanical drilling equipment or by methods such as chemical etching.

[0071] 160. Printing copper paste at the first connecting hole to form a first copper paste structure; In step 160, the first copper paste structure refers to the conductive pillar or conductive filler formed after filling the first connecting hole with copper paste, used to achieve reliable electrical connection between different sub-board pads after lamination. Printing copper paste at the first connecting hole to form the first copper paste structure can be achieved through screen printing technology, filling the first connecting hole with conductive copper paste. After filling, the copper paste usually needs to be baked or cured to harden the copper paste and form a stable conductive structure.

[0072] Step 170 involves matching the first and second sub-boards according to expansion and contraction data, and then stacking and pressing the matched first and second sub-boards through the first positioning holes to form a PCB motherboard. This allows the pads of the first sub-board to be connected to the pads of the second sub-board via the first copper paste structure. In step 170, the PCB motherboard is the final multilayer printed circuit board, integrated from multiple PCB sub-boards through precise alignment, stacking, and pressing processes, possessing complete circuit functionality. Matching the first and second sub-boards according to the acquired expansion and contraction data, and then stacking and pressing them through the first positioning holes, forms the PCB motherboard. This process aims to ensure a reliable connection between the pads of the first sub-board and the pads of the second sub-board via the first copper paste structure. The matching of the sub-boards can be manually selected or adjusted based on the expansion and contraction data to reduce alignment errors. Stacking and pressing can be accomplished by placing the sub-boards in a pressing machine and applying appropriate temperature and pressure to ensure a tight bond between the layers.

[0073] In steps 110-170, this invention achieves precise matching and stacking between sub-boards by meticulously controlling the fabrication of PCB sub-boards, the formation of the first and second dielectric layers, the fabrication of the first positioning holes, and the acquisition of expansion and contraction data, combined with the precise fabrication of the first connecting holes and copper paste filling. Therefore, this method effectively solves the manufacturing challenges of high-layer orthogonal backplanes with large board thicknesses caused by drilling accuracy, hole wall quality, and alignment errors in traditional processes, improving interlayer alignment accuracy and conductivity reliability, thereby meeting the comprehensive requirements of high-end orthogonal backplanes in terms of electrical performance, structural precision, and mass production consistency.

[0074] In step 110, the PCB sub-board is obtained, which specifically includes: sequentially producing the PCB sub-board through the core board cutting process, inner layer patterning process, sub-board lamination process, sub-board drilling process, sub-board electroplating process, sub-board outer layer patterning process, sub-board solder mask process, sub-board gold plating process, and sub-board electrical testing process.

[0075] In this step, the core board cutting process aims to cut the substrate required for PCB manufacturing, such as copper-clad laminate core boards, into boards of predetermined dimensions. This is typically done using precision cutting equipment to ensure dimensional accuracy and material utilization in subsequent processes.

[0076] The inner layer patterning process is used to form internal conductive patterns on the core board. Specifically, through processes such as photolithography, development, and etching, the designed circuit pattern is transferred onto the copper foil layer of the core board to form precise inner layer circuitry.

[0077] The sub-board lamination process involves laminating multilayer core boards, prepreg (PP film), and copper foil under high temperature and pressure to form a multilayer PCB sub-board. This process ensures a tight bond between the layers, forming a stable multilayer board structure.

[0078] The sub-board drilling process uses methods such as mechanical drilling or laser drilling to create various holes on the laminated PCB sub-board, including through holes, positioning holes, and mounting holes. The drilling accuracy directly affects the quality of subsequent electroplating and assembly.

[0079] The sub-board electroplating process uses chemical copper deposition and electroplating to form a conductive copper layer on the hole walls and board surface, achieving electrical connections between different layers. This is crucial for the conductivity of multilayer boards.

[0080] The outer layer patterning process is similar to the inner layer patterning process, used to form conductive patterns on the outermost layer of the PCB sub-board. Pattern plating and etching processes are typically used to construct external circuit connections and pads.

[0081] The solder mask process on the PCB sub-board involves coating a layer of solder mask ink onto the outer pattern of the PCB sub-board and then exposing only the areas of the solder pads that need to be soldered through processes such as exposure, development, and curing. The purpose of the solder mask layer is to prevent short circuits during soldering and to protect the circuitry from environmental corrosion.

[0082] The electroless gold plating process on the daughterboard involves surface treatment of the exposed pad areas, such as electroless nickel-gold plating (ENIG) or OSP (organic solderability protectant). Electroless gold plating aims to improve the solderability, oxidation resistance, and shelf life of the pads.

[0083] The sub-board electrical testing process involves performing electrical performance tests on the completed PCB sub-board, including open / short circuit tests and impedance tests, to ensure that all circuit connections are correct, there are no open or short circuits, and that the circuits meet design requirements.

[0084] By introducing a series of refined and standardized PCB sub-board manufacturing processes through the above technical solution, including core board cutting, inner layer patterning, sub-board lamination, sub-board drilling, sub-board electroplating, outer layer patterning, solder masking, gold plating, and electrical testing, this invention ensures that the obtained PCB sub-boards meet high standards in terms of dimensional accuracy, electrical performance, and surface treatment. This effectively solves the problems of subsequent stacking and lamination difficulties, poor connection reliability, and overall backplane performance degradation caused by unstable sub-board quality. In particular, by strictly controlling each manufacturing step, the expansion and contraction consistency of the sub-board can be significantly improved, laying a solid foundation for subsequent precise matching and stacking and lamination based on expansion and contraction data, thereby ensuring the connection accuracy and long-term reliability of the orthogonal backplane.

[0085] In step 120, a first dielectric layer is fabricated in the first interconnect outer layer and / or the second interconnect outer layer, see [link to relevant documentation]. Figure 2 Specifically, it includes:

[0086] The first dielectric layer is formed by pressing and curing PP films into the first connecting outer layer and the second connecting outer layer, respectively.

[0087] Alternatively, a first dielectric layer is formed by pressing and curing a PP film on the outer layer of the first connection, and air compression is performed on the outer layer of the second connection to make the expansion and contraction changes of the first sub-board and the second sub-board consistent.

[0088] In one specific embodiment, a first dielectric layer is formed by pressing and curing PP films onto the first and second connecting outer layers. During PP film curing, a first stage of curing is performed at a temperature of 80℃-140℃ and a heating rate of 3℃ / min, or a second stage of curing is performed at a temperature of 200℃-220℃ for 120 minutes. Curing the PP film ensures a stronger bond during subsequent fast-pressing, improving the overall stability of the PCB board.

[0089] In one specific implementation, a PP film is cured and pressed onto the outer layer of the second connection. The first sub-board does not need to cure the PP film, but it needs to be air-pressed separately. The air-pressing ensures that the number of times the first sub-board and the second sub-board are pressed are consistent, and the expansion and contraction changes are consistent. Curing the PP film makes the subsequent quick-pressing of the PP film more secure and improves the overall stability of the PCB board.

[0090] In this step, the present invention forms a first dielectric layer by laminating and curing a PP film. This refers to using the PP film as an insulating material and laminating it under specific temperature and pressure conditions, causing the PP film to flow and cure, thereby forming a uniform dielectric layer with good insulating properties on the surface of the first or second connecting outer layer. The selection of the PP film should consider its dielectric constant, loss factor, and compatibility with the PCB substrate to meet the electrical performance requirements of the orthogonal backplane. Temperature profile and pressure control during the lamination process are crucial to ensure sufficient resin curing while avoiding voids or delamination.

[0091] When a PP film is laminated and cured to form the first dielectric layer on the first connecting outer layer, and air compression is performed on the second connecting outer layer, the air compression process refers to subjecting the unlaminated PP film to a thermal cycle and pressure treatment similar to that applied to the laminated PP film. This process aims to simulate the thermal stress generated on the material during lamination, allowing the second sub-board to undergo a similar processing procedure to the first sub-board even without a dielectric layer. This effectively balances the dimensional changes, i.e., expansion and contraction, that may occur between the first and second sub-boards during subsequent processing.

[0092] Through the above technical solutions, whether both the first and second sub-boards are laminated and cured with PP film, or one is laminated with PP film while the other is subjected to air compression, the core purpose is to ensure that the first and second sub-boards undergo similar processing during the first dielectric layer fabrication stage. This effectively avoids the problem of inconsistent expansion and contraction between different sub-boards due to differences in dielectric layer fabrication methods, thus providing a more stable foundation for subsequent positioning hole fabrication and expansion and contraction data acquisition. Ultimately, this improves the alignment accuracy and product reliability when the first and second sub-boards are stacked and laminated to form the PCB motherboard.

[0093] In step 130, first positioning holes are made in the first sub-board and the second sub-board, and expansion and contraction data of the first sub-board and the second sub-board are obtained based on the first positioning holes, specifically including:

[0094] 210. Obtain the pre-defined standard drawings for the first and second sub-boards. Corner reference points are set at the four corners of the standard drawings. In step 210, the standard drawings are engineering files generated during the PCB sub-board design phase, which define in detail the sub-board's geometric dimensions, layer stack-up structure, pad locations, and reference points for manufacturing and inspection. The four corner reference points are pre-defined geometric reference points on the drawings, located at the edges or specific areas of the sub-board. They are typically used to determine the overall size and position of the sub-board. By connecting these four corner reference points, the geometric center point of the sub-board in its ideal state can be accurately calculated. This center point serves as the benchmark for subsequent expansion and contraction data calculations. This step ensures that the starting point for expansion and contraction data calculations is based on accurate design standards.

[0095] 220. Connect the diagonally opposite corner points with a first connecting line, and the intersection of the two first connecting lines is taken as the standard center point. In step 220, by connecting these four corner points, the geometric center point of the sub-board under ideal conditions can be accurately calculated. This center point serves as the reference for subsequent expansion and contraction data calculations. This step ensures that the starting point for expansion and contraction data calculations is based on accurate design standards.

[0096] 230. Connect adjacent corner points using a second connecting line. The center point coordinates of the second connecting line are used as positioning coordinates. Add any positioning coordinate to a preset offset to form a foolproof coordinate. In step 220, the positioning coordinates are reference positions used to create physical positioning holes on the actual sub-board. These coordinates are typically calculated based on the center point of the second connecting line between adjacent corner points on standard drawings to ensure the positioning holes align with the design. Figure 1 To improve the reliability of the positioning process and prevent operational errors, this invention introduces a foolproof coordinate system. A foolproof coordinate system is a special positioning point formed by adding a preset offset to the conventional positioning coordinate system. For example, a fixed offset can be added to the X or Y direction of one of the four positioning coordinates (such as the upper right corner), making its position significantly different from the other three. This design allows for clear differentiation of the identity and orientation of each hole during subsequent hole fabrication or measurement, avoiding mispositioning caused by factor plate symmetry or operator negligence, thereby improving positioning accuracy and efficiency.

[0097] 240. Based on the positioning coordinates and the error-proof coordinates, first positioning holes are fabricated on the first and second sub-boards respectively. In step 240, the first positioning holes are actual physical holes, precisely fabricated on the first and second sub-boards as physical alignment references in the subsequent stacking and pressing process. The fabrication of these holes requires high-precision equipment, such as CNC drilling machines or laser drilling machines, to ensure that their positions are highly consistent with the calculated positioning coordinates and error-proof coordinates. The size and shape of the first positioning holes are typically standardized to facilitate use with positioning pins or fixtures on automated production lines. These physical holes are a crucial link connecting design data with the actual manufacturing process, providing a reliable physical basis for subsequent precise measurement and alignment.

[0098] 250. Obtain the actual coordinates of the first positioning hole. After compensating for the error-proof coordinates with a preset offset, connect the non-adjacent actual coordinates using a third connecting line. The intersection of the two third connecting lines is taken as the actual center point. In step 250, after the first positioning hole is manufactured, a high-precision measuring device, such as an optical measuring system (e.g., a CCD vision inspection device) or a coordinate measuring machine, is needed to accurately measure the actual physical position of each first positioning hole, thereby obtaining its actual coordinates on the sub-board. Due to expansion and contraction during the manufacturing process, these actual coordinates usually have slight deviations from the positioning coordinates during design. For error-proof holes, after obtaining their actual coordinates, the previously set preset offset needs to be subtracted to restore their coordinates to the same reference system as the regular first positioning holes for unified geometric calculation. Subsequently, by connecting these compensated actual first positioning hole coordinates, the actual geometric center point of the sub-board can be calculated. This actual center point reflects the true geometric position of the sub-board in its current manufacturing state.

[0099] 260. Calculate the expansion / contraction data based on the difference between the actual center point and the standard center point. In step 260, by comparing the actual center point coordinates obtained in the previous step with the standard center point coordinates initially determined from the standard drawing, the deviation values ​​in the X and Y directions can be calculated. These deviation values ​​are the precise expansion / contraction data, quantifying the overall expansion or contraction of the sub-board during processing. This expansion / contraction data serves as the basis for precise compensation during subsequent sub-board matching and stacking, ensuring high-precision alignment can be achieved through data-driven methods even if the sub-board experiences expansion / contraction.

[0100] In one specific embodiment, the exposure coefficients of the outer layer patterns on the first and second sub-boards are made identical. A CCD drill picks up the corner points of the outer layer pattern on either the first or second sub-board, centers the PAD (Pressurized PAD) on each corner, and drills four 4.775mm bonding PIN-LAM holes (the first positioning holes) using a 1:1 expansion / contraction ratio. The PIN-LAM hole positions can be designed according to the PCB sub-board dimensions, such as in the middle of an 18*21 inch board. A coordinate measuring machine can be used to measure the intersection points of the diagonal centers of the corner points on the sub-board and the four circular PIN-LAM holes in the X and Y directions, i.e., the X and Y distances between the two intersection points. When designing the first positioning holes, any one of the four first positioning holes can be designed with a foolproof offset, such as a 9.55mm offset, to facilitate alignment during the subsequent bonding process. See [link to documentation]. Figure 11-12 The corner points include corner point one, corner point two, corner point three, and corner point four; the first positioning holes include positioning hole one, positioning hole two, positioning hole three, and positioning hole four. S1 is the actual center point; S2 is the standard center point; the lines connecting corner point one and corner point four, and corner point two and corner point three are the first connecting lines; the lines connecting corner point one and corner point two, corner point two and corner point four, and corner point three and corner point four, and corner point one and corner point three are the second connecting lines; the line connecting positioning hole two and positioning hole four is the third connecting line. The position of the first positioning hole can be determined based on the corner points, then the standard center point can be calculated based on the corner points, and the actual center point can be calculated based on the first positioning holes. The expansion and contraction data are obtained by calculating the difference between the standard center point and the actual center point.

[0101] Through the technical solutions in steps 210-260, this invention can accurately obtain the expansion and contraction data of the first and second sub-boards during the manufacturing process, thereby effectively solving the alignment accuracy problem caused by dimensional deformation. Specifically, by obtaining the corner points of the standard drawing and calculating the standard center point, a reliable design benchmark is provided for the calculation of expansion and contraction data. Introducing error-proof coordinates and making corresponding positioning holes not only ensures the accuracy of positioning hole manufacturing and measurement, but also significantly improves the error-proof capability of operation, avoiding measurement errors caused by misoperation. Subsequently, by measuring the coordinates of the actual positioning holes with high precision and compensating for the error-proof holes, the actual geometric state of the sub-board can be truly reflected, thereby calculating the accurate actual center point. Finally, by comparing the difference between the actual center point and the standard center point, quantified expansion and contraction data is obtained. This accurate expansion and contraction data enables intelligent matching or precise compensation based on the actual deformation of each sub-board during subsequent stacking and pressing processes, thereby significantly improving the alignment accuracy between the pads of the first and second sub-boards, effectively reducing connection defects caused by misalignment, and significantly improving the yield of the PCB motherboard and the reliability of electrical connections.

[0102] In step 140, a second dielectric layer is fabricated outside the first dielectric layer, see [link to previous step]. Figure 3 Specifically, it includes:

[0103] 310. The first and second sub-boards undergo a browning treatment. In step 310, browning is a chemical modification process for the copper surface, which significantly increases the copper surface area and roughness by forming a micro-rough oxide layer. This oxide layer is typically brown or black and has good wettability and mechanical anchoring properties. This treatment greatly improves the bonding strength between the copper layer and the subsequent bonding dielectric material (such as PP film), effectively preventing delamination that may occur during subsequent lamination, drilling, electroplating, and long-term use, thereby ensuring the structural integrity of the PCB motherboard and the reliability of electrical connections. This treatment is typically carried out by immersing the PCB sub-boards in a chemical solution containing an oxidant (such as sodium chlorate or sodium hydroxide), with precise control of the treatment time, temperature, and solution concentration to obtain a uniform and strongly adhering oxide layer.

[0104] 320. A second dielectric layer is formed on the first and / or second connecting outer layers using fast-pressed PP and PET films, respectively, with the second dielectric layer located outside the first dielectric layer. In step 320, the PP film is a dielectric material made by impregnating glass fiber cloth with resin and semi-curing it. Under heating and pressurization, the resin flows and cures, forming an insulating layer and bonding adjacent conductive layers. The PET film here can serve as a temporary carrier film or protective film, providing a smooth surface during the fast-pressing process and may be peeled off after pressing to obtain a smooth dielectric layer surface. The fast-pressing process refers to using a shorter pressing cycle to achieve rapid curing and molding of the dielectric layer by optimizing temperature, pressure, and time parameters, thereby improving production efficiency. This process helps to shorten the manufacturing cycle while ensuring the quality of interlayer bonding. Furthermore, the second dielectric layer is located outside the first dielectric layer. This structural relationship clarifies the stacking order of the PCB motherboard, i.e., the second dielectric layer is constructed outside or on top of the first dielectric layer after its formation. This layer-by-layer stacking method is the foundation of multilayer PCB manufacturing, ensuring sufficient insulation between conductive layers and providing the necessary dielectric foundation for subsequent first-hole fabrication and copper paste printing.

[0105] In one specific embodiment, a second medium layer is formed by fast-pressing PP film and PET film respectively in the first connecting outer layer and the second connecting outer layer, and the second medium layer is located outside the first medium layer. When fast-pressing the PP film, the fast-pressing parameters can be set to pressure of 25 kg, temperature of 100 °C, and fast-pressing time of 90 s. The PET film can protect the PP film, and the second medium layer can provide PP connection between the subsequent laser carrier and the mother plate lamination layer.

[0106] In one specific embodiment, a second dielectric layer is formed on the second connecting outer layer by fast-pressing a PP film and a PET film, and the second dielectric layer is located outside the first dielectric layer. During fast-pressing of the PP film, the fast-pressing parameters can be set to a pressure of 25 kg, a temperature of 100°C, and a fast-pressing time of 90 s. The PET film protects the PP film. No operation is required on the first connecting outer layer, or the first sub-board can be pneumatically pressed using the fast-pressing parameters for the second dielectric layer. The second dielectric layer enables the PP connection between the subsequent laser carrier and the motherboard lamination layer. See also... Figure 8 10 is the first sub-plate; 11 is the first connecting outer layer; 12 is the first dielectric layer; 13 is the second dielectric layer; 14 is the PP film; 15 is the PET film; 51 is the upper platen of the fast press; 52 is the lower platen of the fast press; the second dielectric layer is formed by placing the first sub-plate, PP film and PET film sequentially on the lower platen and pressing them together by the fast press.

[0107] It should be noted that the first dielectric layer provides a good hole shape for subsequent laser-drilled first connection holes. Without the first dielectric layer, the hole shape will be poor, the copper paste inside the hole will be irregular, and short circuits will be likely. The second dielectric layer is used to connect the first and second daughter boards during PCB motherboard lamination through a PP film. Without the second dielectric layer, the daughter board layers will lack the PP film to connect and be laminated into the PCB motherboard.

[0108] Through steps 310-320, the copper surfaces of the first and second sub-boards are first browned, which greatly enhances the adhesion between the copper layer and the subsequent dielectric layer, effectively avoiding the risk of delamination. Subsequently, the second dielectric layer is efficiently and reliably formed using fast-pressing PP and PET films, ensuring not only the insulation performance and structural stability of the dielectric layer but also improving production efficiency through the fast-pressing process. Simultaneously, the stacking relationship of the second dielectric layer outside the first dielectric layer is clearly defined, ensuring the correct construction of the multilayer structure. Therefore, the solution of this invention significantly improves the interlayer bonding reliability, electrical performance, and manufacturing efficiency of orthogonal backplane PCB motherboards, providing a solid guarantee for the stable operation of high-density, high-performance orthogonal backplanes.

[0109] In step 150, a first connection hole is formed in the first dielectric layer and the second dielectric layer. The first connection hole penetrates the first dielectric layer and the second dielectric layer, and the position of the first connection hole matches the pads of the first sub-board and / or the second sub-board. Specifically, the first connection hole is formed in the first dielectric layer and the second dielectric layer by laser engraving, wherein the diameter of the connection is less than or equal to the pad diameter of the first sub-board or the pad diameter of the second sub-board.

[0110] In this step, the first connecting holes are created by laser drilling in the first and second dielectric layers. Laser drilling is a non-contact, high-precision processing method that uses a focused laser beam to ablate or vaporize the material, thereby forming the desired first connecting holes in the first and second dielectric layers. This method is particularly suitable for creating small-diameter, high-density holes and holes that need to penetrate multiple layers of different dielectric materials. Compared to traditional mechanical drilling, laser drilling offers higher processing accuracy, faster speed, and significantly reduces mechanical stress on the substrate, thus avoiding dielectric layer delamination or damage to surrounding structures. Depending on the characteristics of the dielectric material and the required hole diameter accuracy, different types of lasers can be selected, such as CO2 lasers, ultraviolet lasers, or excimer lasers.

[0111] The diameter of the first connecting hole must be less than or equal to the diameter of the pad on the first daughterboard or the pad on the second daughterboard. This dimensional constraint is crucial for ensuring reliable electrical connections. It means that the first connecting hole must be completely within the boundary of the corresponding pad on either the first or second daughterboard. If the diameter of the first connecting hole is larger than the pad diameter, the hole may extend beyond the pad's boundaries, potentially causing short circuits with adjacent traces or pads, or preventing subsequent copper paste from forming sufficient contact area with the pad. By strictly controlling the diameter of the first connecting hole to be less than or equal to the pad diameter, it ensures that the first copper paste structure formed within the first connecting hole can establish a complete and reliable electrical connection with the pad, thereby optimizing conductivity and connection integrity. This also places higher demands on the precision of the laser drilling process to maintain such tight tolerances.

[0112] In one specific embodiment, when both the first sub-board and the second sub-board are provided with a first dielectric layer and a second dielectric layer, first connection holes can be formed in the first dielectric layer and the second dielectric layer of the first sub-board and the second sub-board, respectively. When only the second sub-board is provided with a first dielectric layer and a second dielectric layer, first connection holes can be formed in the first dielectric layer and the second dielectric layer of the second sub-board.

[0113] It should be noted that, while making the first connecting hole, the hole position of the first positioning hole can be laser-drilled in the first dielectric layer and the second dielectric layer according to the position of the first positioning hole, so as to facilitate subsequent positioning and pressing.

[0114] The above technical solution utilizes laser drilling technology to fabricate the first connecting hole, enabling a high-precision, non-contact drilling process that effectively avoids dielectric layer damage or delamination issues that may occur with traditional mechanical drilling. Simultaneously, strictly controlling the diameter of the first connecting hole to be less than or equal to the diameter of the corresponding pad ensures that the first connecting hole is completely located within the pad area. This provides precise positioning for subsequent copper paste filling, avoids short-circuit risks, and guarantees a sufficient and reliable electrical connection between the first copper paste structure and the pad. This significantly improves the connection reliability and production yield of the PCB motherboard, and is particularly suitable for manufacturing orthogonal backplanes with high-density interconnects.

[0115] In step 160, copper paste is printed at the first connecting hole to form a first copper paste structure, specifically including:

[0116] 410. Copper paste is screen-printed onto the first connecting hole using a vacuum plugging device. In step 410, the copper paste is screen-printed using a vacuum plugging device. This device creates a negative pressure environment, which helps to completely draw in the copper paste and fill it into the first connecting hole, thereby effectively avoiding defects such as bubbles, voids, or uneven filling that may occur with traditional screen printing. At the same time, by setting the squeegee thickness to 40mm, controlling the squeegee speed to 15mm / s, maintaining the squeegee pressure at 0.6Mpa, and using a squeegee angle of 10-15 degrees, these optimized parameters ensure that the copper paste has good fluidity and filling properties during the screen printing process, while avoiding damage to the edge of the first connecting hole and precisely controlling the filling amount of copper paste to form a smooth and full first copper paste structure.

[0117] 420. The first sub-board and / or the second sub-board are baked to solidify the copper paste into a first copper paste structure, and the PET film of the second dielectric layer is removed. In step 420, the first sub-board and / or the second sub-board are baked to solidify the liquid or semi-liquid copper paste printed onto the first connector hole, thereby transforming it into a solid state through a thermal polymerization reaction, thus forming a first copper paste structure with stable mechanical strength and good electrical conductivity. The baking temperature is set to 90°C and the baking time is 30 minutes. These parameters are determined comprehensively based on the characteristics of the copper paste used and the heat resistance of the PCB sub-board, aiming to ensure that the copper paste can be fully cured to achieve optimal physical and electrical properties, while avoiding potential damage to the PCB sub-board due to excessively high temperature or excessively long baking time. In addition, the PET film is usually used as a temporary carrier or protective layer and is laminated together with the PP film when making the second dielectric layer. After the copper paste has cured, the PET film is removed to expose the solidified first copper paste structure, allowing it to directly participate in the subsequent stacking and lamination process and reliably connect with the pads of the other sub-board. The film peeling process needs to be carried out smoothly to avoid physical damage to the already formed first copper paste structure.

[0118] In one specific implementation, when both the first and second sub-boards have first connecting holes, a first copper paste structure can be fabricated on each sub-board. When only the second sub-board has first connecting holes, the first copper paste structure can be fabricated on the second sub-board. The first copper paste structure is a copper pillar solidified and protruding from the pads of the first or second sub-board. When both the first and second sub-boards have first copper paste structures, during the lamination of the PCB motherboard, the first copper paste structure can be fully laminated and filled between the pads of the first and second sub-boards. When only the second sub-board has the first copper paste structure, process steps can be saved, and production speed can be improved.

[0119] By employing the technical solutions in steps 410-420, using vacuum plugging equipment and precisely controlling screen printing parameters, efficient and uniform filling of copper paste into the tiny first connection holes can be ensured, effectively avoiding voids, bubbles, or excess adhesive that may occur with traditional screen printing. Subsequently, precise baking and curing allow the first copper paste structure to fully solidify, forming a stable electrical connection and improving the reliability and mechanical strength of the connection. Finally, the PET film is removed, revealing the complete first copper paste structure, providing a high-quality connection interface for subsequent stacking and lamination. These optimization measures work together to significantly improve the quality and consistency of the internal connections of the orthogonal backplane, thereby ensuring the overall performance and long-term reliability of the PCB motherboard.

[0120] In step 170, the first and second daughter boards are matched according to expansion and contraction data and stacked and pressed together through the first positioning hole to form a PCB motherboard. See [link to relevant documentation]. Figure 5 Specifically, it includes:

[0121] 510. Acquire expansion and contraction data for multiple first sub-boards and multiple second sub-boards, and group first and second sub-boards whose expansion and contraction data are within the same preset range. In step 510, expansion and contraction data is a key parameter for measuring the dimensional changes of PCB sub-boards during manufacturing, reflecting the dimensional expansion or contraction that may occur in different process stages such as lamination and baking. Acquiring expansion and contraction data for multiple sub-boards is to comprehensively understand the dimensional consistency of sub-boards in the production batch, providing a data basis for subsequent precise matching. Specifically, high-precision optical measurement equipment, such as automatic optical inspection equipment or coordinate measuring machines, can be used to accurately measure specific reference points or first positioning holes on the sub-boards. By comparing these measurement data with the standard dimensions on the design drawings, the expansion and contraction amount and direction of each sub-board can be calculated. This detailed expansion and contraction data can be recorded and stored in a database for batch analysis and filtering.

[0122] The core strategy of this method is to match the first and second sub-boards whose expansion and contraction data fall within the same preset range as a group. By setting a preset expansion and contraction range, sub-boards with similar expansion and contraction characteristics are grouped together to form a "group". The purpose of this grouping and matching is to ensure that the sub-boards within the same group have high dimensional compatibility during subsequent lamination, thereby minimizing alignment deviations caused by expansion and contraction differences. In practice, software algorithms can be used to analyze and classify the acquired expansion and contraction data. For example, an allowable expansion and contraction deviation threshold, such as ±X micrometers or ±Y%, can be set, marking the first and second sub-boards whose expansion and contraction amounts fall within this threshold as the same group. In addition, more complex clustering algorithms can be used to automatically group sub-boards based on the similarity of expansion and contraction data to achieve more refined matching. The similarity includes multiple dimensions such as the absolute value, relative value, or direction of expansion and contraction.

[0123] 520. After the first and second sub-boards of the same group are positioned and stacked along the first positioning holes, they are subjected to lamination and sintering to form a PCB motherboard. In step 520, ensuring a high degree of matching of the expansion and contraction characteristics of the sub-boards, and using the first positioning holes for precise alignment before lamination and sintering, is crucial to ensuring excellent electrical connectivity and mechanical stability of the laminated PCB motherboard. The positioning and stacking process can be completed by automated equipment, for example, using a high-precision vision recognition system to identify the first positioning holes on the sub-boards and driving a robotic arm to precisely align and stack the first and second sub-boards of the same group. After stacking, the sub-board assembly is sent to a laminator for lamination and sintering. During this process, by applying preset high temperature and high pressure, the dielectric layer between the sub-boards is solidified, and the first copper paste structure forms a reliable electrical connection. Lamination parameters, such as temperature, pressure, and time, are precisely controlled according to the material properties used and the design requirements of the final product to ensure optimal lamination results.

[0124] In a specific example, the first and second sub-boards with the smallest or closest differences in the intersection points of the center points of the diagonal lines of the outer layer pattern PADs at the four corners of the sub-board and the perpendicular intersection points of the four circular PIN-LAM holes in the XY direction are combined and pressed together for sintering. Four circular PIN-LAM holes are used for pressing, and the first copper paste structure can be sintered at 180℃-190℃ for 1 hour. See also... Figure 9 , Figure 9 The diagram shows a schematic of a PCB motherboard formed by pressing a first daughter board and a second daughter board together according to an embodiment of the present invention; the pads of the first daughter board are connected to the pads of the second daughter board through a first copper paste structure.

[0125] Specific matching methods could be:

[0126] Compare the dimensions of the first and second sub-boards and select those with dimensions within the same range.

[0127] Compare the positional accuracy of the first positioning holes on the first and second sub-boards, and select those with the same size range.

[0128] Compare the differences between the center points of the diagonals of the four corner points of the first sub-board and the second sub-board and the perpendicular intersection points of the four first positioning holes in the XY direction, and select the same range of dimensions.

[0129] Through the technical solutions in steps 510-520, this invention ensures that the selected first and second sub-boards have a highly consistent dimensional change trend before stacking and lamination. This refined matching strategy significantly reduces alignment deviations caused by differences in expansion and contraction of the sub-boards, thereby ensuring precise alignment of the pads on the first and second sub-boards when connected via the first copper paste structure. This not only effectively avoids defects such as poor connections, open circuits, or short circuits, improving the electrical connection reliability and overall performance of the PCB motherboard, but also significantly increases production yield, reduces scrap rates and rework costs, achieving efficient and high-quality orthogonal backplane manufacturing.

[0130] Example 2:

[0131] Based on Embodiment 1, the present invention also provides a second embodiment of the orthogonal backplane fabrication method, and provides a third sub-board solution. Similar to the first and second sub-boards, the third sub-board also needs to have a specific connecting outer layer for subsequent dielectric layer fabrication and interconnection hole formation. The second sub-board serves as an intermediate layer, with one side connected to the first sub-board and the other side connected to the newly introduced third sub-board; therefore, the second sub-board needs to have a third connecting outer layer. Correspondingly, the third sub-board has a fourth connecting outer layer as its interface with the second sub-board. These connecting outer layers are typically copper foil layers on the surface of the PCB sub-board, used to carry circuit patterns and provide electrical connection points.

[0132] When the PCB sub-board also includes a third sub-board, the second sub-board is further provided with a third connecting outer layer, and the third sub-board is provided with a fourth connecting outer layer. See [link to relevant documentation]. Figure 6 It also includes:

[0133] 610. A third dielectric layer is fabricated on the third and / or fourth connecting outer layers. In step 610, the third dielectric layer is typically formed by laminating and curing a PP film. Its function is to provide electrical insulation and to provide a foundation for the subsequent fabrication of the second connecting holes. The fabrication method can be to laminate and cure the PP film on both the third and fourth connecting outer layers separately, or to laminate the PP film on only one side and perform air compression on the other side to ensure that the expansion and contraction characteristics of each sub-board remain consistent during subsequent processing. Furthermore, the fabrication of the first and third dielectric layers on the second and third connecting outer layers of the second sub-board can be performed in the same step; that is, step 610 can be implemented in the same process as step 120.

[0134] 620. Second positioning holes are fabricated on the third sub-board, and the expansion and contraction data of the third sub-board are obtained based on these holes. In step 620, the second positioning holes serve as reference points for mechanical positioning, and their positional accuracy directly affects the alignment accuracy of the final PCB motherboard. After fabricating the second positioning holes, the expansion and contraction data of the third sub-board during the fabrication process can be obtained by measuring the actual positions of these holes and comparing them with standard design drawings. This expansion and contraction data is crucial for the subsequent precise matching and stacking of different sub-boards, effectively compensating for dimensional changes in the material during processing. Furthermore, step 620 can be implemented in the same process as step 130.

[0135] 630. A fourth dielectric layer is fabricated on the third and / or fourth connecting outer layers. In step 630, the fourth dielectric layer is typically formed using fast-pressed PP and PET films and is located outside the third dielectric layer. Prior to fabrication, the sub-board is typically subjected to a browning treatment to enhance the surface roughness of the copper foil and improve the adhesion between the dielectric layer and the copper foil. Furthermore, the second and fourth dielectric layers are fabricated on the second and third connecting outer layers of the second sub-board, respectively, and can be fabricated in the same step; that is, step 630 can be implemented in the same process as step 140.

[0136] 640. A second connecting hole is fabricated in the third and fourth dielectric layers. The second connecting hole penetrates both dielectric layers and its position matches the pads of the second and / or third sub-board. In step 640, the fabrication of the second connecting hole typically employs laser engraving technology to ensure a small hole diameter and high positional accuracy, thereby enabling reliable connection with the pads. The diameter of the second connecting hole is typically designed to be less than or equal to the diameter of the corresponding pad to ensure the effectiveness of subsequent copper paste filling and the reliability of the connection.

[0137] 650. Copper paste is printed at the second connection hole to form a second copper paste structure. In step 650, copper paste, a conductive material, is precisely filled into the second connection hole using a vacuum plugging device with specific squeegee parameters (such as squeegee thickness, speed, pressure, and angle). After filling, the copper paste needs to be baked and cured to form a stable second copper paste structure, thereby achieving electrical connection between the pads of the second and third sub-boards. Finally, the PET film is removed to expose the second copper paste structure.

[0138] Step 660 involves matching the first, second, and third sub-boards according to their expansion and contraction data, and then stacking and pressing them together through the first and second positioning holes to form a PCB motherboard. In step 660, sub-boards with expansion and contraction data within the same preset range are grouped, and then the first, second, and third sub-boards in the same group are precisely aligned and stacked along their respective second positioning holes. After stacking, a pressing and sintering process is performed to solidify and connect the sub-boards and dielectric layers together, ultimately forming a PCB motherboard with a multi-layer interconnect structure. This method, based on expansion and contraction data matching and second positioning hole stacking, effectively ensures the alignment accuracy and connection reliability between the multi-layer sub-boards.

[0139] In the embodiments of steps 610-660, by introducing a third daughterboard and setting a third and fourth connection outer layer for the second and third daughterboards respectively, the present invention can extend the number of layers of the orthogonal backplane to three or more. By fabricating a third and fourth dielectric layer on the newly added connection outer layer, fabricating a second positioning hole for the third daughterboard to obtain its expansion and contraction data, and fabricating a second connection hole and printing copper paste between the second and third daughterboards, the present invention provides a complete and accurate multilayer daughterboard interconnection scheme. Finally, the first, second, and third daughterboards are matched according to their respective expansion and contraction data and precisely stacked and pressed together through the second positioning hole, effectively solving the alignment deviation and connection reliability problems that may occur when stacking multilayer daughterboards. This enables the fabrication of multilayer orthogonal backplanes with more complex structures and more powerful functions, meeting the needs of higher density and more complex circuit designs.

[0140] In addition, PCB sub-boards can also be configured with a fourth sub-board, a fifth sub-board, etc., and their lamination process is the same as that of the first sub-board, the second sub-board, and the third sub-board being laminated into the PCB motherboard.

[0141] In one specific implementation, the PCB sub-board includes a first sub-board, a second sub-board, and a third sub-board. The first sub-board may be a multilayer board with layers L1-L26, where L26 is the first connecting outer layer. The second sub-board may be a multilayer board with layers L27-L52, where L27 is the second connecting outer layer and L52 is the third connecting outer layer. The first sub-board may also be a multilayer board with layers L53-L78, where L53 is the fourth connecting outer layer.

[0142] The process of laminating the first, second, and third daughter boards into a PCB motherboard is as follows:

[0143] The process involves core board cutting, patterning, sub-board lamination, sub-board drilling, sub-board electroplating, sub-board patterning, sub-board solder resisting, sub-board electroplating, and sub-board electrical testing to fabricate the first, second, and third sub-boards respectively.

[0144] The first connecting outer layer of the first sub-board and the fourth connecting outer layer of the third sub-board are pre-set with crimping holes. The crimping holes need to be partially plugged by semi-resin plugging treatment to prevent the PP film from being squeezed onto the board surface and affecting the electrical test points. Then, the excess resin remaining around the crimping holes is removed by laser treatment.

[0145] A PP film is pressed and cured onto each of the first, second, third, and fourth connecting outer layers to form the first dielectric layer. Alternatively, in this step, only the second and third connecting outer layers can be pressed and cured with PP film, while the first and second sub-plates are subjected to air pressure to ensure consistent expansion and contraction.

[0146] First and second positioning holes are fabricated on the first, second, and third sub-boards, respectively. The positioning holes are determined based on the four corner points of the PCB sub-board, and the deviation between the positioning holes and the corner points is determined using a CCD as expansion / contraction data. For example... Figure 11-12 As shown, the four positioning holes are positioning hole one, positioning hole two, positioning hole three and positioning hole four, and the four corner points are corner point one, corner point two, corner point three and corner point four.

[0147] A second dielectric layer is formed by pressing a PP film and a PET film on the outside of the first dielectric layer. This provides a carrier for the subsequent laser-engraved second connection hole and allows for connection through the second dielectric layer during PCB motherboard lamination.

[0148] After the first, second, and third sub-boards are browned, the second connecting holes are made by laser processing on the first and second dielectric layers. At the same time, excess PP film inside the holes of the second connecting holes can also be cleaned by laser processing.

[0149] Copper paste is screen-printed at the second connection hole using a vacuum plugging machine. After the copper paste has cured, the PET film is peeled off, causing the second copper paste structure to protrude from the PCB sub-board surface.

[0150] The first, second, and third sub-boards with small expansion and contraction data differences are grouped into a PCB sub-board. The first, second, and third sub-boards are stacked together using the first and second positioning holes as positioning references. The first, second, and third sub-boards are then pressed together into a multi-layer PCB motherboard through pressing and sintering.

[0151] See Figure 10 , Figure 10 The diagram shows a schematic of a PCB motherboard formed by pressing a first daughterboard, a second daughterboard, and a third daughterboard together according to an embodiment of the present invention. The pads of the first daughterboard are connected to the pads of the second daughterboard through a first copper paste structure, and the pads of the second daughterboard are connected to the pads of the third daughterboard through a second copper paste structure.

[0152] Example 3:

[0153] Based on Embodiment 1 or Embodiment 2, the present invention also provides a third embodiment of the orthogonal backplane fabrication method to ensure that the final product has excellent electrical connectivity and mechanical stability, especially for the pre-set crimp holes used in connectors, where the integrity, cleanliness, and dimensional accuracy of the hole walls are crucial. Specifically, before fabricating the first dielectric layer of the first connecting outer layer and / or the second connecting outer layer, see [link to documentation]. Figure 7 It also includes:

[0154] 710. Perform semi-resin plugging treatment on the pre-designed crimp holes of the PCB sub-board. In step 710, the pre-designed crimp holes are holes on the PCB sub-board designed for mounting crimp connectors or other circuit components. The semi-resin plugging treatment aims to protect and fill these critical holes in advance. This treatment prevents other process materials, such as dielectric materials, copper paste, electroplating solutions, etc., from accidentally entering or contaminating the crimp holes during subsequent processes such as dielectric layer fabrication, connector hole fabrication, or copper paste printing, thereby affecting the quality of the crimp connection. Semi-resin plugging treatment also provides structural support for the crimp holes and helps to form a smooth surface in subsequent processes, providing a good foundation for subsequent laser cleaning. The selection of resin materials typically considers their insulation, heat resistance, adhesion to the PCB substrate, and subsequent processability.

[0155] 720. After completing the semi-resin plugging process, excess resin around the pre-set crimping holes is cleaned using laser resurfacing. In step 720, laser resurfacing technology is used to precisely clean these areas. Laser resurfacing utilizes a high-energy-density laser beam to ablate or vaporize the target area, removing excess resin around the pre-set crimping holes and at the hole openings with extremely high precision, while avoiding damage to the PCB substrate or hole walls. By precisely controlling laser parameters, such as power, pulse width, and scanning speed, the dimensional accuracy of the crimping holes and the cleanliness of the hole walls can be ensured, providing ideal interface conditions for subsequent crimping connections.

[0156] In a specific example, the PCB sub-board includes a first sub-board, a second sub-board, and a third sub-board. The first connecting outer layer of the first sub-board and the fourth connecting outer layer of the third sub-board both have pre-set crimping holes. Semi-resin plugging can be performed on the first and fourth connecting outer layers using a printing pressure of 0.5 MPa, a speed of 80 mm / s, and one printing pass to prevent the PP adhesive from being squeezed onto the board surface and affecting the electrical test points. The resin on the PADs next to the crimping holes on the first connecting outer layer of the first sub-board and the fourth connecting outer layer of the third sub-board is burned off to prevent poor contact between the resin on the PADs and the next layer of copper paste.

[0157] By employing the aforementioned technical solution, before fabricating the first dielectric layer, the pre-set crimping holes on the PCB sub-board undergo a semi-resin plugging process, followed by laser cleaning to remove excess resin around the crimping holes. This effectively solves the potential contamination and precision issues that pre-set crimping holes may face during orthogonal backplane manufacturing. The semi-resin plugging process effectively isolates the crimping holes from subsequent process materials, maintaining the cleanliness and integrity of the hole walls. Laser cleaning further ensures the precise dimensions and residue-free surface of the crimping holes, eliminating potential connection defects or mechanical interference caused by excess resin. This pretreatment significantly improves the reliability and consistency of the crimping holes, thereby guaranteeing the electrical connection performance and mechanical stability of the crimped connectors on the final PCB motherboard, reducing rework rates and product failure risks due to crimping hole issues, and improving the overall manufacturing quality and reliability of the orthogonal backplane.

[0158] Example 4:

[0159] Based on any of the embodiments in Examples 1-3, the present invention also provides an embodiment of an orthogonal backplane manufacturing apparatus to perform the orthogonal backplane manufacturing method of any of the embodiments in Examples 1-3. By acquiring the expansion and contraction data of the sub-board and matching and pressing it accordingly, and combining it with printing copper paste at the connection hole to form a connection structure, the problem of interlayer alignment deviation in the traditional method is effectively solved. This not only improves the interlayer alignment accuracy and reduces the deviation caused by the accumulation of expansion and contraction, but also improves the backplane manufacturing yield and signal transmission performance.

[0160] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. Similarly, for the sake of brevity and to aid in understanding one or more aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0161] Those skilled in the art will understand that the modules in the device of the embodiment can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiment can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components, except that at least some of such features and / or processes or units are mutually exclusive.

[0162] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A method for manufacturing an orthogonal backplate, characterized in that, The method includes: Obtain a PCB sub-board, wherein the PCB sub-board includes at least a first sub-board and a second sub-board, the first sub-board having a first connecting outer layer and the second sub-board having a second connecting outer layer; A first dielectric layer is fabricated in the first connection outer layer and / or the second connection outer layer; First positioning holes are made in the first sub-board and the second sub-board respectively, and expansion and contraction data of the first sub-board and the second sub-board are obtained according to the first positioning holes; A second dielectric layer is fabricated outside the first dielectric layer; A first connection hole is formed in the first dielectric layer and the second dielectric layer. The first connection hole penetrates the first dielectric layer and the second dielectric layer, and the position of the first connection hole matches the pad of the first sub-board and / or the second sub-board. A first copper paste structure is formed by printing copper paste at the first connecting hole; The first sub-board and the second sub-board are matched according to the expansion and contraction data, and the matched first sub-board and the second sub-board are stacked and pressed together through the first positioning hole to form a PCB motherboard, so that the pads of the first sub-board are connected to the pads of the second sub-board through the first copper paste structure. Specifically, first positioning holes are made in the first sub-board and the second sub-board respectively, and expansion and contraction data of the first sub-board and the second sub-board are obtained based on the first positioning holes, including: Obtain the preset standard drawings of the first sub-board and the second sub-board, wherein corner points are set at the four corners of the standard drawings; Connect the diagonally opposite corner points with a first connecting line, and the intersection of the two first connecting lines shall be used as the standard center point; The adjacent corner points are connected by a second connecting line. The center point coordinates of the second connecting line are the positioning coordinates, and any positioning coordinate is added to a preset offset to form a foolproof coordinate. First positioning holes are made on the first sub-plate and the second sub-plate according to the positioning coordinates and the error-proof coordinates; Obtain the actual coordinates of the first positioning hole, and after compensating for the preset offset of the error prevention coordinates, connect the non-adjacent actual coordinates through the third connecting line, and take the intersection of the two third connecting lines as the actual center point. The expansion / contraction data is calculated based on the difference between the actual center point and the standard center point.

2. The method for manufacturing an orthogonal backplate according to claim 1, characterized in that, The process of obtaining the PCB sub-board specifically includes: sequentially producing the PCB sub-board through the following steps: core board cutting process, inner layer patterning process, sub-board lamination process, sub-board drilling process, sub-board electroplating process, sub-board outer layer patterning process, sub-board solder mask process, sub-board gold plating process, and sub-board electrical testing process.

3. The method for manufacturing an orthogonal backplate according to claim 1, characterized in that, Fabricating a first dielectric layer in the first and / or second connection outer layers specifically includes: The first dielectric layer is formed by pressing and curing PP film in the first and second connecting outer layers respectively; Alternatively, a first dielectric layer is formed by pressing and curing a PP film on the first connecting outer layer, and air compression is performed on the second connecting outer layer.

4. The method for manufacturing an orthogonal backplate according to claim 1, characterized in that, Fabricating a second dielectric layer outside the first dielectric layer specifically includes: The first and second sub-boards are subjected to browning treatment; A second dielectric layer is formed in the first connecting outer layer and / or the second connecting outer layer by fast-pressed PP film and PET film, respectively, and the second dielectric layer is located outside the first dielectric layer.

5. The method for manufacturing an orthogonal backplate according to claim 4, characterized in that, Printing copper paste at the first connecting hole to form a first copper paste structure specifically includes: Copper paste is screen-printed onto the first connection hole using a vacuum plugging device; The first sub-board and / or the second sub-board are baked to solidify the copper paste to form a first copper paste structure, and the PET film of the second dielectric layer is removed.

6. The method for manufacturing an orthogonal backplate according to claim 4, characterized in that, The first sub-board and the second sub-board are matched according to the expansion and contraction data, and the matched first sub-board and the second sub-board are stacked and pressed together through the first positioning hole to form a PCB motherboard, specifically including: Obtain expansion and contraction data of multiple first sub-boards and multiple second sub-boards, and group the first sub-boards and second sub-boards whose expansion and contraction data are within the same preset range as a group; After the first and second sub-boards in the same group are positioned and stacked along the first positioning hole, they are pressed and sintered to form the PCB motherboard.

7. The method for manufacturing an orthogonal backplate according to claim 1, characterized in that, When the PCB sub-board further includes a third sub-board, the second sub-board is further provided with a third connecting outer layer, and the third sub-board is provided with a fourth connecting outer layer, and further includes: A third dielectric layer is fabricated in the third and / or fourth connection outer layers; A second positioning hole is made in the third sub-board, and the expansion and contraction data of the third sub-board is obtained according to the second positioning hole; A fourth dielectric layer is fabricated in the third and / or fourth connection outer layers; A second connection hole is formed in the third dielectric layer and the fourth dielectric layer. The second connection hole penetrates the third dielectric layer and the fourth dielectric layer, and the position of the second connection hole matches the pad of the second sub-board and / or the third sub-board. A second copper paste structure is formed by printing copper paste at the second connecting hole; The first sub-board, the second sub-board, and the third sub-board are matched according to the expansion and contraction data and stacked and pressed together through the first positioning hole and the second positioning hole to form a PCB motherboard.

8. The method for manufacturing an orthogonal backplate according to claim 7, characterized in that, Before fabricating the first dielectric layer on the first and / or second interconnect outer layers, the method further includes: The preset crimping holes of the PCB sub-board are treated with semi-resin plugging. After completing the semi-resin plugging process, excess resin around the pre-set crimping holes is cleaned using a laser.

9. An orthogonal backplate manufacturing apparatus, characterized in that, The apparatus is used to perform the orthogonal backplate manufacturing method according to any one of claims 1-8.

Images