Chemical mechanical planarization system, chemical mechanical planarization device and operation method thereof

Abstract

The system includes a platen configured to secure a polishing pad, where the polishing pad includes a slot in a top surface of the polishing pad and an opening extending from the slot to a bottom surface of the polishing pad; the fixer is configured to fix the workpiece on the polishing pad; and an optical inspection device located within the platen, where the optical inspection device is configured to measure a characteristic of a bottom surface of the workpiece through the opening in the polishing pad. The embodiment of the invention also relates to a chemical mechanical planarization system, a chemical mechanical planarization device and an operation method thereof.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a chemical mechanical planarization system, a chemical mechanical planarization apparatus, and a method of operating the same. BACKGROUND

[0002] As layers of a semiconductor device are formed, a planarization process can be implemented to planarize the layers to facilitate the formation of subsequent layers. For example, forming metal features in a substrate or a metal layer can result in uneven topography. Such uneven topography can cause difficulties in the formation of subsequent layers. For example, uneven topography can interfere with photolithography processes that are commonly used to form individual features in a device. Thus, it can be advantageous to planarize the surface of a device after individual features or layers are formed.

[0003] Chemical mechanical polishing (CMP) is a common practice in the formation of integrated circuits. Typically, CMP is used for planarization of semiconductor wafers. CMP takes advantage of the synergistic effect of physical and chemical forces to polish a wafer. It is implemented by applying a load force to the backside of the wafer while the wafer is resting on a polishing pad. The polishing pad is placed against the wafer. Then, both the polishing pad and the wafer are rotated while a slurry containing an abrasive and a reactive chemical passes between them. CMP is an effective method to achieve global planarization of a wafer. SUMMARY

[0004] Some embodiments of the present application provide a chemical mechanical planarization system, comprising: a platen configured to secure a polishing pad, wherein the polishing pad comprises: a plurality of slots in a top surface of the polishing pad; and a plurality of openings extending from the slots to a bottom surface of the polishing pad; a holder configured to secure a workpiece above the polishing pad; and a plurality of optical inspection devices within the platen, wherein the optical inspection devices are configured to measure a property of a bottom surface of the workpiece through the plurality of openings in the polishing pad.

[0005] Some embodiments of the present application provide a chemical mechanical planarization system, comprising: a platen configured to secure a polishing pad, wherein the polishing pad comprises: a plurality of slots in a top surface of the polishing pad; and a plurality of openings extending from the slots to a bottom surface of the polishing pad; a holder configured to secure a workpiece above the polishing pad; and a plurality of optical inspection devices within the platen, wherein the optical inspection devices are configured to measure a property of a bottom surface of the workpiece through the plurality of openings in the polishing pad.

[0006] Yet other embodiments of the present application provide a method of operating a chemical mechanical planarization apparatus, comprising: attaching a polishing pad to a platen, wherein the platen comprises a plurality of light sources and a plurality of optical detectors, wherein the polishing pad comprises a plurality of holes; placing a wafer on the polishing pad, wherein the wafer comprises a gate structure over a plurality of nanostructures; rotating the polishing pad to polish the wafer; while rotating the polishing pad, emitting light from the plurality of light sources through the plurality of holes toward the wafer, and detecting light reflected from the wafer through the plurality of holes toward the plurality of optical detectors using the plurality of optical detectors; and singulating the wafer into a plurality of dies. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the illustrative embodiments can be best understood with reference to the following detailed description when read with the accompanying drawings in which: It should be noted that various components have not been drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion. It is also to be understood that the discussion of any feature can be made in relation to any other feature or combination of features.

[0008] Figure 1 A perspective view of a chemical mechanical polishing (CMP) apparatus according to an embodiment is shown.

[0009] Figure 2 An enlarged cross-sectional view of a CMP apparatus according to an embodiment is shown.

[0010] Figure 3 A partial schematic view of a CMP apparatus in a perspective view according to an embodiment is shown.

[0011] Figure 4 , Figure 5 , Figure 6 and Figure 7 An enlarged cross-sectional view of a CMP apparatus according to some embodiments is shown.

[0012] Figure 8 An enlarged cross-sectional view of a CMP apparatus according to an embodiment is shown.

[0013] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 A top-down plan view of a polishing pad according to some embodiments is shown.

[0014] Figure 17 A perspective view of an exemplary complementary field effect transistor (CFET) according to some embodiments is shown.

[0015] Figure 18 , Figure 19、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 and Figure 25 A cross-sectional view showing an intermediate stage in the manufacture of a CFET structure, in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first component (e.g., over or on) a second component can include embodiments where the first component is formed directly on the second component or where the first component is formed on a third component that is formed on the second component, and so on. Exemplary components, arrangements, and variations thereof are described in more detail below.

[0017] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Chemical mechanical polishing (CMP) is a method of planarizing features created in the manufacture of semiconductor devices. The process uses an abrasive material in an active chemical slurry in combination with a polishing pad. The polishing pad typically has a diameter larger than that of the semiconductor wafer. In some cases, the polishing pad can be formed from a stack of multiple pads, such as a top pad attached to a sub-pad, etc. The pad and wafer are pressed together during the CMP process. The process removes material and tends to flatten irregular topography, leaving the wafer flat or substantially planar. This prepares the wafer for formation of additional overlying circuit elements.

[0019] In a CMP process, the wafer is affixed to a polishing head (also referred to as a "head" or "carrier"). The polishing head and wafer are then rotated while a downward pressure is applied to press the wafer against the polishing pad. In some cases, the polishing pad can also be rotated. A reactive chemical solution (e.g., slurry) is dispensed on the contact surface of the polishing pad to aid in planarization. Thus, the surface of the wafer can be planarized using a combination of mechanical and chemical mechanisms.

[0020] Various representative embodiments are described regarding the operation of CMP tools and, particularly, the inspection of workpieces (e.g., wafers) during CMP tool operation. Slots in the polishing pad of the CMP tool allow for optical inspection of the workpiece during the planarization process. The slots may be located within a top-side groove of the polishing pad. The slots extend through the top and sub-pads forming the polishing pad. Slots in the polishing pad can allow for the use of multiple optical inspection systems within the CMP tool, thereby improving in-situ inspection of the workpiece. Inspecting the workpiece during planarization can, for example, reduce stop layer loss. Various arrangements of grooves, slots, and inspection systems are possible.

[0021] Figure 1 A perspective view of a chemical mechanical polishing (CMP) apparatus 100 (also referred to as a polisher or CMP tool) according to some embodiments is shown. The CMP apparatus 100 includes a platform 140 and a polishing pad 150 attached to the platform 140. In some embodiments, the polishing pad 150 includes a single layer or multiple layers, such as a plurality of pads attached together in a stacked manner. The layers of the polishing pad 150 may include one or more materials, such as felt, polymer-impregnated felt, microporous polymer membrane, microporous synthetic leather, filled polymer membrane, unfilled textured polymer membrane, transparent layer, combinations thereof, etc. Representative polymers include polyurethane, polyolefins, etc. For example, in some embodiments, the polishing pad 150 may include a sub-pad 152 and a top pad 156 attached to the sub-pad 152, as described in more detail below. In some embodiments, the polishing pad 150 includes grooves, channels, channels, openings, recesses, etc.

[0022] like Figure 1 As shown, a polishing head 120 is positioned above a polishing pad 150. During a typical CMP process, a workpiece 130 (e.g., a semiconductor wafer) is secured or attached to the polishing head 120. The workpiece 130 is positioned such that the surface to be polished faces toward the polishing pad 150 (e.g., downwards). The polishing head 120 may be configured to apply a downward force or pressure to bring the workpiece 130 into contact with the polishing pad 150. In some cases, the workpiece 130 may not be in direct contact with the polishing pad 150 during the CMP process. The polishing head 120 is configured to rotate the workpiece 130 above the polishing pad 150 during the CMP process, thereby imparting a mechanical abrasive action to affect the planarization or polishing of the contact surface of the workpiece.

[0023] In some embodiments, the CMP apparatus 100 includes a slurry distributor 110 configured to deposit slurry 115 onto a polishing pad 150. A platform 140 may be configured to rotate such that the slurry 115 is distributed between the workpiece 130 and the polishing pad 150. In some cases, the polishing pad 150 includes grooves that allow the slurry and any removed particles to flow toward the periphery of the polishing pad 150. Figure 1The slurry 115 can be applied to the workpiece 130 by a slurry applicator 120 (not shown in FIG. 1, but shown in subsequent figures) to improve the polishing process. The composition of the slurry 115 can depend on the type of material to be polished or removed.

[0024] Figure 2 An enlarged cross-sectional view of a portion of the CMP apparatus 100 is shown in accordance with some embodiments. Figure 2 The portion shown in FIG. 2 can be similar to the portion shown in FIG. 1. Figure 1 The portion of the CMP apparatus 100 shown in FIG. 2 includes the workpiece 130 connected to the polishing head and the polishing pad 150 attached to the platen 140. The platen 140 also includes the optical inspection system 141 for inspecting the underside of the workpiece 130 during the CMP process. Figure 2

[0025] In some embodiments, the polishing pad 150 includes multiple pads or layers. For example, Figure 2 The polishing pad 150 shown in FIG. 2 includes an upper pad (referred to herein as a top pad 156) attached to a lower pad (referred to herein as a sub-pad 152). The top pad 156 and the sub-pad 152 can be formed of similar or different materials and can have similar or different hardness, texture, or other properties. The top pad 156 and the sub-pad 152 can be secured or attached together to ensure that they do not move independently with respect to each other. As described further in embodiments of the present disclosure, the top pad 156 can have a slot 157 along and within a top surface of the top pad 156. The top pad 156 can also include a top aperture 158 (described in more detail below) located within the slot 157, the top aperture 158 extending through the top pad 156 from the slot 157 to a bottom surface of the top pad 156. The sub-pad 152 can include a sub-aperture 154 extending through the sub-pad 152. In some embodiments, the top aperture 158 and the sub-aperture 154 can be aligned (e.g., can overlap laterally or can exist along the same vertical line). As will be discussed in more detail below, the polishing pad 150 can include various patterns, configurations, or arrangements of the slot 157, the top aperture 158, and the sub-aperture 154.

[0026] The top pad 156 can be attached to the sub-pad 152, and the sub-pad 152 can be attached to the platen 140 using suitable techniques, such as using an adhesive, glue, screws, clamps, etc. (not shown in the figures). For example, in some cases, the sub-pad 152 is attached to the platen 140 using an adhesive, and the top pad 156 is attached to the sub-pad 152 using an adhesive. The adhesive can include, for example, a pressure sensitive adhesive, a reactive hot melt adhesive, a polyurethane adhesive, an epoxy, an adhesive layer or pad, etc. Other techniques are possible.

[0027] ​In some embodiments, the platen 140 includes one or more optical inspection systems 141. The optical inspection systems 141 can rotate with the platen 140, but in other embodiments, the optical inspection systems 141 can be stationary with respect to rotation of the platen 140. The optical inspection systems 141 are devices, components, modules, systems, etc. that can inspect (e.g., measure, monitor, detect, etc.) characteristics of the bottom surface of the workpiece 130 to facilitate the desired planarization implemented by the CMP process. For example, the optical inspection systems 141 can inspect the surface (e.g., bottom or underside surface) of the planarized workpiece 130 to determine the thickness or thickness profile of a layer (e.g., the bottommost layer) of the workpiece 130. As another example, the optical inspection systems 141 can detect the spectrum of light reflected by the bottom surface of the workpiece 130 to determine the composition of the material at the bottom surface of the workpiece 130. In this manner, the optical inspection systems 141 can be able to determine whether the bottommost layer of the workpiece 130 has been removed based on the spectrum of the reflected light. For example, if the bottommost layer covers the stop layer, the polishing operation can be paused when the stop layer is exposed. In this manner, the amount of stop layer material removed by the polishing process can be reduced.

[0028] Characteristics such as roughness, material, reflectivity, absorptivity, etc. can also be determined by the optical inspection systems 141. The optical inspection systems 141 can utilize appropriate techniques such as ellipsometry, interferometry, reflectometry, spectroscopy, imaging, etc. Other techniques or characteristics are possible. In some embodiments, the CMP apparatus 100 can include more than one type of optical inspection system 141. In some embodiments, the optical inspection systems 141 operate during (e.g., concurrently with) the polishing operation of the CMP process. In other embodiments, the polishing operation of the CMP process can be stopped or paused to allow the optical inspection systems 141 to operate.

[0029] As an example, in some embodiments, the optical inspection system 141 may include a light source 142 and a detector 144. The light source 142 may emit light oriented toward a region of the bottom surface of the workpiece 130, and the detector 144 senses the light reflected or scattered from the region of the bottom surface of the workpiece 130. The optical inspection system 141 may determine the characteristics of the region of the bottom surface of the workpiece 130 based on the light received by the detector 144. The light source 142 may be any suitable electromagnetic radiation source, such as a light-emitting diode, laser, lamp, broadband light source, etc., depending on the inspection technique used by the optical inspection system 141. The detector 144 may be any suitable optical detector, optical sensor, light sensor, etc., depending on the inspection technique used by the optical inspection system 141. In some cases, the spectrum of the light emitted by the light source 142 may completely or partially overlap with the spectrum of the light sensed by the detector 144. For example, the optical inspection system 141 can operate in the white light spectrum (e.g., wavelengths in the range of about 300 nm to about 700 nm), in the infrared spectrum (e.g., wavelengths in the range of about 780 nm to about 1400 nm), or with any other suitable wavelength of light.

[0030] like Figure 2 As shown, in order to allow light emitted from light source 142 to reach workpiece 130, and to allow light reflected from workpiece 130 to reach detector 144, sub-pad 152 includes sub-slits 154, and top pad 156 includes top slits 158. Sub-slits 154 are openings in sub-pad 152, and top slits 158 are openings in top pad 156 above sub-slits 154. Thus, an open (or optically transparent) area is provided in polishing pad 150 for light transmission. In this way, light emitted and / or received by optical inspection system 141 can pass through the associated slits 154 / 158 to allow optical inspection of workpiece 130 through polishing pad 150. Therefore, the opening (including slits 154 / 158) extending fully through polishing pad 150 can be considered as "inspection hole 153". Each optical inspection system 141 is aligned with a top aperture 158 and a sub-aperture 154, and in some embodiments, multiple optical inspection systems may be aligned with the same top aperture 158 and / or the same sub-aperture 154. In some embodiments, light emitted by the optical inspection system 141 and light received by the same optical inspection system 141 passes through the same set of apertures 154 / 158.

[0031] In some embodiments, each top aperture 158 is aligned with a slot 157 of the top pad 156. In other words, the portion of the inspection hole 153 that extends through the top pad 156 includes the slot 157 and the top aperture 158. Each top aperture 158 is located below a slot 157 to form a continuous opening (e.g., hole) through the top pad 156 formed by the top aperture 158 and the slot 157. The slot 157 can extend above one or more top apertures 158 or span one or more top apertures 158. In some cases, multiple top apertures 158 can be located below the same slot 157. Aligning the top aperture 158 with the slot 157 allows the top aperture 158 to have a smaller height because the top aperture 158 does not need to extend through the full thickness of the top pad 156. Moreover, locating the top aperture 158 below the slot 157 can reduce the impact of the presence of the top aperture 158 on the polishing of the workpiece 130. Each sub-aperture 154 is located below the top aperture 158 to form a continuous inspection hole 153 through the polishing pad 150. Thus, each sub-aperture 154 is aligned with the top aperture 158 and the slot 157. In this way, each inspection hole 153 includes the slot 157, the top aperture 158, and the sub-aperture 154. In some cases, the slot 157, the top aperture 158, and / or the sub-aperture 154 can be shared by two or more inspection holes 153.

[0032] The slot 157, the top aperture 158, and the sub-aperture 154 can have any suitable length, width, or shape that allows light to pass through the polishing pad 150. For example, Figure 2 Embodiments are shown in which the top aperture 158 below the slot 157 has a smaller width than the slot 157, and in which the sub-aperture 154 below the top aperture 158 has a larger width than the top aperture 158. In other embodiments, the widths of the slot 157, the top aperture 158, and the sub-aperture 154 can be larger, smaller, or about the same as one another in any suitable combination. In some embodiments, the slot 157 can extend to a depth in the top pad 156 in a range from about 0.2 mm to about 2 mm. In some embodiments, the slot 157 can have a width in a range from about 0.3 mm to about 2 mm, the top aperture 158 can have a width in a range from about 0.3 mm to about 2.5 mm, and the sub-aperture can have a width in a range from about 0.3 mm to about 2 mm. In some embodiments, the top pad 156 has a thickness in a range from about 0.5 mm to about 3 mm, and the sub-pad 152 has a thickness in a range from about 0.5 mm to about 3 mm. Other configurations, shapes, widths, thicknesses, or dimensions are possible.

[0033] Figure 3 A partial schematic of the CMP apparatus 100 in perspective view is shown in accordance with some embodiments. Figure 3 The CMP apparatus 100 shown in FIG. 1 can be similar to the CMP apparatus 100 previously described with respect toFigure 1 and Figure 2 Those described. For example, Figure 3 An exploded view of a polishing pad 150, including a top pad 156 and sub-pads 152, is shown. The top pad 156 includes a pattern of grooves 157 and a plurality of top slots 158 aligned with the grooves 157. The sub-pad 152 includes a plurality of sub-slots 154 aligned with the top slots 158. The platform 140 (outlined in dashed lines) includes a plurality of optical inspection systems 141 aligned with the sub-slots 154. The "covered area" of the workpiece 130 is indicated by dashed lines. Figure 3 As shown, the optical inspection system 141 can emit and receive light through the slits 154 / 158 in the polishing pad 150 to inspect different areas of the workpiece 130.

[0034] The pattern, arrangement, or number of slots 157, top slit 158, sub-slit 154, and / or optical inspection system 141 may be consistent with... Figure 3 The differences shown herein, and all suitable variations are considered to be within the scope of embodiments of this disclosure. The optical inspection system 141 can be arranged in a suitable spatial distribution depending on the configuration of the apertures 154 / 158 of the polishing pad 150. Distributing multiple inspection systems 141 across a region of the workpiece 130 allows for the simultaneous inspection of different portions of the workpiece 130. The use of apertures 154 / 158 as described herein allows for the use of multiple optical inspection systems 141 in the CMP process, thereby enabling more sampling locations. This can allow for improved workpiece inspection during planarization, improved planarization uniformity, improved planarization accuracy, and improved yield.

[0035] Figures 4 to 7 An embodiment of a polishing pad 150 including a transparent layer 155 is shown according to some embodiments. Figures 4 to 7 The polishing pad 150 is similar to the one designed for... Figures 1 to 3 The description and Figure 2 The polishing pad 150 shown extends across the inspection aperture 153, except for a transparent layer 155. The transparent layer 155 may be present, for example, to at least partially block the slurry 115 from flowing into the apertures 154 / 158. The transparent layer 155 may also prevent the slurry 115 from flowing onto the stage 140 or onto the components of the optical inspection system 141. In this way, the amount of light absorbed or blocked by the slurry 115 in the inspection aperture 153 can be reduced, and the components of the optical inspection system 141 can be protected from the effects of the slurry 115. Therefore, using a transparent layer 155 within the polishing pad 150 can improve the operation of the optical inspection system 141.

[0036] The transparent layer 155 can be a layer that has a high light transmittance of light (e.g., a transmittance in a range of about 60% to about 99%) in the wavelength range used by the optical inspection system 141. For example, the transparent layer 155 can be formed of a polymeric material such as polymethyl methacrylate (PMMA), although other materials are possible. In some embodiments, the transparent layer 155 can be attached using one or more adhesive layers (not shown), such as those previously described for the polishing pad 150. The transparent layer 155 can have any suitable thickness. The transparent layer 155 can be a single continuous layer within the polishing pad 150 that extends across all of the inspection holes 153 in the polishing pad 150. In some cases, the transparent layer 155 extends entirely across the polishing pad 150. While a single transparent layer 155 is shown in the middle, multiple transparent layers can be present in other embodiments. Figures 4 to 7 While a single transparent layer 155 is shown in the middle, multiple transparent layers can be present in other embodiments. Figures 4 to 7 Some example locations of the transparent layer 155 within the polishing pad 150 are shown, although the transparent layer 155 can have other locations in other embodiments.

[0037] Figure 4 Embodiments are shown in which the polishing pad 150 includes the transparent layer 155 between the sub-pad 152 and the top pad 156. In this way, slurry 115 can be prevented from flowing into the sub-hole gap 154. In some embodiments, the transparent layer 155 can be attached to the sub-pad 152 using an adhesive, and the transparent layer 155 can be attached to the top pad 156 using an adhesive.

[0038] Figure 5 Embodiments are shown in which the polishing pad 150 includes the transparent layer 155 within the sub-pad 152. In other words, the transparent layer 155 extends across the sub-hole gap 154. In this way, slurry 115 can be prevented from flowing into the lower region of the sub-hole gap 154. Figure 6 Embodiments are shown in which the polishing pad 150 includes the transparent layer 155 within the top pad 156. In other words, the transparent layer 155 extends across the top-hole gap 158. In this way, slurry 115 can be prevented from flowing into the lower region of the top-hole gap 158 and into the sub-hole gap 154. In other embodiments, the transparent layer 155 can be located between the slot 157 and the top-hole gap 158, separating the slot 157 from the top-hole gap 158.

[0039] Figure 7 Embodiments are shown in which the polishing pad 150 includes the transparent layer 155 below the sub-pad 152. In other words, the transparent layer 155 is located between the sub-pad 152 and the platen 140. In this way, slurry 115 can be prevented from flowing onto the platen 140 and onto components of the optical inspection system 141. In some embodiments, the transparent layer 155 can be attached to the sub-pad 152 using an adhesive, and the transparent layer 155 can be attached to the platen 140 using an adhesive.

[0040] Figure 8 A polishing pad 150 including a transparent sub-pad 152 is shown according to some embodiments. Figure 8 The polishing pad 150 is similar to the one designed for... Figures 1 to 3 The description and Figure 2 The polishing pad 150 shown is a transparent layer, except that the sub-pad 152 itself is a transparent layer. Therefore, in Figure 8 In this embodiment, there is no sub-aperture 154 because light can pass directly through the transparent sub-pad 152. The optical inspection system 141 can be aligned with the top aperture 158. The transparent sub-pad 152 can have high light transmittance (e.g., transmittance in the range of about 60% to about 99%) within the wavelength range used by the optical inspection system 141. The transparent sub-pad 152 can be formed of materials similar to those described for the transparent layer 155, such as PMMA, but other materials are possible. The use of the transparent sub-pad 152 as described herein can reduce light attenuation due to the presence of the paste 115 and can allow for improved optical inspection during CMP processes. Furthermore, the transparent sub-pad 152 can protect the stage 140 or the components of the optical inspection system 141 from the paste 115.

[0041] Figures 9 to 16 A plan view of a polishing pad 150 according to some embodiments is shown. Figures 9 to 16 A top-down view is shown, with workpiece 130 indicated by dashed lines. During the CMP process, polishing pad 150 and / or workpiece 130 can be rotated, and workpiece 130 can be translated along the surface of polishing pad 150. Polishing pad 150 is similar to that previously shown for... Figures 1 to 7 Those described. For example, Figures 9 to 16 The polishing pad 150 includes the sub-pad 152 (only in the polishing pad 150). Figure 16 The top pad 156 (visible from above) includes one or more grooves 157 located in the top surface of the top pad 156 and a plurality of top perforation slots 158 located within the grooves 157 and extending through the top pad 156. The sub-pad 152 includes a plurality of sub-perforation slots 154 aligned with the top perforation slots 158 (only on the top pad 156). Figure 16 (Visible individually in the middle). Groove 157, top slot 158, and sub-slot 154 together form inspection hole 153 extending through polishing pad 150. Figures 9 to 15 In the top view, the sub-slit 154 has an area similar to or larger than the top slit 158 ​​above, and is therefore not visible in the top-down view. In other embodiments, the sub-slit 154 may have an area smaller than the top slit 158 ​​above. The platform 140 (not visible in the figure) is located below the polishing pad 150 and includes an optical inspection system 141, shown as a circle in the figure. The optical inspection system 141 is aligned with the inspection hole 153, and therefore...Figures 9 to 16 It can be seen through inspection hole 153 in the top-down view.

[0042] Figures 9 to 16 Various configurations and arrangements of the slot 157, inspection hole 153, and optical inspection system 141 are shown. Figures 9 to 16 The polishing pad 150 shown is intended as a non-limiting illustrative example, and any other suitable configuration or arrangement is considered to be within the scope of embodiments of this disclosure. The various features and arrangements described for the polishing pad 150 in embodiments of this disclosure can be combined in any suitable manner. For example, in other embodiments, Figures 9 to 16 The polishing pad 150 may include a transparent layer 155, or may include a combination of a groove 157, an inspection hole 153, and an optical inspection system 141 with various configurations or arrangements.

[0043] Figure 9 A polishing pad 150 with concentric grooves 157 is shown according to some embodiments. For example, the grooves 157 may be arranged in a concentric circle configuration. Figure 9 Three concentric grooves 157 are shown located in the top pad 156, but in other embodiments, a different number of grooves 157 may be present. Inspection holes 153 are evenly arranged around the grooves 157, but in other embodiments, the inspection holes 153 may have a different number or arrangement. Figure 9 In this embodiment, each inspection hole 153 corresponds to one optical inspection system 141. In other words, each optical inspection system 141 is located below a single inspection hole 153, through which it inspects the workpiece 130.

[0044] Figure 10 A polishing pad 150 with concentric grooves 157 is shown according to some embodiments. The polishing pad 150 is similar to Figure 9 The polishing pad 150, in addition to multiple optical inspection systems 141 inspecting the workpiece 130 through the same inspection hole 153. In other words, each inspection hole 153 extends above multiple optical inspection systems 141. Figure 10 In this embodiment, three optical inspection systems 141 are associated with each inspection aperture 153, but in other embodiments, any number of optical inspection systems 141 may use the same inspection aperture 153. In some cases, distributing the optical inspection systems 141 so that multiple optical inspection systems 141 inspect the workpiece 130 through the same inspection aperture 153 may allow for a larger number or higher density of optical inspection systems 141 capable of inspecting the workpiece 130 simultaneously.

[0045] Figure 11 A polishing pad 150 with radial grooves 157A and concentric grooves 157B according to some embodiments is shown. The radial grooves 157A and concentric grooves 157B can form a continuous pattern, such as...Figure 11 In other cases, some slots 157A-157B can be separated from other slots 157A-157B. Another number of slots 157A-157B can be present in other embodiments. As shown in Figure 11 In other embodiments, the different slots 157A-157B in the polishing pad 150 can have different widths. The inspection holes 153 are shown as uniformly arranged on the radial slots 157A, but in other embodiments, the inspection holes 153 can have a different number or arrangement. In Figure 11 In embodiments of the present disclosure, each inspection hole 153 corresponds to a single optical inspection system 141. Figure 12 A polishing pad 150 similar to the polishing pad 150 shown in Figure 11 is shown, except that each inspection hole 153 corresponds to multiple optical inspection systems 141.

[0046] Figure 13 A polishing pad 150 having slots 157 in a grid-like pattern is shown, according to some embodiments. Figure 13 Slots 157 forming a continuous pattern are shown, but in other embodiments, some slots 157 can be separated from each other. The slots 157 can be arranged in a rectangular grid-like pattern or another grid-like pattern. In Figure 13 In embodiments of the present disclosure, each inspection hole 153 corresponds to a single optical inspection system 141.

[0047] Figure 14 A polishing pad 150 having slots 157 in a spiral pattern is shown, according to some embodiments. In some cases, the spiral pattern of slots 157 can allow for improved flow of slurry 115 toward the edge of the polishing pad 150. Other numbers or shapes of slots 157 in a spiral pattern are possible. In Figure 14 In embodiments of the present disclosure, each inspection hole 153 corresponds to a single optical inspection system 141. Figure 15 A polishing pad 150 similar to the polishing pad 150 shown in Figure 14 is shown, except that each inspection hole 153 corresponds to multiple optical inspection systems 141.

[0048] Figure 16 A polishing pad 150 similar to the polishing pad 150 shown in Figure 10 is shown, except that the sub-aperture 154 is smaller than the top aperture 158. In Figure 16 In embodiments of the present disclosure, each top aperture 158 extends over multiple sub-apertures 154, and each sub-aperture 154 corresponds to a single optical inspection system 141. In other embodiments, some sub-apertures 154 can extend over multiple optical inspection systems 141. Because the sub-aperture 154 is smaller than the top aperture 158, in Figure 16 In a top-down view of the sub-pad 152, portions of the sub-pad 152 are visible through the top aperture 158.Figure 16 The polishing pad 150 of FIG. 1 is intended as a representative and non-limiting example.

[0049] Figures 17 to 25 A description is provided of forming a complementary field effect transistor (CFET) structure according to some embodiments. The CMP apparatus and methods described herein can be used in the formation of CFET structures, as in some cases, CFET structures can have very stringent specifications for planarization processes in their manufacturing processes. However, the disclosed CMP apparatus and methods are not limited to the manufacture of CFETs, but can be used during the formation of other types of devices, such as FinFETs, nanostructure FETs, etc.

[0050] Figure 17 An example of a CFET 210 (including FETs (transistors) 210U and 210L) is shown according to some embodiments. Figure 17 is a three-dimensional view in which some components of the CFET are omitted for clarity of illustration. The CFET includes multiple vertically stacked FETs. For example, the CFET can include a lower nanostructure FET 210L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 210U of a second device type (e.g., p-type / n-type) opposite the first device type. The nanostructure FETs 210U and 210L include semiconductor nanostructures 226 (including lower semiconductor nanostructures 226L and upper semiconductor nanostructures 226U) in which the semiconductor nanostructures 226 serve as channel regions for the nanostructure FETs. The lower semiconductor nanostructures 226L are for the lower nanostructure FET 210L, and the upper semiconductor nanostructures 226U are for the upper nanostructure FET 210U. In other embodiments, the CFET can also be applicable to other types of transistors (e.g., FinFETs, nanostructure FETs, etc.).

[0051] A gate dielectric 278 surrounds the respective semiconductor nanostructure 226. A gate electrode 280 (including lower gate electrodes 280L and upper gate electrodes 280U) is located above the gate dielectric 278. Source / drain regions 262 (including lower source / drain regions 262L and upper source / drain regions 262U) are disposed on opposite sides of the gate dielectric 278 and respective gate electrodes 280. The source / drain regions can refer to either the source or the drain, alone or collectively depending on the context. Isolation components (not shown) can be formed to separate the desired source / drain regions 262 and / or the desired gate electrodes 280.

[0052] Figure 17A reference cross-section used in later figures is also shown. Cross-section A-A' is a vertical cross-section parallel to the longitudinal axis of the semiconductor nanostmctures 226 of the CFET and in the direction of current flow, for example, between the source / drain regions 262 of the CFET. For clarity, subsequent figures can refer to this reference cross-section.

[0053] Figures 18 to 25 A cross-sectional view of an intermediate stage in the formation of a CFET structure (as Figure 17 schematically represented in FIG. 1) is shown, in accordance with some embodiments. Figures 18 to 25 A vertical cross-sectional view is shown along a similar cross-section as the vertical reference cross-section A-A' in Figure 14

[0054] In Figure 18 , a wafer is provided, which includes a substrate 220. The substrate 220 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxygen (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multilayer or graded substrate, can also be used. In some embodiments, the semiconductor material of the substrate 220 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; etc. or combinations thereof. The substrate 220 can also be referred to herein as a semiconductor substrate. In some cases, the substrate 220 can be similar to the workpiece 130.

[0055] Semiconductor strips 228 extending upward from the semiconductor substrate 220 are formed. Each of the semiconductor strips 228 includes a semiconductor strip 220' (a patterned portion of the semiconductor substrate 220, also referred to as a semiconductor fin 220') and a multilayer stack 222. The stacked components of the multilayer stack 222 are referred to hereinafter as a nanostmcture. Specifically, the multilayer stack 222 includes a pseudo-nanostmcture 224A, a pseudo-nanostmcture 224B, a lower semiconductor nanostmcture 226L, and an upper semiconductor nanostmcture 226U. The pseudo-nanostmctures 224A and 224B can be further collectively referred to as pseudo-nanostmctures 224, and the lower semiconductor nanostmcture 226L and the upper semiconductor nanostmcture 226U can be further collectively referred to as semiconductor nanostmctures 226.

[0056] ​The pseudo-nanostructure 224A is formed of a first semiconductor material, and the pseudo-nanostructure 224B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be, for example, selected from the candidate semiconductor materials of the semiconductor substrate 220. The first and second semiconductor materials have a high etch selectivity to each other. Thus, in a subsequent process, the pseudo-nanostructure 224B can be removed at a faster rate than the pseudo-nanostructure 224A.

[0057] The semiconductor nanostructures 226 (including the lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U) are formed of one or more third semiconductor materials. The third semiconductor materials can be, for example, selected from the candidate semiconductor materials of the semiconductor substrate 220. The lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U can be formed of the same semiconductor material, or can be formed of different semiconductor materials. Further, the first and second semiconductor materials of the pseudo-nanostructures 224 have a high etch selectivity to the third semiconductor materials of the semiconductor nanostructures 226. Thus, the pseudo-nanostructures 224 can be selectively removed in a subsequent process step without significantly removing the semiconductor nanostructures 226. In some embodiments, the pseudo-nanostructure 224A is formed of or includes silicon germanium, the semiconductor nanostructures 226 are formed of silicon, and the pseudo-nanostructure 224B can be formed of germanium or silicon germanium with a higher percentage of germanium atoms than the pseudo-nanostructure 224A.

[0058] The lower semiconductor nanostructures 226L provide channel regions for lower nanostructure FETs of the CFET. The upper semiconductor nanostructures 226U provide channel regions for upper nanostructure FETs of the CFET. The semiconductor nanostructures 226 directly on / under (e.g., in contact with) the pseudo-nanostructure 224B can be used for isolation, and can or can not be used as channel regions for the CFET. The pseudo-nanostructure 224B is subsequently replaced with an isolation structure. The isolation structure and the pseudo-nanostructure 224B can define boundaries of the lower and upper nanostructure FETs.

[0059] To form the semiconductor strips 228, layers of the first, second, and third semiconductor materials (arranged as shown and described above) can be deposited over the semiconductor substrate 220. The layers of the first, second, and third semiconductor materials can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by processes such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and the like. A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 220 to define the semiconductor strips 228, which include the semiconductor fins 220’, the dummy nanostructures 224, and the semiconductor nanostructures 226. The semiconductor fins and nanostructures can be patterned by any suitable method. For example, the patterning process can include one or more photolithography processes, including a double patterning or multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is less than obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch the layers of the first, second, and third semiconductor materials and the semiconductor substrate 220. The etching can be performed by any acceptable etching process, such as a reactive ion etching (RIE), a neutral beam etching (NBE), and the like, or a combination thereof. The etching can be anisotropic.

[0060] In some embodiments, STI regions (not shown in cross-section A-A’) are formed over the substrate 220 and between adjacent semiconductor strips 228. The STI regions can include a dielectric liner and a dielectric material over the dielectric liner. Each of the dielectric liner and the dielectric material can include an oxide such as silicon oxide, a nitride such as silicon nitride, and the like, or a combination thereof. The formation of the STI regions can include depositing a dielectric layer and performing a planarization process such as a CMP process, a mechanical polishing process, and the like, to remove excess portions of the dielectric material. In some embodiments, the CMP process can use a CMP apparatus or method described herein for Figures 1 to 16 depositing a dielectric layer. The deposition process can include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), and the like, or a combination thereof. In some embodiments, the STI regions include silicon oxide formed by a FCVD process, followed by an anneal process. The dielectric layer is then recessed to define the STI regions. The dielectric layer can be recessed such that upper portions of the semiconductor strips 228 (including the multilayer stacks 222) protrude above the remaining STI regions.

[0061] After the STI regions are formed, a dummy gate stack 242 can be formed over and along the sidewalls of the upper portions of the semiconductor strips 228 (the portions that protrude above the STI regions). Forming the dummy gate stack 242 can include forming a dummy dielectric layer 236 over the semiconductor strips 228. The dummy dielectric layer 236 can include, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 238 is formed over the dummy dielectric layer 236. The dummy gate layer 238 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 238 can be conductive or non-conductive, and can be selected from a group including amorphous silicon, poly-silicon, poly-silicon germanium (poly-SiGe), or the like. A mask layer 240, which can include, for example, silicon nitride, silicon oxynitride, or the like, is formed over the planarized dummy gate layer 238. Next, the mask layer 240 can be patterned by a lithography and etching process to form a mask, which is then used to etch and pattern the dummy gate layer 238, and possibly the dummy dielectric layer 236. The remaining portions of the mask layer 240, dummy gate layer 238, and dummy dielectric layer 236 form the dummy gate stack 242.

[0062] Further, in Figure 18 the gate spacers 244 are formed over the multilayer stack 222 and the exposed sidewalls of the dummy gate stack 242. The gate spacers 244 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by deposition processes such as CVD, ALD, or the like.

[0063] Source / drain recesses 246 are then formed in the semiconductor strips 228. The source / drain recesses 246 are formed by etching, and can extend through the multilayer stack 222 and into the semiconductor strips 220'. The floor of the source / drain recesses 246 can be at a level above, below, or flush with the top surface of the STI regions. In the etching process, the gate spacers 244 and the dummy gate stack 242 mask some portions of the semiconductor strips 228. The etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop the etching of the source / drain recesses 246 when a desired depth is reached.

[0064] In Figure 19In some embodiments, the etching process can include a dry etching process using chlorine gas, with or without plasma. Because the dummy gate stack 242 wraps the sidewalls of the semiconductor nanostmctures 226, the dummy gate stack 242 can support the upper semiconductor nanostmctures 226U so that the upper semiconductor nanostmctures 226U do not collapse when the dummy nanostmctures 224B are removed. Furthermore, while the sidewalls of the dummy nanostmctures 224A are shown to be straight after etching, the sidewalls can be concave or convex.

[0065] The interior spacers 254 are formed on the sidewalls of the recessed dummy nanostmctures 224A, and the dielectric isolation layers 256 are formed between the upper semiconductor nanostmctures 226U (collectively) and the lower semiconductor nanostmctures 226L (collectively). As described in greater detail subsequently, source / drain regions are subsequently formed in the source / drain recesses 246, and the dummy nanostmctures 224A will be replaced with corresponding gate structures. The interior spacers 254 serve as isolation components between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the interior spacers 254 can be used to prevent damage to the subsequently formed source / drain regions from subsequent etching processes, such as etching processes used to form the gate structures. On the other hand, the dielectric isolation layers 256 serve to isolate the upper semiconductor nanostmctures 226U (collectively) from the lower semiconductor nanostmctures 226L (collectively). Furthermore, the intermediate semiconductor nanostmctures (the semiconductor nanostmctures 226 in contact with the dielectric isolation layers 256) and the dielectric isolation layers 256 can define the boundaries of the lower nanostmcture FETs and the upper nanostmcture FETs.

[0066] The internal spacer 254 and dielectric isolation layer 256 can be formed by: conformally depositing insulating material in the source / drain trench 246, on the sidewalls of the pseudo-nanostructure 224A, and between the upper semiconductor nanostructure 226U and the lower semiconductor nanostructure 226L; and then etching the insulating material. The insulating material can be a non-low-k dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. The insulating material can be formed by deposition processes such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion retained on the sidewalls of the pseudo-nanostructure 224A (thus forming the internal spacer 254) and a portion retained between the upper semiconductor nanostructure 226U and the lower semiconductor nanostructure 226L (thus forming the dielectric isolation layer 256).

[0067] Similarly, Figure 19 As shown, a lower epitaxial source / drain region 262L and an upper epitaxial source / drain region 262U are formed. The lower epitaxial source / drain region 262L is formed in the lower portion of the source / drain recess 246. The lower epitaxial source / drain region 262L is in contact with the lower semiconductor nanostructure 226L, but not with the upper semiconductor nanostructure 226U. An internal spacer 254 electrically insulates the lower epitaxial source / drain region 262L from the pseudo-nanostructure 224A, which is replaced with a replacement gate in a subsequent process.

[0068] The lower epitaxial source / drain regions 262L are epitaxially grown and have a conductivity type appropriate for the device type (p-type or n-type) of the lower nanoscale FET. When the lower epitaxial source / drain regions 262L are n-type source / drain regions, the corresponding material can include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain regions 262L are p-type source / drain regions, the corresponding material can include silicon or silicon germanium doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain regions 262L can be in-situ doped and can or can not be implanted with corresponding p-type or n-type dopants. During epitaxy of the lower epitaxial source / drain regions 262L, the upper semiconductor nanoscale structures 226U can be masked to prevent unwanted epitaxial growth on the upper semiconductor nanoscale structures 226U. After growth of the lower epitaxial source / drain regions 262L, the mask on the upper semiconductor nanoscale structures 226U can then be removed. Due to the epitaxial process used to form the lower epitaxial source / drain regions 262L, the upper surface of the lower epitaxial source / drain regions 262L has facets that laterally extend outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 262L remain separated after the epitaxial process is complete. In other embodiments, the facets cause adjacent lower epitaxial source / drain regions 262L of the same FET to merge.

[0069] A first contact etch stop layer (CESL) 266 and a first ILD 268 are formed over the lower epitaxial source / drain regions 262L. The first CESL 266 can be formed of a dielectric material that has a high etch selectivity with respect to etching of the first ILD 268, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process such as CVD, ALD, etc. The first ILD 268 can be formed of a dielectric material that can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 268 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0070] The formation process can include deposition of a conformal CESL layer, deposition of material for the first ILD 268, and a subsequent planarization process and then an etch back process. In some embodiments, the planarization process can use a CMP process such as described herein for the first ILD 268. In some embodiments, the etch back process can use a dry etch process such as described herein for the first ILD 268. Figures 1 to 16The CMP apparatus or method described. In some embodiments, the first ILD 268 is first etched, leaving the first CESL 266 unetched. An anisotropic etch process is then implemented to remove portions of the first CESL 266 that are above the recessed first ILD 268. After the recessing, the sidewalls of the upper semiconductor nanostructure 226U are exposed.

[0071] An upper epitaxial source / drain region 262U is then formed in the upper portion of the source / drain recess 246. The upper epitaxial source / drain region 262U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 226U. The material of the upper epitaxial source / drain region 262U can be selected from the same set of candidate materials used to form the lower source / drain region 262L, depending on the desired conductivity type of the upper epitaxial source / drain region 262U. The conductivity type of the upper epitaxial source / drain region 262U can be opposite to that of the lower epitaxial source / drain region 262L. For example, the upper epitaxial source / drain region 262U can be oppositely doped from the lower epitaxial source / drain region 262L. The upper epitaxial source / drain region 262U can be in-situ doped with n-type or p-type dopants and / or can be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 262U can remain separated after the epitaxial process, or can be merged.

[0072] After the epitaxial source / drain region 262U is formed, a second CESL 270 and a second ILD 272 are formed. The materials and formation methods can be similar to those of the first CESL 266 and the first ILD 268, respectively, and are not discussed in detail here. The formation process can include depositing layers for the CESL 270 and the ILD 272, and implementing a planarization process, such as a CMP process, to remove excess portions of the corresponding layers. In some embodiments, the CMP process can use a slurry such as that described herein with respect to the CMP process for the first CESL 266 and the first ILD 268. Figures 1 to 16 The CMP apparatus or method described. In other embodiments, the planarization process removes the mask layer 240.

[0073] In some embodiments, a hard mask 273 can be formed on the second ILD 272. The hard mask 273 can be formed, for example, by recessing the second ILD 272 using a suitable etch process, and then depositing a material of the hard mask 273 on the second ILD 272. The hard mask material can be a suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, etc. The hard mask material can be deposited using a suitable technique, such as ALD, CVD, etc. A planarization process, such as a CMP process, can be implemented to remove excess hard mask material. In some embodiments, the CMP process can use a slurry such as that described herein with respect to the CMP process for the first CESL 266 and the first ILD 268. Figures 1 to 16The described CMP apparatus or method. In some embodiments, the hard mask 273 may be used as a CMP stop layer for a subsequent planarization process.

[0074] Figures 20 to 24 The replacement gate process is illustrated, in which the dummy gate stack 242 and the dummy nanostructure 224A are replaced with a replacement gate stack 290. (Reference) Figure 20 The gate replacement process includes first removing the remaining portion of the dummy gate stack 242 and the dummy nanostructure 224A. The dummy gate stack 242 is removed in one or more etching processes, thereby defining a trench between the gate spacers 244 and exposing the upper portion of the semiconductor strip 228. The remaining portion of the dummy nanostructure 224A is then removed by etching, such that the trench extends between the semiconductor nanostructures 226. In the etching process, the dummy nanostructure 224A is etched at a rate faster than that of the semiconductor nanostructure 226, the dielectric isolation layer 256, and the internal spacers 254. The etching can be isotropic. For example, when the dummy nanostructure 224A is formed of silicon germanium and the semiconductor nanostructure 226 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0075] Then, a gate dielectric 278 is deposited in the recesses between the gate spacers 244 and on the exposed semiconductor nanostructure 226. The gate dielectric 278 is conformally formed on the exposed surface of the recesses (removed gate stack 242 and pseudo nanostructure 224A) including the semiconductor nanostructure 226 and the gate spacers 244. In some embodiments, the gate dielectric 278 encapsulates all (e.g., four) sides of the semiconductor nanostructure 226. Specifically, the gate dielectric 278 may be formed on the top surface of the semiconductor fin 220'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 226; and the sidewalls of the gate spacers 244. The gate dielectric 278 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 278 may include high dielectric constant (high k) materials having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 278 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 278 located above the second ILD 272. Although a single-layer gate dielectric 278 is shown, the gate dielectric 278 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0076] like Figure 20As shown in FIG. 2A, a lower electrode material 274 is formed on the gate dielectric 278 around the lower semiconductor nanostructure 226L and the upper semiconductor nanostructure 226U. For example, at this step in the process, the lower electrode material 274 wraps around the lower semiconductor nanostructure 226L and the upper semiconductor nanostructure 226U. Subsequently, the lower electrode material 274 is removed from the upper semiconductor nanostructure 226U. The lower electrode material 274 can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single layer gate electrode is shown, the lower electrode material 274 can include any number of work function adjusting layers, any number of barrier layers, any number of adhesion layers, and fill materials.

[0077] The lower electrode material 274 is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower electrode material 274 can include one or more work function adjusting layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower electrode material 274 includes an n-type work function adjusting layer, which can be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower electrode material 274 includes a p-type work function adjusting layer, which can be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or alternatively, the lower electrode material 274 can include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0078] In some embodiments, the planarization process removes an upper portion of the lower electrode material 274 and the gate dielectric 278, such that the planarization process stops on the mask layer 273, as shown in FIG. 2B. Thus, the mask layer 273 can act as a CMP stop layer. In other embodiments, the planarization process stops on the CESL 270, and thus the CESL 270 acts as a CMP stop layer. In some embodiments, the CMP process can use a slurry that is selective to the CESL 270, such as the slurry described herein with respect to FIG. 2B. Figure 21 Figure 21 In some embodiments, the planarization process removes an upper portion of the lower electrode material 274 and the gate dielectric 278, such that the planarization process stops on the mask layer 273, as shown in FIG. 2B. Thus, the mask layer 273 can act as a CMP stop layer. In other embodiments, the planarization process stops on the CESL 270, and thus the CESL 270 acts as a CMP stop layer. In some embodiments, the CMP process can use a slurry that is selective to the CESL 270, such as the slurry described herein with respect to FIG. 2B. Figures 1 to 16 ​The described CMP apparatus or method. For example, the techniques described herein can allow monitoring of the removal of the lower electrode material 274, enabling the CMP process to be stopped when the mask layer 273 (or CESL 270) is exposed. In this way, the loss of the mask layer 273 (or CESL 270) can be reduced. The techniques described herein allow for more precise stopping of the planarization process and a more uniform topography after planarization, which can improve the uniformity and control of the subsequent recessing of the lower electrode material 274, as described below. In some cases, the planarization techniques described herein can reduce over-etching or under-etching during the recessing of the lower electrode material 274.

[0079] exist Figure 22 In this configuration, the lower electrode material 274 is recessed, with the remaining lower electrode material 274 forming the lower gate electrode 280L. The lower electrode material 274 can be recessed such that the top surface of the remaining lower electrode material 274 is approximately aligned with the dielectric isolation layer 256. For example, the top surface of the lower electrode material 274 can be aligned with... Figure 22 The indicated location 277 is approximately flush with the ground, but other locations are possible. The recessed process may include any acceptable etching process that can be implemented to recess the gate electrode layer, such as dry etching, wet etching, or combinations thereof. The etching may be isotropic. Etching the lower gate electrode 280L may expose the upper semiconductor nanostructure 226U. In some embodiments, the lower gate electrode 280L encloses the lower semiconductor nanostructure 226L.

[0080] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 280L. The isolation layer serves as an isolation component between the lower gate electrode 280L and the subsequently formed upper gate electrode 280U. The isolation layer may be formed by: conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof); and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 226U.

[0081] exist Figure 23In this embodiment, an upper electrode material 276 is formed on the isolation layer (if present) described above or on the lower gate electrode 280L. In some embodiments, the upper electrode material 276 encapsulates the upper semiconductor nanostructure 226U. The upper electrode material 276 may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 280L. The upper electrode material 276 is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper electrode material 276 may include one or more work function adjustment layers formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer upper electrode material 276 is shown, the upper electrode material 276 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0082] exist Figure 24 In this process, a removal process is performed to remove the upper portion of the upper electrode material 276, wherein the remaining upper electrode material 276 forms the upper gate electrode 280U. The upper gate electrode 280U is disposed between and encapsulates the upper semiconductor nanostructures 226U. In some embodiments, planarization processes such as CMP, etch-back processes, and combinations thereof can be utilized. In some embodiments, the planarization process may remove the mask layer 273. After the planarization process, the top surfaces of the upper gate electrode 280U, the gate dielectric 278, the second ILD 272, and the gate spacer 244 may be substantially flush or coplanar (within process variations). In some embodiments, the CMP process may use processes such as those described herein. Figures 1 to 16 The described CMP apparatus or method. For example, the technique described herein allows monitoring of the removal of the top electrode material 276, thereby enabling the CMP process to be stopped when the second ILD 272 is exposed. The technique described herein allows for more precise stopping of the planarization process and a more uniform morphology.

[0083] Each corresponding pair of gate dielectric 278 and gate electrode 280 (including upper gate electrode 280U and / or lower gate electrode 280L) may be collectively referred to as a “gate structure” 290 (including upper gate structure 290U and lower gate structure 290L). Each gate structure 290 extends along three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of semiconductor nanostructure 226. The lower gate structure 290L may also extend along the sidewalls and / or top surface of semiconductor fin 220'.

[0084] exist Figure 25In some embodiments, additional processing steps are performed on the CFET structure. A silicide region 294 and a source / drain contact plug 296U are formed through the second ILD 272 to electrically couple to the upper epitaxial source / drain region 262U and / or the lower epitaxial source / drain region 262L. An etch stop layer (ESL) 304 and a third ILD 306 are formed. In some embodiments, the ESL 304 may include a dielectric material with high etch selectivity relative to the etch of the third ILD 306, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 306 can be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0085] Similarly, Figure 25 As shown, a gate mask 292 is formed over the gate structure 290. The formation process may include: recessing the gate structure 290; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.; and performing a planarization process to remove excess dielectric material over the second ILD 272.

[0086] An upper gate contact plug 308 and a source / drain contact plug 310 are formed to contact the upper gate electrode 280U and the upper source / drain contact plug 296U, respectively. The active devices shown are collectively referred to as device layer 312.

[0087] A front interconnect structure 314 is formed on device layer 312. The front interconnect structure 314 includes a dielectric layer 316 and layers of conductive components 318 / 320 located within the dielectric layer 316. The dielectric layer 316 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 316 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 316 may also include a polymer layer.

[0088] Conductive components 318 / 320 may include wires 318 and vias 320, which can be formed using an inlay process. Conductive components 318 / 320 may include metal wires 318 and metal vias 320, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias. Depending on how the corresponding die is packaged, the top surface components in conductive component 318 may include bonding pads, metal pillars, solder areas, etc.

[0089] In some embodiments, a backside interconnect structure can be formed. The backside interconnect structure can provide electrical connections to the lower gate stack 290L and the lower source / drain regions 262L through a backside of the device layer 312 (e.g., a side opposite the frontside interconnect structure 314). The backside interconnect structure can be similar to the frontside interconnect structure 314 described above, and is not repeated here. In some embodiments, connections to the lower gate stack 290L and the lower source / drain regions 262L are made by contacts (sometimes referred to as contact plugs), and the backside interconnect structure can be omitted. In some embodiments, forming the backside interconnect structure includes thinning the semiconductor substrate 220 using a planarization process, which can be similar to the planarization processes described herein for Figures 1 to 16 CMP apparatuses and methods are described.

[0090] In some embodiments, a plurality of CFET structures are formed on a wafer, and the wafer is subsequently singulated into individual dies. In some cases, the wafer can be similar to the semiconductor substrate 220. The singulation process can include a sawing process, a laser process, an etching process, or a combination thereof. The CFET structures described with respect to Figures 17 to 25 The CFET structures described are examples, and other configurations or process steps are possible. The CMP apparatuses and methods described herein can allow for improved uniformity and yield for the formation of CFET structures, or for the formation of any other suitable structures or devices.

[0091] Embodiments can achieve advantages. Embodiments described herein can allow for in-situ inspection of a workpiece (e.g., a wafer) during planarization of the workpiece. Planarization can include a polishing process, such as a CMP process. Thus, embodiments described herein can be used within a CMP tool or the like. By forming an inspection hole that extends through a polishing pad, an optical inspection system underneath the polishing pad can inspect a bottom surface of the workpiece during a planarization process. For example, the optical inspection system can measure a thickness of a bottom layer of the workpiece, or determine when a bottom layer of the workpiece has been removed. This can allow for more precise and reliable layer thinning or layer removal. For example, measuring a reflection spectrum of light from the workpiece can allow a CMP tool or operator to determine when a layer (e.g., an etch stop layer or another type of layer) has been partially or completely removed. The planarization process can then stop (e.g., remove the workpiece from the polishing pad) more precisely or more quickly after the last desired layer has been removed. In some cases, embodiments described herein can reduce undesirable layer loss or can eliminate the need for a CMP stop layer.

[0092] By having the inspection hole include a portion of the slot in the top pad, the impact of the inspection hole on the planarization process can be minimized. In this way, fewer defects can be introduced during planarization. In some embodiments, the polishing pad can include a transparent layer that reduces the impact of slurry during optical inspection. Embodiments described herein can allow for a greater number or density of optical inspection systems, which can allow for more accurate and detailed inspection of the workpiece during planarization. Many variations of the slot, inspection hole, and optical inspection system are possible, allowing for improved process flexibility and compatibility with application-specific needs.

[0093] According to embodiments, a system includes a platen configured to secure a polishing pad, wherein the polishing pad includes a slot in a top surface of the polishing pad and an opening extending from the slot to a bottom surface of the polishing pad, a holder configured to secure a workpiece above the polishing pad, and an optical inspection device within the platen, wherein the optical inspection device is configured to measure a property of the bottom surface of the workpiece through the opening in the polishing pad. In embodiments, the polishing pad includes a transparent layer extending across the opening. In embodiments, the property is a thickness of an underlayer of the workpiece. In embodiments, the slot is in a concentric circle. In embodiments, the slot is in a spiral arrangement. In embodiments, the optical inspection device is configured to rotate with the platen. In embodiments, each optical inspection device includes a light source and a light sensor. In embodiments, each opening extends over more than one optical inspection device.

[0094] According to embodiments, an apparatus includes a platen configured to rotate, wherein the platen includes an optical inspection system, wherein each optical inspection system includes a light source and a light sensor, respectively, and a polishing pad attached to the platen, wherein the polishing pad includes a first pad including first apertures extending through the first pad, wherein each first aperture is aligned with at least one optical inspection system, and a second pad on the first pad, wherein the second pad includes second apertures extending through the second pad, wherein each second aperture is aligned with at least one first aperture, and first slots in a top side of the second pad opposite the first pad, wherein each first slot extends over at least one second aperture. In embodiments, the second pad includes second slots in the top side, wherein the second slots are separated from the second apertures. In embodiments, the first apertures and the second apertures have a same width. In embodiments, the first apertures and the second apertures have different widths. In embodiments, at least one second aperture extends over multiple optical inspection systems. In embodiments, the light source is a broadband light source. In embodiments, the light sensor is a spectrometer.

[0095] According to embodiments, a method includes: attaching a polishing pad to a platen, wherein the platen includes a light source and an optical detector, wherein the polishing pad includes an aperture; placing a wafer on the polishing pad, wherein the wafer includes a gate structure over a plurality of nanostructures; rotating the polishing pad to polish the wafer; while rotating the polishing pad, emitting light from the light source through the aperture toward the wafer, and detecting light reflected from the wafer through the aperture toward the optical detector using the optical detector; and singulating the wafer into a plurality of dies. In embodiments, the method includes determining a thickness of an underlayer of the wafer based on the light detected by the optical detector. In embodiments, the method includes stopping rotation of the polishing pad based on the thickness. In embodiments, polishing the wafer includes polishing a surface of the gate structure. In embodiments, the polishing pad includes a slot aligned with the aperture.

[0096] Some embodiments of the present application provide a chemical mechanical planarization system, comprising: a platen configured to secure a polishing pad, wherein the polishing pad comprises: a plurality of slots in a top surface of the polishing pad; and a plurality of openings extending from the slots to a bottom surface of the polishing pad; a holder configured to secure a workpiece over the polishing pad; and a plurality of optical inspection devices within the platen, wherein the optical inspection devices are configured to measure a property of a bottom surface of the workpiece through the plurality of openings in the polishing pad.

[0097] In some embodiments, the polishing pad further comprises a transparent layer extending across the plurality of openings. In some embodiments, the property is a thickness of an underlayer of the workpiece. In some embodiments, the slots of the plurality of slots are in concentric circles. In some embodiments, the slots of the plurality of slots are in a spiral arrangement. In some embodiments, the plurality of optical inspection devices are configured to rotate with the platen. In some embodiments, each optical inspection device comprises a light source and a light sensor. In some embodiments, each opening of the plurality of openings extends over more than one optical inspection device.

[0098] Other embodiments of the present application provide a chemical mechanical planarization apparatus, comprising: a platen configured to rotate, wherein the platen comprises a plurality of optical inspection systems, wherein each optical inspection system comprises a light source and a light sensor, respectively; and a polishing pad attached to the platen, wherein the polishing pad comprises: a first pad comprising a plurality of first apertures extending through the first pad, wherein each first aperture is aligned with at least one optical inspection system; and a second pad on the first pad, wherein the second pad comprises: a plurality of second apertures extending through the second pad, wherein each second aperture is aligned with at least one first aperture; and a plurality of first slots in a top side of the second pad opposite the first pad, wherein each first slot extends over at least one second aperture.

[0099] In some embodiments, the second pad further includes a plurality of second grooves located in the top side, wherein the second grooves are separated from the plurality of second slits. In some embodiments, the first slit and the second slit have the same width. In some embodiments, the first slit and the second slit have different widths. In some embodiments, at least one second slit extends above a plurality of optical inspection systems. In some embodiments, the light source is a broadband light source. In some embodiments, the light sensor is a spectrometer.

[0100] Further embodiments of this application provide a method for operating a chemical mechanical planarization apparatus, comprising: attaching a polishing pad to a stage, wherein the stage includes a plurality of light sources and a plurality of optical detectors, wherein the polishing pad includes a plurality of holes; placing a wafer on the polishing pad, wherein the wafer includes a gate structure located above a plurality of nanostructures; rotating the polishing pad to polish the wafer; while rotating the polishing pad, emitting light from the plurality of light sources through the plurality of holes toward the wafer, and using the plurality of optical detectors to detect the light reflected from the wafer through the plurality of holes toward the plurality of optical detectors; and dicing the wafer into a plurality of dies.

[0101] In some embodiments, the method further includes: determining the thickness of the underlying layer of the wafer based on the light detected by the optical detector. In some embodiments, the method further includes: stopping the rotation of the polishing pad based on the thickness. In some embodiments, polishing the wafer includes polishing the surface of the gate structure. In some embodiments, the polishing pad further includes a plurality of grooves aligned with the plurality of holes.

[0102] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A chemical mechanical planarization system, comprising: A worktable, configured to hold a polishing pad, wherein the polishing pad comprises: Multiple grooves are located in the top surface of the polishing pad; and Multiple openings extend from the groove to the bottom surface of the polishing pad; A retainer configured to hold the workpiece on the polishing pad; and Multiple optical inspection devices are located within the stage, wherein the optical inspection devices are configured to measure the characteristics of the bottom surface of the workpiece through the multiple openings in the polishing pad.

2. The chemical mechanical planarization system according to claim 1, wherein, The polishing pad also includes a transparent layer extending across the plurality of openings.

3. The chemical mechanical planarization system according to claim 1, wherein, The characteristic is the thickness of the bottom layer of the workpiece.

4. The chemical mechanical planarization system according to claim 1, wherein, The slots in the plurality of slots are located in concentric circles.

5. The chemical mechanical planarization system according to claim 1, wherein, The slots in the plurality of slots are arranged in a spiral.

6. The chemical mechanical planarization system according to claim 1, wherein, The plurality of optical inspection devices are configured to rotate together with the stage.

7. The chemical mechanical planarization system according to claim 1, wherein, Each optical inspection device includes a light source and a light sensor.

8. The chemical mechanical planarization system according to claim 1, wherein, Each of the plurality of openings extends above more than one optical inspection device.

9. A chemical mechanical planarization apparatus, comprising: A rotating platform, comprising multiple optical inspection systems, each including a light source and a light sensor; and A polishing pad, attached to the platform, wherein the polishing pad comprises: A first pad includes a plurality of first slits extending through the first pad, wherein each first slit is aligned with at least one optical inspection system; and A second pad, located on top of the first pad, wherein the second pad comprises: A plurality of second perforations extend through the second pad, wherein each second perforation is aligned with at least one first perforation; and A plurality of first grooves are located on the top side of the second pad opposite to the first pad, wherein each first groove extends above at least one second hole.

10. A method for operating a chemical mechanical planarization apparatus, comprising: A polishing pad is attached to a platform, wherein the platform includes multiple light sources and multiple optical detectors, and wherein the polishing pad includes multiple holes; A wafer is placed on the polishing pad, wherein the wafer includes a gate structure located above a plurality of nanostructures; Rotate the polishing pad to polish the wafer; While the polishing pad is rotated, light is emitted from the plurality of light sources through the plurality of apertures toward the wafer, and the light reflected from the wafer through the plurality of apertures toward the plurality of optical detectors is detected using the plurality of optical detectors; and The wafer is divided into multiple dies.

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