Physical IP verification device and method, computer equipment and medium

Abstract

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a physical IP verification device, a verification method, a computer device and a medium. BACKGROUND

[0002] With the upgrade and development of the Peripheral Component Interconnect Express (PCIe) protocol, the signal modulation and coding method transmitted through the PCIe bus has also changed, the highest transmission rate has been improved, and more complex coding methods such as Non-Return-to-Zero (NRZ) 2-level pulse amplitude modulation (PAM4) have been adopted. With the evolution of the PCIe protocol, it is necessary to provide a physical intellectual property core (PHY IP) that can meet higher transmission rates and adapt to updated versions, that is, a PCIe physical layer subsystem that complies with the PCIe protocol specification, which brings challenges to chip verification during chip design and development, and it is necessary to ensure that new features and various design optimizations added with the evolution of the PCIe protocol can be accurately and unbiasedly implemented on the PHY IP series of products that comply with the latest PCIe protocol such as PCIe6. In addition, not only the PCIe protocol, but also other communication protocols such as SERializer / DESerializer (SERDES) protocol, Serial Advanced Technology Attachment (SATA) protocol, Universal Serial Bus (USB) protocol, Ethernet physical IP protocol, DisplayPort (DP) protocol or High Definition Multimedia Interface (HDMI) protocol, there is a similar demand, that is, how to ensure that the physical layer subsystem developed based on these communication protocols and interface standards can not only reflect new features and design optimizations, but also meet protocol consistency verification, physical layer subsystem level functional verification completeness and standardized protocol verification. Moreover, considering the different stages of chip design and development, from the front-end Register Transfer Level (RTL) verification to the middle-end netlist verification and the back-end silicon verification, there may be different verification schemes with different focuses and the chip design scheme may face frequent front-end and back-end coordination and changes. The technical scheme of chip verification in the prior art lacks sufficient flexibility and inclusiveness, and it is difficult to meet the above verification requirements while improving verification efficiency and shortening chip development cycle.

[0003] Therefore, the present application provides a physical IP verification device, a verification method, a computer device and a medium, which are used to solve the technical problems in the prior art. SUMMARY

[0004] In a first aspect, the present application provides a physical IP verification apparatus. The physical IP verification apparatus comprises: a first reusable multi-mode test sequence generator configured to provide a multi-mode and multi-level first test vector set, wherein the multi-mode and multi-level first test vector set supports a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode, and wherein the multi-mode and multi-level first test vector set further supports a plurality of levels of a communication protocol stack including a transaction layer, a data link layer, and a physical layer, and wherein the communication protocol stack is a PCIe protocol stack, a Serdes protocol stack, a SATA protocol stack, a USB protocol stack, an Ethernet physical IP protocol stack, a display interface protocol stack, or a HDMI protocol stack; a verification component physical interface configured to interact with the first reusable multi-mode test sequence generator and to provide a parameterized physical interface interface configured to configure an interface operation mode, an interface version, and an interface data bit width of the physical interface, thereby supporting a physical layer level interface requirement of a dual-mode interface form of a design under test, wherein the physical layer level interface requirement of the dual-mode interface form of the design under test includes a physical model based physical layer level interface requirement and a real physical design based physical layer level interface requirement; a second reusable multi-mode test sequence generator configured to provide a multi-mode and multi-level second test vector set, wherein the multi-mode and multi-level second test vector set supports a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode, and wherein the multi-mode and multi-level second test vector set further supports the plurality of levels of the communication protocol stack; and a verification component serial interface configured to interact with the second reusable multi-mode test sequence generator and to provide a parameterized serial interface interface configured to configure a serial interface, thereby supporting a serial port layer level interface requirement of the dual-mode interface form of the design under test, wherein the serial port layer level interface requirement of the dual-mode interface form of the design under test includes a physical model based serial port layer level interface requirement and a real physical design based serial port layer level interface requirement.

[0005] By the first aspect of the present application, the following improvements and beneficial technical effects are achieved: two modes of the design under test are supported, a mode based on a physical model and a mode based on a real physical intellectual property core, which can take into account different simulation requirements and scenarios such as acceleration simulation efficiency and integrated verification; root device single mode, endpoint device single mode or root device and endpoint device dual mode are supported, and customized settings are supported, so that uplink and downlink scenarios and device characteristics can be simulated; a first and a second test vector set supporting multi-mode and multi-level and a first and a second reusable multi-mode test sequence generator are integrated in the verification device of a test suite, and a physical interface and a serial interface supporting the dual-mode docking mode of the design under test are also integrated, so that a test suite achieves the effect of multiple test suites, has strong flexibility and high inclusiveness; protocol consistency verification, physical layer subsystem level functional verification completeness and standardized protocol verification are supported, a rich set of test vectors is provided, different levels of docking test scenarios and completeness verification requirements such as transaction layer, data link layer and physical layer can be met, hierarchical debugging interaction interfaces and debugging means are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-grained low-power management is also supported.

[0006] In a possible implementation manner of the first aspect of the present application, the design under test is docked between the verification component physical interface and the verification component serial interface in a physical model mode or a real physical design mode, and at least before the physical IP verification device starts protocol consistency verification of the design under test, the physical model mode of the design under test or the real physical design mode of the design under test is selected for protocol consistency verification of the design under test.

[0007] In a possible implementation manner of the first aspect of the present application, when the development completion degree of the design under test is not higher than a first preset threshold, a feature function table covered by the first test vector set and the second test vector set includes data path basic rate flow test and control path handshake test, and the verification component physical interface and the verification component serial interface cooperate to support setting impedance matching resistance values of a physical link transceiver end and skipping calibration circuit and adaptive adjustment circuit.

[0008] In a possible implementation manner of the first aspect of the present application, when the development completion degree of the design under test is higher than the first preset threshold and not higher than a second preset threshold, a feature function table covered by the first test vector set and the second test vector set includes data path full-rate flow test, power management test and loopback path test, and the verification component physical interface and the verification component serial interface cooperate to support setting circuit unit power states under multi-gear power management, loopback path bypass branch circuit and hardware logic processing and built-in self-test.

[0009] In a possible implementation of the first aspect of the application, when the development completion degree of the design under test is higher than the second preset threshold and is not higher than a third preset threshold, the feature function list covered by the first test vector set and the second test vector set includes low-power sub-state test of full power spectrum, the calibration circuit and adaptive adjustment circuit, eye Figure Two boundary test and equalization circuit test, the verification component physical interface cooperates with the verification component serial interface to support physical initialization acceleration mode and non-acceleration mode, modeling of the calibration circuit and adaptive adjustment circuit, modeling of the receiving side channel margin circuit and modeling of the sending side equalization circuit.

[0010] In a possible implementation of the first aspect of the application, when the development completion degree of the design under test is higher than the third preset threshold, the feature function list covered by the first test vector set and the second test vector set includes multi-protocol type highest rate test, multi-interface bus bit width test, debugging diagnostic circuit test and abnormal protection circuit test, the verification component physical interface cooperates with the verification component serial interface to support calibration and tuning based on post-simulation simulation data and impedance matching resistance value level setting of the physical link transceiver.

[0011] In a possible implementation of the first aspect of the application, the physical model form of the design under test or the real physical design form of the design under test is selected for protocol conformance verification of the design under test based on the development completion degree of the design under test, and the test results of the test cases for the protocol conformance verification of the physical model form of the design under test are optionally reused for the protocol conformance verification of the real physical design form of the design under test.

[0012] In a possible implementation of the first aspect of the application, when the real physical design form of the design under test changes the impedance matching resistance value, the step amount of the calibration circuit and adaptive adjustment circuit, or the horizontal eye width / vertical eye height / eye diagram boundary of the two-dimensional eye diagram of the channel margin circuit relative to the physical model form of the design under test, the test cases for the protocol conformance verification of the physical model form of the design under test are re-run or incrementally tested.

[0013] In a possible implementation of the first aspect of the application, when the real physical design form of the design under test changes the working voltage, working current, peak power or circuit cell area associated with power integrity and signal integrity relative to the physical model form of the design under test, the test cases for the protocol conformance verification of the physical model form of the design under test that are strongly related to the electrical characteristics of the physical circuit are re-run.

[0014] In a possible implementation form of the first aspect of the application, the real physical design modality of the design under test comprises a physical encoding sublayer, a physical layer soft core logic and a physical layer hard core logic.

[0015] In a possible implementation form of the first aspect of the application, the first reusable multi-mode test sequence generator cooperates with the second reusable multi-mode test sequence generator to initiate a root device and endpoint device dual-mode protocol conformance verification flow when the design under test is a root device and endpoint device dual-mode, or to initiate a root device single-mode protocol conformance verification flow when the design under test is a root device single-mode, or to initiate an endpoint device single-mode protocol conformance verification flow.

[0016] In a possible implementation form of the first aspect of the application, the verification component physical interface cooperates with the verification component serial interface to set an interface operation mode of a physical interface associated with the design under test to be either a native PIPE operation mode or a Serdes PIPE operation mode, to set an interface version associated with the design under test, and to set an interface data bit width associated with the design under test.

[0017] In a possible implementation form of the first aspect of the application, the verification component physical interface cooperates with the verification component serial interface to support respective interfacing test scenarios and completeness test scenarios of the design under test operating at multiple levels of the communication protocol stack.

[0018] In a possible implementation form of the first aspect of the application, the verification component physical interface cooperates with the verification component serial interface to support PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0 and PCIe 6.0.

[0019] In a possible implementation form of the first aspect of the application, the verification component physical interface cooperates with the verification component serial interface to support interface data bit widths of 1 symbol, 2 symbols, 4 symbols and 8 symbols, wherein 1 symbol is 8 bits.

[0020] In a possible implementation form of the first aspect of the application, the physical IP verification apparatus supports hierarchical and fine-grained low power management, supports a debug interaction interface for transaction layer record interaction, and supports a four-level encoding four-level pulse amplitude modulation mode.

[0021] In a second aspect, the present application provides a physical IP verification method. The physical IP verification method comprises: selecting a physical model form of a design under test or a real physical design form of the design under test; selecting a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode of the design under test; determining physical layer interface requirements of a dual mode interface form of the design under test and serial port layer interface requirements of the dual mode interface form of the design under test, wherein the physical layer interface requirements of the dual mode interface form of the design under test comprise physical layer interface requirements based on a physical model and physical layer interface requirements based on a real physical design, and the serial port layer interface requirements of the dual mode interface form of the design under test comprise serial port layer interface requirements based on a physical model and serial port layer interface requirements based on a real physical design; and performing protocol consistency verification of the design under test by using a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. The first reusable multi-mode test sequence generator is configured to provide a multi-mode and multi-level first test vector set, the multi-mode and multi-level first test vector set supports a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode, and the multi-mode and multi-level first test vector set also supports multiple levels of a communication protocol stack including a transaction layer, a data link layer, and a physical layer, the communication protocol stack is a PCIe protocol stack, a Serdes protocol stack, a SATA protocol stack, a USB protocol stack, an Ethernet physical IP protocol stack, a display interface protocol stack, or a HDMI protocol stack. The verification component physical interface interacts with the first reusable multi-mode test sequence generator and provides a parameterized physical interface interface for configuring interface working modes, interface versions, and interface data bit widths of the physical interface, thereby supporting the physical layer interface requirements of the dual mode interface form of the design under test. The second reusable multi-mode test sequence generator is configured to provide a multi-mode and multi-level second test vector set, the multi-mode and multi-level second test vector set supports a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode, and the multi-mode and multi-level second test vector set also supports multiple levels of the communication protocol stack. The verification component serial interface interacts with the second reusable multi-mode test sequence generator and provides a parameterized serial interface interface for configuring the serial interface, thereby supporting the serial port layer interface requirements of the dual mode interface form of the design under test.

[0022] By the second aspect of the present application, the following improvements and beneficial technical effects are achieved: two modes of the design under test are supported, a mode based on a physical model and a mode based on a real physical intellectual property core, which can take into account different simulation requirements and scenarios such as acceleration simulation efficiency and integrated verification; root device single mode, endpoint device single mode, or root device and endpoint device dual mode are supported, and customized settings are supported, so that uplink and downlink scenarios and device characteristics can be simulated; a first and a second test vector set supporting multi-mode and multi-level and a first and a second reusable multi-mode test sequence generator are integrated in a verification device of a test suite, and a physical interface and a serial interface supporting the dual-mode docking mode of the design under test are also integrated, so that a test suite achieves the effect of multiple test suites, has strong flexibility and high inclusiveness; protocol consistency verification, physical layer subsystem level functional verification completeness, and standardized protocol verification are supported, rich test vector sets are provided, different levels of docking test scenarios and completeness verification requirements such as transaction layer, data link layer, and physical layer can be met, hierarchical debugging interaction interfaces and debugging means are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-grained low-power management is also supported.

[0023] In a possible implementation manner of the second aspect of the present application, the design under test is docked between the verification component physical interface and the verification component serial interface in a physical model mode or a real physical design mode, and at least before performing protocol consistency verification of the design under test, the physical model mode of the design under test or the real physical design mode of the design under test is selected for the protocol consistency verification of the design under test.

[0024] In a possible implementation manner of the second aspect of the present application, the selection of the physical model mode of the design under test or the selection of the real physical design mode of the design under test for the protocol consistency verification of the design under test is determined based on the development completion degree of the design under test, and the test results of test cases for the protocol consistency verification of the physical model mode of the design under test are optionally reused for the protocol consistency verification of the real physical design mode of the design under test.

[0025] In a third aspect, the embodiments of the present application further provide a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method according to any one of the implementation manners of any one of the above aspects when executing the computer program.

[0026] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and the computer instructions cause a computer device to perform the method according to any one of the implementation manners of any one of the aspects above when the computer instructions run on the computer device.

[0027] In a fifth aspect, the embodiments of the present application further provide a computer program product, which includes instructions stored on a computer readable storage medium, and the instructions cause a computer device to perform the method according to any one of the implementation manners of any one of the aspects above when the instructions run on the computer device. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0029] Figure One A schematic diagram of a physical IP verification device provided by the embodiments of the present application is shown in FIG. 1. Figure Two A flowchart of a process of configuring a test vector set and an interface based on the development completion degree of a design under test provided by the embodiments of the present application is shown in FIG. 2. Figure Three A schematic diagram of a physical IP verification device provided by the embodiments of the present application is shown in FIG. 1. Figure One A flowchart of a process of automatically verifying a PCIe 6 physical layer level test suite by the physical IP verification device shown in FIG. 1 is shown in FIG. 3. Figure Four A flowchart of a physical IP verification method provided by the embodiments of the present application is shown in FIG. 4. Figure Five A structural schematic diagram of a computer device provided by the embodiments of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be further described in detail below with reference to the drawings.

[0031] It should be understood that in the description of the present application, "at least one" means one or more than one, and "multiple" means two or more than two. In addition, the words "first", "second", and the like, unless otherwise specified, are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor indicating or implying sequence.

[0032] Figure One A schematic diagram of a physical IP verification device provided by the embodiments of the present application is shown in FIG. 1. Figure OneAs shown, the physical IP verification apparatus comprises a first reusable multi-mode test sequence generator A110, a verification component physical interface 130, a second reusable multi-mode test sequence generator A120, and a verification component serial interface 132. The first reusable multi-mode test sequence generator A110 is configured to provide a multi-mode and multi-level first test vector set A112. The multi-mode and multi-level first test vector set A112 supports a root complex (RC) mode, an end point (EP) mode, or a dual mode of RC and EP (DM) mode. The multi-mode and multi-level first test vector set A112 also supports multiple levels of a communication protocol stack including a transaction layer, a data link layer, and a physical layer. The communication protocol stack is a PCI Express (PCIe) protocol stack, a SERializer / DESerializer (SERDES) protocol stack, a Serial Advanced Technology Attachment (SATA) protocol stack, a Universal Serial Bus (USB) protocol stack, an Ethernet physical IP protocol stack, a DisplayPort (DP) protocol stack, or a High Definition Multimedia Interface (HDMI) protocol stack. The verification component physical interface 130 interacts with the first reusable multi-mode test sequence generator A110 and provides a parameterized physical interface interface for configuring an interface operation mode, an interface version, and an interface data bit width of the physical interface, thereby supporting a physical layer interface mating requirement of a dual-mode mating form of a design under test (DUT) 150. The physical layer interface mating requirement of the dual-mode mating form of the DUT 150 includes a physical model based physical layer interface mating requirement and a real physical design based physical layer interface mating requirement. The second reusable multi-mode test sequence generator A120 is configured to provide a multi-mode and multi-level second test vector set A122. The multi-mode and multi-level second test vector set A122 supports the RC mode, the EP mode, or the DM mode. The multi-mode and multi-level second test vector set A122 also supports the multiple levels of the communication protocol stack. The verification component serial interface 132 interacts with the second reusable multi-mode test sequence generator A120 and provides a parameterized serial interface interface for configuring a serial interface, thereby supporting a serial layer interface mating requirement of the dual-mode mating form of the DUT 150.The serial interface level docking requirements of the dual-mode docking form of the design under test 150 include physical model based serial interface level docking requirements and real physical design based serial interface level docking requirements. Figure One It is also shown that the design under test 150 is docked between the verification component physical interface 130 and the verification component serial interface 132, optionally in a physical model form 152 of the design under test 150 or in a real physical design form 154 of the design under test 150.

[0033] Referring to Figure One, the multi-mode and multi-level first test vector set A112 also supports multiple levels of a communication protocol stack including a transaction layer, a data link layer and a physical layer, the multi-mode and multi-level second test vector set A122 also supports multiple levels of the communication protocol stack, and a physical layer interface 130 of the verification component supports a physical layer interface requirement of the dual-mode interface form of the design under test 150 and a serial interface 132 of the verification component supports a serial layer interface requirement of the dual-mode interface form of the design under test 150. In this way, various communication protocols and interface standards can be adapted as long as they meet the hierarchical structure design of the communication protocol stack, including but not limited to PCIe protocols (such as PCIe6), Serdes protocols, SATA protocols, USB protocols, Ethernet physical IP protocols, display interface protocols, and HDMI protocols. Moreover, the interface requirements of the dual-mode interface form of the design under test 150 are decomposed into physical layer interface requirements and serial layer interface requirements, which facilitates the configuration of the physical layer interface requirements of the dual-mode interface form of the design under test 150 through the verification component physical interface 130 (interface working mode, interface version and interface data bit width), and the configuration of the serial layer interface requirements of the dual-mode interface form of the design under test 150 through the verification component serial interface 132, so that the two interface forms of the design under test 150 are supported, which are the physical model form 152 of the design under test 150 based on a physical model and the real physical design form 154 of the design under test 150 based on a real physical design. This means that different interface forms of the design under test 150 can be integrated according to simulation requirements and scene requirements, so that the acceleration simulation efficiency and integration verification requirements can be considered, which is beneficial to cover all new features of communication protocols and interface standards and can realize flexible configuration and friendly interaction through a parameterized interface. For example, in different stages of chip design development, from the register transfer level (RTL) verification in the front end to the netlist verification in the middle end and the silicon verification in the back end, there may be different focuses of the verification scheme and the chip design scheme may face frequent front-end and back-end coordination and changes. Therefore, by simultaneously supporting the physical model-based verification in the early design and the real physical design-based verification in the later design, the development degree of the physical intellectual property core (PHY IP) can be combined at different iteration development nodes to select the appropriate design interface form, which is beneficial to improve the overall simulation verification efficiency.For example, the upgrade and development of PCIe protocol, the signal modulation and coding mode of the transmission through PCIe bus has also changed, the highest transmission rate has been improved, and more complex coding mode has been adopted, such as from Non-Return-to-Zero, 2-level pulse amplitude modulation (NRZ) to 4-level pulse amplitude modulation (PAM4). With the evolution of PCIe protocol, it is necessary to provide a physical layer intellectual property core that can meet higher transmission rate and adapt to the updated version, that is, a PCIe physical layer subsystem that complies with the PCIe protocol specification. Generally, depending on the development level of the physical layer intellectual property core, typical iterative development nodes usually include: digital / analog design circuit functions reach 30% completion, 50% completion and 85% completion, respectively. Here, when the completion is low, such as 30% completion, the focus of chip verification is on the basic flow of test data path and the basic request-to-response handshake interaction of control path, and the electrical characteristic parameters may not be completed at the time of testing. Generally, in the early stage of chip development, the outermost interface specification of the physical layer is first determined, which is beneficial to the chip top-level integration of the physical layer peripheral (PHY Wrapper) and the connection between different IPs / subsystems of the system-level chip, and the single-point function circuit inside the physical layer intellectual property core can be gradually improved according to the iteration plan, such as first determining the electrical characteristics of the interface. Therefore, when designing the circuit in the early stage of chip development, the test usually starts from the handshake, which ensures the correct interaction with the upper computer and system application layer. Taking the PCIe protocol as an example, by flexibly configuring the interface, different versions of the physical interface for the PCIe (PIPE) are supported, such as PIPE5 or PIPE6. In addition, Figure One The physical IP verification device shown realizes support for different interface data bus widths by a multi-mode and multi-level test vector set, a reusable multi-mode test sequence generator, and a parameterized and configurable interface, can be compatible with different data bit widths and application requirements, also supports easily extended sequence patterns, supports rich test cases, supports the highest transmission rate complying with the PCIe6 protocol specification, further supports hierarchical and fine-grained low power management, and also supports rich debugging means, such as supporting debugging through simulation record text analysis and graphical interface and protocol analyzer (PA). The following will be described in combination withFigure Two To further illustrate how to configure the test vector set and the interface based on the development completion degree of the design under test.

[0034] Figure Two A flowchart of configuring the test vector set and the interface based on the development completion degree of the design under test is provided for the embodiments of the present application. As shown in Figure TwoAs shown, in step S201, a configuration process is started. Then, in step S210, it is judged whether the development completion degree of the design under test is higher than a first preset threshold 30%, if not, step S212 is executed to configure the test vector set and the interface according to a first configuration. If the development completion degree of the design under test is higher than the first preset threshold 30%, step S220 is executed to judge whether the development completion degree of the design under test is higher than a second preset threshold 50%, if not, step S222 is executed to configure the test vector set and the interface according to a second configuration. If the development completion degree of the design under test is higher than the second preset threshold 50%, step S230 is executed to judge whether the development completion degree of the design under test is higher than a third preset threshold 85%, if not, step S232 is executed to configure the test vector set and the interface according to a third configuration. If the development completion degree of the design under test is higher than the third preset threshold 85%, step S242 is executed to configure the test vector set and the interface according to a fourth configuration. In this way, the test vector set and the interface are configured according to the development completion degree of the design under test, by setting specific comparison values, i.e., the first, second and third preset thresholds, and setting the corresponding first, second and third configurations, and in combination with the flexible selection of the design under test interface form based on the physical model or the real physical design, and in combination with the rich and diversified configuration and debugging functions provided by the above test suite and verification device. These configuration and debugging functions are based on the parameterized flexible selection, multi-mode flexible configuration of the general verification device framework, verification components and configuration interface (such as PCIe6 PHY IP Test Suite), support various types of standard protocol consistency integrated verification requirements (such as PCIe6 PHY IP). These configuration and debugging functions include but are not limited to: supporting parameterization, users can flexibly select and configure the required mode and bus width, etc.; based on the general verification methodology, with strong extensibility and polymorphism; supporting the dual-mode interface form of the design under test, users can flexibly select; supporting physical initialization acceleration mode (PHY FAST SIM Mode) and non-acceleration mode (Normal Mode); supporting different versions of PIPE interface, parameters can be configured; supporting typical rates under different versions of PCIe protocol and different PIPE interface bus widths, parameters can be configured; supporting original PIPE working mode or Serdes PIPE working mode, parameters can be configured. In this way, a general verification device and method are provided, which can be used for PAM4 PCIe6 physical layer intellectual property core verification and other communication protocol and interface standards, effectively integrating and expanding the rich underlying library of the verification component (based on the verification component physical interface and the verification component serial interface two interface interfaces respectively), providing a dual-mode verification component that is easy for users to extend hierarchically and rich test suite sequence mode, with the characteristics and advantages of strong configuration interface flexibility and diversified device working modes.And, the universal verification device and method support single mode of end device or double mode of root device and end device, support flexible configuration of control interface, provide rich sequence mode and test suite test vector set, support user to complete protocol verification device integration and protocol consistency docking verification of test suite of physical layer intellectual property core based on higher integration efficiency, lower learning cost and less manpower input. And, based on the universal verification device, the integration and debugging cost of protocol consistency verification of physical layer subsystem in actual project development can be effectively reduced, the verification period of protocol standardization docking test is shortened, and the completeness of full quantization protocol docking verification of PCIe6 PHY IP dimension and the efficiency of reusable verification device are effectively improved. The following will be described in detail based on Table 1, how to configure test vector set and interface based on the development completion degree of the design under test. Table 1

[0035] Referring to Figure One , Figure Twoand Table 1, for ease of illustration, the PCIe protocol and the physical interface for high-speed serial peripheral interconnect bus, i.e. PIPE interface, are used as examples, it should be understood that the design and verification of the physical layer IP of other protocols, such as SERDES related protocols, can also be applied. Here, the verification component physical interface cooperates with the verification component serial interface to set the interface operating mode of the physical interface associated with the design under test to be the native PIPE operating mode or the Serdes PIPE operating mode, set the interface version associated with the design under test, and set the interface data bit width associated with the design under test. As can be seen, as the development of the design under test progresses, at multiple iterative development nodes, such as from 30% to 50% to 85%, the feature function table covered by the first test vector set and the second test vector set, the features supported by the PIPE interface, and the features supported by the verification component physical interface cooperating with the verification component serial interface, all change accordingly or remain unchanged. For example, when the development of the design under test is low, such as not higher than a first preset threshold (30%), the impedance matching resistance value of the physical link transceiver end can be set to an ideal value such as 50 ohms, and the corresponding impedance selection gear is set, and the calibration circuit and the self-adaption circuit are skipped, which helps to improve the simulation and verification efficiency, and better adapt to the verification focus in the early circuit design stage, that is, cooperate with the feature function table covered by the first test vector set and the second test vector set, that is, data path full-rate flow-through test, power management test, and loopback path test. As the development of the design under test improves, the parameters of the electrical characteristics have been completed, such as higher than the first preset threshold (30%) and not higher than the second preset threshold (50%), at which time the circuit unit power state under multi-gear power management, loopback path bypass branch circuit and hardware logic processing, and built-in self-test are supported, so that the power state of each circuit unit can be controlled in detail, and better adapt to, for example, power management test. When the development of the design under test is already high, such as higher than the second preset threshold (50%) and not higher than the third preset threshold (85%), at which time the physical initialization acceleration mode and the non-acceleration mode, the modeling of the calibration circuit and the self-adaption circuit, the modeling of the RX lane margin circuit, and the modeling of the TX equalization circuit are supported according to the design of the digital analog circuit.Thus, by modeling the calibration circuit and the adaptive adjustment circuit, different step sizes in the algorithm execution process can be accurately simulated, and by modeling the receive-side channel margin circuit, the boundary adjustment of the two dimensions of the eye diagram horizontal time eye width and the vertical voltage amplitude eye height can be accurately simulated. In addition, by modeling the transmit-side equalization circuit, different voltage amplitudes and channel insertion losses and the corresponding gear setting indexes can be accurately simulated. When the development degree of the to-be-tested design is high enough (higher than 85%) or even reaches the highest value, i.e., 100%, it means that the real physical design form is used as the to-be-tested design interface form, so a complete set of test vectors needs to be covered. At this time, the electrical characteristics under the real physical design form need to be considered, the simulation data based calibration and optimization are supported, and the impedance matching resistance value gear setting of the physical link transceiver is supported. Thus, the phase-locked loop circuit can generate more fine, hierarchical and different frequency band clocks, and the resistance value and the corresponding gear setting can be matched, so as to better adapt to the characteristic function table covered by the first test vector set and the second test vector set, i.e., multi-protocol type highest rate test, multi-interface bus bit width test, debugging and diagnosis circuit test and abnormal protection circuit test. Thus, Figure One The physical IP verification device shown provides a general-purpose verification device and method with strong protocol universality and application diversification. In addition to being suitable for short cycle, multiple rounds, continuous agile iteration development and testing of PAM4 PCIe6 PHY, it can also be applied to other protocol types and PHY IP circuit design and development, such as SATA / USB / ETH PHY IP, and the corresponding test suite test vector is selected according to different PHY types and development stage nodes.

[0036] Referring back to Figure One , Figure OneThe physical IP verification device shown has the following improvements and beneficial technical effects: 1) It supports two docking modes for the design under test (DUT): one based on a physical model and the other based on a real physical IP core, which can take into account different simulation needs and scenarios such as accelerating simulation efficiency and integrating verification. 2) It supports single-mode root device, single-mode endpoint device, or dual-mode root device / endpoint device, and supports customized settings, thereby simulating uplink and downlink scenarios and device characteristics. 3) The verification device of a single test suite integrates first and second test vector sets supporting multiple modes and multiple levels, as well as first and second reusable multi-mode test sequence generators. It also integrates physical interfaces and serial interfaces supporting dual-mode docking modes of the DUT, thus achieving the effect of multiple test suites with one test suite, which is highly flexible and inclusive. 4) Supports protocol consistency verification, physical layer subsystem level functional verification completeness and standardized protocol verification, provides rich test vector sets, can meet the docking test scenarios and completeness verification requirements of different layers such as transaction layer, data link layer, physical layer, etc., supports rich debugging interaction interface and debugging methods, supports different physical interface versions and interface data bus width, and also supports hierarchical and fine-grained low power management.

[0037] Figure Three A method based on the embodiments of this application is provided. Figure One The diagram illustrates the automated verification process of the PCIe 6 physical layer level test suite using the physical IP verification device. Figure Three As shown, in step S301, the verification process is initiated. Then, in step S310, it is determined whether to select the actual physical design form of the design under test. If not, step S312 is executed to use the physical model form of the design under test; if yes, step S314 is executed to use the actual physical design form of the design under test. After step S312 or step S314, step S320 is executed to determine whether to select the root device / endpoint device dual mode. If not, step S330 is executed to determine whether to enable the root device single mode. If still no, step S334 is executed to enable the endpoint device single mode. If the determination in step S330 is yes, step S332 is executed to enable the root device single mode. If the determination in step S320 is yes, step S322 is executed to enable the root device / endpoint device dual mode. After step S322, step S332, or step S334, step S340 is executed to determine whether to select PIPE6 version. If not, step S344 is executed to enable PIPE5 version; if yes, step S342 is executed to enable PIPE6 version. After step S342 or S344, step S350 is executed to send the test suite stimulus sequence and perform PCIe6 protocol verification.

[0038] See Figure One、 Figure Two Also Figure Three , a universal verification device and method are provided, which can be used for PAM4 PCIe6 physical layer intellectual property core verification and other communication protocols and interface standards, effectively integrating and expanding the rich underlying library of verification components (based on two interface interfaces of verification component physical interface and verification component serial interface, respectively), providing a dual-mode verification component with user-level hierarchical expansion and rich test suite sequence mode, with the characteristics and advantages of strong configuration interface flexibility and diversified device working mode. Moreover, the universal verification device and method support single-mode endpoint devices or dual-mode root devices and endpoint devices, support flexible configuration of the control interface, provide rich sequence mode and test suite test vector set, support users to complete the integration of the protocol verification device of the physical layer intellectual property core and the protocol consistency docking verification of the test suite based on higher integration efficiency, lower learning cost and less manpower input. Moreover, based on the universal verification device, the integration of protocol consistency verification of the physical layer subsystem and the debugging cost of basic flow test vectors can be effectively reduced in actual project development, the verification period of protocol standardization docking test is shortened, and the completeness of full-quantitative protocol docking verification of, for example, PCIe6 PHY IP dimension and the efficiency of reusable verification devices are effectively improved.

[0039] Referring to Figure One 、 Figure Two 、 Figure Three Also in Table 1, in a possible implementation, the design under test is optionally docked between the verification component physical interface and the verification component serial interface in the form of a physical model or a real physical design, and at least before the physical IP verification device starts the protocol consistency verification of the design under test, the physical model form of the design under test or the real physical design form of the design under test is selected for the protocol consistency verification of the design under test. In this way, two design under test docking forms are supported, based on the form of a physical model and based on a real physical intellectual property core, which can take into account different simulation needs and scenarios such as acceleration simulation efficiency and integrated verification.

[0040] In one possible implementation, when the development completion degree of the design under test is not higher than a first preset threshold, the feature function list covered by the first test vector set and the second test vector set includes data path basic rate throughput test and control path handshake test, and the verification component physical interface cooperates with the verification component serial interface to support setting impedance matching resistance value of physical link transceiver end and skipping calibration circuit and self adaption circuit. In this way, the test vector set and the interface are configured based on the development completion degree of the design under test. When the development completion degree of the design under test is low, for example, not higher than the first preset threshold (30%), the impedance matching resistance value of the physical link transceiver end can be set to an ideal value, for example, 50 ohms, and the corresponding impedance selection gear is set, and the calibration circuit and the self adaption circuit are skipped, which helps to improve the simulation verification efficiency and better adapt to the verification focus in the early circuit design stage, that is, the feature function list covered by the first test vector set and the second test vector set, that is, the data path full rate throughput test, the power consumption management test and the loopback path test.

[0041] In one possible implementation, when the development completion degree of the design under test is not higher than a first preset threshold, the feature function list covered by the first test vector set and the second test vector set includes data path basic rate throughput test and control path handshake test, and the verification component physical interface cooperates with the verification component serial interface to support setting impedance matching resistance value of physical link transceiver end and skipping calibration circuit and self adaption circuit. In this way, the test vector set and the interface are configured based on the development completion degree of the design under test. When the development completion degree of the design under test is low, for example, not higher than the first preset threshold (30%), the impedance matching resistance value of the physical link transceiver end can be set to an ideal value, for example, 50 ohms, and the corresponding impedance selection gear is set, and the calibration circuit and the self adaption circuit are skipped, which helps to improve the simulation verification efficiency and better adapt to the verification focus in the early circuit design stage, that is, the feature function list covered by the first test vector set and the second test vector set, that is, the data path full rate throughput test, the power consumption management test and the loopback path test.

[0042] In one possible implementation, when the development completion degree of the design under test is not higher than a first preset threshold, the feature function list covered by the first test vector set and the second test vector set includes data path basic rate throughput test and control path handshake test, and the verification component physical interface cooperates with the verification component serial interface to support setting impedance matching resistance value of physical link transceiver end and skipping calibration circuit and self adaption circuit. In this way, the test vector set and the interface are configured based on the development completion degree of the design under test. When the development completion degree of the design under test is low, for example, not higher than the first preset threshold (30%), the impedance matching resistance value of the physical link transceiver end can be set to an ideal value, for example, 50 ohms, and the corresponding impedance selection gear is set, and the calibration circuit and the self adaption circuit are skipped, which helps to improve the simulation verification efficiency and better adapt to the verification focus in the early circuit design stage, that is, the feature function list covered by the first test vector set and the second test vector set, that is, the data path full rate throughput test, the power consumption management test and the loopback path test. Figure TwoThe verification component physical interface cooperates with the verification component serial interface to support physical initialization acceleration mode and non-acceleration mode, modeling of the calibration circuit and adaptive adjustment circuit, modeling of the receive side lane margin circuit, and modeling of the transmit side equalization circuit. In this way, the test vector set and interface are configured based on the development completeness of the design under test, and when the development completeness of the design under test is already high, for example, higher than a second preset threshold (50%) and not higher than a third preset threshold (85%), further enhancement of the circuit with strong correlation of electrical characteristics and tuning of the parameters is needed according to the design of the digital analog circuit, and the physical initialization acceleration mode and non-acceleration mode, modeling of the calibration circuit and adaptive adjustment circuit, modeling of the receive side lane margin circuit, and modeling of the transmit side equalization circuit are supported. In this way, through the modeling of the calibration circuit and adaptive adjustment circuit, different step sizes in the algorithm execution process can be accurately simulated, and through the modeling of the receive side lane margin circuit, boundary adjustment of the two dimensions of the horizontal time eye width and the vertical voltage amplitude eye height of the eye diagram can be accurately simulated. In addition, through the modeling of the transmit side equalization circuit, different voltage amplitudes and channel insertion loss and the corresponding gear setting index can be accurately simulated.

[0043] In a possible implementation, when the development completeness of the design under test is higher than the third preset threshold, the characteristic function table covered by the first test vector set and the second test vector set includes multi-protocol type highest rate test, multi-interface bus bit width test, debugging and diagnosis circuit test, and abnormal protection circuit test, and the verification component physical interface cooperates with the verification component serial interface to support calibration and tuning based on simulation post-simulation data and impedance matching resistance value gear setting of the physical link transceiver. In this way, the test vector set and interface are configured based on the development completeness of the design under test, and when the development completeness of the design under test is already high enough (higher than 85%) or even reaches the highest value, that is, 100%, it means that the real physical design form is used as the design under test interface form, and therefore a complete set of test vectors needs to be covered, and at this time, the electrical characteristics under the real physical design form need to be considered, and calibration and tuning based on simulation post-simulation data and impedance matching resistance value gear setting of the physical link transceiver are supported. In this way, the phase-locked loop circuit can generate more fine, hierarchical, and different frequency band clocks, and the impedance value and the corresponding gear setting can also be matched, so as to better adapt to the characteristic function table covered by the first test vector set and the second test vector set, that is, the multi-protocol type highest rate test, the multi-interface bus bit width test, the debugging and diagnosis circuit test, and the abnormal protection circuit test.

[0044] In one possible implementation, the selection of either the physical model form of the design under test (DUT) or the actual physical design form of the DUT for protocol conformance verification is determined based on the development completion level of the DUT. Furthermore, the test results of test cases for protocol conformance verification of the physical model form of the DUT can optionally be reused for protocol conformance verification of the actual physical design form of the DUT. See also... Figure One , Figure Two , Figure Three As shown in Table 1, with the gradual improvement of the completion rate of the design under test (DUT) at multiple iterative development nodes, such as from 30% to 50% and then to 85%, the feature function tables covered by the first and second test vector sets, the features supported by the PIPE interface, and the features supported by the physical interface and serial interface of the verification component all changed or remained unchanged. When the completion rate is low, such as 30%, the focus of chip verification is on testing the basic flow of the data path and the basic request-to-response handshake interaction of the control path, and the electrical characteristic parameters may not have been completed at the time of testing. Typically, in the early stages of chip development, clarifying the outermost interface specification of the physical layer first is beneficial for the top-level chip of the system-on-a-chip to start integrating the physical layer periphery (PHY Wrapper) and the connections between different IPs / subsystems. The single-point functional circuits inside the physical layer intellectual property core can be gradually improved according to the iterative plan, for example, by first determining the electrical characteristics of the interface. Therefore, in the early stages of chip development, circuit design typically begins with testing the handshake mechanism to ensure correct interaction with the host computer and system application layer. However, as chip development progresses, some parameters set based on the physical model in the early circuit design may deviate significantly. Consequently, early test results may be limited compared to the current chip design. For example, the handshake protocol is based on feedback time, and significant changes in circuit delays or timing paths may necessitate re-verifying the handshake test results or test cases from earlier tests. To address this, the test results of early test cases—specifically, those verifying protocol conformance for the physical model of the design under test—can be selectively reused by examining changes in certain key parameters. Alternatively, past test cases can be rerun. Therefore, the test results of protocol conformance verification for the physical model of the design under test can be optionally reused for protocol conformance verification of the actual physical design of the design under test. This improves overall verification efficiency while ensuring the completeness and correctness of the verification results.

[0045] In one possible implementation, when the real physical design form of the design under test changes the impedance matching resistance value, the step size of the calibration circuit and the adaptive adjustment circuit, or the horizontal eye width / vertical eye height / eye diagram boundary of the two-dimensional eye diagram of the channel margin circuit, relative to the physical model form of the design under test, the test case for protocol conformance verification of the physical model form of the design under test is re-run or incrementally tested. In this way, as the degree of completion of chip development increases, by examining the changes of certain key parameters, the incrementally increased test vectors can be realized, that is, the early test results are selectively reused. The key parameter changes, such as electrical characteristics, time delay, operating voltage, operating current, peak power, etc., may be deviated from the initial design during the development process, so some test vectors can still be reused, and some must be retested. It helps to optimize the verification efficiency. Here, by examining whether the impedance matching resistance value, the step size of the calibration circuit and the adaptive adjustment circuit, or the horizontal eye width / vertical eye height / eye diagram boundary of the two-dimensional eye diagram of the channel margin circuit is changed, combined with the change list (Change List) and the feature list (Feature List) plan supported by the version iteration step by step during the circuit design stage, the test cases that have been tested are selectively re-run, or the early development test results are selectively reused, that is, the early development test results are selectively reused. In this way, it helps to improve the overall verification efficiency.

[0046] In one possible implementation, when the real physical design form of the design under test changes the operating voltage, operating current, peak power or circuit cell area associated with signal integrity and power integrity (SIPI) relative to the physical model form of the design under test, the test case for the protocol conformance verification of the physical circuit electrical characteristics strongly related to the physical model form of the design under test is re-run. Thus, considering the reuse of test vector results and possible re-run cases, for example, the handshake protocol is based on the end-to-end feedback time from response to request, assuming that as the function and complexity of the circuit increases, the internal pipeline delay usually also increases accordingly, the circuit delay increases, which may mean that the test results of the early detection handshake success need to be re-verified. To this end, by increasing the test vectors, new test vectors are added as the development degree of completion improves, which helps to shorten the overall verification time. Here, by examining some key changes, such as electrical characteristics, delay, signal integrity (SI) and power integrity (PI) also called power consumption integrity, and examining the related operating voltage / operating current, peak power and circuit cell area, etc., the circuit micro-architecture, core unit may be adjusted and optimized continuously according to the simulation data during the development process, and thus some test vectors can still be reused, and some must be retested. This helps to optimize the verification efficiency.

[0047] In one possible implementation, the real physical design form of the design under test includes a physical layer code sub-layer (PCS), a physical layer process unit (PPU) and a physical layer media attachment (PMA). Thus, two design under test docking forms are supported, based on the form of the physical model and the form based on the real physical intellectual property core, which can take into account different simulation needs and scenarios such as acceleration simulation efficiency and integrated verification.

[0048] In a possible implementation, the first reusable multi-mode test sequence generator cooperates with the second reusable multi-mode test sequence generator to initiate a root device and endpoint device dual-mode protocol conformance verification flow when the design under test is a root device and endpoint device dual-mode, or to initiate a root device single-mode protocol conformance verification flow when the design under test is a root device single-mode, or to initiate an endpoint device single-mode protocol conformance verification flow. In this way, root device single-mode, endpoint device single-mode or root device and endpoint device dual-mode are supported, customized settings are supported, and thus uplink and downlink scenarios and device characteristics can be simulated.

[0049] In a possible implementation, the verification component physical interface cooperates with the verification component serial interface to set an interface operation mode of a physical interface associated with the design under test to be a native PIPE operation mode or a Serdes PIPE operation mode, to set an interface version associated with the design under test, and to set an interface data bit width associated with the design under test. In this way, protocol conformance verification, functional verification completeness at a physical layer subsystem level, and standardized protocol verification are supported, a rich set of test vectors is provided, different levels of interfacing test scenarios and completeness verification requirements at a transaction layer, a data link layer, a physical layer, and the like can be met, a hierarchical rich debugging interactive interface and debugging means are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-grained low-power management is also supported.

[0050] In a possible implementation, the verification component physical interface cooperates with the verification component serial interface to support respective interfacing test scenarios and completeness test scenarios of the design under test operating at multiple levels of the communication protocol stack. In this way, a universal verification apparatus and method are provided, with strong protocol universality and application diversity, which can be applied not only to short-cycle, multi-round, continuous agile iteration development and testing of PAM4 PCIe 6 PHY, but also to other protocol types and PHY IP circuit design and development, such as SATA / USB / ETH PHY IP, and the like, and corresponding test suite test vectors are selected according to different PHY types and development stage nodes.

[0051] In a possible implementation, the verification component physical interface cooperates with the verification component serial interface to support PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, and PCIe 6.0. In this way, verification requirements of various versions of the PCIe protocol are supported.

[0052] In a possible implementation, the verification component physical interface cooperates with the verification component serial interface to support 1-symbol, 2-symbol, 4-symbol and 8-symbol interface data bit widths, where 1-symbol is 8 bits. In this way, various interface data bit widths are supported.

[0053] In a possible implementation, the physical IP verification device supports hierarchical and fine-grained low-power management, supports a debugging interactive interface for transaction layer record interaction, and supports a four-level pulse amplitude modulation mode of four-level coding. In this way, short-cycle, multi-round, continuous agile iterative development and testing of the PAM4 PCIe6 PHY are supported, hierarchical rich debugging interactive interfaces and debugging means are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-grained low-power management is supported.

[0054] Figure Four A flowchart of a physical IP verification method provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the physical IP verification method includes the following steps. Figure Four

[0055] Step S401: A physical model form of a design under test or a real physical design form of the design under test is selected.

[0056] Step S403: The design under test is selected to be a root device single mode, an endpoint device single mode, or a root device and endpoint device dual mode.

[0057] Step S405: Physical layer interface connection requirements of a dual-mode connection form of the design under test and serial port layer interface connection requirements of the dual-mode connection form of the design under test are determined, where the physical layer interface connection requirements of the dual-mode connection form of the design under test include physical layer interface connection requirements based on a physical model and physical layer interface connection requirements based on a real physical design, and the serial port layer interface connection requirements of the dual-mode connection form of the design under test include serial port layer interface connection requirements based on a physical model and serial port layer interface connection requirements based on a real physical design.

[0058] Step S407: Protocol consistency verification of the design under test is performed by using a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface.

[0059] Referring to Figure Four ​, the first reusable multi-mode test sequence generator is configured to provide a multi-mode and multi-level first test vector set, the multi-mode and multi-level first test vector set supports root device single mode, endpoint device single mode or root device and endpoint device dual mode, and the multi-mode and multi-level first test vector set also supports multiple levels of a communication protocol stack including a transaction layer, a data link layer and a physical layer, the communication protocol stack is a PCIe protocol stack, a Serdes protocol stack, a SATA protocol stack, a USB protocol stack, an Ethernet physical IP protocol stack, a display interface protocol stack or an HDMI protocol stack. The verification component physical interface interacts with the first reusable multi-mode test sequence generator and provides a parameterized physical interface interface for configuring an interface working mode, an interface version and an interface data bit width of the physical interface, thereby supporting physical layer interface requirements of the dual-mode docking form of the design under test. The second reusable multi-mode test sequence generator is configured to provide a multi-mode and multi-level second test vector set, the multi-mode and multi-level second test vector set supports root device single mode, endpoint device single mode or root device and endpoint device dual mode, and the multi-mode and multi-level second test vector set also supports multiple levels of the communication protocol stack. The verification component serial interface interacts with the second reusable multi-mode test sequence generator and provides a parameterized serial interface interface for configuring the serial interface, thereby supporting serial port layer interface requirements of the dual-mode docking form of the design under test.

[0060] Figure Four The physical IP verification method has the following improvements and beneficial technical effects. 1) Two design docking forms are supported, one based on a physical model and the other based on a real physical intellectual property core, which can balance the simulation requirements and scenarios of acceleration simulation efficiency and integrated verification. 2) Root device single mode, endpoint device single mode or root device and endpoint device dual mode are supported, and customized settings are supported, thereby being able to simulate uplink and downlink scenarios and device characteristics. 3) The verification device of a test suite integrates the first and second reusable multi-mode test sequence generators supporting multi-mode and multi-level first and second test vector sets, and also integrates the physical interface and serial interface supporting the dual-mode docking form of the design under test, so that one test suite achieves the effect of multiple test suites, has strong flexibility and high inclusiveness. 4) Protocol consistency verification, physical layer subsystem level functional verification completeness and standardized protocol verification are supported, rich test vector sets are provided, different level docking test scenarios and completeness verification requirements of the transaction layer, the data link layer and the physical layer are met, hierarchical debugging interaction interfaces and debugging means are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-grained low-power management is also supported.

[0061] Reference is made to Figure FourIn one possible implementation, the design under test is optionally interfaced between the verification component physical interface and the verification component serial interface in a physical model form or a real physical design form, and at least before performing protocol conformance verification of the design under test, the physical model form of the design under test or the real physical design form of the design under test is selected for the protocol conformance verification of the design under test. In this way, two design under test interfacing forms are supported, based on a physical model form and a real physical intellectual property core form respectively, which can take into account different simulation requirements and scenarios such as acceleration simulation efficiency and integrated verification.

[0062] In one possible implementation, the selection of the physical model form of the design under test or the selection of the real physical design form of the design under test for the protocol conformance verification of the design under test is determined based on the development completion degree of the design under test, and the test results of the test cases for the protocol conformance verification of the physical model form of the design under test are optionally reused for the protocol conformance verification of the real physical design form of the design under test. As the development completion degree of the design under test is gradually improved, at multiple iterative development nodes, for example, from 30% to 50% to 85%, the characteristic function table covered by the first test vector set and the second test vector set, the characteristics supported by the PIPE interface, and the characteristics supported by the cooperation of the verification component physical interface and the verification component serial interface also change accordingly or remain unchanged. When the completion degree is low, for example, 30% completion degree, the focus of chip verification is on the basic flow of the test data path and the basic Request-To-Response handshake interaction of the control path, and the electrical characteristic parameters may not be completed at the time of testing. Generally, in the early stage of chip development, the interface specification of the outermost physical layer is determined first, which is beneficial to the connection between the chip top-level integrated physical layer wrapper and different IP / subsystems of the system-level chip, and the single-point functional circuit inside the physical layer intellectual property core can be gradually improved according to the iteration plan, for example, the electrical characteristics of the interface are determined first. Therefore, when the circuit is designed in the early stage of chip development, the test usually starts from the handshake, so as to ensure the correct interaction with the host computer and the system application layer. Therefore, as the chip development project advances, some parameters set based on the physical model in the early stage of circuit design may have a large deviation, and therefore the early test results may have limitations with respect to the current chip design, for example, the handshake protocol is based on feedback time, and when the circuit delay or timing path changes greatly, the test results or test cases of the early handshake test results may need to be reverified. Therefore, for the early test results, that is, the test results of the test cases for the protocol conformance verification of the physical model form of the design under test, the early test results can be selectively reused by observing the changes of some key parameters, or the past test cases can be selected to run again, and therefore the test results of the test cases for the protocol conformance verification of the physical model form of the design under test are optionally reused for the protocol conformance verification of the real physical design form of the design under test. In this way, the overall verification efficiency is improved while the completeness and correctness of the verification results are ensured.

[0063] Figure Fiveis a structural schematic diagram of a computing device provided in an embodiment of the present application. The computing device 500 includes one or more processors 510, a communication interface 520, and a memory 530. The processor 510, the communication interface 520, and the memory 530 are connected to each other through a bus 540. Optionally, the computing device 500 can further include an input / output interface 550 connected with an input / output device for receiving a parameter set by a user and the like. The computing device 500 can be used to implement part or all of the functions of the device embodiments or the system embodiments in the above-described embodiments of the present application; the processor 510 can also be used to implement part or all of the operation steps of the method embodiments in the above-described embodiments of the present application. For example, the specific implementation of the computing device 500 performing various operations can refer to the specific details in the above-described embodiments, for example, the processor 510 is used to perform part or all of the steps in the above-described method embodiments or part or all of the operations in the above-described method embodiments. For another example, in the embodiments of the present application, the computing device 500 can be used to implement part or all of the functions of one or more components in the above-described device embodiments, in addition, the communication interface 520 can be specifically used for communication functions necessary for implementing the functions of these devices, components, and the like, and the processor 510 can be specifically used for processing functions necessary for implementing the functions of these devices, components, and the like.

[0064] It should be understood that, Figure Five The computing device 500 can include one or more processors 510, and the plurality of processors 510 can cooperatively provide processing capability in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the plurality of processors 510 can constitute a processor sequence or a processor array, or the plurality of processors 510 can be divided into a main processor and an auxiliary processor, or the plurality of processors 510 can have different architectures such as using a heterogeneous computing architecture. In addition, Figure Five The computing device 500 shown, the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 can include more or fewer components than those shown, or combine certain components, or split certain components, or have a different arrangement of components. Figure Five

[0065] ​The processor 510 can have various specific implementations. For example, the processor 510 can include one or more combinations of a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), a data processing unit (DPU), or the like, and embodiments of the present application are not limited in this regard. The processor 510 can also be a single core processor or a multiple core processor. The processor 510 can be a combination of a CPU and a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 510 can also be implemented by a logic device with built-in processing logic, such as an FPGA or a digital signal processor (DSP), etc. The communication interface 520 can be a wired interface or a wireless interface, used for communication with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless local area network interface, etc.

[0066] The memory 530 can be a non-volatile memory, for example, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The memory 530 can also be a volatile memory, which can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, for example, a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchlink DRAM (SLDRAM), and a direct rambus RAM (DR RAM). The memory 530 can also be used for storing programs codes and data to be used in the processor 510 to invoke the program codes stored in the memory 530 to execute the partial or all of the steps of the above method embodiments, or to execute the corresponding functions of the above device embodiments. Further, the computing device 500 can include more or less components, or have different configurations of components than those shown, depending upon the needs of the user. Figure Five More or less components can be used or different configurations of components can be used.

[0067] The bus 540 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 540 can be divided into an address bus, a data bus, a control bus, etc. In addition to including a data bus, the bus 540 can also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity,Figure Five Only one bus or bus type is used in the figure, but it is understood that the computer system 1000 can use multiple buses, bus types, and / or other bus configurations, combinations, and / or variations thereof.

[0068] The method and device provided by the embodiments of the present application are based on the same inventive concept, and the embodiments, implementation manners, examples, or implementation modes of the method and device are similar in principle for solving problems, and thus the embodiments, implementation manners, examples, or implementation modes of the method and device can be referred to each other, and the repeated parts will not be described herein. The embodiments of the present application further provide a system, which includes a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0069] The embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0070] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, an apparatus (system) or a computer program product. The present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application can be implemented partially or wholly in software, hardware, firmware or any combination thereof. When implemented in software, the embodiments of the present application can be implemented in the form of a computer program product storing computer available instructions. The present application can take the form of a computer program product embodied in one or more computer available storage medium(s) having computer-usable program code stored therein. The computer program code can be used to program a computer (or other programmable devices) to implement a process or operate as described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer program code can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, such as from a website, a computer, a server or a data center to another website, computer, server or data center through a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless network, microwave, etc.) medium. The computer readable storage medium can be any available medium or a collection of medium accessible by a computer or a data storage device such as a server, data center, etc. containing one or more medium. The medium can be a magnetic medium (e.g., a floppy diskette, a hard disk drive, a magnetic tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid state disk, a random access memory, a flash memory, a read only memory, a programmable read only memory, an electrically programmable read only memory, a register, or any other suitable storage medium.

[0071] The embodiments of the present application are described with reference to the flowchart and / or block diagram of the method, apparatus (system) and computer program product according to the embodiments of the present application. Each block in the flowchart and / or block diagram and combinations of blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processor or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure One The flowchart and / or block diagram can include one or more flowcharts and / or one or more block diagrams. Figure One The flowchart and / or block diagram can include one or more flowcharts and / or one or more block diagrams. The flowchart and / or block diagram can include one or more flowcharts and / or one or more block diagrams.Figure One One or more processes and / or boxes Figure One The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure One One or more processes and / or boxes Figure One The steps of the function specified in one or more boxes.

[0072] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A physical IP verification device, characterized in that, The physical IP verification device includes: A first reusable multi-mode test sequence generator is used to provide a multi-mode and multi-level first test vector set, wherein the multi-mode and multi-level first test vector set supports root device single mode, endpoint device single mode, or root device and endpoint device dual mode, and the multi-mode and multi-level first test vector set also supports multiple layers of communication protocol stacks including transaction layer, data link layer and physical layer, wherein the communication protocol stack is PCIe protocol stack, SerDes protocol stack, SATA protocol stack, USB protocol stack, Ethernet physical IP protocol stack, display interface protocol stack or HDMI protocol stack; Verify the physical interface of the component, interact with the first reusable multi-mode test sequence generator and provide a parameterized physical interface interface for configuring the interface working mode, interface version and interface data bit width of the physical interface, thereby supporting the physical layer docking requirements of the dual-mode docking form of the design under test. The physical layer docking requirements of the dual-mode docking form of the design under test include physical layer docking requirements based on physical models and physical layer docking requirements based on real physical designs. A second reusable multi-mode test sequence generator is used to provide a multi-mode and multi-level second test vector set, wherein the multi-mode and multi-level second test vector set supports root device single mode, endpoint device single mode, or root device and endpoint device dual mode, and the multi-mode and multi-level second test vector set also supports multiple levels of the communication protocol stack; and The verification component has a serial interface that interacts with the second reusable multimode test sequence generator and provides a parameterized serial interface for configuring the serial interface to support the serial port level docking requirements of the dual-mode docking form of the design under test. The serial port level docking requirements of the dual-mode docking form of the design under test include serial port level docking requirements based on physical models and serial port level docking requirements based on actual physical designs.

2. The physical IP verification device according to claim 1, characterized in that, The design under test can optionally be interfaced between the physical interface of the verification component and the serial interface of the verification component in either a physical model form or a real physical design form. Furthermore, at least before the physical IP verification device initiates the protocol conformance verification of the design under test, the physical model form or the real physical design form of the design under test is selected for use in the protocol conformance verification of the design under test.

3. The physical IP verification device according to claim 2, characterized in that, When the development completion rate of the design under test is not higher than the first preset threshold, the feature function table covered by the first test vector set and the second test vector set includes basic data path rate current flow test and control path handshake test. The physical interface of the verification component cooperates with the serial interface of the verification component to support setting the impedance matching resistance value of the physical link transceiver end and skipping the calibration circuit and adaptive adjustment circuit.

4. The physical IP verification device according to claim 3, characterized in that, When the development completion rate of the design under test is higher than the first preset threshold and not higher than the second preset threshold, the feature function table covered by the first test vector set and the second test vector set includes full-rate data path current flow test, power management test and loopback path test. The physical interface of the verification component cooperates with the serial interface of the verification component to support setting the power consumption status of circuit units under multi-level power management, loopback path bypass branch circuit and hardware logic processing, and built-in self-test.

5. The physical IP verification device according to claim 4, characterized in that, When the development completion rate of the design under test is higher than the second preset threshold and not higher than the third preset threshold, the feature function table covered by the first test vector set and the second test vector set includes low-power sub-state testing of the full power spectrum, the calibration circuit and adaptive adjustment circuit, eye diagram two-dimensional boundary testing, and equalization circuit testing. The physical interface of the verification component cooperates with the serial interface of the verification component to support physical initialization accelerated mode and non-accelerated mode, modeling of the calibration circuit and adaptive adjustment circuit, modeling of the receiver-side channel margin circuit, and modeling of the transmitter-side equalization circuit.

6. The physical IP verification device according to claim 5, characterized in that, When the development completion rate of the design under test is higher than the third preset threshold, the feature function table covered by the first test vector set and the second test vector set includes multi-protocol type maximum rate test, multi-interface bus width test, debugging and diagnostic circuit test, and abnormal protection circuit test. The physical interface of the verification component cooperates with the serial interface of the verification component to support calibration and optimization based on post-simulation data and the setting of impedance matching resistor value at the physical link transceiver end.

7. The physical IP verification device according to claim 2, characterized in that, The selection of either the physical model form of the design under test or the actual physical design form of the design under test for protocol consistency verification is determined based on the development completion level of the design under test. Furthermore, the test results of the test cases for protocol consistency verification of the physical model form of the design under test can optionally be reused for protocol consistency verification of the actual physical design form of the design under test.

8. The physical IP verification device according to claim 7, characterized in that, When the actual physical design of the design under test changes the impedance matching resistor value, the step size of the calibration circuit and the adaptive adjustment circuit, or the horizontal eye width / vertical eye height / eye diagram boundary of the two-dimensional eye diagram of the channel margin circuit relative to the physical model of the design under test, the test cases for protocol conformance verification of the physical model of the design under test are rerun or incrementally tested.

9. The physical IP verification device according to claim 7, characterized in that, When the actual physical design of the design under test changes the operating voltage, operating current, peak power, or circuit unit area associated with power integrity and signal integrity compared to the physical model of the design under test, the test cases for protocol conformance verification that are strongly related to the electrical characteristics of the physical circuit for the physical model of the design under test shall be rerun.

10. The physical IP verification device according to claim 2, characterized in that, in, The actual physical design form of the design under test includes the physical coding sublayer, the physical layer soft core logic, and the physical layer hard core logic.

11. The physical IP verification device according to claim 2, characterized in that, The first reusable multimode test sequence generator cooperates with the second reusable multimode test sequence generator to: initiate a root device and endpoint device dual-mode protocol conformance verification process when the design under test is a root device and endpoint device dual-mode, or initiate a root device single-mode protocol conformance verification process when the design under test is a root device single-mode, or initiate an endpoint device single-mode protocol conformance verification process.

12. The physical IP verification device according to claim 2, characterized in that, The physical interface of the verification component cooperates with the serial interface of the verification component to set the interface working mode of the physical interface associated with the design under test to be either native PIPE working mode or Serdes PIPE working mode, set the interface version associated with the design under test, and set the interface data bit width associated with the design under test.

13. The physical IP verification device according to claim 2, characterized in that, The physical interface of the verification component works in conjunction with the serial interface of the verification component to support the design under test in various docking test scenarios and completeness test scenarios at multiple layers of the communication protocol stack.

14. The physical IP verification device according to claim 2, characterized in that, The physical interface of the verification component works in conjunction with the serial interface of the verification component to support PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0 and PCIe 6.

0.

15. The physical IP verification device according to claim 2, characterized in that, The physical interface of the verification component works in conjunction with the serial interface of the verification component to support interface data bit widths of 1 symbol, 2 symbols, 4 symbols and 8 symbols, where 1 symbol is 8 bits.

16. The physical IP verification device according to claim 2, characterized in that, The physical IP verification device supports hierarchical and fine-grained low-power management, supports a debugging interface for transaction layer recording, and supports a four-level pulse amplitude modulation mode with four-level encoding.

17. A physical IP verification method, characterized in that, The physical IP verification method includes: Select the physical model form of the design to be tested or the actual physical design form of the design to be tested; Select whether the design under test is root device single mode, endpoint device single mode, or root device and endpoint device dual mode. The physical layer docking requirements of the dual-mode docking form of the design under test and the serial port layer docking requirements of the dual-mode docking form of the design under test are determined. The physical layer docking requirements of the dual-mode docking form of the design under test include physical layer docking requirements based on physical models and physical layer docking requirements based on actual physical designs. The serial port layer docking requirements of the dual-mode docking form of the design under test include serial port layer docking requirements based on physical models and serial port layer docking requirements based on actual physical designs. The protocol conformance verification of the design under test is performed using a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. The first reusable multi-mode test sequence generator is used to provide a multi-mode and multi-level first test vector set. This multi-mode and multi-level first test vector set supports root device single-mode, endpoint device single-mode, or root device / endpoint device dual-mode. Furthermore, the multi-mode and multi-level first test vector set supports multiple layers of a communication protocol stack, including the transaction layer, data link layer, and physical layer. The communication protocol stack can be a PCIe protocol stack, a SerDes protocol stack, a SATA protocol stack, a USB protocol stack, an Ethernet physical IP protocol stack, a display interface protocol stack, or an HDMI protocol stack. The verification component's physical interface interacts with the first reusable multi-mode test sequence generator and provides a parameterized physical interface for configuring the physical interface's operating mode, version, and data bit width, thereby supporting the physical-level docking requirements of the dual-mode docking configuration of the design under test. The second reusable multi-mode test sequence generator is used to provide a multi-mode and multi-level second test vector set. The multi-mode and multi-level second test vector set supports root device single mode, endpoint device single mode, or root device and endpoint device dual mode. The multi-mode and multi-level second test vector set also supports multiple levels of the communication protocol stack. The verification component's serial interface interacts with the second reusable multimode test sequence generator and provides a parameterized serial interface for configuring the serial interface to support the serial port-level docking requirements of the dual-mode docking configuration of the design under test.

18. The physical IP verification method according to claim 17, characterized in that, The design under test may optionally be interfaced between the physical interface of the verification component and the serial interface of the verification component in either a physical model form or a real physical design form. Furthermore, at least before performing protocol conformance verification of the design under test, the physical model form or the real physical design form of the design under test is selected for use in the protocol conformance verification of the design under test.

19. The physical IP verification method according to claim 17, characterized in that, The selection of either the physical model form of the design under test or the actual physical design form of the design under test for protocol consistency verification is determined based on the development completion level of the design under test. Furthermore, the test results of the test cases for protocol consistency verification of the physical model form of the design under test can optionally be reused for protocol consistency verification of the actual physical design form of the design under test.

20. A computer device, characterized in that, The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method according to any one of claims 17 to 19.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer device, cause the computer device to perform the method according to any one of claims 17 to 19.

Images