Phase frequency detector and related equipment

Abstract

The invention provides a phase frequency detector and related equipment. The phase frequency detector comprises two triggers, an AND operation unit, a detection unit and two delay modules, the input end of the first D flip-flop is connected to a reference clock, and the input end of the second D flip-flop is connected to a feedback clock; the first delay module adjusts the pulse width of the positive pulse signal according to a first gear signal output by the detection unit, and provides the adjusted positive pulse signal to the pull-up switch; the second delay module adjusts the pulse width of the negative pulse signal according to a second gear signal output by the detection unit, and provides the adjusted negative pulse signal to the pull-down switch. According to the phase frequency detector, two delay modules are introduced to adjust the pulse width of a pulse signal, when the mismatch problem of the charge pump is eliminated, it only needs to guarantee that the adjusted positive pulse width and negative pulse width are matched with a current source in the charge pump, phase discrimination of the phase frequency detector is not affected, and deflection between a reference clock and a feedback clock can be eliminated.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a frequency and phase detector and related equipment. Background Technology

[0002] In a phase-locked loop (PLL), the charge pump (CP) converts the phase difference output by the phase frequency detector (PFD) into a current output. After passing through a filter (LPF), the output is a control voltage Vctrl, which is used to adjust the output of the voltage-controlled oscillator (VCO).

[0003] When there is a current mismatch in the charge pump, it will cause a fixed phase difference between the input and output of the phase-locked loop, and will also introduce glitches into the phase noise curve, affecting the jitter of the output signal. How to overcome these problems has become a difficult problem of concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a frequency and phase detector and related equipment to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a frequency and phase detector, the frequency and phase detector comprising: two flip-flops, an AND operation unit, a detection unit, and two delay modules; The input of the first D flip-flop is used to connect to the reference clock, and the input of the second D flip-flop is used to connect to the feedback clock. The output of the first D flip-flop is connected to the input of the first delay module and the first input of the AND operation unit; the output of the second D flip-flop is connected to the input of the second delay module and the second input of the AND operation unit; and the output of the AND operation unit is connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop. The control terminals of the first delay module and the second delay module are both connected to the detection unit. The output terminal of the first delay module is connected to the control terminal of the pull-up switch in the charge pump, and the output terminal of the second delay module is connected to the control terminal of the pull-down switch in the charge pump. The first delay module is used to adjust the pulse width of the positive pulse signal according to the first gear signal output by the detection unit, and provide the adjusted positive pulse signal to the pull-up switch; The second delay module is used to adjust the pulse width of the negative pulse signal according to the second gear signal output by the detection unit, and to provide the adjusted negative pulse signal to the pull-down switch; The positive pulse signal is a pulse signal generated by the first D flip-flop sampling the reference clock, and the negative pulse signal is a pulse signal generated by the second D flip-flop sampling the feedback clock.

[0006] By introducing two delay modules into the frequency and phase detector and adjusting the pulse width of the pulse signal, when eliminating the mismatch problem of the charge pump, it is only necessary to ensure that the adjusted positive pulse width and negative pulse width match the current source in the charge pump (i.e., I1 × adjusted UP pulse width = I2 × adjusted DN pulse width). It is not required that I1 × initial UP pulse width = I2 × initial DN pulse width, so that it will not affect the phase detection of the frequency and phase detector and can eliminate the skew between the reference clock and the feedback clock.

[0007] Optionally, the delay module includes a selection unit, an operation unit, and N delay units connected in sequence; The nth input terminal of the selection unit is connected to the output terminal of the nth delay unit. The first input terminal of the OR operation unit, the N+1th input terminal of the selection unit, and the input terminal of the first delay unit are used to receive the input signal, which is the positive pulse signal or the negative pulse signal. The output terminal of the selection unit is connected to the second input terminal of the OR operation unit, and the output terminal of the OR operation unit serves as the output terminal of the delay module. The control terminal of the selection unit serves as the control terminal of the delay module and is connected to the detection unit for receiving a gear position signal. The gear position signal is used to adjust the conduction relationship between the input and output terminals of the selection unit.

[0008] The delay module uses cascaded delay units, and the output can be adjusted by selecting the unit. The structure is simple and reliable, ensuring the effectiveness of clock skew removal.

[0009] Optionally, the acquisition end of the detection unit is connected to the output end of the charge pump, and during the debugging phase of the frequency and phase detector, the input ends of the two triggers are connected to the same debugging clock. The detection unit is used to monitor the output voltage of the charge pump and determine the first and second gear signals corresponding to the frequency and phase detector during normal operation based on the output voltage.

[0010] Based on the output voltage of the charge pump, the debugging is completed quickly and accurately, ensuring that the obtained first and second gear signals can perfectly eliminate the charge pump mismatch problem.

[0011] Optionally, the detection unit includes a comparator, a first capacitor, and a digital control unit; One terminal of the first capacitor is grounded, and the other terminal of the first capacitor and the inverting input terminal of the comparator are connected to the output terminal of the charge pump. The non-inverting input terminal of the comparator is connected to a reference voltage. The output terminal of the comparator is connected to the digital control unit. The first set of output terminals of the digital control unit is connected to the first delay module, and the second set of output terminals of the digital control unit is connected to the second delay module.

[0012] The detection unit has a simple structure, resulting in higher debugging accuracy, shorter debugging time, and no additional leakage current.

[0013] Secondly, embodiments of the present invention provide a phase-locked loop, the phase-locked loop including the frequency and phase detector described above.

[0014] Thirdly, embodiments of the present invention provide an electronic device including the aforementioned phase-locked loop.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the connection diagrams of a frequency and phase detector provided in an embodiment of the present invention.

[0018] Figure 2 This is the second connection diagram of the frequency and phase detector provided in the embodiment of the present invention.

[0019] Figure 3 This is one of the signal timing diagrams provided in the embodiments of the present invention.

[0020] Figure 4 This is a connection diagram of the delay module provided in an embodiment of the present invention.

[0021] Figure 5 This is the second signal timing diagram provided in an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the connection of the selection unit provided in an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the connection of the detection unit provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] This invention provides a frequency and phase detector; please refer to [the relevant documentation]. Figure 1 , Figure 1 This is one of the connection diagrams of a frequency and phase detector provided in an embodiment of the present invention. The frequency and phase detector includes: two flip-flops, an AND operation unit, a detection unit, and two delay modules. The two flip-flops include a first D flip-flop (DFF1) and a second D flip-flop (DFF2), and the two delay modules include a first delay module and a second delay module.

[0029] The input of the first D flip-flop (DFF1) is used to connect to the reference clock (REFCLK), and the input of the second D flip-flop (DFF2) is used to connect to the feedback clock (FBCLK). Here, the feedback clock is the feedback clock of the phase-locked loop to which the frequency and phase detector belongs. The power supply terminals of the first and second D flip-flops are connected to the power supply VDD.

[0030] The output of the first D flip-flop is connected to the input of the first delay module and the first input of the AND operation unit. The output of the second D flip-flop is connected to the input of the second delay module and the second input of the AND operation unit. The output of the AND operation unit is connected to the reset terminals of the first and second D flip-flops.

[0031] The control terminals of the first delay module and the second delay module are both connected to the detection unit. The output terminal of the first delay module is connected to the control terminal of the pull-up switch (K1) in the charge pump, and the output terminal of the second delay module is connected to the control terminal of the pull-down switch (K2) in the charge pump.

[0032] Please continue to refer to this. Figure 1 The charge pump includes a first current source (I1), a pull-up switch (K1), a pull-down switch (K2), and a second current source (I2) connected in sequence. The other end of the first current source (I1) is connected to the power supply VDD, and the other end of the second current source (I2) is grounded. The output end of the charge pump is located between the pull-up switch (K1) and the pull-down switch (K2).

[0033] When the pull-up switch (K1) is closed, the charge pump has an incoming current under the control of the first current source (I1). When the pull-down switch (K2) is closed, the charge pump has an outgoing current under the control of the second current source (I2).

[0034] The key to solving the current mismatch problem of charge pumps in this invention lies in the inclusion of a delay module. To further illustrate the role of the delay module, embodiments of this invention also provide... Figure 2 , Figure 2 This is the second connection diagram of the frequency and phase detector provided in the embodiment of the present invention. Figure 2 As Figure 1 In comparison, it is with Figure 1 The only difference is the removal of the delay module and detection unit; the connection relationships will not be elaborated here. The following section combines... Figure 3 To provide a detailed explanation Figure 3 This is one of the signal timing diagrams provided in the embodiments of the present invention.

[0035] exist Figure 3In the scenario shown, the reference clock (REFCLK) leads the feedback clock (FBCLK) in phase. When the rising edge of REFCLK arrives, the positive pulse signal (UP) output by the first D flip-flop is high, and the negative pulse signal (DN) output by the second D flip-flop is low. The negative pulse signal (DN) only goes high when the rising edge of the feedback clock (FBCLK) arrives. After processing by the AND operation unit, the reset signal (RST) goes from low to high, simultaneously resetting the first D flip-flop DFF1 and the second D flip-flop DFF2, causing the positive pulse signal (UP) and the negative pulse signal (DN) to go from high to low.

[0036] The positive pulse signal (UP) and the negative pulse signal (DN) control the current switch of the charge pump CP. When the positive pulse signal (UP) is high, the pull-up switch (K1) is closed, and the first current source (I1) operates. When the negative pulse signal (DN) is high, the pull-down switch (K2) is closed, and the second current source (I2) operates. When the reference clock (REFCLK) and the feedback clock (FBCLK) are phase-aligned, the pulse width of the positive pulse signal (UP) is equal to the pulse width of the negative pulse signal (DN). Ideally, the current flowing into and out of the charge pump CP should be zero.

[0037] When the reference clock (REFCLK) and feedback clock (FBCLK) are phase aligned, but the charge pump current is mismatched, i.e., I1 is not equal to I2. For example, if I1 is greater than I2, the outflowing current is greater than 0. The subsequent phase-locked loop will adjust the phase of the feedback clock (FBCLK) to lead, thereby increasing the pulse width of the negative pulse signal (DN), so that I1 × UP pulse width = I2 × DN pulse width. This results in a skew between the reference clock (REFCLK) and the feedback clock (FBCLK).

[0038] This invention introduces adjustable delay modules into the positive pulse path and negative pulse path of the phase-frequency detector (PFD). The detection circuit detects the mismatch of the charge pump current and outputs corresponding range signals based on the detection results, such as the first range signal (UP_ctrl) and the second range signal (DN_ctrl) mentioned below, to adjust the pulse width of the positive pulse signal (UP) and the pulse width of the negative pulse signal (DN), thereby compensating for the mismatch of the charge pump. The specific explanation is as follows.

[0039] The first delay module is used to adjust the pulse width of the positive pulse signal (UP) according to the first gear signal (UP_ctrl) output by the detection unit, and provide the adjusted positive pulse signal to the pull-up switch. When the positive pulse signal is high, the pull-up switch is closed.

[0040] The second delay module is used to adjust the pulse width of the negative pulse signal (DN) according to the second gear signal (DN_ctrl) output by the detection unit, and provide the adjusted negative pulse signal to the pull-down switch. When the negative pulse signal is high, the pull-down switch is closed.

[0041] The positive pulse signal is generated by the first D flip-flop sampling the reference clock, and the negative pulse signal is generated by the second D flip-flop sampling the feedback clock. The first gear signal is the gear signal input from the detection unit to the first delay module; the negative pulse signal is the pulse signal generated by the second D flip-flop sampling the feedback clock, and the second gear signal is the gear signal input from the detection unit to the second delay module.

[0042] The frequency and phase detector provided in this embodiment of the invention introduces two delay modules to adjust the pulse width of the pulse signal. When eliminating the mismatch problem of the charge pump, it is only necessary to ensure that the adjusted positive pulse width and negative pulse width match the current source in the charge pump (i.e., I1 × adjusted UP pulse width = I2 × adjusted DN pulse width). It is not required that I1 × initial UP pulse width = I2 × initial DN pulse width. Therefore, it will not affect the phase detection of the frequency and phase detector and can eliminate the skew between the reference clock and the feedback clock.

[0043] Wherein, the initial UP pulse width is the pulse width of the positive pulse signal output by the first D flip-flop, and the initial DN pulse width is the pulse width of the negative pulse signal output by the second D flip-flop.

[0044] Building upon the foregoing, this embodiment of the invention also provides an optional implementation method for the delay module structure. Please refer to [link / reference]. Figure 4 , Figure 4 This is a connection diagram of a delay module provided in an embodiment of the present invention. The delay module includes a selection unit, an OR operation unit, and N sequentially connected delay units. The output terminal of the i-th delay unit is connected to the input terminal of the (i+1)-th delay unit, where 1 ≤ i ≤ N-1. Each delay unit includes an even number of sequentially connected inverters; the number of inverters can be, but is not limited to, 2. In the diagram, delayn represents the output signal of the n-th delay unit.

[0045] The nth input terminal of the selection unit is connected to the output terminal of the nth delay unit (1≤n≤N), or the first input terminal of the arithmetic unit, the N+1th input terminal of the selection unit, and the input terminal of the first delay unit are connected to the upper-level module (which can be the output terminal of the first D flip-flop or the output terminal of the second D flip-flop) to receive the input signal. The input signal (IN) is the positive pulse signal output by the first D flip-flop or the negative pulse signal output by the second D flip-flop.

[0046] The output of the selection unit is connected to the second input of the OR operation unit, and the output of the OR operation unit serves as the output of the delay module.

[0047] The control terminal of the selection unit serves as the control terminal of the delay module and is connected to the detection unit. It is used to receive the gear position signal ctrl (including the first gear position signal UP_ctrl and the second gear position signal DN_ctrl). The gear position signal is used to adjust the conduction relationship between the input and output terminals of the selection unit.

[0048] It should be understood that when the conduction relationship changes, the magnitude of the pulse width change will also change accordingly.

[0049] Please refer to Figure 5 , Figure 5 This is a second signal timing diagram provided in an embodiment of the present invention. Taking the first input and output terminals of the selection unit being turned on as an example, at this time, the OR operation unit receives the output signal delay1 of the first delay unit and performs an OR operation on delay1 and IN to obtain the output signal OUT with increased pulse width.

[0050] In the frequency and phase detector provided in this embodiment of the invention, the delay module adopts cascaded delay units, and the output is adjusted by selecting the unit. The structure is simple and reliable, and the clock skew removal effect is guaranteed.

[0051] Please refer to Figure 6 , Figure 6 This is a connection diagram of the selection unit provided in an embodiment of the present invention. Assume the delay module includes four delay units, and the selection unit includes selector 1 (Mux1), selector 2 (Mux2), selector 3 (Mux3), and selector 4 (Mux4). The first input terminal of selector 1 serves as the first input terminal of the selection unit and is connected to the output terminal of the first delay unit; the second input terminal of selector 1 serves as the second input terminal of the selection unit and is connected to the output terminal of the second delay unit; the first input terminal of selector 2 serves as the third input terminal of the selection unit and is connected to the output terminal of the third delay unit; the second input terminal of selector 2 serves as the fourth input terminal of the selection unit and is connected to the output terminal of the fourth delay unit; the first input terminal of selector 4 serves as the fifth input terminal of the selection unit and receives the input signal (IN).

[0052] The outputs of selector 1 and selector 2 are connected to the input of selector 3. The output of selector 3 is connected to the second input of selector 4. The output of selector 4 serves as the output of the selection unit and is used to connect to the second input of the OR operation unit.

[0053] The control terminals of selector 1, selector 2, selector 3, and selector 4 serve as the control terminals of the selection unit. They are connected to the detection unit to receive the gear signal ctrl of the selection unit, thereby switching the conduction relationship of the selector and providing different signals to the operation unit.

[0054] Building upon the preceding text, this invention also provides an optional implementation method for quickly and accurately completing debugging and ensuring that the acquired first and second gear signals can perfectly eliminate the charge pump mismatch problem. Please continue to refer to... Figure 1 The acquisition end of the detection unit is connected to the output end of the charge pump.

[0055] During the debugging phase of the frequency and phase detector, the inputs of the two flip-flops are connected to the same debugging clock to ensure phase alignment. The debugging clock can be, but is not limited to, the reference clock.

[0056] The detection unit is used to monitor the output voltage (Vc) of the charge pump and determine the first and second gear signals corresponding to the frequency and phase detector during normal operation based on the output voltage.

[0057] The normal operating phase involves connecting the input of the first D flip-flop (DFF1) to the reference clock (REFCLK) and the input of the second D flip-flop (DFF2) to the feedback clock (FBCLK). It should be noted that during the normal operating phase after pulse width modulation, the detection unit does not need to acquire the output voltage Vc of the charge pump.

[0058] Based on the preceding text, this invention also provides an optional implementation method for obtaining the first and second gear signals during normal operation based on the output voltage, as detailed below.

[0059] After entering the debugging phase, the detection unit is used to send the 0th gear signal to the first delay module and the second delay module.

[0060] Understandably, at this time, the N+1th input and output of the selection unit in the two delay modules are turned on. When the delay module receives the input signal, it will not make any adjustment to the pulse width and will directly transmit it to the back end.

[0061] The detection unit is used to acquire the output voltage of the charge pump for M sampling cycles and verify whether the output voltage of the M sampling cycles alternates. If no alternation occurs, the gear signal sent to the first delay module and the second delay module is adjusted. After the circuit stabilizes (here, the phase-locked loop circuit is stable), the output voltage of the charge pump for M sampling cycles is acquired again until alternation occurs. The gear signal sent to the first delay module at this time is determined as the first gear signal, and the gear signal sent to the second delay module at this time is determined as the second gear signal.

[0062] Specifically, when the output voltage Vc is lower than the reference voltage Vref, the output voltage Vc is higher than the reference voltage Vref, the output voltage Vc is lower than the reference voltage Vref, and the output voltage Vc is higher than the reference voltage Vref in sequence, it is considered that the output voltage changes alternately over M sampling periods.

[0063] Regarding how to adjust the gear signal sent to the first delay module and the second delay module when the output voltage does not change alternately over M sampling cycles, this embodiment of the invention also provides an optional implementation method, please refer to the following.

[0064] When the output voltage does not change alternately over M sampling cycles, the detection unit controls the gear position signal (DN_ctrl) sent to the second delay module to increase by one level when the output voltage (Vc) in the Mth sampling cycle exceeds the reference voltage (Vref). This results in an increase in the pulse width of the corresponding adjusted negative pulse signal, while the gear position signal sent to the first delay module remains unchanged.

[0065] When the output voltage (Vc) in the Mth sampling period is lower than the reference voltage (Vref), the gear position signal (UP_ctrl) sent to the first delay module is increased by one level, and the pulse width of the corresponding adjusted positive pulse signal increases. At this time, the gear position signal sent to the second delay module remains unchanged.

[0066] When the delay module receives the nth gear signal, the nth input and output terminals of the selection unit in the delay module are turned on, or the operation unit performs an OR operation on the input signal of the delay module and the output signal delayn of the nth delay unit, thereby extending the pulse width of the input signal, 1≤n≤N.

[0067] The debugging method provided in this embodiment of the invention has higher debugging accuracy, shorter debugging time, and does not cause additional leakage current.

[0068] Building upon the foregoing, regarding the structure of the detection unit, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 7 , Figure 7 This is a schematic diagram of the connection of the detection unit provided in an embodiment of the present invention.

[0069] The detection unit includes a comparator (U1), a first capacitor (C1), and a digital control unit.

[0070] One terminal of the first capacitor is grounded (VSS), the other terminal of the first capacitor and the inverting input terminal of the comparator are connected to the output terminal of the charge pump, the non-inverting input terminal of the comparator is connected to the reference voltage, the output terminal of the comparator is connected to the digital control unit, the first set of output terminals of the digital control unit is connected to the first delay module (the control terminal of the selection unit therein), and the second set of output terminals of the digital control unit is connected to the second delay module (the control terminal of the selection unit therein).

[0071] The detection unit can detect the output voltage Vc of the charge pump. Ideally, the current I1 equals I2. When there is a mismatch in the charge pump, assuming the current I1 is greater than I2, the current charges the first capacitor C1. When the output voltage Vc exceeds the reference voltage Vref, the comparator U1 outputs low. Conversely, when the current I1 is less than I2, the first capacitor C1 discharges, and the output voltage Vc begins to decrease. When the output voltage Vc is less than the reference voltage Vref, the comparator U1 outputs high.

[0072] Optionally, after entering the debugging stage, if the output voltage (Vc) of the charge pump exceeds the reference voltage (Vref), the comparator outputs a low level; if the output voltage (Vc) of the charge pump is lower than the reference voltage (Vref), the comparator outputs a high level. The digital control unit is used to determine whether the output voltage changes alternately over M sampling periods based on the output of the comparator over M sampling periods.

[0073] When the output of the comparator for M sampling periods is alternating between 010101…, it is determined that the output voltage for M sampling periods changes alternately.

[0074] If the output voltage does not change alternately during M sampling cycles, and the output of the comparator is low during the Mth sampling cycle, the digital control unit controls the gear signal (DN_ctrl) sent to the second delay module to increase by one level (corresponding to an increase in the pulse width of the adjusted negative pulse signal).

[0075] If the comparator outputs a high level in the Mth sampling period, the digital control unit controls the gear signal (UP_ctrl) sent to the first delay module to increase by one level (corresponding to an increase in the pulse width of the adjusted positive pulse signal).

[0076] This invention also provides a phase-locked loop, which includes the aforementioned frequency and phase detector.

[0077] This invention also provides an electronic device including the phase-locked loop described above.

[0078] In summary, the frequency and phase detector and related devices provided in this embodiment of the invention include: two flip-flops, an AND operation unit, a detection unit, and two delay modules; the input of the first D flip-flop is connected to a reference clock, and the input of the second D flip-flop is connected to a feedback clock; the first delay module adjusts the pulse width of the positive pulse signal according to the first position signal output by the detection unit, and provides the adjusted positive pulse signal to the pull-up switch; the second delay module adjusts the pulse width of the negative pulse signal according to the second position signal output by the detection unit, and provides the adjusted negative pulse signal to the pull-down switch. The frequency and phase detector introduces two delay modules to adjust the pulse width of the pulse signal. When eliminating the mismatch problem of the charge pump, it is only necessary to ensure that the adjusted positive pulse width and negative pulse width match the current source in the charge pump (i.e., I1 × adjusted UP pulse width = I2 × adjusted DN pulse width), and it is not required that I1 × initial UP pulse width = I2 × initial DN pulse width. Therefore, it will not affect the phase detection of the frequency and phase detector, and can eliminate the skew between the reference clock and the feedback clock.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0080] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A frequency and phase detector, characterized in that, The frequency and phase detector includes: two flip-flops, an AND operation unit, a detection unit, and two delay modules; The input of the first D flip-flop is used to connect to the reference clock, and the input of the second D flip-flop is used to connect to the feedback clock. The output of the first D flip-flop is connected to the input of the first delay module and the first input of the AND operation unit; the output of the second D flip-flop is connected to the input of the second delay module and the second input of the AND operation unit; and the output of the AND operation unit is connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop. The control terminals of the first delay module and the second delay module are both connected to the detection unit. The output terminal of the first delay module is connected to the control terminal of the pull-up switch in the charge pump, and the output terminal of the second delay module is connected to the control terminal of the pull-down switch in the charge pump. The first delay module is used to adjust the pulse width of the positive pulse signal according to the first gear signal output by the detection unit, and provide the adjusted positive pulse signal to the pull-up switch; The second delay module is used to adjust the pulse width of the negative pulse signal according to the second gear signal output by the detection unit, and to provide the adjusted negative pulse signal to the pull-down switch; The positive pulse signal is a pulse signal generated by the first D flip-flop sampling the reference clock, and the negative pulse signal is a pulse signal generated by the second D flip-flop sampling the feedback clock.

2. The frequency and phase detector as described in claim 1, characterized in that, The delay module includes a selection unit, an OR operation unit, and N delay units connected in sequence. The nth input terminal of the selection unit is connected to the output terminal of the nth delay unit. The first input terminal of the OR operation unit, the N+1th input terminal of the selection unit, and the input terminal of the first delay unit are used to receive the input signal, which is the positive pulse signal or the negative pulse signal. The output terminal of the selection unit is connected to the second input terminal of the OR operation unit, and the output terminal of the OR operation unit serves as the output terminal of the delay module. The control terminal of the selection unit serves as the control terminal of the delay module and is connected to the detection unit for receiving a gear position signal. The gear position signal is used to adjust the conduction relationship between the input and output terminals of the selection unit.

3. The frequency and phase detector as described in claim 2, characterized in that, The delay unit comprises an even number of inverters connected in sequence.

4. The frequency and phase detector as described in claim 1, characterized in that, The acquisition end of the detection unit is connected to the output end of the charge pump. During the debugging phase of the frequency and phase detector, the input ends of the two triggers are connected to the same debugging clock. The detection unit is used to monitor the output voltage of the charge pump and determine the first and second gear signals corresponding to the frequency and phase detector during normal operation based on the output voltage.

5. The frequency and phase detector as described in claim 4, characterized in that, After entering the debugging phase, the detection unit is used to send a 0th-order gear signal to the first delay module and the second delay module; The detection unit is used to acquire the output voltage of the charge pump for M sampling periods and verify whether the output voltage of the M sampling periods alternates. If no alternation occurs, the gear signal sent to the first delay module and the second delay module is adjusted. After the circuit stabilizes, the output voltage of the charge pump is acquired again for M sampling periods until alternation occurs. The gear signal sent to the first delay module at this time is determined as the first gear signal, and the gear signal sent to the second delay module at this time is determined as the second gear signal.

6. The frequency and phase detector as described in claim 5, characterized in that, When the output voltage does not change alternately over M sampling cycles, the detection unit controls the gear position signal sent to the second delay module to increase by one level when the output voltage in the Mth sampling cycle exceeds the reference voltage; and controls the gear position signal sent to the first delay module to increase by one level when the output voltage in the Mth sampling cycle is lower than the reference voltage.

7. The frequency and phase detector as described in claim 6, characterized in that, The detection unit includes a comparator, a first capacitor, and a digital control unit; One terminal of the first capacitor is grounded, and the other terminal of the first capacitor and the inverting input terminal of the comparator are connected to the output terminal of the charge pump. The non-inverting input terminal of the comparator is connected to a reference voltage. The output terminal of the comparator is connected to the digital control unit. The first set of output terminals of the digital control unit is connected to the first delay module, and the second set of output terminals of the digital control unit is connected to the second delay module.

8. The frequency and phase detector as described in claim 7, characterized in that, After entering the debugging phase, if the output voltage of the charge pump exceeds the reference voltage, the comparator outputs a low level; if the output voltage of the charge pump is lower than the reference voltage, the comparator outputs a high level. The digital control unit is used to determine whether the output voltage changes alternately over M sampling periods based on the output of the comparator over M sampling periods. If the output voltage does not change alternately during M sampling cycles, and the output of the comparator is low during the Mth sampling cycle, the digital control unit controls the gear signal sent to the second delay module to increase by one level. If the output of the comparator is high in the Mth sampling period, the digital control unit controls the gear signal sent to the first delay module to increase by one level.

9. A phase-locked loop, characterized in that, The phase-locked loop includes the frequency and phase detector as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the phase-locked loop as described in claim 9.

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