Efficient back contact battery electrode structure

Abstract

The invention discloses an efficient back contact battery electrode structure, and relates to the technical field of battery preparation, the efficient back contact battery electrode structure comprises a silicon wafer, fine grids and main grids, the main grid closest to a first edge area or a second edge area of the silicon wafer is a first main grid, and the first main grid is a discontinuous main grid structure and is divided into a plurality of discrete Pad point structures; the plurality of Pad point-shaped structures form positive and negative polarity main grid units, and the positive and negative polarity main grid units comprise a plurality of groups of first polarity main grid units and second polarity main grid units which are arranged in a crossed manner and are connected with the corresponding polarity fine grids to form comb-tooth-shaped patterns. According to the invention, the edge main grid is designed into a discrete Pad point-shaped structure, and the comb-tooth-shaped polar main grid units are formed, so that the carrier transmission path is shortened, the carrier recombination loss is reduced, the problem that the edge carrier is difficult to collect in the edge region in the traditional structural layout is solved, and compared with the existing mainstream process, the method does not introduce additional process steps, and is easy to implement. And dependence on insulation paste is eliminated.

Description

Technical Field

[0001] This invention relates to the field of battery manufacturing technology, specifically a high-efficiency back-contact battery electrode structure. Background Technology

[0002] Back contact (BC) cells, as a type of high-efficiency photovoltaic cells, are based on the core concept of integrating all the positive and negative electrodes on the back of the cell, thereby eliminating grid lines from the front of the cell, maximizing the light absorption area, and increasing the short-circuit current density.

[0003] In traditional battery-powered (BC) cells, the back electrodes typically employ an interdigitated arrangement, where positive and negative electrodes (P-regions and N-regions) alternate to form a cross-finger structure. Due to layout constraints at the cell's edge, only one polarity (e.g., P-type) of the main grid line can usually be placed. This main grid line and the area below it physically occupy the edge position, preventing the other polarity (e.g., N-type) region from crossing it to collect photogenerated carriers generated at the edge. This structure results in photogenerated carriers at the very edge of the cell, although some are generated, because these carriers must bypass the main grid blocking area. The transport path changes from normal vertical-lateral recombination transport to pure lateral long-distance transport, significantly increasing the recombination probability during transport. This is equivalent to passively "sacrificing" a portion of the effective power generation area. In subsequent IV testing, this loss directly manifests as a reduction in the short-circuit current (Isc) and affects the fill factor (FF), ultimately preventing the cell's conversion efficiency from reaching its theoretical optimum.

[0004] In the current mainstream design of BC batteries, to eliminate the impact of the "discarded" area, the method of printing insulating adhesive is usually used to isolate grid lines of different polarities and prevent short circuits. For example, the electrode structure, back contact battery and back contact battery assembly described in the patent publication number CN119208406A avoid battery leakage and short circuits by applying insulating adhesive to the intersection of grid lines of different polarities. However, this method is highly dependent on materials and requires an additional insulating adhesive coating process, which increases production costs and complexity. Moreover, this process has high requirements for the width of the insulating adhesive and the accuracy of the printing position. During long-term use, the insulating adhesive may age or fall off, which may affect battery performance.

[0005] Based on this, a highly efficient back-contact battery electrode structure is now provided, which can eliminate the drawbacks of existing technical solutions. Summary of the Invention

[0006] The purpose of this invention is to provide a highly efficient back contact battery electrode structure to solve the problems of difficult edge carrier collection in traditional structures and the complexity of processes caused by the reliance on insulating adhesive in existing mainstream designs.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A high-efficiency back-contact battery electrode structure includes a silicon wafer, multiple fine grids and multiple main grids disposed on the back of the silicon wafer. The multiple main grids, located away from the first and second edge regions of the silicon wafer, form a continuous main grid structure. The continuous main grid structure extends along a second direction of the silicon wafer. The main grid closest to the first or second edge region of the silicon wafer is a first main grid. The first main grid is a discontinuous main grid structure and is divided into several discrete Pad-like structures. Several Pad-like structures form positive and negative polarity main grid units. The second direction of the silicon wafer is the length direction of the battery. The positive and negative polarity main grid units include several sets of first polarity main grid units and second polarity main grid units. The first polarity main grid units and second polarity main grid units are arranged in an interlaced manner and connected to the fine grids of the corresponding polarity to form a comb-like pattern.

[0008] Preferably, the positive and negative polarity main gate unit extends a pseudo main gate along the second direction of the silicon wafer. The linewidth of the pseudo main gate is greater than the linewidth of the fine gate and less than the linewidth of the main gate. The width of the fine gate is 10~200μm and the width of the pseudo main gate is 20~300μm.

[0009] Preferably, the positive and negative polarity main gate units collect photogenerated carriers from the first and second edge regions of the silicon wafer through a comb-like distribution.

[0010] Preferably, the length of a single polarity main gate unit along the first direction of the silicon wafer is 100~3000μm, and the length along the second direction of the silicon wafer is 0.3~30mm, and it is rectangular in shape. The first direction of the silicon wafer is the width direction of the cell.

[0011] Preferably, the main gate unit of a single polarity spans the area of ​​2 to 40 fine gates of the same polarity, and the number of positive and negative polarity main gate units is 2 to 40 groups. When the number of positive and negative polarity main gate units conflicts with the number of fine gates spanned, the number of positive and negative polarity main gate units shall prevail.

[0012] Preferably, on the side near the second main gate, the main gate units of the same polarity are alternately connected with pseudo main gates to form a bow-shaped continuous main gate structure, wherein the second main gate is the continuous main gate closest to the first edge or second edge region of the silicon wafer.

[0013] Preferably, when the positive and negative polarity main gate units are arranged alternately in the order of first polarity and second polarity, there is a pair of adjacent pseudo-main gates of the same polarity in the first polarity main gate unit.

[0014] Preferably, when the positive and negative polarity main gate units are arranged alternately in the order of first polarity and second polarity, there is at least one long thin gate in the second polarity main gate unit, and the length of the long thin gate is longer than the length of the thin gate.

[0015] Preferably, when the positive and negative polarity main gate units are arranged alternately in the order of first polarity and second polarity, the spacing between the first polarity main gate unit and the second polarity main gate unit is small, that is, no fine gate is provided between the first polarity main gate unit and the second polarity main gate unit.

[0016] Preferably, when the spacing between the first polarity main gate unit and the second polarity main gate unit is large, i.e., a fine gate is provided, the pseudo main gate is led out from the upper or lower side of the corresponding main gate unit, extends along the second direction, and surrounds the middle of the main gate unit of the next polarity.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention presents a highly efficient back-contact battery electrode structure. By designing the edge main grid as a discontinuous pad-like structure and forming a comb-like cross-arranged polar main grid unit, and introducing a pseudo-main grid and a long, thin grid structure, the transport path of charge carriers from the edge region to the main grid is shortened, reducing recombination losses during transport. This solves the problem in traditional layouts where the main grid lines occupy edge positions, making it difficult to collect edge charge carriers in the other polar region. This improves the charge carrier collection efficiency in the battery edge region, ultimately increasing the battery's conversion efficiency. Compared with existing mainstream processes, this invention does not introduce additional complex process steps, is compatible with existing mainstream back-contact battery manufacturing processes, and eliminates the dependence on insulating adhesive in existing mainstream solutions, resulting in higher process stability and longer battery life. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of the back contact battery electrode of the present invention.

[0019] Figure 2 For the present invention Figure 1 A magnified view of a portion of the image.

[0020] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0021] Figure 4 This is a schematic diagram of the main gate unit in Embodiment 2 of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0023] Figure reference numerals: 1. Fine gate; 2. Main gate; 3. Positive and negative polarity main gate unit; 31. First polarity main gate unit; 32. Second polarity main gate unit; 33. Pseudo-main gate; 34. Same polarity pseudo-main gate; 35. Long fine gate. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0025] Example 1 In this embodiment, as Figure 1 and Figure 2 As shown, a high-efficiency back-contact battery electrode structure includes a silicon wafer, multiple fine grids 1 and multiple main grids 2 disposed on the back of the silicon wafer. The fine grids 1 are distributed in a comb-like cross pattern near the edge of the silicon wafer. The multiple main grids 2, located away from the first and second edges of the silicon wafer, form a continuous main grid structure that extends along a second direction of the silicon wafer. The main grid 2 closest to the first or second edge of the silicon wafer is the first main grid, which is a discontinuous main grid structure divided into several discrete pad-like structures. Several pad-shaped structures form positive and negative polarity main gate units 3. The positive and negative polarity main gate units 3 collect photogenerated carriers from the first edge and second edge regions of the silicon wafer through a comb-like distribution. The second direction of the silicon wafer is the length direction of the cell. The positive and negative polarity main gate units 3 include several groups of first polarity main gate units 31 and second polarity main gate units 32. The first polarity main gate units 31 and second polarity main gate units 32 have different polarities, and the first polarity main gate units 31 and second polarity main gate units 32 are arranged in a cross pattern and connected to the corresponding polarity fine gate 1 to form a comb-like pattern. Among them, such as Figure 1 and Figure 2 As shown, a pseudo-gate 33 extends from the positive and negative polarity main gate unit 3 along the second direction of the silicon wafer. The pseudo-gate 33 specifically refers to the conductive gate line extending from the positive and negative polarity main gate unit 3 along the second direction of the silicon wafer. Its function is to collect and gather the current from the fine gate 1, but it does not directly serve as the main current channel connecting the battery to the external circuit. The linewidth of the pseudo-gate 33 is between that of the fine gate 1 and the main gate 2, which optimizes the current collection path and reduces the series resistance. The linewidth of the pseudo-gate 33 is greater than that of the fine gate 1 and less than that of the main gate 2. The width of the fine gate 1 is 10. ~200μm, the width of the pseudo main gate 33 is 20~300μm. In this embodiment, the width of the fine gate 1 is preferably 20~50μm. On the side close to the second main gate, the main gate unit of the same polarity and the pseudo main gate 33 are alternately connected to form a bow-shaped continuous main gate structure. The second main gate is a continuous main gate closest to the first edge or the second edge region of the silicon wafer. The second main gate is a continuous main gate structure, which is distinguished from the discontinuous first main gate close to the edge. The second main gate and the bow-shaped pseudo main gate 33 together constitute the main path for current to be led out to the outside. Among them, such as Figure 1 and Figure 2As shown, the length of a single polarity main gate unit along the first direction of the silicon wafer is 100~3000μm, and the length along the second direction of the silicon wafer is 0.3~30mm, and it is rectangular in shape. In this embodiment, the length along the first direction of the silicon wafer is preferably 300~1000μm, and the length along the second direction of the silicon wafer is preferably 3~10mm. The first direction of the silicon wafer is the width direction of the cell. Among them, such as Figure 1 and Figure 2 As shown, a single polarity main gate unit spans the area of ​​2 to 40 fine gates 1 of the same polarity. The number of positive and negative polarity main gate units 3 is 2 to 40. When the number of positive and negative polarity main gate units conflicts with the number of fine gates spanned, the number of positive and negative polarity main gate units shall prevail. In this embodiment, the number of positive and negative polarity main gate units 3 is preferably 4 to 12 pairs. Specifically, in this embodiment, every two main gate units of different polarities form a group, and the range of a group of main gate units is as follows: Figure 2 As shown, a group of main gate units form a comb-like distribution that is coupled to each other, which is used to collect the carriers in the "discard region" that were originally blocked by the main gate. When using the back contact battery electrode structure in this invention, the probes or PCB modules used for subsequent IV tests are all arranged with contacts of different polarities in a cross pattern.

[0026] Example 2 The difference from Example 1 is that, as in Example 1, Figure 3 and Figure 4 As shown, Figure 3 for Figure 1 In the dashed section, there is an optimized schematic diagram of the side near the first edge region of the silicon wafer. The side near the second edge region of the silicon wafer retains the features of Embodiment 1, that is, the right side remains unchanged (not shown in the figure). When the positive and negative polarity main gate units 3 are arranged alternately in the order of first polarity and second polarity, there is a pair of adjacent pseudo main gates 34 of the same polarity in the first polarity main gate unit 31. The pseudo main gates 34 of the same polarity cooperate with the long thin gate 35 to form a symmetrical current collection network in the local area. There is at least one long thin gate 35 in the second polarity main gate unit 32. The length of the long thin gate 35 is longer than the length of the thin gate 1. This embodiment is a better arrangement for the main gate units that are not on the top and bottom edges. That is, the optimized arrangement in this embodiment can be used for the main gate units in the middle. Among them, such as Figure 3 and Figure 4 As shown, when the positive and negative polarity main gate units 3 are arranged alternately in the order of first polarity and second polarity, the spacing between the first polarity main gate unit 31 and the second polarity main gate unit 32 is small, that is, no fine gate 1 is provided between the first polarity main gate unit 31 and the second polarity main gate unit 32. Specifically, this embodiment achieves bidirectional transport of charge carriers to the nearest main grid unit through a symmetrical design. This symmetrical design halves the distance for the pseudo-main grid to collect charge carriers, resulting in a more aesthetically pleasing electrode pattern and improved printing accuracy of automated screen printing. The core of the symmetrical design lies in discretizing the continuous main grid in the edge region into alternating positive and negative polarity main grid units 3, and cooperating with the comb-shaped connected fine grid 1 and the same polarity pseudo-main grid 34. This constructs multiple close-range, symmetrical collection nodes for photogenerated charge carriers in the edge region of the battery, so that charge carriers generated at any position on the edge can be collected by their nearest positive or negative polarity main grid unit, achieving a "bidirectional shortening" of the collection path. This is equivalent to shortening the average transport distance of charge carriers by nearly half, significantly reducing the recombination probability during the transport process, thereby efficiently recovering the traditional "discard area" and ultimately improving the short-circuit current and conversion efficiency of the battery. Specifically, both Embodiment 1 and Embodiment 2 involve a small distance between the first polar main gate unit 31 and the second polar main gate unit 32, meaning there is no fine gate structure between them. Figures 1-4 The rectangular shape in the grid is the main grid unit, and different colors represent different polarities.

[0027] Example 3 The difference from Examples 1 and 2 is that, as shown in Examples 2, ... Figure 5 As shown, Figure 5 for Figure 1 The dashed section includes the portion of the second main gate. The left side of the second main gate is rearranged. When the distance between the first polarity main gate unit 31 and the second polarity main gate unit 32 is large, i.e., a fine gate 1 is provided, the lead-out method of the pseudo main gate 33 should be appropriately modified. The pseudo main gate 33 is led out from the upper or lower side of the corresponding main gate unit, extends along the second direction and wraps around to the middle of the next polarity main gate unit, so as to collect the carriers in the "discard region" blocked by the original main gate. At the same time, on the side close to the second main gate, the same polarity main gate unit and the pseudo main gate 33 are alternately connected to maintain the bow-shaped continuous main gate structure. The remaining features are consistent with those of Embodiment 1.

[0028] In summary, this invention solves the problem in traditional BC battery back-side interdigitated electrode layouts where the main grid lines occupy edge positions, making it difficult to collect edge carriers in the other polarity region. This is achieved through an electrode design of "discrete main grid unit - comb-shaped connection - symmetrical collection". At the same time, it eliminates the reliance on insulating adhesive in existing mainstream solutions, simplifies the production process, saves material losses, thereby reducing battery manufacturing costs and improving battery efficiency and stability.

[0029] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high efficiency back contact cell electrode structure, characterized by, The application relates to a silicon wafer, a plurality of fine grids (1) and a plurality of main grids (2) arranged on the back of the silicon wafer, a plurality of the main grids (2) away from the first edge and the second edge region of the silicon wafer are continuous main grid structures, the continuous main grid structures extend along the second direction of the silicon wafer, the nearest main grid (2) to the first edge or the second edge region of the silicon wafer is a first main grid, the first main grid is a discontinuous main grid structure and is divided into a plurality of discrete pad point structures, the plurality of pad point structures form positive and negative polarity main grid units (3), the second direction of the silicon wafer is the length direction of the battery, the positive and negative polarity main grid units (3) comprise a plurality of groups of first polarity main grid units (31) and second polarity main grid units (32), the first polarity main grid units (31) and the second polarity main grid units (32) are arranged in an interlaced mode and are connected with corresponding polarity fine grids (1) to form a comb-shaped pattern.

2. The high efficiency back contact cell electrode structure of claim 1, wherein, The positive and negative polarity main grid units (3) extend out a pseudo main grid (33) along the second direction of the silicon wafer, the line width of the pseudo main grid (33) is greater than the line width of the fine grid (1) and smaller than the line width of the main grid (2), the width of the fine grid (1) is 10-200 mu m, and the width of the pseudo main grid (33) is 20-300 mu m.

3. The high efficiency back contact cell electrode structure of claim 1, wherein, The positive and negative polarity main grid units (3) collect photo-generated carriers in the first edge and the second edge region of the silicon wafer through the comb-shaped distribution.

4. The high efficiency back contact cell electrode structure of claim 1, wherein, The length of the main grid unit of a single polarity along the first direction of the silicon wafer is 100-3000 mu m, the length along the second direction of the silicon wafer is 0.3-30 mm, and the shape is rectangular, and the first direction of the silicon wafer is the width direction of the battery.

5. The high efficiency back contact cell electrode structure of claim 4, wherein, The main grid unit of a single polarity spans the regions of 2-40 fine grids (1) of the same polarity, and the number of the positive and negative polarity main grid units is 2-40 groups, and when the number of the positive and negative polarity main grid units conflicts with the number of the fine grids to be spanned, the number of the positive and negative polarity main grid units is used as the criterion.

6. The high efficiency back contact cell electrode structure of claim 4, wherein, On the side close to the second main grid, the main grid units of the same polarity are alternately connected with the pseudo main grid (33) to form an arch-shaped continuous main grid structure, and the second main grid is the nearest continuous main grid to the first edge or the second edge region of the silicon wafer.

7. The high efficiency back contact cell electrode structure of claim 1, wherein, When the positive and negative polarity main grid units (3) are arranged in an alternating cycle of the first polarity and the second polarity, a pair of adjacent pseudo main grids (34) of the same polarity exist in the first polarity main grid unit (31).

8. The high efficiency back contact cell electrode structure of claim 7, wherein, When the positive and negative polarity main grid units (3) are arranged in an alternating cycle of the first polarity and the second polarity, at least one long fine grid (35) exists in the second polarity main grid unit (32), and the length of the long fine grid (35) is longer than that of the fine grid (1).

9. The high efficiency back contact cell electrode structure of claim 7, wherein, When the positive and negative polarity main grid units (3) are arranged in an alternating cycle of the first polarity and the second polarity, the spacing between the first polarity main grid unit (31) and the second polarity main grid unit (32) is small, that is, no fine grid (1) is arranged between the first polarity main grid unit (31) and the second polarity main grid unit (32).

10. The high efficiency back contact cell electrode structure of claim 2, wherein, When the distance between the first polarity main grid unit (31) and the second polarity main grid unit (32) is large, i.e. a fine grid (1) is provided, the pseudo main grid (33) is led out from the upper side or the lower side of the corresponding main grid unit, elongated in the second direction and encircles to the middle part of the main grid unit of the next polarity.

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