Wafer thinning method

Abstract

The invention discloses a wafer thinning method, which comprises the steps of presetting a wafer thinning target thickness, manufacturing a hole with the depth consistent with the target thickness in a surface, deviating from a to-be-thinned surface, of a wafer, and filling a detection material different from a wafer material; temporarily bonding the wafer to a glass or sapphire carrier through an organic material, and carrying out mechanical pre-thinning; putting the wafer into inductively coupled plasma etching equipment of an integrated mass spectrometer, carrying out non-contact etching, and when the mass spectrometer detects characteristic ion signals of a detection material, automatically stopping etching; and finally, removing the temporary bonding structure to finish thinning. According to the method, the target thickness is accurately calibrated through the hole depth, the non-contact processing characteristics of mass spectrometer real-time end point detection and plasma etching are combined, the thinning thickness tolerance is smaller than or equal to + / -1 [mu] m, the fragment rate is smaller than or equal to 0.5%, the thickness uniformity is remarkably improved, the technology is compatible with existing semiconductor equipment, the method is suitable for high-precision requirement scenes such as 3D packaging, and the method is suitable for large-scale popularization and application. The method is especially suitable for thinning processing of LED wafers and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer thinning method, which is especially suitable for 3D packaging scenarios with extremely high thickness precision requirements, can realize precise control of wafer thinning thickness, and reduce the risk of wafer breakage in the wafer thinning process. BACKGROUND

[0002] With the development of semiconductor technology towards high density and high integration, 3D packaging technology has become a key field of core competitiveness of semiconductor enterprises; 3D packaging realizes the integration of chip functions by stacking multiple wafers, and puts forward strict requirements for the thickness of the thinned wafer; currently, 15 μm thin wafers can be processed in the industry, but further reduction in thickness will result in a sharp increase in the breakage rate due to insufficient wafer structure strength; at the same time, the existing thinning process still cannot meet the precision requirements of 3D packaging for "micron-level thickness tolerance".

[0003] The existing wafer thinning process mainly includes three types: mechanical grinding, chemical etching and chemical mechanical planarization, and related technical solutions have been disclosed in many patents, as follows: 1. Patent "Wafer Thinning Method and Wafer" (Application No. 202411012632.X): By etching a hole with a thickness consistent with the target thickness on the non-thinning surface of the wafer, filling wear-resistant material, and combining temporary bonding and grinding thinning to achieve thickness control. However, its core relies on the final precision of mechanical grinding, and the uneven stress on the wafer during mechanical grinding can easily result in a thickness tolerance of ±5 μm or more, which is difficult to meet the high precision requirements.

[0004] 2. Patent "Grinding Disc Inclination Self-adjusting Method, Device and Wafer Thinning Equipment" (Application No. 202510407524.0): Adjust the inclination of the grinding disc through a surface shape prediction model to improve grinding uniformity; however, this method still belongs to the category of "mechanical processing precision optimization" and cannot fundamentally solve the inherent "physical contact type processing tolerance" problem of mechanical grinding, and for 15-30 μm thin wafers, the grinding pressure is still prone to cause wafer breakage.

[0005] 3. Patent "Method for Precise Control of Wafer Thinning Thickness" (Grant Announcement No. CN103035489B): Etch a groove in the silicon wafer and fill the material to determine the thinning end point, but the physical properties of the filler and the wafer substrate are not significantly different, and the thinning end point identification relies on manual or indirect measurement, which is prone to cause a thickness deviation of ±3 μm or more due to "blurred filler-substrate boundary".

[0006] 4. Patent "wafer thinning process" (authorized announcement number CN109742017B): based on "mass-thickness correlation" calculation chemical corrosion time, through multiple corrosion to realize thickness control, but chemical corrosion exists "anisotropic corrosion" problem, the difference of corrosion rate of wafer edge and center is easy to lead to poor thickness uniformity, and the small deviation of corrosion time will directly magnify the thickness error.

[0007] In summary, the core defects of the prior art are: the thinning end point control depends on mechanical precision or indirect parameters (mass, time), lacks a "direct, real-time end point recognition mechanism", resulting in low thinning precision; at the same time, the physical pressure of mechanical grinding and the uniformity of chemical corrosion are insufficient, which further aggravates the risk of broken thin wafers.

[0008] In order to solve the above problems, it is urgent to provide a wafer thinning method which can realize "precise end point control + low damage processing". SUMMARY

[0009] The purpose of the present application is to solve the problems of low wafer thinning precision (thickness tolerance ±3μm or more) and high broken wafer rate (usually >3%) in the prior art, and to provide a wafer thinning method which combines hole depth calibration, real-time detection by mass spectrometer and plasma etching to realize high-precision low-damage processing with a thinning thickness tolerance of ≤±1μm and a broken wafer rate of ≤0.5%.

[0010] To solve the above technical problems, the technical solution adopted by the present application is: A wafer thinning method, comprising the following steps: S1, providing a wafer to be thinned, and presetting a target thickness of the wafer to be thinned; S2, making a hole on the side of the wafer away from the surface to be thinned, the depth of the hole being consistent with the target thickness; S3, filling a detection material in the hole, the detection material being different from the composition material of the wafer; S4, fixing the wafer on a carrier disc by temporary bonding; S5, mechanically pre-thinning the wafer, the pre-thinning wafer thickness being greater than the target thickness and leaving a thickness difference; S6, placing the pre-thinned wafer into a plasma etching device equipped with a mass spectrometer for plasma etching thinning; S7, when the mass spectrometer detects the detection material, the plasma etching device automatically stops etching; S8, removing the carrier disc and the bonding material of temporary bonding to complete wafer thinning.

[0011] Preferably, in step S2, the number of holes is 2-5, and is distributed in the upper, middle, lower, left and right regions of the wafer.

[0012] Preferably, in step S2, the shape of the hole is circular, square or diamond, and the size is 10-100 μm.

[0013] Preferably, the size of the hole is 30-50 μm.

[0014] Preferably, in step S3, the detection material is Ta, Ni or W metal, and is filled in the hole by using photolithography, deposition and stripping process.

[0015] Preferably, in step S4, the temporarily bonded bonding material is BCB or PI organic material, and the carrier disc is a glass or sapphire transparent substrate.

[0016] Preferably, in step S5, the thickness of the wafer after mechanical pre-thinning is 30-40 μm.

[0017] Preferably, in step S6, the plasma etching equipment is an inductively coupled plasma etching equipment.

[0018] Preferably, the inductively coupled plasma etching equipment has a real-time data interaction function with the mass spectrometer, and the etching rate difference of the wafer to be thinned is controlled within ±3%.

[0019] Preferably, the wafer to be thinned is an LED wafer, which sequentially comprises a sapphire substrate, an N-GaN layer, an MQW layer, a P-GaN layer, an ITO layer, an insulating layer and an electrode layer from bottom to top, wherein the object to be thinned is the sapphire substrate.

[0020] By using the above technical solutions, the present application has the following beneficial effects compared with the prior art: 1. The thinning precision is significantly improved: the existing mechanical grinding relies on the precision of the grinding disc, and the thickness tolerance is ±3-5 μm; by using "hole depth calibration (tolerance ±0.8 μm) + mass spectrometer real-time detection (response deviation ±0.2 μm)", the thickness tolerance is controlled within ±1 μm, which meets the demand of micron-level precision for 3D packaging.

[0021] 2. The fragment rate is greatly reduced: in the prior art, thin wafers (≤30 μm) are easily broken due to mechanical grinding pressure, and the fragment rate is >3%; the mechanical pre-thinning of the present application is only processed to 30-40 μm (high structural strength), and the fine thinning uses non-contact ICP etching without mechanical pressure, and the fragment rate is ≤0.5%.

[0022] 3. Strong process compatibility: the "lithography-etching-bonding-ICP etching" adopted by the application are mature processes in the semiconductor industry, without the need for additional special equipment (only need to integrate mass spectrometer on the existing ICP equipment), which is convenient for industrialization. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to make the technical personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0024] Figure 1 Flow chart of a wafer thinning method of the present application; Figure 2 Schematic diagram of the wafer structure of step S1 in embodiment one of the present application; Figure 3 Schematic diagram of the wafer structure of step S2 in embodiment one of the present application; Figure 4 Schematic diagram of the wafer structure of step S3 in embodiment one of the present application; Figure 5 Schematic diagram of the wafer structure of step S4 in embodiment one of the present application; Figure 6 Schematic diagram of the wafer structure of step S5 in embodiment one of the present application; Figure 7 Schematic diagram of the wafer structure of step S6 in embodiment one of the present application; Figure 8 Schematic diagram of the wafer structure of step S8 in embodiment one of the present application; Wherein, 1, sapphire substrate; 2, N-GaN layer; 3, MQW layer; 4, P-GaN layer; 5, ITO layer; 6, insulating layer; 7, electrode layer; 8, detection material; 9, bonding material; 10, carrier disc. DETAILED DESCRIPTION

[0025] In order to make the technical personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be combined. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0028] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned partial terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0029] In addition, the terms "mount", "set", "provided with", "connected", "connected", "sleeved" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0030] It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0031] Embodiment one Please refer to Figures 1-8 The present application provides a wafer thinning method, which is realized by the following steps, and the technical details and principles of each step are as follows: S1, wafer preparation and target thickness preset: provide the wafer to be thinned (such as LED wafer, silicon-based wafer, etc.), preset the target thickness of thinning according to the subsequent packaging requirements (usually 10-50 μm); take the LED wafer as an example, its initial structure includes sapphire substrate 1 (thickness 630 μm), N-GaN layer 2, MQW layer 3, P-GaN layer 4, ITO layer 5, insulating layer 6 and electrode layer 7 from bottom to top, the total thickness is 640 μm, and the preset target thickness of the sapphire substrate 1 is 20 μm.

[0032] S2, hole making (target thickness calibration): using the mature "photoetching-etching-stripping" process in the semiconductor industry, holes are made on the side of the wafer away from the side to be thinned (such as the electrode layer 7 side of the LED wafer, not the sapphire substrate 1 side):

[0033] The hole depth is strictly consistent with the preset target thickness (such as 20 μm), and the hole depth tolerance is ≤±0.8 μm through the photoresist pattern precision (±0.5 μm) and the plasma etching depth control (±0.3 μm), which provides accurate "physical calibration" for the subsequent thinning endpoint; The number of holes is 2-5 (preferably 5), which are evenly distributed in the upper, middle, lower, left and right areas of the wafer (such as the center and four symmetrical points 50 mm away from the edge of a 300 mm diameter wafer), avoiding the endpoint misjudgment caused by local processing deviation of a single hole; The hole shape can be selected as circular, square or diamond, and the size is 10-100 μm (preferably 20-70 μm, more preferably 30-50 μm) - too small size is easy to cause insufficient filling of the subsequent detection material, and mass spectrometer is difficult to detect; too large size may damage the wafer surface circuit structure, and the size range of 30-50 μm can balance the detection sensitivity and wafer structure integrity.

[0034] S3, detection material 8 filling: using the "photoetching-deposition-stripping" process to fill the detection material 8 in the hole, the detection material 8 needs to meet two core conditions: ① completely different from the material of the wafer (such as containing Al, O, Ga, N elements, selecting Ta, Ni or W metal), ensuring that the mass spectrometer can accurately identify; ② having stable physical and chemical properties, not reacting with the wafer material; taking Ta metal as an example, its atomic weight (180.95) is significantly different from the main elements in the wafer (Al: 27, O: 16, Ga: 70), and the mass spectrometer can quickly identify through the characteristic ion peak (such as

[0035] S4, temporary bonding fixation: the wafer is fixed on the carrier disc 10 (temporary substrate) through temporary bonding technology, the bonding material 9 is selected from BCB (benzocyclobutene) or PI (polyimide) organic material, and the carrier disc 10 is selected from transparent material such as glass or sapphire:​ The bonding process needs to ensure that there is no air bubble between the wafer and the carrier 10 (air bubble rate ≤ 0.1%), so as to avoid wafer breakage caused by uneven local stress during subsequent mechanical pre-thinning; The transparent carrier 10 facilitates energy transmission during subsequent laser dissociation (step S8), while not affecting the observation of the wafer surface structure.

[0036] S5, mechanical pre-thinning (rough thinning): a diamond grinding wheel grinding equipment is used to mechanically pre-thin the wafer surface to be thinned (such as the sapphire substrate 1 side of the LED wafer), so as to reduce the thickness from the initial value (such as 630 μm) to 30-40 μm - the thickness is still greater than the target thickness (20 μm), leaving a "fine thinning allowance" of 10-20 μm: The mechanical pre-thinning is only used to quickly remove most of the excess material, so as to avoid low efficiency caused by excessive processing amount during subsequent plasma etching; The pre-thinning thickness is controlled at 30-40 μm, which not only ensures that the wafer has sufficient structural strength (low risk of fragmentation), but also reserves a reasonable allowance for subsequent precise etching.

[0037] S6, plasma etching thinning (fine thinning): the pre-thinned wafer is placed in an inductively coupled plasma (ICP) etching equipment configured with a mass spectrometer, and physical etching thinning is performed: The ICP etching is a "non-contact processing", which realizes material removal by high-energy ion bombardment on the wafer surface, and there is no mechanical pressure, which can significantly reduce the risk of wafer fragmentation; The etching gas is selected according to the wafer material (such as Mixed gas), and the etching rate is controlled at 1-5 μm / min, so as to ensure etching uniformity (rate difference ≤ ± 3%).

[0038] S7, mass spectrometer linkage end control: during the ICP etching process, the mass spectrometer collects the gas phase ion signals generated by etching in real time: When the etching does not reach the hole position, the mass spectrometer only detects the characteristic ions of the wafer substrate (such as , of the sapphire substrate 1); When the etching depth reaches the hole depth (i.e. the target thickness), the detection material 8 (such as Ta) in the hole is stripped by ion bombardment, and the mass spectrometer detects the characteristic ion peak (mass-to-charge ratio 181) of , and immediately sends a stop signal to the ICP etching equipment to realize automatic shutdown of etching - the detection and shutdown response time is ≤ 0.5 s, the etching depth deviation is ≤ ± 0.2 μm, and finally the thinning thickness tolerance is ≤ ± 1 μm.

[0039] S8, temporary bonding removal: irradiate the transparent carrier 10 side with a laser dissociation technique (such as ultraviolet laser with wavelength 355 nm) to cause thermal decomposition of the BCB or PI bonding material 9, and then remove the carrier 10 and the residual bonding material 9 by mechanical peeling or organic solvent cleaning to obtain a thinned wafer (such as a sapphire substrate 1 LED wafer with a thickness of 20 μm).

[0040] Example Two The present application provides a wafer thinning method, specifically for LED wafer thinning, and the technical details and principles of each step are as follows: 1. Experimental materials and equipment Wafer to be thinned: LED wafer (diameter 150 mm), structure: "sapphire substrate 1 (630 μm) - N-GaN layer 2 (5 μm) - MQW layer 3 (0.5 μm) - P-GaN layer 4 (2 μm) - ITO layer 5 (0.1 μm) - insulating layer 6 (0.5 μm) - Au / Pt / Cr electrode layer 7 (0.3 μm)", total thickness 640 μm; Detection material 8: Ta metal target (purity 99.99%); Bonding material 9: BCB glue (model Cyclotene 3022-46); Carrier 10: sapphire substrate 1 (thickness 500 μm, light transmittance > 90%); Equipment: photoresist coater (Tokyo Electron ACT 8), ICP etcher (can integrate mass spectrometer, etching rate difference ± 2%), diamond grinder (DISCO DFG-850), laser dissociation equipment (Coherent HyperRapid NX). 2. Implementation steps

[0041] S1, set the target thickness of the sapphire substrate 1 to be thinned to 20 μm; S2, make 5 circular holes on the electrode layer 7 side of the LED wafer: photoresist pattern size 40 μm, use ICP etching (gas, etching rate 2 μm / min, etching time 10 min), hole depth 20 μm, distributed at the center of the wafer and (x=100 mm, y=0), (x=0, y=100 mm), (x=-100 mm, y=0), (x=0, y=-100 mm) positions; S3, deposit Ta metal (thickness 20 μm) by magnetron sputtering, and then remove the Ta metal outside the holes by photoresist-removing process, leaving only the Ta filling layer inside the holes; S4, use a diamond grinder to grind the sapphire substrate 1 to a thickness of 20 μm, and then remove the sapphire substrate 1 and the residual electrode layer 7 by mechanical peeling or organic solvent cleaning to obtain a thinned wafer (such as a sapphire substrate 1 LED wafer with a thickness of 20 μm); S5, use a laser dissociation technique (such as ultraviolet laser with wavelength 355 nm) to irradiate the transparent carrier 10 side to cause thermal decomposition of the BCB or PI bonding material 9, and then remove the carrier 10 and the residual bonding material 9 by mechanical peeling or organic solvent cleaning to obtain a thinned wafer (such as a sapphire substrate 1 LED wafer with a thickness of 20 μm); S6, use a laser dissociation technique (such as ultraviolet laser with wavelength 355 nm) to irradiate the transparent carrier 10 side to cause thermal decomposition of the BCB or PI bonding material 9, and then remove the carrier 10 and the residual bonding material 9 by mechanical peeling or organic solvent cleaning to obtain a thinned wafer (such as a sapphire substrate 1 LED wafer with a thickness of 20 μm).S4. Bond the electrode layer 7 side of the wafer to the sapphire carrier disk 10 with BCB adhesive at a bonding temperature of 150℃ and a pressure of 0.5MPa for 30 minutes to ensure no air bubbles. S5. Use a diamond polishing machine to perform mechanical pre-thinning on side 1 of the sapphire substrate at a polishing rate of 50 μm / min, thinning to a thickness of 35 μm (leaving a 15 μm fine thinning allowance). S6, Place the wafer into the ICP etching machine of the integrated mass spectrometer, and introduce... / Ar mixed gas (volume ratio 1:3), etching power 800W, etching rate 3μm / min; S7, during the etching process, the mass spectrometer monitors the mass-to-charge ratio in real time at 181 ( The ion signal, when the signal intensity reaches a threshold (≥ When the counts / s) are reached, the ICP etching machine automatically stops. At this time, the etching time is about 5 minutes, and the thickness of the sapphire substrate 1 is reduced to 20μm. S8, using a 355nm ultraviolet laser (energy density 10) The sapphire substrate was irradiated on all 10 sides to release the BCB adhesive. The remaining adhesive layer was then removed by cleaning with isopropanol to obtain the thinned LED wafer.

[0042] 3. Test Results Thickness accuracy: Measured at 20 randomly selected points on the wafer, thickness range 19.2-20.8μm, tolerance ±0.8μm; Fragmentation rate: Of 100 wafers processed continuously, only 1 wafer broke during mechanical pre-thinning, with a fragmentation rate of 1% (close to the target of 0.5%, the deviation was due to the initial grinding parameter adjustment). Wafer integrity: The surface is free of scratches and chipping, and the electrode layer 7 and insulating layer 6 are structurally intact, without any damage caused by etching.

[0043] Comparative Example 1 (Existing mechanical grinding method, based on patent CN103035489B) 1. Experimental Design Using the method described in patent CN103035489B: etch trenches (20 μm deep) in the N-GaN layer 2 of the LED wafer, and fill them with... Subsequently, the sapphire substrate 1 was mechanically ground down to the bottom of the trench to remove... .

[0044] 2. Test Results Thickness accuracy: Thickness range of 17-23μm at 20 measurement points, tolerance ±3μm; Fragmentation rate: Out of 100 wafers processed, 6 were broken, resulting in a fragmentation rate of 6%. Defect: 30% of the wafer surfaces have grinding scratches, which affect the bonding quality of subsequent packaging.

[0045] Comparative analysis of examples and comparative examples:

[0046] From the above comparison, the present application is significantly better than the existing mechanical grinding method by the combination scheme of "hole calibration + mass spectrometry detection + ICP etching", which solves the core problem of precision and fragmentation rate.

[0047] In addition, it should be noted that: 1. The selection flexibility of the detection material 8 is that, in addition to Ta, Ni (mass-to-charge ratio 58) and W (mass-to-charge ratio 184) can also be used as the detection material 8, as long as the characteristic ion peak does not overlap with the wafer material; for example, a silicon-based wafer (containing Si: mass-to-charge ratio 28) can use Ni, and the mass spectrometer recognizes the end point through the signal of mass-to-charge ratio 58.

[0048] 2. Parameter adaptation of plasma etching equipment For wafers of different materials, the ICP etching parameters need to be adjusted: for example, a silicon-based wafer can use a mixed gas of / Ar, and the etching rate is 5 μm / min; a silicon carbide wafer can use a mixed gas of / Ar, and the etching rate is 2 μm / min, and the difference in etching rate should be ≤±3% to avoid uneven thickness caused by local etching too fast.

[0049] 3. Alternative scheme of temporary bonding material 9 In addition to BCB glue, PI glue (model Kapton HN) can also be used for temporary bonding, and its high temperature resistance (long-term use temperature 260℃) is more suitable for wafers that need high temperature etching (such as silicon carbide wafers), but the energy density of laser dissociation needs to be adjusted accordingly (such as 12 ).

[0050] Finally, it should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacements for some of the technical features, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for thinning a wafer, characterized in that, Includes the following steps: S1, providing a wafer to be thinned, and presetting the target thickness for thinning the wafer; S2, a hole is made on the side of the wafer away from the surface to be thinned, and the depth of the hole is the same as the target thickness; S3, fill the hole with a detection material, the detection material being different from the constituent material of the wafer; S4, the wafer is fixed to the carrier disk by temporary bonding; S5, perform mechanical pre-thinning on the wafer, and after pre-thinning, the wafer thickness is greater than the target thickness and a thickness difference is left; S6. Place the pre-thinned wafer into a plasma etching apparatus equipped with a mass spectrometer for plasma etching and thinning. S7, When the mass spectrometer detects the detection material, the plasma etching equipment automatically stops etching; S8 removes the temporary bonding carrier and bonding material, completing wafer thinning.

2. The wafer thinning method according to claim 1, characterized in that, In step S2, the number of holes is 2-5, and they are distributed in the upper, middle, lower, left and right regions of the wafer.

3. The wafer thinning method according to claim 1 or 2, characterized in that, In step S2, the shape of the hole is circular, square, or rhomboid, and the size is 10-100μm.

4. The wafer thinning method according to claim 3, characterized in that, The size of the hole is 30-50 μm.

5. The wafer thinning method according to claim 1, characterized in that, In step S3, the detection material is Ta, Ni, or W metal, which is filled into the holes using photolithography, deposition, and resist removal processes.

6. The wafer thinning method according to claim 1, characterized in that, In step S4, the bonding material for the temporary bonding is BCB or PI organic material, and the carrier disk is a glass or sapphire transparent substrate.

7. The wafer thinning method according to claim 1, characterized in that, In step S5, the thickness of the wafer after mechanical pre-thinning is 30-40 μm.

8. The wafer thinning method according to claim 1, characterized in that, In step S6, the plasma etching equipment is an inductively coupled plasma etching equipment.

9. The wafer thinning method according to claim 8, characterized in that, The inductively coupled plasma etching equipment has a real-time data interaction function with the mass spectrometer, and the etching rate difference of the wafer to be thinned is controlled within ±3%.

10. The wafer thinning method according to claim 1, characterized in that, The wafer to be thinned is an LED wafer, which, from bottom to top, includes a sapphire substrate, an N-GaN layer, an MQW layer, a P-GaN layer, an ITO layer, an insulating layer, and an electrode layer, wherein the thinning target is the sapphire substrate.

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