Central air conditioning system

Abstract

The embodiment of the invention provides a central air conditioning system, and relates to the technical field of air conditioners. According to the central air-conditioning system, real-time long-distance signal transmission can be achieved by improving the repeater, and signal transmission can be stopped in time when signal conflicts occur. The central air conditioning system comprises a first bus, a second bus and a repeater. The repeater comprises a main control chip, a first control circuit, a second control circuit, a first switching circuit and a second switching circuit, the signal end of the first control circuit is electrically connected with the first bus; the signal end of the second control circuit is electrically connected with the second bus; the first switch circuit is electrically connected between the first output end of the first control circuit and the first input end of the second control circuit; the second switching circuit is electrically connected between the first output end of the second control circuit and the first input end of the first control circuit; the first control circuit and the second control circuit are configured to convert the differential signal and the single-ended signal.

Description

Technical Field

[0001] This invention relates to the field of air conditioning technology, and more particularly to a central air conditioning system. Background Technology

[0002] With the development of science and technology, the application of electrical appliances is becoming more and more common, and air conditioning has become an integral part of the daily lives of more and more people.

[0003] Currently, central air conditioning systems generally use the Homebus communication protocol for communication, which enables convenient interaction and control between devices.

[0004] However, due to the limitations of HomeBus' hardware design and communication mechanism, the communication bus length is generally no more than 1,000 meters. This cannot meet the long-distance communication requirements in large public building projects, and often requires the deployment of large-scale central air conditioning systems in the form of split buses, which has an adverse impact on system integration and deployment costs. Summary of the Invention

[0005] This invention provides a central air conditioning system that can transmit signals over long distances in real time by improving the repeater, and can stop signal transmission in time when there is a signal conflict.

[0006] The central air conditioning system includes: a first bus, a second bus, and a repeater. The first bus is configured to transmit differential signals; the second bus is configured to transmit differential signals; the repeater includes: a main control chip, a first control circuit, a second control circuit, a first switching circuit, and a second switching circuit; the signal terminal of the first control circuit is electrically connected to the first bus; the second output terminal of the first control circuit is electrically connected to the first detection terminal of the main control chip; the signal terminal of the second control circuit is electrically connected to the second bus; and the second output terminal of the second control circuit is electrically connected to the second detection terminal of the main control chip.

[0007] The control terminal of the first switching circuit is electrically connected to the first control terminal of the main control chip; the first switching circuit is electrically connected between the first output terminal of the first control circuit and the first input terminal of the second control circuit; the first output terminal of the first control circuit and the first input terminal of the second control circuit are configured to transmit single-ended signals; the control terminal of the second switching circuit is electrically connected to the second control terminal of the main control chip; the second switching circuit is electrically connected between the first output terminal of the second control circuit and the first input terminal of the first control circuit; the first output terminal of the second control circuit and the first input terminal of the first control circuit are configured to transmit single-ended signals.

[0008] The first control circuit is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal is the same as the signal at the first input terminal, and transmit the first result signal to the first detection terminal; if not, the main control chip is configured to control the second switching circuit to open; the second control circuit is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal is the same as the signal at the first input terminal, and transmit the first result signal to the first detection terminal; if not, the main control chip is configured to control the first switching circuit to open.

[0009] Based on the above solutions, some embodiments of this application provide a central air conditioning system. In this system, when a repeater has a signal on only one side of the bus, it can transmit the signal to the other side in real time, improving the overall performance and response speed of the repeater's signal transmission. Simultaneously, when signals are transmitted on both sides of the bus, the main control chip can shut down the corresponding switching circuit to block signal transmission, ensuring that even if two or more nodes start sending data simultaneously, the entire network will not fall into an infinite loop of conflict. Furthermore, when multiple air conditioning systems transmit signals over long distances, the signal gradually weakens. Converting differential signals to single-ended signals using a repeater can improve the signal's anti-interference capability and further strengthen the signal. Then, converting the single-ended signal back to a differential signal suitable for air conditioning system communication completes long-distance communication.

[0010] In some embodiments, the first transmitting terminal of the main control chip is electrically connected to the first input terminal of the first control circuit, and the second transmitting terminal of the main control chip is electrically connected to the first input terminal of the second control circuit; when the signal at the first output terminal and the signal at the first input terminal of the first control circuit are different, the main control chip is configured to output a blocking signal to the first input terminal of the first control circuit and the first input terminal of the second control circuit; when the signal at the first output terminal and the signal at the first input terminal of the second control circuit are different, the main control chip is configured to output a blocking signal to the first input terminal of the first control circuit and the first input terminal of the second control circuit.

[0011] In some embodiments, the first output terminal of the first control circuit is also electrically connected to the first receiving terminal and the first external interrupt terminal of the main control chip; the first output terminal of the second control circuit is also electrically connected to the second receiving terminal and the second external interrupt terminal of the main control chip; the main control chip is further configured to control the first switching circuit to turn on when receiving a single-ended signal from the first output terminal of the first control circuit; and to control the second switching circuit to turn on when receiving a single-ended signal from the first output terminal of the second control circuit.

[0012] In some embodiments, the first bus includes: a first bus and a second bus; the signal terminals of the first control circuit include: a first terminal and a second terminal; the first control circuit includes: a first conversion circuit and a first comparison circuit. A first terminal of the first conversion circuit is electrically connected to a first terminal of the first control circuit, a second terminal of the first conversion circuit is electrically connected to a second terminal of the first control circuit, a first output terminal of the first conversion circuit is electrically connected to a first output terminal of the first control circuit, and a first input terminal of the first conversion circuit is electrically connected to a first input terminal of the first control circuit; a first input terminal of the first comparison circuit is electrically connected to a first output terminal of the first conversion circuit, a second input terminal of the first comparison circuit is electrically connected to a first input terminal of the first conversion circuit, and an output terminal of the first comparison circuit is electrically connected to a second output terminal of the first control circuit.

[0013] The first conversion circuit is configured to convert the differential signal and the single-ended signal; the first comparison circuit is configured to compare whether the signal at the first output terminal and the signal at the first input terminal of the first conversion circuit are the same, and transmit the first result signal to the first detection terminal; if not, the main control chip is configured to control the second switching circuit to open.

[0014] In some embodiments, the first conversion circuit includes: a first receiving coupling circuit, a first transmitting coupling circuit, and a first driving chip; a first end of the first receiving coupling circuit is electrically connected to a first end of the first conversion circuit, and a second end of the first receiving coupling circuit is electrically connected to a second end of the first conversion circuit; a first end of the first transmitting coupling circuit is electrically connected to a first end of the first conversion circuit, and a second end of the first transmitting coupling circuit is electrically connected to a second end of the first conversion circuit.

[0015] The first input terminal of the first driver chip is electrically connected to the third terminal of the first receiving coupling circuit, and the second input terminal of the first driver chip is electrically connected to the fourth terminal of the first receiving coupling circuit; the first output terminal of the first driver chip is electrically connected to the third terminal of the first transmitting coupling circuit; the second output terminal of the first driver chip is electrically connected to the fourth terminal of the first transmitting coupling circuit; the first driver chip is configured to convert differential signals from the first bus into single-ended signals and convert single-ended signals from the second control circuit into differential signals.

[0016] In some embodiments, the first receiving coupling circuit includes: a first capacitor and a second capacitor; a first terminal of the first capacitor is electrically connected to a first terminal of the first receiving coupling circuit, and a second terminal of the first capacitor is electrically connected to a third terminal of the first receiving coupling circuit; a first terminal of the second capacitor is electrically connected to a second terminal of the first receiving coupling circuit, and a second terminal of the second capacitor is electrically connected to a fourth terminal of the first receiving coupling circuit.

[0017] The first transmitting coupling circuit includes a third capacitor and a fourth capacitor; the first terminal of the third capacitor is electrically connected to the first terminal of the first transmitting coupling circuit, and the second terminal of the third capacitor is electrically connected to the second terminal of the first transmitting coupling circuit; the first terminal of the fourth capacitor is electrically connected to the first terminal of the first transmitting coupling circuit, and the second terminal of the third capacitor is electrically connected to the second terminal of the first transmitting coupling circuit.

[0018] In some embodiments, the first conversion circuit further includes: a first bus driving circuit; a first terminal of the first bus driving circuit is electrically connected to a third output terminal of the first driving chip; a second terminal of the first bus driving circuit is electrically connected to a fourth output terminal of the first driving chip; a third terminal of the first bus driving circuit is electrically connected to a first output terminal of the first driving chip; a fourth terminal of the first bus driving circuit is electrically connected to a second output terminal of the first driving chip; and a fifth and a sixth terminal of the first bus driving circuit are electrically connected to a ground terminal.

[0019] The first bus driving circuit includes: a first transistor and a second transistor; the control terminal of the first transistor is electrically connected to a first terminal of the first bus driving circuit, the first terminal of the first transistor is electrically connected to a third terminal of the first bus driving circuit, and the second terminal of the first transistor is electrically connected to a fifth terminal of the first bus driving circuit; the control terminal of the second transistor is electrically connected to a second terminal of the first bus driving circuit, the first terminal of the second transistor is electrically connected to a fourth terminal of the first bus driving circuit, and the second terminal of the second transistor is electrically connected to a sixth terminal of the first bus driving circuit.

[0020] In some embodiments, the first switching circuit includes: a fifth transistor, a sixth transistor, and a first resistor; the control terminal of the fifth transistor is electrically connected to the control terminal of the first switching circuit; the second terminal of the fifth transistor is electrically connected to a ground terminal; the control terminal of the sixth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the sixth transistor is electrically connected to the first terminal of the first switching circuit, and the second terminal of the sixth transistor is electrically connected to the second terminal of the first switching circuit; the first terminal of the first resistor is electrically connected to the first terminal of the first switching circuit, and the second terminal of the first resistor is electrically connected to the first terminal of the fifth transistor.

[0021] In some embodiments, the second bus includes: a first second bus and a second second bus; the signal terminals of the second control circuit include: a first terminal and a second terminal; the second control circuit includes: a second conversion circuit and a second comparison circuit; the first terminal of the second conversion circuit is electrically connected to the first terminal of the second control circuit, the second terminal of the second conversion circuit is electrically connected to the second terminal of the second control circuit, the first output terminal of the second conversion circuit is electrically connected to the first output terminal of the second control circuit, and the first input terminal of the second conversion circuit is electrically connected to the first input terminal of the second control circuit; the first input terminal of the second comparison circuit is electrically connected to the first output terminal of the second conversion circuit, the second input terminal of the second comparison circuit is electrically connected to the first input terminal of the second conversion circuit, and the output terminal of the second comparison circuit is electrically connected to the second output terminal of the second control circuit.

[0022] The second conversion circuit is configured to convert the differential signal and the single-ended signal; the second comparison circuit is configured to compare whether the signal at the first output terminal and the signal at the first input terminal of the second conversion circuit are the same, and transmit the first result signal to the second detection terminal; if not, the main control chip is configured to control the first switching circuit to open.

[0023] In some embodiments, the second conversion circuit includes: a second receiving coupling circuit, a second transmitting coupling circuit, and a second driver chip; a first terminal of the second receiving coupling circuit is electrically connected to a first signal input terminal of the second conversion circuit, and a second terminal of the second receiving coupling circuit is electrically connected to a second signal input terminal of the second conversion circuit; a first terminal of the second transmitting coupling circuit is electrically connected to a first signal input terminal of the second conversion circuit, and a second terminal of the second transmitting coupling circuit is electrically connected to a second signal input terminal of the second conversion circuit.

[0024] The first input terminal of the second driver chip is electrically connected to the third terminal of the second receiving coupling circuit, and the second input terminal of the second driver chip is electrically connected to the fourth terminal of the second receiving coupling circuit; the first output terminal of the second driver chip is electrically connected to the third terminal of the second transmitting coupling circuit; the second output terminal of the second driver chip is electrically connected to the fourth terminal of the second transmitting coupling circuit; the second driver chip is configured to convert differential signals from the second bus into single-ended signals and convert single-ended signals from the first control circuit into differential signals.

[0025] In some embodiments, the second receiving coupling circuit includes: a fifth capacitor and a sixth capacitor; a first terminal of the fifth capacitor is electrically connected to a first terminal of the second receiving coupling circuit, and a second terminal of the fifth capacitor is electrically connected to a third terminal of the second receiving coupling circuit; a first terminal of the sixth capacitor is electrically connected to a second terminal of the second receiving coupling circuit, and a second terminal of the sixth capacitor is electrically connected to a fourth terminal of the second receiving coupling circuit.

[0026] The second transmitting coupling circuit includes a seventh capacitor and an eighth capacitor; the first terminal of the seventh capacitor is electrically connected to the first terminal of the second transmitting coupling circuit, and the second terminal of the seventh capacitor is electrically connected to the second terminal of the second transmitting coupling circuit; the first terminal of the eighth capacitor is electrically connected to the first terminal of the second transmitting coupling circuit, and the second terminal of the seventh capacitor is electrically connected to the second terminal of the second transmitting coupling circuit.

[0027] In some embodiments, the second conversion circuit further includes: a second bus driving circuit; a first terminal of the second bus driving circuit is electrically connected to a third output terminal of the second driving chip; a second terminal of the first bus driving circuit is electrically connected to a fourth output terminal of the second driving chip; a third terminal of the second bus driving circuit is electrically connected to a first output terminal of the second driving chip; a fourth terminal of the second bus driving circuit is electrically connected to a second output terminal of the second driving chip; and a fifth and a sixth terminal of the second bus driving circuit are electrically connected to a ground terminal.

[0028] The second bus driving circuit includes a third transistor and a fourth transistor; the control terminal of the third transistor is electrically connected to a first terminal of the second bus driving circuit, the first terminal of the third transistor is electrically connected to a third terminal of the second bus driving circuit, and the second terminal of the third transistor is electrically connected to a fifth terminal of the second bus driving circuit; the control terminal of the fourth transistor is electrically connected to a second terminal of the second bus driving circuit, the first terminal of the fourth transistor is electrically connected to a fourth terminal of the second bus driving circuit, and the second terminal of the fourth transistor is electrically connected to a sixth terminal of the second bus driving circuit.

[0029] In some embodiments, the second switching circuit includes: a seventh transistor, an eighth transistor, and a second resistor; the control terminal of the seventh transistor is electrically connected to the control terminal of the first switching circuit; the second terminal of the seventh transistor is electrically connected to a ground terminal; the control terminal of the eighth transistor is electrically connected to the first terminal of the seventh transistor, the first terminal of the eighth transistor is electrically connected to the first terminal of the second switching circuit, and the second terminal of the eighth transistor is electrically connected to the second terminal of the second switching circuit; the first terminal of the second resistor is electrically connected to the first terminal of the second switching circuit, and the second terminal of the second resistor is electrically connected to the first terminal of the seventh transistor. Attached Figure Description

[0030] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0031] Figure 1 A schematic diagram of a central air conditioning system provided in an embodiment of this application;

[0032] Figure 2 A structural block diagram of a repeater provided in an embodiment of this application;

[0033] Figure 3 A structural block diagram of a repeater signal routing provided in an embodiment of this application;

[0034] Figure 4 A structural block diagram of another repeater signal routing provided in an embodiment of this application;

[0035] Figure 5 A structural block diagram of another repeater provided in the embodiments of this application;

[0036] Figure 6 A structural block diagram of a repeater as provided in this application embodiment;

[0037] Figure 7 A structural block diagram of the overall signal routing of a repeater provided in an embodiment of this application;

[0038] Figure 8 Another structural block diagram of the overall signal routing of a repeater provided in this application embodiment;

[0039] Figure 9 A structural block diagram of a first control circuit provided in an embodiment of this application;

[0040] Figure 10 A structural block diagram of a first conversion circuit provided in an embodiment of this application;

[0041] Figure 11 A circuit diagram of a first receiving coupling circuit provided in an embodiment of this application;

[0042] Figure 12 A circuit diagram of a first transmitting coupling circuit provided in an embodiment of this application;

[0043] Figure 13 A structural block diagram of a first bus driving circuit provided in an embodiment of this application;

[0044] Figure 14A circuit diagram of a first bus driving circuit provided in an embodiment of this application;

[0045] Figure 15 A circuit diagram of a first switching circuit provided in an embodiment of this application;

[0046] Figure 16 A structural block diagram of a second control circuit provided in an embodiment of this application;

[0047] Figure 17 A structural block diagram of a second conversion circuit provided in an embodiment of this application;

[0048] Figure 18 A circuit diagram of a second receiving coupling circuit provided in an embodiment of this application;

[0049] Figure 19 A circuit diagram of a second transmitting coupling circuit provided in an embodiment of this application;

[0050] Figure 20 A structural block diagram of a second bus driving circuit provided in an embodiment of this application;

[0051] Figure 21 A circuit diagram of a second bus driving circuit provided in an embodiment of this application;

[0052] Figure 22 A circuit diagram of a second switching circuit provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0055] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Furthermore, when describing pipelines, the terms "connected" and "linked" as used in this invention have the meaning of enabling conduction. The specific meaning needs to be understood in conjunction with the context.

[0057] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0058] With the development of science and technology, the application of electrical appliances is becoming more and more common, and air conditioning has become an integral part of the daily lives of more and more people.

[0059] Currently, central air conditioning systems generally use the Homebus communication protocol for communication, which enables convenient interaction and control between devices.

[0060] However, due to the limitations of HomeBus' hardware design and communication mechanism, the communication bus length is generally no more than 1,000 meters. This cannot meet the long-distance communication requirements in large public building projects, and often requires the deployment of large-scale central air conditioning systems in the form of split buses, which has an adverse impact on system integration and deployment costs.

[0061] Based on this, embodiments of the present invention provide a central air conditioning system. For example... Figure 1 As shown, the central air conditioning system 1000 includes: a first bus 100, a second bus 200, multiple air conditioning systems 300, and a repeater 400. The multiple air conditioning systems 300 are electrically connected to each other via the first bus 100 and the second bus 200. The repeater 400 is disposed between the first bus 100 and the second bus 200. A first terminal of the repeater is electrically connected to the first bus 100, and a second terminal of the repeater is electrically connected to the second bus 200.

[0062] The first bus 100 is configured to transmit differential signals; the second bus 200 is configured to transmit differential signals.

[0063] In some embodiments, the first bus 100 and the second bus 200 are Homebus buses.

[0064] like Figure 2As shown, the repeater 400 includes: a main control chip 10, a first control circuit 20, a second control circuit 30, a first switching circuit 40, and a second switching circuit 50.

[0065] The signal terminal 20X of the first control circuit 20 is electrically connected to the first bus 100; the second output terminal 204 of the first control circuit 20 is electrically connected to the first detection terminal HBS1-Diff of the main control chip 10.

[0066] The signal terminal 30X of the second control circuit 30 is electrically connected to the second bus 200; the second output terminal 304 of the second control circuit 30 is electrically connected to the second detection terminal HBS2-Diff of the main control chip 10.

[0067] The control terminal 401 of the first switching circuit 40 is electrically connected to the first control terminal Switch1 of the main control chip 10; the first switching circuit 40 is electrically connected between the first output terminal 203 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30.

[0068] The first output terminal 203 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30 are configured to transmit single-ended signals.

[0069] The control terminal 501 of the second switching circuit 50 is electrically connected to the second control terminal Switch2 of the main control chip 10; the second switching circuit 50 is electrically connected between the first output terminal 303 of the second control circuit 30 and the first input terminal 205 of the first control circuit 20.

[0070] The first output terminal 303 of the second control circuit 30 and the first input terminal 205 of the first control circuit 20 are configured to transmit single-ended signals.

[0071] The first control circuit 20 is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal 203 and the signal at the first input terminal 205 are the same, and transmit the first result signal to the first detection terminal HBS1-Diff; if not, the main control chip 10 is configured to control the second switching circuit 50 to disconnect.

[0072] The second control circuit 30 is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal 303 and the signal at the first input terminal 305 are the same, and transmit the second result signal to the second detection terminal HBS2-Diff; if not, the main control chip 10 is configured to control the first switching circuit 40 to disconnect.

[0073] Among them, the first result signal and the second result signal are level signals.

[0074] The first control circuit 20 is configured to convert differential signals and single-ended signals, meaning that the first control circuit 20 is configured to convert the differential signal received at its signal terminal 20X into a single-ended signal and output it from its first output terminal 203, and is also configured to convert the single-ended signal received at its first input terminal 205 into a differential signal and output it from its signal terminal 20X.

[0075] The second control circuit 30 is configured to convert differential signals and single-ended signals, meaning that the second control circuit 30 is configured to convert the differential signal received at its signal terminal 30X into a single-ended signal and output it from its first output terminal 303, and is also configured to convert the single-ended signal received at its first input terminal 305 into a differential signal and output it from its signal terminal 30X.

[0076] In some embodiments, when the signal at the first output terminal 203 is the same as the signal at the first input terminal 205, the first result signal is a low-level signal; when the signal at the first output terminal 203 is different from the signal at the first input terminal 205, the first result signal is a high-level signal. Similarly, when the signal at the first output terminal 303 is the same as the signal at the first input terminal 305, the second result signal is a low-level signal; when the signal at the first output terminal 303 is different from the signal at the first input terminal 305, the second result signal is a high-level signal.

[0077] For example, refer to Figure 3 The first bus 100 transmits the differential signal to the signal terminal 20X of the first control circuit 20. The first control circuit 20 converts the differential signal into a single-ended signal, and the first output terminal 203 of the first control circuit 20 outputs the single-ended signal to the first switching circuit 40. When the first switching circuit 40 is turned on, the single-ended signal is transmitted to the first input terminal 305 of the second control circuit 30 via the first switching circuit 40. The second control circuit 30 converts the single-ended signal into a differential signal, and the signal terminal 30X of the second control circuit 30 transmits the differential signal to the second bus 200.

[0078] During the transmission of the differential signal from the first bus 100 to the second bus 200, the second control circuit 30 compares whether the signal at the first output terminal 303 and the signal at the first input terminal 305 are the same, and transmits the second result signal to the second detection terminal HBS2-Diff of the main control chip 10.

[0079] Here, the signal compared by the first output terminal 303 of the second control circuit 30 refers to: the differential signal of the first bus 100 is converted into a single-ended signal and transmitted to the first input terminal 305 of the second control circuit 30; the second control circuit 30 then converts the single-ended signal into a differential signal and transmits it to the second bus 200; at the same time, the second control circuit 30 converts the differential signal from the second bus 200 and outputs it as a single-ended signal through the first output terminal 303.

[0080] The differential signal from the second bus includes two cases: the first is the differential signal from the first bus 100 that is transmitted to the second bus 200 after a series of conversions; the second is the differential signal obtained by superimposing the differential signal from the first bus 100 that is transmitted to the second bus 200 after a series of conversions and the differential signal from the second bus 200 that is transmitted to the repeater.

[0081] If the signal at the first output terminal 303 is the same as the signal at the first input terminal 305, it means that the signal received by the repeater only comes from the first bus, and the second bus itself does not transmit a signal to the repeater. The second output terminal 304 of the second control circuit 30 outputs a low level to the second detection terminal HBS2-Diff of the main control chip 10. The main control chip 10 does not perform any action when it detects the low level. That is to say, at this time, the first switch circuit 40 remains in the conducting state, the signal is transmitted normally, and the first bus 100 can transmit the differential signal to the second bus 200.

[0082] If the signal at the first output terminal 303 is different from the signal at the first input terminal 305, it indicates that the repeater receives signals not only from the first bus but also from the second bus. The second output terminal 304 of the second control circuit 30 outputs a high level to the second detection terminal HBS2-Diff of the main control chip 10. The main control chip 10 detects the high level and determines that a communication conflict has occurred. At this time, the first control terminal Switch1 of the main control chip 10 controls the first switch circuit 40 to open, preventing the signal from the first bus 100 from being transmitted to the second bus. In this way, stopping signal transmission does not cause the entire repeater to fall into an infinite loop of conflict.

[0083] It should be noted that the signals at the first output terminal 303 and the first input terminal 305 are different because: the signal at the first input terminal 305 is a single-ended signal from the differential signal of the first bus 100, which is converted and transmitted to the first input terminal 305 of the second control circuit 30. The signal at the first output terminal 303 is the result of: the differential signal of the first bus 100 being converted into a single-ended signal and transmitted to the first input terminal 305 of the second control circuit 30; the second control circuit 30 then converts the single-ended signal back into a differential signal and transmits it to the second bus 200; simultaneously, the second control circuit 30 combines this differential signal with the differential signal transmitted from the second bus itself, performs a further conversion, and then outputs a single-ended signal via the first output terminal 303. Therefore, the two signals are different.

[0084] Similarly, refer to Figure 4The second bus 200 transmits the differential signal to the signal terminal 30X of the second control circuit 30. The second control circuit 30 converts the differential signal into a single-ended signal, and the first output terminal 303 of the second control circuit 30 outputs the single-ended signal to the second switching circuit 50. When the second switching circuit 50 is turned on, the single-ended signal is transmitted to the first input terminal 205 of the first control circuit 20 via the second switching circuit 50. The first control circuit 20 converts the single-ended signal into a differential signal, and the signal terminal 20X of the first control circuit 20 transmits the differential signal to the first bus 100.

[0085] During the transmission of the differential signal from the second bus 200 to the first bus 100, the first control circuit 20 compares whether the signal at the first output terminal 203 and the signal at the first input terminal 205 are the same, and transmits the second result signal to the first detection terminal HBS1-Diff of the main control chip 10.

[0086] Here, the signal compared by the first output terminal 203 of the first control circuit 20 refers to: the differential signal of the second bus 200 is converted into a single-ended signal and transmitted to the first input terminal 205 of the first control circuit 20; the first control circuit 20 then converts the single-ended signal into a differential signal and transmits it to the first bus 100; at the same time, the first control circuit 20 converts the differential signal from the first bus 100 and outputs it as a single-ended signal through the first output terminal 203.

[0087] The differential signal from the first bus includes two cases: the first is the differential signal from the second bus 200 transmitted to the first bus 100 after a series of conversions; the second is the differential signal obtained by superimposing the differential signal from the second bus 200 transmitted to the first bus 100 after a series of conversions and the differential signal from the first bus 100 itself transmitted to the repeater.

[0088] If the signal at the first output terminal 203 is the same as the signal at the first input terminal 205, it means that the signal received by the repeater only comes from the second bus, and the first bus itself does not transmit a signal to the repeater. The second output terminal 204 of the first control circuit 20 outputs a low level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 does not perform any action when it detects the low level. That is to say, at this time, the second switch circuit 50 remains in the conducting state, the signal is transmitted normally, and the second bus 200 can transmit the differential signal to the first bus 100.

[0089] If the signal at the first output terminal 203 is different from the signal at the first input terminal 205, it indicates that the repeater receives signals not only from the second bus but also from the first bus. The second output terminal 204 of the first control circuit 20 outputs a high level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 detects the high level and determines that a communication conflict has occurred. At this time, the second control terminal Switch2 of the main control chip 10 controls the second switch circuit 50 to open, preventing signals from the second bus 200 from being transmitted to the second bus. In this way, stopping signal transmission does not cause the entire repeater to fall into an infinite loop of conflict.

[0090] It should be noted that the signals at the first output terminal 203 and the first input terminal 205 are different because: the signal at the first input terminal 205 is a single-ended signal from the differential signal of the second bus 200, which is converted and transmitted to the first input terminal 205 of the first control circuit 20. The signal at the first output terminal 203 is the result of: the differential signal of the second bus 200 being converted into a single-ended signal and transmitted to the first input terminal 205 of the first control circuit 20; the first control circuit 20 then converts the single-ended signal back into a differential signal and transmits it to the first bus 100; simultaneously, the first control circuit 20 combines this differential signal with the differential signal transmitted from the first bus itself, performs further conversion, and then outputs a single-ended signal via the first output terminal 203. Therefore, the two signals are different.

[0091] In this system, multiple air conditioning systems 300 communicate with each other via a first bus and a second bus using differential signals. A differential signal consists of two voltage signals with equal amplitude but opposite phase, typically used to suppress common-mode interference and improve anti-interference capabilities. The main purpose of converting a differential signal to a single-ended signal is for waveform shaping. After long-distance transmission, the waveform of a differential signal becomes poor, meaning the signal has weakened and needs shaping to further enhance and improve the waveform. The main purpose of converting a single-ended signal to a differential signal is for differential signal regeneration, allowing for further long-distance transmission. Differential signals achieve interference cancellation by applying equal but opposite AC voltages and currents to the two lines, significantly reducing radiation loss. This makes differential signals particularly suitable for high-speed data transmission applications.

[0092] Therefore, converting differential signals to single-ended signals first can enhance the signal and improve its anti-interference ability; then converting single-ended signals to differential signals further completes the communication between multiple air conditioning systems.

[0093] In summary, some embodiments of this application provide a central air conditioning system in which a repeater can transmit signals to the other side in real time when there is a signal on only one side of the bus, thereby improving the overall performance and response speed of the repeater's signal transmission. Simultaneously, when signals are transmitted on both sides of the bus, the corresponding switching circuit can be shut down by the main control chip to block signal transmission, ensuring that even if two or more nodes start sending data simultaneously, the entire network will not fall into an infinite loop of conflict. Furthermore, when multiple air conditioning systems transmit signals over long distances, the signal gradually weakens. Converting differential signals to single-ended signals using a repeater can improve the signal's anti-interference capability and further strengthen the signal. Then, converting the single-ended signal back to a differential signal suitable for air conditioning system communication completes long-distance communication.

[0094] like Figure 5 As shown, the first transmitting terminal UART1-TXD of the main control chip 10 is electrically connected to the first input terminal 205 of the first control circuit 20, and the second transmitting terminal UART2-TXD of the main control chip is electrically connected to the first input terminal 305 of the second control circuit 30.

[0095] When the signal at the first output terminal 203 of the first control circuit 20 and the signal at the first input terminal 205 are different, the main control chip 10 is configured to output a blocking signal to the first input terminal 205 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30.

[0096] When the signal at the first output terminal 303 of the second control circuit 30 is different from the signal at the first input terminal 305, the main control chip 10 is configured to output a blocking signal to the first input terminal 205 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30.

[0097] The first bus 100 includes a first bus 110 and a second bus 120; the signal terminal 20X of the first control circuit 20 includes a first terminal 201 and a second terminal 202.

[0098] The second bus 200 includes: a first second bus 210 and a second second bus 220; the signal terminal 30X of the second control circuit 30 includes: a first terminal 301 and a second terminal 302.

[0099] like Figure 6 As shown, the first output terminal 203 of the first control circuit 20 is also electrically connected to the first receiving terminal UART1-RXD and the first external interrupt terminal MCU-IRQ1 of the main control chip 10.

[0100] The first output terminal 303 of the second control circuit 30 is also electrically connected to the second receiving terminal UART2-RXD and the second external interrupt terminal MCU-IRQ2 of the main control chip 10.

[0101] The main control chip 10 is also configured to control the first switching circuit 40 to turn on when it receives a single-ended signal from the first output terminal 203 of the first control circuit 20; and to control the second switching circuit 50 to turn on when it receives a single-ended signal from the first output terminal 303 of the second control circuit 30.

[0102] For example, the first bus 100 transmits the differential signal to the first terminal 201 and the second terminal 202 of the first control circuit 20. The first control circuit 20 converts the differential signal into a single-ended signal and transmits it from the first output terminal 203 to the first receiving terminal UART1-RXD of the main control chip 10 and the first external interrupt terminal MCU-IRQ1 of the main control chip 10.

[0103] The main control chip 10 will generate a serial port receive interrupt after its first receiving terminal UART1-RXD receives a complete byte.

[0104] The first external interrupt terminal MCU-IRQ1 of the main control chip 10 is configured to be triggered by the falling edge. Once the first output terminal 203 of the first control circuit 20 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection.

[0105] Similarly, the second bus 200 transmits the differential signal to the first terminal 301 and the second terminal 302 of the second control circuit 30. The second control circuit 30 converts the differential signal into a single-ended signal and transmits it from the first output terminal 303 to the second receiving terminal UART2-RXD of the main control chip 10 and the second external interrupt terminal MCU-IRQ2 of the main control chip 10. At the same time, it also transmits the single-ended signal to the first input terminal 205 of the first control circuit 20.

[0106] Similarly, the first control circuit 20 converts the differential signal into a single-ended signal and transmits it from the first output terminal 203 to the first input terminal 305 of the second control circuit 30.

[0107] Among them, the second receiving terminal UART2-RXD of the main control chip 10 will generate a serial port receive interrupt after receiving a complete byte.

[0108] The second external interrupt terminal MCU-IRQ2 of the main control chip 10 is configured to be triggered by the falling edge. Once the first output terminal 303 of the second control circuit 30 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection.

[0109] The main purpose of the serial port receive interrupt generated by the main control chip is to determine that a complete byte of data has been relayed and to shut down either the first switch circuit 40 or the second switch circuit 50, thus restoring the repeater to its normal state, where both switches are in the off state. Specifically, when data is received via the serial port, the serial port receive interrupt is set. As long as the serial port interrupt is enabled, the main control chip will enter the serial port interrupt handler. By using the serial port interrupt, the processor can avoid spending excessive time polling the serial port, thereby improving the overall system performance and response speed.

[0110] It's important to note that Carrier Sense Multiple Access with Collision Detection (CSMA / CD) is a protocol used in Ethernet LANs to implement multi-point access and collision detection. Its working principle is as follows: Before sending data, a node first listens to the channel status. If the channel is idle, the node can begin sending data; if the channel is busy, the node needs to wait for a period before retrying. When the node finds the channel idle, it immediately begins sending data and continues listening to the channel. If a collision is detected during data transmission (i.e., another node simultaneously begins sending data), that node immediately stops sending and enters a backoff phase. Once a collision occurs, all nodes involved in the collision stop sending and randomly select a time delay before retrying to send data. This mechanism ensures that even if two or more nodes begin sending data simultaneously, the entire network will not fall into an infinite collision loop.

[0111] For example, refer to Figure 7 For the first control circuit 20: the first input terminal 205 of the first control circuit 20 receives a single-ended signal from the second control circuit 30, and the first control circuit 20 converts the single-ended signal from the second control circuit 30 into a differential signal. The differential signal is transmitted to the first bus 100 via the first terminal 201 and the second terminal 202 of the first control circuit 20. At the same time, the differential signal of the second bus 200 is converted into a differential signal on the first bus 100 and a differential signal on the first bus 100 itself transmitted to the repeater. The differential signal obtained by superimposing the two differential signals is converted into a single-ended signal again and compared with the single-ended signal from the second control circuit 30.

[0112] If the signals of the two are the same, it means that the signal only comes from the second bus and the first bus has no signal transmitted to the repeater. The second output terminal 204 of the first control circuit 20 outputs a low level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 does not take any action when it detects the low level. That is to say, the second switch circuit 50 remains on at this time, the signal is transmitted normally, and the second bus 200 can transmit the differential signal to the first bus 100.

[0113] If the signals from the two are different, it means that the signal comes not only from the second bus, but also from the first bus. The second output terminal 204 of the first control circuit 20 outputs a high level to the first detection terminal HBS1-Diff of the main control chip 10. When the main control chip 10 detects the high level, it determines that a communication conflict has occurred.

[0114] After a collision is detected, the main control chip 10 will control the second switch circuit 50 to disconnect. Then, the main control chip 10 will send a blocking signal 0XAA through the first receiving terminal UART1-TXD. The blocking signal will be sent to the first input terminal 205 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30. Through the conversion of the first control circuit 20 and the second control circuit 30, the blocking signal will be transmitted to the first bus 100 and the second bus 200 on both sides of the repeater 400.

[0115] After the blocking signal is sent to the first bus 100 and the second bus 200, the communication nodes on both sides of the repeater 400 will detect a communication conflict. According to the CSMA / CD principle, the communication nodes on both sides will stop sending data to the first bus and the second bus, and enter the communication logic of contending for the bus again after a random delay.

[0116] When the repeater 400 feeds back the blocking signal 0XAA to the first bus 100 and the second bus 200 on both sides, the first receiving terminal UART1-TXD and the second receiving terminal UART2-TXD of the main control chip synchronously receive the data from the first output terminal 203 of the first control circuit 20 and the first output terminal 303 of the second control circuit 30. This continues until both the first receiving terminal UART1-TXD and the second receiving terminal UART2-TXD receive the blocking signal 0XAA on the bus. At this point, the blocking is considered successful. Otherwise, the main control chip 10 continues to send blocking signals to the first bus 100 and the second bus 200. After successful blocking, the main control chip 10 controls the repeater to return to its normal state (i.e., the repeater is in an idle state).

[0117] For example, refer to Figure 8 For the second control circuit 30: the first input terminal 305 of the second control circuit 30 receives the single-ended signal from the first control circuit 20, and the second control circuit 30 converts the single-ended signal from the first control circuit 20 into a differential signal. The differential signal is transmitted to the second bus 200 via the first terminal 301 and the second terminal 302 of the second control circuit 30. At the same time, the differential signal of the first bus 100 is converted into a differential signal on the second bus 200 and a differential signal on the second bus 200 that is transmitted to the repeater. The differential signal obtained by superimposing the two differential signals is converted into a single-ended signal again and compared with the single-ended signal from the first control circuit 20.

[0118] If the signals of the two are the same, it means that the signal only comes from the first bus 100 and the second bus 200 has no signal transmitted to the repeater 400. The second output terminal 304 of the second control circuit 30 outputs a low level to the second detection terminal HBS2-Diff of the main control chip 10. The main control chip 10 does not take any action when it detects the low level. That is to say, the first switch circuit 40 remains in the conducting state at this time, the signal is transmitted normally, and the first bus 100 can transmit the differential signal to the second bus 200.

[0119] If the two signals are different, it means that the signal comes not only from the first bus 100, but also from the second bus 200. The second output terminal 304 of the second control circuit 30 outputs a high level to the second detection terminal HBS2-Diff of the main control chip 10. When the main control chip 10 detects the high level, it determines that a communication conflict has occurred.

[0120] After a collision is detected, the main control chip 10 will control the first switching circuit 40 to disconnect. Then, the main control chip 10 will send a blocking signal 0XAA through the second receiving terminal UART2-TXD. The blocking signal will be sent to the first input terminal 305 of the second control circuit 30 and the first input terminal 205 of the first control circuit 20. Through the conversion between the first control circuit 20 and the second control circuit 30, the blocking signal will be transmitted to the first bus 100 and the second bus 200 on both sides of the repeater 400.

[0121] After the blocking signal is sent to the first bus 100 and the second bus 200, the communication nodes on both sides of the repeater 400 will detect a communication conflict. According to the CSMA / CD principle, the communication nodes on both sides will stop sending data to the first bus 100 and the second bus 200, and enter the communication logic of contending for the bus again after a random delay.

[0122] When the repeater 400 feeds back the blocking signal 0XAA to the first bus 100 and the second bus 200 on both sides, the first receiving terminal UART1-TXD and the second receiving terminal UART2-TXD of the main control chip synchronously receive the data from the first output terminal 203 of the first control circuit 20 and the first output terminal 303 of the second control circuit 30. This continues until both the first receiving terminal UART1-TXD and the second receiving terminal UART2-TXD receive the blocking signal 0XAA on the bus. At this point, the blocking is considered successful. Otherwise, the main control chip 10 continues to send blocking signals to the first bus 100 and the second bus 200. After successful blocking, the main control chip 10 controls the repeater to return to its normal state (i.e., the repeater is in an idle state).

[0123] The above control process enables the detection of communication conflicts on both sides of the repeater and the feedback of communication conflicts to both sides.

[0124] In summary, some embodiments of this application provide a central air conditioning system in which the repeater uses carrier detection and collision detection to achieve signal transmission and collision feedback. When there is a signal on only one side of the bus, the signal can be transmitted to the other side in real time. By generating a serial port receive interrupt through the main control chip, it can be determined that a complete byte has been relayed, allowing the repeater to return to its normal idle state. At the same time, when there is signal transmission on both sides, the corresponding switching circuit can be turned off by the main control chip to block signal transmission. Carrier detection and collision detection ensure that even if two or more nodes start sending data simultaneously, the entire network will not fall into an infinite loop of collision. Furthermore, the blocking signal issued by the main control chip can cause the air conditioning system to stop sending data and enter the communication logic of contending for the bus again after a random delay; this will not cause signal transmission collisions. Further, when multiple air conditioning systems transmit signals over long distances, the signal will gradually weaken. By using the repeater to convert the differential signal into a single-ended signal, the waveform of the signal can be shaped and the signal can be enhanced. Then, the single-ended signal can be converted into a differential signal suitable for air conditioning system communication to complete long-distance communication.

[0125] like Figure 9 As shown, the first control circuit 20 includes a first conversion circuit 21 and a first comparison circuit 22.

[0126] The first conversion circuit 21 includes: a first terminal 211, a second terminal 212, a first output terminal HBS1-Out, and a first input terminal HBS1-In.

[0127] The first terminal 211 of the first conversion circuit 21 is electrically connected to the first terminal 201 of the first control circuit 20, the second terminal 212 of the first conversion circuit 21 is electrically connected to the second terminal 202 of the first control circuit 20, the first output terminal HBS1-Out of the first conversion circuit 21 is electrically connected to the first output terminal 203 of the first control circuit 20, and the first input terminal HBS1-In of the first conversion circuit 21 is electrically connected to the first input terminal 205 of the first control circuit 20.

[0128] The first comparator circuit 22 includes a first input terminal 221, a second input terminal 222, and an output terminal 223.

[0129] The first input terminal 221 of the first comparison circuit 22 is electrically connected to the first output terminal HBS1-Out of the first conversion circuit 21. The second input terminal 222 of the first comparison circuit 22 is electrically connected to the first input terminal HBS1-In of the first conversion circuit 21. The output terminal 223 of the first comparison circuit 22 is electrically connected to the first detection terminal HBS1-Diff of the main control chip 10, which is also electrically connected to the second output terminal 204 of the first control circuit.

[0130] The first conversion circuit 21 is configured to convert the differential signal from the first bus 100 into a single-ended signal, and to convert the single-ended signal from the second control circuit 30 into a differential signal and transmit it to the first bus 100.

[0131] During the transmission of signals from the second bus to the first bus, the first comparison circuit 22 is configured to compare whether the signal at the first output terminal HBS1-Out of the first conversion circuit 21 is the same as the signal at the first input terminal HBS1-In; if they are different, the main control chip 10 is configured to control the second switching circuit 50 to disconnect.

[0132] In some embodiments, the first comparison circuit 22 is an XOR gate circuit, mainly used to detect whether the signal at the first output terminal HBS1-Out and the signal at the first input terminal HBS1-In of the first conversion circuit 21 are the same. If they are the same, a low level "0" is output; if they are different, a high level "1" is output.

[0133] The first switching circuit 40 is configured to turn on when the main control chip 10 receives a signal from the first output terminal HBS1-Out of the first conversion circuit 21.

[0134] For example, the first bus 100 transmits the differential signal to the first terminal 201 and the second terminal 202 of the first control circuit 20, and then transmits the differential signal to the first terminal 211 and the second terminal 212 of the first conversion circuit 21. The first conversion circuit 21 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS1-Out to the first receiving terminal UART1-RXD of the main control chip 10 and the first external interrupt terminal MCU-IRQ1 of the main control chip 10.

[0135] After the first receiving terminal UART1-RXD of the main control chip 10 receives a complete byte, it will generate a serial port receive interrupt. The first external interrupt terminal MCU-IRQ1 of the main control chip 10 is configured to be triggered by the falling edge. Once the first output terminal HBS1-Out of the first conversion circuit 21 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection.

[0136] At this time, the first control terminal Switch1 of the main control chip 10 outputs a high level, which turns on the first switch circuit 40, so that the single-ended signal can be transmitted to the second control circuit.

[0137] The specific process is as follows: The first bus 100 transmits the differential signal to the first terminal 211 and the second terminal 212 of the first conversion circuit 21. The first conversion circuit 21 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS1-Out to the first external interrupt terminal MCU-IRQ1 of the main control chip 10. The first external interrupt terminal MCU-IRQ1 of the main control chip 10 is configured to be triggered by a falling edge. Once the first output terminal HBS1-Out of the first conversion circuit 21 has a signal output, it will be detected immediately. As a result, the first control terminal Switch1 of the main control chip outputs a high level, which turns on the first switch circuit 40 and transmits the single-ended signal to the second control circuit 30.

[0138] For the first control circuit, the above process refers to the transmission of differential signals from the first bus 100 to the second bus 200; and the specific process of transmitting differential signals from the second bus 200 to the first bus 100 is as follows:

[0139] The first input terminal 205 of the first conversion circuit 21 receives a single-ended signal from the second control circuit 30. The first conversion circuit 21 converts the single-ended signal from the second control circuit 30 into a differential signal. While transmitting the differential signal to the first bus 100 via the first terminal 211 and the second terminal 212 of the first conversion circuit 21, the differential signal is converted back into a single-ended signal and compared with the single-ended signal from the second control circuit 30 via the first comparison circuit 22.

[0140] If the signals of the two are the same, it means that the signal only comes from the second bus and the first bus has no signal transmitted to the repeater. The second output terminal 223 of the first comparator circuit 22 outputs a low level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 will work normally if it detects the low level.

[0141] If the two signals are different, it means that the signal comes not only from the second bus, but also from the first bus. The second output terminal 223 of the first comparison circuit 22 outputs a high level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 detects the high level and determines that a communication conflict has occurred.

[0142] After a collision is detected, the main control chip 10 will control the second switch circuit 50 to disconnect. Then, the main control chip 10 will send a blocking signal 0XAA through the first transmitting terminal UART1-TXD. The blocking signal will be sent to the first input terminal 205 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30. Through the conversion of the first control circuit 20 and the second control circuit 30, the blocking signal will be transmitted to the first bus 100 and the second bus 200 on both sides of the repeater 400.

[0143] After the blocking signal is sent to the first bus 100 and the second bus 200, the communication nodes on both sides of the repeater 400 will detect a communication conflict. According to the CSMA / CD principle, the communication nodes on both sides will stop sending data to the first bus and the second bus, and enter the communication logic of contending for the bus again after a random delay.

[0144] When the repeater 400 feeds back the blocking signal 0XAA to the first bus 100 and the second bus 200 on both sides, the first receiving terminal UART1-TXD and the second receiving terminal UART2-TXD of the main control chip synchronously receive data from the first output terminal 203 of the first control circuit 20 and the first output terminal 303 of the second control circuit 30. This continues until both the first receiving terminal UART1-RXD and the second receiving terminal UART2-RXD receive the blocking signal 0XAA on the bus. At this point, the blocking is considered successful. Otherwise, the main control chip 10 continues to send blocking signals to the first bus 100 and the second bus 200. After successful blocking, the main control chip 10 controls the repeater to return to its normal state (i.e., the repeater is in an idle state).

[0145] like Figure 10 As shown, the first conversion circuit 21 includes: a first receiving coupling circuit 24, a first transmitting coupling circuit 25, and a first driving chip IC1.

[0146] The first terminal 241 of the first receiving coupling circuit 24 is electrically connected to the first terminal 211 of the first conversion circuit 21, and the second terminal 242 of the first receiving coupling circuit 24 is electrically connected to the second terminal 212 of the first conversion circuit 21.

[0147] The first terminal 251 of the first transmitting coupling circuit 25 is electrically connected to the first terminal 211 of the first conversion circuit 21, and the second terminal 252 of the first transmitting coupling circuit 25 is electrically connected to the second terminal 212 of the first conversion circuit 21.

[0148] The first input terminal IN11 of the first driver chip IC1 is electrically connected to the third terminal 243 of the first receiving coupling circuit 24; the second input terminal IN12 of the first driver chip IC1 is electrically connected to the fourth terminal 244 of the first receiving coupling circuit 24; the first output terminal OutB of the first driver chip IC1 is electrically connected to the third terminal 253 of the first transmitting coupling circuit 25; and the second output terminal OutA of the first driver chip IC1 is electrically connected to the fourth terminal 254 of the first transmitting coupling circuit 25.

[0149] The third output terminal Out of the first driver chip IC1 is electrically connected to the first output terminal HBS1-Out of the first conversion circuit, and the third input terminal IN of the first driver chip IC1 is electrically connected to the first input terminal HBS1-In of the first conversion circuit.

[0150] The first driver chip IC1 is configured to convert differential signals from the first bus 100 into single-ended signals and single-ended signals from the second bus 200 into differential signals.

[0151] For example, the first bus 100 transmits the differential signal via the first receiving coupling circuit 24 to the first input terminal IN11 and the second input terminal IN12 of the first driver chip IC1. The first driver chip IC1 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS1-Out to the first receiving terminal UART1-RXD of the main control chip 10 and the first external interrupt terminal MCU-IRQ1 of the main control chip 10.

[0152] After the first receiving terminal UART1-RXD of the main control chip 10 receives a complete byte, it generates a serial port receive interrupt. The first external interrupt terminal MCU-IRQ1 of the main control chip 10 is configured to be triggered by a falling edge. Once the first output terminal HBS1-Out of the first conversion circuit 21 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection. At this time, the first control terminal Switch1 of the main control chip 10 outputs a high level, which turns on the first switching circuit 40, thereby allowing the single-ended signal to be transmitted to the second control circuit.

[0153] The first receiving coupling circuit 24 is configured to remove the DC component from the differential signal from the first bus and couple the differential signal to the first driver chip IC1 for amplification, thereby enhancing the weak differential signal.

[0154] Similarly, the first transmitting coupling circuit 25 is configured to remove the DC component from the differential signal from the second bus, and the differential signal is amplified by the first driver chip IC1. The amplified signal can also be output through coupling, thus realizing the transmission of signal and energy.

[0155] In some embodiments, the first receiving coupling circuit 24 and the first transmitting coupling circuit 25 can also suppress low-frequency interference.

[0156] like Figure 11 As shown, the first receiving coupling circuit 24 includes: a first capacitor C1 and a second capacitor C2.

[0157] The first end of the first capacitor C1 is electrically connected to the first end 241 of the first receiving coupling circuit 24, and the second end of the first capacitor C1 is electrically connected to the third end 243 of the first receiving coupling circuit 24.

[0158] The first end of the second capacitor C2 is electrically connected to the second end 242 of the first receiving coupling circuit 24, and the second end of the second capacitor C2 is electrically connected to the fourth end 244 of the first receiving coupling circuit 24.

[0159] like Figure 12 As shown, the first transmitting coupling circuit 25 includes a third capacitor C3 and a fourth capacitor C4.

[0160] The first end of the third capacitor C3 is electrically connected to the first end 251 of the first transmitting coupling circuit 25, and the second end of the third capacitor C3 is electrically connected to the third end 253 of the first transmitting coupling circuit 25.

[0161] The first terminal of the fourth capacitor C4 is electrically connected to the second terminal 252 of the first transmitting coupling circuit 25, and the second terminal of the third capacitor C3 is electrically connected to the fourth terminal 254 of the first transmitting coupling circuit 25.

[0162] like Figure 13 As shown, in some embodiments, the first conversion circuit 21 further includes a first bus driving circuit 26.

[0163] The first terminal 261 of the first bus driver circuit 26 is electrically connected to the third output terminal Outb of the first driver chip IC1; the second terminal 262 of the first bus driver circuit 26 is electrically connected to the fourth output terminal Outa of the first driver chip IC1; the third terminal 263 of the first bus driver circuit 26 is electrically connected to the first output terminal OutB of the first driver chip IC1; the fourth terminal 264 of the first bus driver circuit 26 is electrically connected to the second output terminal OutA of the first driver chip IC1; and the fifth terminal 265 and the sixth terminal 266 of the first bus driver circuit 26 are electrically connected to the ground terminal GND.

[0164] like Figure 14 As shown, the first bus driving circuit 26 includes: a first transistor Q1 and a second transistor Q2.

[0165] The control terminal of the first transistor Q1 is electrically connected to the first terminal 261 of the first bus driving circuit 26, the first terminal of the first transistor Q1 is electrically connected to the third terminal 263 of the first bus driving circuit 26, and the second terminal of the first transistor Q1 is electrically connected to the fifth terminal 265 of the first bus driving circuit 26.

[0166] The control terminal of the second transistor Q2 is electrically connected to the second terminal 262 of the first bus driving circuit 26, the first terminal of the second transistor Q2 is electrically connected to the fourth terminal 264 of the first bus driving circuit 26, and the second terminal of the second transistor Q2 is electrically connected to the sixth terminal 266 of the first bus driving circuit 26.

[0167] like Figure 15 As shown, the first switching circuit 40 includes: a fifth transistor Q5, a sixth transistor Q6, and a first resistor R1.

[0168] The control terminal of the fifth transistor Q5 is electrically connected to the control terminal 401 of the first switching circuit 40; the second terminal of the fifth transistor Q5 is electrically connected to the ground terminal GND.

[0169] The control terminal of the sixth transistor Q6 is electrically connected to the first terminal of the fifth transistor Q5, the first terminal of the sixth transistor Q6 is electrically connected to the first terminal of the first switching circuit 40, and the second terminal of the sixth transistor Q6 is electrically connected to the second terminal of the first switching circuit 40.

[0170] The first end of the first resistor R1 is electrically connected to the first end of the first switching circuit 40, and the second end of the first resistor R1 is electrically connected to the first end of the fifth transistor Q5.

[0171] In some embodiments, the fifth transistor Q5 is an NMOS transistor, and the sixth transistor Q6 is a PMOS transistor. The NMOS transistor is turned on when it receives a high level and turned off when it receives a low level; the PMOS transistor is turned off when it receives a high level and turned on when it receives a low level.

[0172] For example, if the first bus 100 has a differential signal but the second bus 200 does not, the first bus 100 transmits the differential signal to the first terminal 201 and the second terminal 202 of the first control circuit 20, and then transmits the differential signal to the first terminal 211 and the second terminal 212 of the first conversion circuit 21. The first conversion circuit 21 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS1-Out to the first receiving terminal UART1-RXD of the main control chip 10 and the first external interrupt terminal MCU-IRQ1 of the main control chip 10.

[0173] The first switch circuit 40 is turned on by the interrupt service of the first external interrupt terminal MCU_IRQ1. Once the first external interrupt terminal MCU_IRQ1 detects a signal transmission, it can immediately turn on the first switch circuit 40.

[0174] During the interrupt service, the main control chip 10 outputs a high level to the control terminal of the first switching circuit 40. At this time, the fifth transistor Q5 receives the high level and turns on, causing the potential of the first terminal of the fifth transistor Q5 to be pulled down to the potential of the ground terminal, which is a low level. The control terminal of the sixth transistor Q6 is electrically connected to the first terminal of the fifth transistor Q5, so the potential of the control terminal of the sixth transistor Q6 is also a low level. The sixth transistor Q6 receives the low level and turns on, so the single-ended signal from the first output terminal HBS1-Out of the first conversion circuit can be transmitted from the first terminal of the first switching circuit 40 to the second terminal of the first switching circuit 40, and then the single-ended signal is transmitted to the second control circuit 30. The second control circuit converts the single-ended signal into a differential signal and transmits the differential signal to the second bus 200, thereby completing the signal transmission from the first bus 100 to the second bus 200.

[0175] After a complete byte is transmitted on the first bus 100, the first receiving terminal UART1-RXD of the main control chip 10 will trigger a receive interrupt. During this interrupt service, the main control chip 10 will output a low level to the control terminal of the first switching circuit 40, causing the first switching circuit 40 to disconnect. The above control process completes the transmission of a complete byte of information from the first bus 100 to the second bus 200.

[0176] The function of the first receiver, UART1_RXD, is to determine when a complete byte has been relayed and to restore the repeater to an idle state. This idle state restoration is completed within the interrupt service routine triggered by the first receiver, UART1_RXD. At this point, the repeater is essentially disconnected and cannot transmit signals until the next byte signal arrives.

[0177] like Figure 16 As shown, the second control circuit 30 includes: a second conversion circuit 31 and a second comparison circuit 32.

[0178] The second conversion circuit 31 includes: a first terminal 311, a second terminal 312, a first output terminal HBS2-Out, and a first input terminal HBS2-In.

[0179] The first terminal 311 of the second conversion circuit 31 is electrically connected to the first terminal 301 of the second control circuit 30, the second terminal 312 of the second conversion circuit 31 is electrically connected to the second terminal 302 of the second control circuit 30, the first output terminal HBS2-Out of the second conversion circuit 31 is electrically connected to the first output terminal 303 of the second control circuit 30, and the first input terminal HBS2-In of the second conversion circuit 31 is electrically connected to the first input terminal 305 of the second control circuit 30.

[0180] The second comparator circuit 32 includes a first input terminal 321, a second input terminal 322, and an output terminal 323.

[0181] The first input terminal 321 of the second comparison circuit 32 is electrically connected to the first output terminal HBS2-Out of the second conversion circuit 31, the second input terminal 322 of the second comparison circuit 32 is electrically connected to the first input terminal HBS2-In of the second conversion circuit 31, and the output terminal 323 of the second comparison circuit 32 is electrically connected to the second detection terminal HBS2-Diff of the main control chip 10.

[0182] The second conversion circuit 31 is configured to convert the differential signal from the second bus 200 into a single-ended signal and convert the single-ended signal from the first control circuit 20 into a differential signal for transmission to the second bus 200.

[0183] During the transmission of signals from the first bus to the second bus, the second comparison circuit 32 is configured to compare whether the signal at the first output terminal HBS2-Out of the second conversion circuit 31 is the same as the signal at the first input terminal HBS2-In; if they are different, the main control chip 10 is configured to control the first switching circuit 40 to disconnect.

[0184] In some embodiments, the second comparison circuit 32 is an XOR gate circuit, mainly used to detect whether the signal at the first output terminal HBS2-Out and the signal at the first input terminal HBS2-In of the second conversion circuit 31 are the same. If they are the same, a low level "0" is output; if they are different, a high level "1" is output.

[0185] The second switching circuit 50 is configured to turn on when the main control chip 10 receives a signal from the first output terminal HBS2-Out of the second conversion circuit 31.

[0186] For example, the second bus 200 transmits the differential signal to the first terminal 301 and the second terminal 302 of the second control circuit 30, and then transmits the differential signal to the first terminal 311 and the second terminal 312 of the second conversion circuit 31. The second conversion circuit 31 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS2-Out to the second receiving terminal UART2-RXD of the main control chip 10 and the second external interrupt terminal MCU-IRQ2 of the main control chip 10.

[0187] Among them, the second receiving terminal UART2-RXD of the main control chip 10 will generate a serial port receive interrupt after receiving a complete byte.

[0188] The second external interrupt terminal MCU-IRQ2 of the main control chip 10 is configured to be triggered by the falling edge. Once the first output terminal HBS2-Out of the second conversion circuit 31 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection.

[0189] At this time, the second control terminal Switch2 of the main control chip 10 outputs a high level, which turns on the second switch circuit 50, so that the single-ended signal can be transmitted to the first control circuit.

[0190] The specific process is as follows: The second bus 200 transmits the differential signal to the first terminal 311 and the second terminal 312 of the second conversion circuit 31. The second conversion circuit 31 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS2-Out to the second external interrupt terminal MCU-IRQ2 of the main control chip 10. The first external interrupt terminal MCU-IRQ2 of the main control chip 10 is configured to be triggered by a falling edge. Once the first output terminal HBS2-Out of the second conversion circuit 31 has a signal output, it will be detected immediately, thereby causing the second control terminal Switch2 of the main control chip 10 to output a high level, thus turning on the second switch circuit 50. The single-ended signal is then transmitted to the first control circuit 20.

[0191] For the second control circuit, the above process refers to the transmission of the differential signal from the second bus 200 to the first bus 100; and the specific process of the transmission of the differential signal from the first bus 100 to the second bus 200 is as follows.

[0192] The first input terminal 305 of the second conversion circuit 31 receives a single-ended signal from the first control circuit 20. The second conversion circuit 31 converts the single-ended signal from the first control circuit 20 into a differential signal. While transmitting the differential signal to the second bus 200 via the first terminal 311 and the second terminal 312 of the second conversion circuit 31, the differential signal is converted back into a single-ended signal and compared with the single-ended signal from the first control circuit 20 via the second comparison circuit.

[0193] If the signals from both are the same, it means that the signal only comes from the first bus and no signal is transmitted to the repeater from the second bus. The second output terminal 323 of the second comparator circuit 32 outputs a low level to the second detection terminal HBS2-Diff of the main control chip 10. The main control chip 10 will work normally if it detects the low level.

[0194] If the two signals are different, it means that the signal comes not only from the first bus, but also from the second bus. The second output terminal 223 of the first comparison circuit 22 outputs a high level to the first detection terminal HBS1-Diff of the main control chip 10. The main control chip 10 detects the high level and determines that a communication conflict has occurred.

[0195] After a collision is detected, the main control chip 10 will control the first switching circuit 40 to disconnect. Then, the main control chip 10 will send a blocking signal 0XAA through the second transmitting terminal UART2-TXD. The blocking signal will be sent to the first input terminal 205 of the first control circuit 20 and the first input terminal 305 of the second control circuit 30. Through the conversion of the first control circuit 20 and the second control circuit 30, the blocking signal will be transmitted to the first bus 100 and the second bus 200 on both sides of the repeater 400.

[0196] After the blocking signal is sent to the first bus 100 and the second bus 200, the communication nodes on both sides of the repeater 400 will detect a communication conflict. According to the CSMA / CD principle, the communication nodes on both sides will stop sending data to the first bus and the second bus, and enter the communication logic of contending for the bus again after a random delay.

[0197] When the repeater 400 feeds back the blocking signal 0XAA to the first bus 100 and the second bus 200 on both sides, the first transmitting terminal UART1-TXD and the second transmitting terminal UART2-TXD of the main control chip synchronously receive data from the first output terminal 203 of the first control circuit 20 and the first output terminal 303 of the second control circuit 30. This continues until both the first receiving terminal UART1-RXD and the second receiving terminal UART2-RXD receive the blocking signal 0XAA on the bus. At this point, the blocking is considered successful. Otherwise, the main control chip 10 continues to send blocking signals to the first bus 100 and the second bus 200. After successful blocking, the main control chip 10 controls the repeater to return to its normal state (i.e., the repeater is in an idle state).

[0198] like Figure 17 As shown, the second conversion circuit 31 includes: a second receiving coupling circuit 34, a second transmitting coupling circuit 35, and a second driver chip IC2.

[0199] The first terminal 341 of the second receiving coupling circuit 34 is electrically connected to the first terminal 311 of the second conversion circuit 31, and the second terminal 342 of the second receiving coupling circuit 34 is electrically connected to the second terminal 312 of the second conversion circuit 31.

[0200] The first terminal 351 of the second transmitting coupling circuit 35 is electrically connected to the first terminal 311 of the second conversion circuit 31, and the second terminal 352 of the second transmitting coupling circuit 35 is electrically connected to the second terminal 312 of the second conversion circuit 31.

[0201] The first input terminal IN21 of the second driver chip IC2 is electrically connected to the third terminal 343 of the second receiving coupling circuit 34; the second input terminal IN22 of the second driver chip IC2 is electrically connected to the fourth terminal 344 of the second receiving coupling circuit 34; the first output terminal OutB of the second driver chip IC2 is electrically connected to the third terminal 353 of the second transmitting coupling circuit 35; and the second output terminal OutA of the second driver chip IC2 is electrically connected to the fourth terminal 354 of the second transmitting coupling circuit 35.

[0202] The third output terminal Out of the second driver chip IC2 is electrically connected to the first output terminal HBS2-Out of the second conversion circuit 31, and the third input terminal IN of the second driver chip IC2 is electrically connected to the first input terminal HBS2-In of the second conversion circuit 31.

[0203] The second driver chip IC2 is configured to convert differential signals from the second bus 200 into single-ended signals and single-ended signals from the first bus 100 into differential signals.

[0204] For example, the second bus 200 transmits the differential signal via the second receiving coupling circuit 34 to the first input terminal IN21 and the second input terminal IN22 of the second driver chip IC2. The second driver chip IC2 converts the differential signal into a single-ended signal and transmits it from the first output terminal HBS2-Out to the second receiving terminal UART2-RXD of the main control chip 10 and the second external interrupt terminal MCU-IRQ2 of the main control chip 10.

[0205] After the second receiving terminal UART2-RXD of the main control chip 10 receives a complete byte, it generates a serial port receive interrupt. The second external interrupt terminal MCU-IRQ2 of the main control chip 10 is configured to be triggered by a falling edge. Once the first output terminal HBS2-Out of the second conversion circuit 31 has a signal output, it will be detected immediately, thus realizing carrier detection in carrier sense multiple access / collision detection. At this time, the second control terminal Switch2 of the main control chip 10 outputs a high level, which turns on the second switching circuit 50, thereby allowing the single-ended signal to be transmitted to the first control circuit.

[0206] The second receiving coupling circuit 34 is configured to remove the DC component from the differential signal from the second bus and couple the differential signal to the second driver chip IC2 for amplification, thereby enhancing the weak differential signal.

[0207] Similarly, the second transmitting coupling circuit 35 is configured to remove the DC component from the differential signal from the first bus, and the differential signal is amplified by the second driver chip IC2. The amplified signal can also be output through coupling, thus realizing the transmission of signal and energy.

[0208] In some embodiments, the second receiving coupling circuit 34 and the second transmitting coupling circuit 35 can also suppress low-frequency interference.

[0209] like Figure 18 As shown, the second receiving coupling circuit 34 includes a fifth capacitor C5 and a sixth capacitor C6.

[0210] The first end of the fifth capacitor C5 is electrically connected to the first end of the second receiving coupling circuit 34, and the second end of the fifth capacitor C5 is electrically connected to the third end of the second receiving coupling circuit 34.

[0211] The first terminal of the sixth capacitor C6 is electrically connected to the second terminal of the second receiving coupling circuit 34, and the second terminal of the sixth capacitor C6 is electrically connected to the fourth terminal of the second receiving coupling circuit 34.

[0212] like Figure 19 As shown, the second transmitting coupling circuit 35 includes a seventh capacitor C7 and an eighth capacitor C8.

[0213] The first terminal of the seventh capacitor C7 is electrically connected to the first terminal 351 of the second transmitting coupling circuit 35, and the second terminal of the seventh capacitor C7 is electrically connected to the third terminal 353 of the second transmitting coupling circuit 35.

[0214] The first terminal of the eighth capacitor C8 is electrically connected to the second terminal 352 of the second transmitting coupling circuit 35, and the second terminal of the seventh capacitor C7 is electrically connected to the fourth terminal 354 of the second transmitting coupling circuit 35.

[0215] like Figure 20 As shown, the second conversion circuit 31 also includes a second bus drive circuit 36.

[0216] The first terminal 361 of the second bus driver circuit 36 ​​is electrically connected to the third output terminal Outb of the second driver chip IC2; the second terminal 362 of the second bus driver circuit 36 ​​is electrically connected to the fourth output terminal Outa of the second driver chip IC2; the third terminal 363 of the second bus driver circuit 36 ​​is electrically connected to the first output terminal OutB of the second driver chip IC2; the fourth terminal 364 of the second bus driver circuit 36 ​​is electrically connected to the second output terminal OutA of the second driver chip IC2; and the fifth terminal 365 and the sixth terminal 366 of the second bus driver circuit 36 ​​are electrically connected to the ground terminal GND.

[0217] like Figure 21 As shown, the second bus drive circuit 36 ​​includes a third transistor Q3 and a fourth transistor Q4.

[0218] The control terminal of the third transistor Q3 is electrically connected to the first terminal 361 of the second bus drive circuit 36, the first terminal of the third transistor Q3 is electrically connected to the third terminal 363 of the second bus drive circuit 36, and the second terminal of the third transistor Q3 is electrically connected to the fifth terminal 365 of the second bus drive circuit 36.

[0219] The control terminal of the fourth transistor Q4 is electrically connected to the second terminal 362 of the second bus drive circuit 36, the first terminal of the fourth transistor Q4 is electrically connected to the fourth terminal 364 of the second bus drive circuit 36, and the second terminal of the fourth transistor Q4 is electrically connected to the sixth terminal 366 of the second bus drive circuit 36.

[0220] like Figure 22 As shown, the second switching circuit 50 includes: a seventh transistor Q7, an eighth transistor Q8, and a second resistor R2.

[0221] The control terminal of the seventh transistor Q7 is electrically connected to the control terminal of the first switching circuit 40; the second terminal of the seventh transistor Q7 is electrically connected to the ground terminal.

[0222] The control terminal of the eighth transistor Q8 is electrically connected to the first terminal of the seventh transistor Q7, the first terminal of the eighth transistor Q8 is electrically connected to the first terminal of the second switching circuit 50, and the second terminal of the eighth transistor Q8 is electrically connected to the second terminal of the second switching circuit 50.

[0223] The first end of the second resistor R2 is electrically connected to the first end of the second switching circuit 50, and the second end of the second resistor R2 is electrically connected to the first end of the seventh transistor Q7.

[0224] In some embodiments, the seventh transistor Q7 is an NMOS transistor, and the eighth transistor Q8 is a PMOS transistor. The NMOS transistor is turned on when it receives a high level and turned off when it receives a low level; the PMOS transistor is turned off when it receives a high level and turned on when it receives a low level.

[0225] For example, if the second bus 200 has a differential signal but the first bus 100 does not, the second bus 200 transmits the differential signal to the first terminal 301 and the second terminal 302 of the second control circuit 30, and then transmits the differential signal to the first terminal 311 and the second terminal 312 of the second conversion circuit 31. The second conversion circuit 31 converts the differential signal into a single-ended signal and transmits it from the second output terminal HBS2-Out to the second receiving terminal UART2-RXD of the main control chip 10 and the second external interrupt terminal MCU-IRQ2 of the main control chip 10.

[0226] The second switch circuit 50 is turned on by the interrupt service of the second external interrupt terminal MCU_IRQ2. Once the second external interrupt terminal MCU_IRQ2 detects a signal transmission, it can immediately turn on the second switch circuit 50.

[0227] During the interrupt service, the main control chip 10 outputs a high level to the control terminal of the second switching circuit 50. At this time, the seventh transistor Q7 receives the high level and turns on, causing the potential of the first terminal of the seventh transistor Q7 to be pulled down to the potential of the ground terminal GND, which is a low level. The control terminal of the eighth transistor Q8 is electrically connected to the first terminal of the seventh transistor Q7, so the potential of the control terminal of the eighth transistor Q8 is also a low level. The eighth transistor Q8 receives the low level and turns on, so the single-ended signal from the first output terminal HBS2-Out of the second conversion circuit can be transmitted from the first terminal of the second switching circuit 50 to the second terminal of the second switching circuit 50, and then the single-ended signal is transmitted to the first control circuit 20. The first control circuit 20 converts the single-ended signal into a differential signal and transmits the differential signal to the first bus 100, thereby completing the signal transmission from the second bus 200 to the first bus 100.

[0228] After a complete byte is transmitted on the second bus 200, the second receiver terminal UART2-RXD of the main control chip 10 will trigger a receive interrupt. During this interrupt service, the main control chip 10 will output a low level to the control terminal 501 of the second switching circuit 50, causing the second switching circuit 50 to disconnect. The above control process completes the transmission of a complete byte of information from the second bus 200 to the first bus 100.

[0229] The function of the second receiver, UART2_RXD, is to determine when a complete byte has been relayed and to restore the repeater to an idle state. This idle state restoration is completed within the interrupt service routine triggered by the second receiver, UART2_RXD. At this point, the repeater is essentially disconnected and cannot transmit signals until the next byte signal arrives.

[0230] In summary, some embodiments of this application provide a central air conditioning system in which the repeater uses carrier detection and collision detection to achieve signal transmission and collision feedback. When there is a signal on only one side of the bus, the signal can be transmitted to the other side in real time. By generating a serial port receive interrupt through the main control chip, it can be determined that a complete byte has been relayed, allowing the repeater to return to its normal idle state. At the same time, when there is signal transmission on both sides, the corresponding switching circuit can be turned off by the main control chip to block signal transmission. Carrier detection and collision detection ensure that even if two or more nodes start sending data simultaneously, the entire network will not fall into an infinite loop of collision. Furthermore, the blocking signal issued by the main control chip can cause the air conditioning system to stop sending data and enter the communication logic of contending for the bus again after a random delay; this will not cause signal transmission collisions. Further, when multiple air conditioning systems transmit signals over long distances, the signal will gradually weaken. By converting the differential signal into a single-ended signal through the repeater, the waveform of the signal can be shaped and the signal can be enhanced. Then, the single-ended signal can be converted into a differential signal suitable for air conditioning system communication to complete long-distance communication.

[0231] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A central air conditioning system, characterized in that, The central air conditioning system includes: The first bus is configured to transmit differential signals; The second bus is configured to transmit differential signals; Repeater, including: Main control chip; A first control circuit, wherein the signal terminal of the first control circuit is electrically connected to the first bus; and the second output terminal of the first control circuit is electrically connected to the first detection terminal of the main control chip. The second control circuit has its signal terminal electrically connected to the second bus; the second output terminal of the second control circuit is electrically connected to the second detection terminal of the main control chip. A first switching circuit, wherein the control terminal of the first switching circuit is electrically connected to the first control terminal of the main control chip; the first switching circuit is electrically connected between the first output terminal of the first control circuit and the first input terminal of the second control circuit; the first output terminal of the first control circuit and the first input terminal of the second control circuit are configured to transmit single-ended signals. The second switching circuit has its control terminal electrically connected to the second control terminal of the main control chip; the second switching circuit is electrically connected between the first output terminal of the second control circuit and the first input terminal of the first control circuit; the first output terminal of the second control circuit and the first input terminal of the first control circuit are configured to transmit single-ended signals. The first control circuit is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal is the same as the signal at the first input terminal, and transmit the first result signal to the first detection terminal; if not, the main control chip is configured to control the second switching circuit to disconnect. The second control circuit is configured to convert differential signals and single-ended signals, compare whether the signal at the first output terminal is the same as the signal at the first input terminal, and transmit the second result signal to the second detection terminal; if not, the main control chip is configured to control the first switching circuit to disconnect.

2. The central air conditioning system according to claim 1, characterized in that, The first transmitting end of the main control chip is electrically connected to the first input end of the first control circuit, and the second transmitting end of the main control chip is electrically connected to the first input end of the second control circuit. When the signal at the first output terminal and the signal at the first input terminal of the first control circuit are different, the main control chip is configured to output a blocking signal to the first input terminal of the first control circuit and the first input terminal of the second control circuit. When the signal at the first output terminal and the signal at the first input terminal of the second control circuit are different, the main control chip is configured to output a blocking signal to the first input terminal of the first control circuit and the first input terminal of the second control circuit.

3. The central air conditioning system according to claim 2, characterized in that, The first output terminal of the first control circuit is also electrically connected to the first receiving terminal and the first external interrupt terminal of the main control chip; the first output terminal of the second control circuit is also electrically connected to the second receiving terminal and the second external interrupt terminal of the main control chip. The main control chip is also configured to control the first switching circuit to turn on when it receives a single-ended signal from the first output terminal of the first control circuit; and to control the second switching circuit to turn on when it receives a single-ended signal from the first output terminal of the second control circuit.

4. The central air conditioning system according to any one of claims 1 to 3, characterized in that, The first bus includes: a first bus and a second bus; the signal terminals of the first control circuit include: a first terminal and a second terminal; the first control circuit includes: A first conversion circuit, wherein a first terminal of the first conversion circuit is electrically connected to a first terminal of the first control circuit, a second terminal of the first conversion circuit is electrically connected to a second terminal of the first control circuit, a first output terminal of the first conversion circuit is electrically connected to a first output terminal of the first control circuit, and a first input terminal of the first conversion circuit is electrically connected to a first input terminal of the first control circuit. A first comparison circuit, wherein the first input terminal of the first comparison circuit is electrically connected to the first output terminal of the first conversion circuit, the second input terminal of the first comparison circuit is electrically connected to the first input terminal of the first conversion circuit, and the output terminal of the first comparison circuit is electrically connected to the second output terminal of the first control circuit. The first conversion circuit is configured to convert the differential signal and the single-ended signal; The first comparison circuit is configured to compare whether the signal at the first output terminal of the first conversion circuit is the same as the signal at the first input terminal, and transmit the first result signal to the first detection terminal; if not, the main control chip is configured to control the second switching circuit to open.

5. The central air conditioning system according to claim 4, characterized in that, The first conversion circuit includes: A first receiving coupling circuit, wherein a first terminal of the first receiving coupling circuit is electrically connected to a first terminal of the first conversion circuit, and a second terminal of the first receiving coupling circuit is electrically connected to a second terminal of the first conversion circuit. A first transmitting coupling circuit, wherein a first terminal of the first transmitting coupling circuit is electrically connected to a first terminal of the first conversion circuit, and a second terminal of the first transmitting coupling circuit is electrically connected to a second terminal of the first conversion circuit; A first driver chip, wherein a first input terminal of the first driver chip is electrically connected to a third terminal of the first receiving coupling circuit, a second input terminal of the first driver chip is electrically connected to a fourth terminal of the first receiving coupling circuit, a first output terminal of the first driver chip is electrically connected to a third terminal of the first transmitting coupling circuit, and a second output terminal of the first driver chip is electrically connected to a fourth terminal of the first transmitting coupling circuit. The first driver chip is configured to convert differential signals from the first bus into single-ended signals and single-ended signals from the second control circuit into differential signals.

6. The central air conditioning system according to claim 5, characterized in that, The first receiving coupling circuit includes: A first capacitor, wherein a first terminal of the first capacitor is electrically connected to a first terminal of the first receiving coupling circuit, and a second terminal of the first capacitor is electrically connected to a third terminal of the first receiving coupling circuit. The second capacitor has its first terminal electrically connected to the second terminal of the first receiving coupling circuit, and its second terminal electrically connected to the fourth terminal of the first receiving coupling circuit. The first transmitting coupling circuit includes: The third capacitor has its first terminal electrically connected to the first terminal of the first transmitting coupling circuit, and its second terminal electrically connected to the second terminal of the first transmitting coupling circuit. The fourth capacitor has its first terminal electrically connected to the first terminal of the first transmitting coupling circuit, and the second terminal of the third capacitor is electrically connected to the second terminal of the first transmitting coupling circuit.

7. The central air conditioning system according to claim 6, characterized in that, The first conversion circuit further includes: a first bus driving circuit; The first terminal of the first bus driving circuit is electrically connected to the third output terminal of the first driving chip; the second terminal of the first bus driving circuit is electrically connected to the fourth output terminal of the first driving chip; the third terminal of the first bus driving circuit is electrically connected to the first output terminal of the first driving chip; the fourth terminal of the first bus driving circuit is electrically connected to the second output terminal of the first driving chip; the fifth and sixth terminals of the first bus driving circuit are electrically connected to the ground terminal; the first bus driving circuit includes: The first transistor has its control terminal electrically connected to the first terminal of the first bus driving circuit, its first terminal electrically connected to the third terminal of the first bus driving circuit, and its second terminal electrically connected to the fifth terminal of the first bus driving circuit. The second transistor has its control terminal electrically connected to the second terminal of the first bus driving circuit, its first terminal electrically connected to the fourth terminal of the first bus driving circuit, and its second terminal electrically connected to the sixth terminal of the first bus driving circuit.

8. The central air conditioning system according to any one of claims 1 to 3, characterized in that, The first switching circuit includes: a fifth transistor, a sixth transistor, and a first resistor; The control terminal of the fifth transistor is electrically connected to the control terminal of the first switching circuit; the second terminal of the fifth transistor is electrically connected to the ground terminal. The control terminal of the sixth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the sixth transistor is electrically connected to the first terminal of the first switching circuit, and the second terminal of the sixth transistor is electrically connected to the second terminal of the first switching circuit. The first end of the first resistor is electrically connected to the first end of the first switching circuit, and the second end of the first resistor is electrically connected to the first end of the fifth transistor.

9. The central air conditioning system according to any one of claims 1 to 3, characterized in that, The second bus includes: a first second bus and a second second bus; the signal terminals of the second control circuit include: a first terminal and a second terminal; the second control circuit includes: The second conversion circuit has a first terminal electrically connected to the first terminal of the second control circuit, a second terminal electrically connected to the second terminal of the second control circuit, a first output terminal electrically connected to the first output terminal of the second control circuit, and a first input terminal electrically connected to the first input terminal of the second control circuit. The second comparison circuit has its first input terminal electrically connected to the first output terminal of the second conversion circuit, its second input terminal electrically connected to the first input terminal of the second conversion circuit, and its output terminal electrically connected to the second output terminal of the second control circuit. The second conversion circuit is configured to convert the differential signal and the single-ended signal; The second comparison circuit is configured to compare whether the signal at the first output terminal and the signal at the first input terminal of the second conversion circuit are the same, and transmit the first result signal to the second detection terminal; if not, the main control chip is configured to control the first switching circuit to disconnect.

10. The central air conditioning system according to claim 9, characterized in that, The second conversion circuit includes: The second receiving coupling circuit has a first terminal electrically connected to the first signal input terminal of the second conversion circuit, and a second terminal electrically connected to the second signal input terminal of the second conversion circuit. The second transmitting coupling circuit has a first terminal electrically connected to the first signal input terminal of the second conversion circuit, and a second terminal electrically connected to the second signal input terminal of the second conversion circuit. The second driver chip has a first input terminal electrically connected to the third terminal of the second receiving coupling circuit, a second input terminal electrically connected to the fourth terminal of the second receiving coupling circuit, a first output terminal electrically connected to the third terminal of the second transmitting coupling circuit, and a second output terminal electrically connected to the fourth terminal of the second transmitting coupling circuit. The second driver chip is configured to convert differential signals from the second bus into single-ended signals and single-ended signals from the first control circuit into differential signals.

11. The central air conditioning system according to claim 10, characterized in that, The second receiving coupling circuit includes: The fifth capacitor has its first terminal electrically connected to the first terminal of the second receiving coupling circuit, and its second terminal electrically connected to the third terminal of the second receiving coupling circuit. The sixth capacitor has its first terminal electrically connected to the second terminal of the second receiving coupling circuit, and its second terminal electrically connected to the fourth terminal of the second receiving coupling circuit. The second transmitting coupling circuit includes: A seventh capacitor, wherein the first terminal of the seventh capacitor is electrically connected to the first terminal of the second transmitting coupling circuit, and the second terminal of the seventh capacitor is electrically connected to the second terminal of the second transmitting coupling circuit; The eighth capacitor has its first terminal electrically connected to the first terminal of the second transmitting coupling circuit, and the second terminal of the seventh capacitor is electrically connected to the second terminal of the second transmitting coupling circuit.

12. The central air conditioning system according to claim 11, characterized in that, The second conversion circuit further includes: a second bus driving circuit; The first terminal of the second bus driving circuit is electrically connected to the third output terminal of the second driving chip; the second terminal of the first bus driving circuit is electrically connected to the fourth output terminal of the second driving chip; the third terminal of the second bus driving circuit is electrically connected to the first output terminal of the second driving chip; the fourth terminal of the second bus driving circuit is electrically connected to the second output terminal of the second driving chip; the fifth and sixth terminals of the second bus driving circuit are electrically connected to the ground terminal; the second bus driving circuit includes: The third transistor has its control terminal electrically connected to the first terminal of the second bus driving circuit, its first terminal electrically connected to the third terminal of the second bus driving circuit, and its second terminal electrically connected to the fifth terminal of the second bus driving circuit. The fourth transistor has its control terminal electrically connected to the second terminal of the second bus driving circuit, its first terminal electrically connected to the fourth terminal of the second bus driving circuit, and its second terminal electrically connected to the sixth terminal of the second bus driving circuit.

13. The central air conditioning system according to any one of claims 1 to 3, characterized in that, The second switching circuit includes: a seventh transistor, an eighth transistor, and a second resistor; The seventh transistor has its control terminal electrically connected to the control terminal of the first switching circuit; the second terminal of the seventh transistor is electrically connected to the ground terminal. The eighth transistor has its control terminal electrically connected to the first terminal of the seventh transistor, its first terminal electrically connected to the first terminal of the second switching circuit, and its second terminal electrically connected to the second terminal of the second switching circuit. The second resistor has its first end electrically connected to the first end of the second switching circuit, and its second end electrically connected to the first end of the seventh transistor.

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