Adaptive multichannel sequencer for power management integrated circuits

Abstract

A PMIC includes a controller configured to determine a power-on mode based on a configuration stored in a memory, the power-on mode indicating a dynamic power-on operation when the power-on mode indicates the dynamic power-on operation. The dynamic power-on operation is performed by determining a first channel of a plurality of channels associated with a first dynamic sequence number that is a lowest dynamic sequence number of a plurality of dynamic sequence numbers, enabling the first channel, monitoring the first channel to determine whether the first channel is in a first voltage stabilization state, and determining a second channel associated with a second dynamic serial number in the plurality of dynamic serial numbers in the plurality of channels when the first channel is monitored; when the power-on pattern indicates a time-based power-on operation: causing a slot counter to traverse a plurality of slot numbers.

Description

Technical Field

[0001] This disclosure relates to power management in electronic circuits, and to power management integrated circuits for use in electronic devices. Background Technology

[0002] A power management integrated circuit (PMIC) is a device configured to manage the power supply to various components of an electronic device. For example, in a vehicle platform, a PMIC can be provided to manage the power supply to components of various vehicle subsystems, such as automotive infotainment systems, vehicle safety systems (e.g., vehicle radar systems and telematics), and other components such as sensors, communication interfaces, and other devices. PMICs can be applied to other types of electronic devices, such as mobile devices, industrial equipment, and other devices requiring power management and, particularly, a reliable power supply at varying voltages, where the PMIC can serve as a power source for different components of the electrical device. Summary of the Invention

[0003] The summary portion of this invention is neither intended nor should be construed as representing the full extent and scope of this disclosure. Additional benefits, features, and embodiments of this disclosure are set forth in the accompanying drawings and the description below, and as claimed. Therefore, it should be understood that the summary portion may not encompass all aspects and embodiments claimed herein.

[0004] Furthermore, the disclosure herein is not intended to limit or constrain in any way. Moreover, this disclosure is intended to provide those skilled in the art with an understanding of one or more representative embodiments supporting the claims. Therefore, it is important that the claims be considered within the scope of constructions having various features including those of this disclosure, provided that such constructions do not depart from the scope of the methods and apparatus consistent with this disclosure (including the initially filed claims). Furthermore, this disclosure is intended to cover and include obvious improvements and modifications to this disclosure.

[0005] In some aspects, the technology described herein relates to a power management integrated circuit, the power management integrated circuit comprising: a power input terminal; a plurality of power output terminals, wherein each of the power output terminals is associated with a channel among a plurality of channels; a memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each channel among the plurality of channels; and a controller configured to: receive a control input indicating that a power-on operation should be performed; determine a power-on mode based on the configuration stored in the memory; and perform the dynamic power-on operation by means of the power-on mode indicating a dynamic power-on operation. Power-on operation: Identify a first channel among the plurality of channels associated with a first dynamic sequence number that is the lowest dynamic sequence number among the plurality of dynamic sequence numbers, enable the first channel, monitor the first channel to determine whether the first channel is in a first regulated state, and while monitoring the first channel, identify a second channel among the plurality of channels associated with a second dynamic sequence number among the plurality of dynamic sequence numbers; when the power-on mode indicates a time-based power-on operation: cause a time slot counter to traverse the plurality of time slot numbers; and when the current value of the time slot counter is equal to the time slot number associated with a third channel among the plurality of channels in the configuration data, enable the third channel.

[0006] In some aspects, the technology described herein relates to a power management integrated circuit, the power management integrated circuit comprising: a power input terminal; a plurality of power output terminals, wherein each of the power output terminals is associated with a channel among a plurality of channels; a memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each channel among the plurality of channels; and a controller configured to perform a dynamic device power-on operation by: determining a first channel among the plurality of channels associated with a first dynamic sequence number that is the lowest dynamic sequence number among the plurality of dynamic sequence numbers, enabling the first channel, monitoring the first channel to determine whether the first channel is in a first regulated state, determining a second channel among the plurality of channels associated with a second dynamic sequence number among the plurality of dynamic sequence numbers while monitoring the first channel, determining that the first channel is in the first regulated state, and enabling the second channel.

[0007] In some aspects, the technology described herein relates to a method comprising: determining a first channel among a plurality of channels of a power management integrated circuit that is associated with a first dynamic serial number in the memory of the power management integrated circuit, wherein the first dynamic serial number is the lowest dynamic serial number among the plurality of dynamic serial numbers; enabling the first channel; monitoring the first channel to determine whether the first channel is in a first regulated state of a specified voltage value; while monitoring the first channel, determining a second channel among the plurality of channels that is associated with a second dynamic serial number among the plurality of dynamic serial numbers; determining that the first channel is in the first regulated state; and enabling the second channel. Attached Figure Description

[0008] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] In the attached diagram:

[0010] Figure 1 It is a circuit diagram depicting an electrical device that includes a power management integrated circuit.

[0011] Figure 2 It is a flowchart depicting a method that can be implemented by a controller to perform a time-based power-on operation.

[0012] Figure 3 It is a flowchart depicting a method that can be implemented by a controller to perform dynamic power-on operations on the device.

[0013] Figure 4 This is a diagram illustrating how the dynamic sequencing method according to the present invention can enable channels.

[0014] Figure 5 It is a block diagram depicting the functional components of a controller configured to perform time-based and dynamic power-on and power-off operations as disclosed herein.

[0015] Figure 6 It is a circuit diagram depicting a system configured to selectively enable and / or disable channels of the PMIC based on dynamic power-on operation. Detailed Implementation

[0016] This disclosure relates to power management in electronic circuits, and more particularly to a power management integrated circuit (PMIC) for use in an electronic device. A PMIC is a circuit configured to manage the electrical power supply to various components of an electrical device. The PMIC is configured to generate output signals on various channels, wherein the signals output at each channel may have different electrical characteristics, such as different voltages. These various signals can then be supplied to different components of the device, which may require different power signals for their respective operations.

[0017] For example, a PMIC that is part of the vehicle's electrical system can generate different power signals at different output channels. These power signals can be used to supply power to the vehicle's entertainment system at one voltage, to the vehicle's radar system at another voltage, and to the vehicle's telematics system at yet another voltage.

[0018] In many cases, it is desirable to power on various components of a particular electronic device in a specific sequence. For each channel of the PMIC in use, this sequence should allow each channel to reach its designated regulated voltage before another channel is enabled and other components are powered on. Similarly, when the device transitions from a powered-on state to a powered-off state, the PMIC can be configured to implement a specific power-down sequence, where the PMIC channels are deactivated in a predetermined sequence (in many cases, the reverse of the order in which time slots are enabled) to allow for the implementation of an appropriate power-down sequence for the device. In some cases, the PMIC can be used to manage the power supply to device components as part of other power state transitions, such as when the device transitions from a standby state to a powered-on or powered-off state, and from a powered-on or powered-off state back to a standby state.

[0019] In typical applications, the various channels of a particular PMIC can be used to provide a variety of functions, including providing power to enable specific device components to operate (e.g., in a power signal), or powering specific input / output (IO) channels of the device to enable monitoring operations, etc.

[0020] When providing this functionality, enabling and disabling PMIC channel groups may require precise sequencing during device power-up and / or power-down transitions to allow proper operation of various device components and subsystems powered and controlled by the PMIC. This precise sequencing also provides predictability to allow multiple additional independent PMICs to operate in parallel, thereby creating larger and more scalable power architectures for a variety of systems and applications.

[0021] The high level of flexibility offered by PMICs (particularly in terms of enabling and disabling different PMIC channels to implement desired power-up or power-down sequences) can be beneficial due to the diversity of devices and applications that can utilize them. This flexibility allows PMICs to meet different requirements depending on the application and the specific operating conditions of each application or device in which the PMIC operates. Such requirements may prioritize speed, confirmed channel or time slot availability, and timing compatibility across platforms among many other factors.

[0022] To address these needs, highly configurable PMICs offer a variety of dynamic sequencing strategies, enabling specific device channels to be enabled and confirmed as available (i.e., fully powered on and regulated) before other PMIC channels are enabled. PMICs can implement, for example, time-based power-on sequence options, where the timing sequence in which specific channels are enabled is controlled according to a predetermined timing schedule. In such fixed-sequence or fixed-timing implementations, for example, the device power-on process may require the PMIC to traverse multiple time slots (or simply “slots”) at a predetermined rate (e.g., up to approximately 100 or more time slots), where specific output channels are designated to be enabled in specific time slots. As the PMIC traverses available time slots, it determines which channels are enabled in which time slots, and when the PMIC reaches a time slot with associated channels, those channels are enabled at that time. Thus, by associating PMIC channels with specific time slot numbers, a fixed timing sequence can be defined, specifying the order in which certain channels should be enabled and at what time within the sequence during power-on operation. A similar sequence (usually the opposite of the power-on sequence) can be defined, specifying the sequence and timing for deactivating the channel during power-down operations by traversing the time slots in reverse order.

[0023] In contrast to the fixed-time-based sequencing described above, the PMIC of the present invention can be configured to implement "dynamic" sequencing, wherein channels are activated in a predetermined order, but instead of being activated according to a predetermined timing schedule, the channels are activated sequentially based on the previous channel having been fully activated and reaching its regulated voltage. Therefore, this dynamic method still activates channels in a predetermined order, but advances the sequence of channels to be activated as quickly as possible within the predetermined order.

[0024] In the PMIC of this invention, this dynamic sequencing method can be an important capability during device power-up. However, during device power-down, in certain situations, it may be advantageous to use a time-based strategy that provides sufficient discharge time for appropriate channel deactivation.

[0025] To provide this functionality, the PMIC of the present invention is configured to use a register configuration per channel (e.g., a memory structure stored in the PMIC's memory) to determine a default time-slot-based sequencing scheme, which can be used to compute the turn-on sequence in order to improve dynamic power-on sequencing.

[0026] The PMIC of this invention utilizes algorithms to determine the order in which channels are enabled (e.g., via generating a channel “enabled” signal) during device power-up, state-to-state transitions, or power-down transitions. As described herein, this sequencing scheme is configurable and can be combined for aspects of time-based channel selection processes and dynamic channel selection processes that include a state transition sequence (e.g., a power-up sequence) of N channels. In various embodiments, such a PMIC can be configured to control the operation of approximately 16 channels, or more generally, to control the operation of 2 to 20 channels. Various PMICs are contemplated for implementation, utilizing different numbers of channels depending on the specific system or device application. The PMIC can be configured to be implemented with a certain number of time slots (e.g., 100-500 time slots, or in some cases, 255 time slots).

[0027] The PMIC of this invention is thus configured to provide reduced or minimal latency when executing power-up routines, avoiding the relatively large idle time associated with unused time slots in conventional time-based PMIC device power-up procedures, despite the described dynamic sequencing. As described herein, this enables high availability and predictability of power-up behavior, which further enables power-up and power-down synchronization across multiple PMIC devices in a particular application.

[0028] In many PMIC implementations, the number of available channels is less than the number of available time slots. Therefore, if the PMIC of this invention is configured in its dynamic operating mode, as described below, a large number of unused time slots (referred to as “gaps”) can be skipped over a relatively short period to enable back-to-back power-on of non-adjacent channels. As described below, in the PMIC of this invention, this capability is achieved by the PMIC implementing a binary search algorithm on the channels in use to determine which channel among those still to be enabled has the smallest time slot value.

[0029] In this disclosure, the PMIC can perform a binary search algorithm when the previous channel is fully powered on (i.e., during the ramp-up). Thus, by the time the previous channel is fully powered on and reaches its desired regulated voltage, the PMIC, through this parallel execution of the search algorithm, will have identified the next time slot value in the sequence (i.e., the next time slot associated with the channel to be enabled). The channel associated with that time slot can then be enabled without delay after the previous channel has achieved a regulated state. This allows the device power-on sequence to have no delay or minimal delay between the enabling and regulated state of a channel and the enabling of the next channel in the sequence. In some cases, a channel reaching full regulation may require the channel to fulfill a specific set of conditions, including achieving a specific desired voltage followed by a delay allowing the channel's voltage to stabilize, or, in the case of a channel performing input / output operations, determining that the channel has achieved regulation once the channel has been associated and its input buffer has been set to a high value.

[0030] In various embodiments, the PMIC of the present invention allows the timeslot value of any channel to be changed between power-on and power-off transitions. Therefore, the starting point of the power-off sequence may not be known before shutdown. Thus, power-off sequencing may involve determining the highest timeslot value with associated channels, which can be achieved by taking the two's complement of the timeslot value for each channel (essentially inverting all timeslot values), and the power-off operation can be implemented.

[0031] Figure 1 This is a circuit diagram depicting an electrical device 100 including a power management integrated circuit 102. Device 100 includes one or more power sources 104a-104c, which may include a battery, A / C power supply, or other power supply. Device 100 includes multiple components, including an application processor 106, a communication processor 108, an interface unit 110, and a specific function unit 112. Each component is connected to the PMIC 102, such that the PMIC 102 can supply power to the various components through one or more of its available channels.

[0032] exist Figure 1 In this diagram, only power connections are shown between PMIC 102 and the various components 106, 108, 110, and 112, but other connections, such as control signal or data connections, may exist. PMIC 102 is connected to one or more power supplies 104a-104c. PMIC 102 is configured to utilize the various power supplies 104a-104c to generate output electrical supply signals that can be supplied to each of components 106, 108, 110, and 112.

[0033] To enable proper operation of device 100, the PMIC includes a controller 114 and a memory 116. As described herein, memory 116 may include several registers configured to store data indicating specific sequences in which output channels of PMIC 102 should be enabled and / or disabled during various state transitions, such as power-on or power-off operations.

[0034] In device 100, power supplies 104a-104c may include a combination of a main battery, a backup battery, a battery charger, or an A / C power supply. PMIC 102 is configured to use one or more of the power supplies 104a-104c to generate regulated power signals that can be used by various components of device 100. This may involve controller 114 operating PMIC 102 to generate power signals suitable for different power domains (e.g., at different voltages) for use by various components of device 100.

[0035] In an embodiment of PMIC 102, memory 116 is configured to store a table indicating, for each channel of PMIC 102, the timeslot number in which the channel should be enabled as part of a power-on operation, and conversely, the timeslot number in which the channel should be deactivated as part of a device power-down operation. These values ​​are used when PMIC 102 is performing a time-based power-on or power-down operation. Additionally, according to this disclosure, memory 116 also stores values ​​(e.g., 4-bit or 8-bit numeric values) for each channel indicating the order in which a particular channel should be enabled as part of a dynamic process when PMIC 102 performs a dynamic power-on operation.

[0036] Examples of data stored in memory 116 are shown in Table 1 below.

[0037] <![CDATA[ aisle ]]> <![CDATA[ Dynamic serial number ]]> <![CDATA[ Sequential power-on / power-off time slots ]]> <![CDATA[ Dynamic hierarchy ]]> REG1 0000_0010 Time slot 1 Level 1 REG2 0000_0100 Time slot 3 Level 2 REG3 0000_1000 Time slot 7 Level 4 REG4 0000_0111 Time slot 6 Level 3 REG5 0000_1011 Time slot 10 Level 5 GPIO1 0000_1011 Time slot 10 Level 5 GPIO2 0000_0010 Time slot 1 Level 1 GPIO3 0000_0000 Turn off Turn off RSTB 0000_1101 Time slot 12 Level 6

[0038] Table 1

[0039] In Table 1, the first column identifies a specific channel of the PMIC 102, which may include regulated voltage (“REG”) channels and input / output (“GPIO”) channels. For a given channel, the second column identifies a value indicating the order in which the channel should be enabled as part of a dynamic power-on operation. The third column specifies a timeslot number for each channel, at which the corresponding channel should be enabled or disabled as part of a time-based power-on or power-off operation. The fourth column specifies the channel hierarchy, where various defined levels in the hierarchy column indicate the expected sequence in which channels should be enabled or disabled without reference to specific timeslot values. Thus, the hierarchy column describes the sequence in which channels should be enabled during dynamic power-on operations, as described herein.

[0040] In various embodiments, PMIC 102, and specifically, the controller 114 of PMIC 102, is configured to use data stored in memory 116 to implement a time-based power-on procedure. To further illustrate, Figure 2 This is a flowchart depicting a method 200 that can be implemented by controller 114 to perform a time-based power-on operation.

[0041] At block 202, a time-based power-on operation is initiated. In one or more embodiments, the time-based power-on operation is typically initiated by a signal sent by the master PMIC state machine when transitioning from a power-off state to a power-on state. The power-on operation mode will typically be determined by the PMIC's one-time programmable bit (OTP). In the example startup operation, when the device is powered on, the device initiates a fuseloading process, where a predefined device configuration (e.g., according to a configuration file stored in the PMIC's memory) is decoded, wherein the configuration specifies the device's default sequence, voltage, and operating mode. Typically, the device may include input / output pins that can be used (e.g., by applying a specific voltage via an external component) to initiate the power-on process at the system level. At block 204, controller 114 initializes the slot counter to the value 0. After initiating the slot counter at block 202, controller 114 performs two operations in parallel. At block 206, controller 114 is configured to access values ​​stored in memory 116 to determine if any channels are associated with a time slot having a value equal to the current value of slot_counter. If so, controller 114 enables those channels. For example, referring to Table 1 above, if the current value of slot_counter is "7", controller 114 will enable channel "REG3". If the current value of slot_counter is "10", controller 114 will enable channel "REG5" and general purpose input / output 1 "GPIO1". However, if the current value of slot_counter is "9", the controller will not enable any channels as part of executing block 206.

[0042] When determining which channels to enable based on the current value of slot_counter as part of execution block 206, controller 114 is configured at block 208 to wait for a time period slot_duration. The length of slot_duration in typical applications can be 30µs, 120µs, 250µs, 500µs, or other durations. Typically, the slot duration depends on the device's timing requirements and the timing specifications of the channels being used. The duration of slot_duration is usually chosen such that any channel enabled in a given slot can reach its fully regulated voltage before the slot ends.

[0043] Once slot_duration expires, at box 212, it is determined whether all time slots in PMIC 102 have been processed (e.g., whether the current value of slot_counter equals the total number of available time slots in PMIC 102) and / or all time slots are considered powered on (e.g., when PMIC 102 has enabled all regulators configured to be enabled). If so, method 200 ends. If additional time slots remain, the value of slot_counter is incremented at box 214, and method 200 returns to boxes 206 and 208.

[0044] use Figure 2 This method, by associating various channels of PMIC 102 with specific time slots, and due to the implementation of predetermined and fixed time slot durations (i.e., at block 208 of method 200), allows for precise control over the sequence and timing of enabling different channels of PMIC 102. While this time-based method provides a means of precisely specifying the order and sequence in which channels of PMIC 102 are enabled, such methods can lead to system inefficiencies. For example, in many cases, a channel may be enabled and reach its regulated voltage in a shorter time than expected by a time-based sequence. In such cases, other channels could be enabled earlier, but PMIC 102 must wait until an unused time slot has elapsed before enabling another channel.

[0045] During the time-based power-down operation, controller 114 essentially reverses method 200, causing the channels of PMIC 102 to be deactivated in the reverse order of their activation. One way to implement such an algorithm is to take the two's complement of all time slot values ​​(essentially inverting all time slot values) and identify the first (i.e., lowest) inverse time slot value associated with the channel. The time slot values ​​can then be inverted again, where the first inverse time slot value (after inversion) becomes the highest time slot value associated with the channel. Then, Figure 2 The time-based algorithm can be run in reverse, starting with the highest timeslot value and decreasing through all available timeslot numbers to implement a power-off operation. Alternatively, this can be achieved by reversing all timeslot values ​​(essentially reversing the order of the timeslot values) and executing the algorithm. Figure 2 The method is to implement time-based power-down operations, where the time slot in box 206 is powered down instead of powered on.

[0046] Therefore, typically, when a power-down operation is performed, the slot_counter will be initiated to the maximum slot number associated with a specific channel in memory 116. That channel will be deactivated, and the controller 114 will decrement the slot_counter value (i.e., in...). Figure 2(At box 214) (simultaneously implement slot_duration delay) until all channels are deactivated.

[0047] As discussed above, these time-based methods allow for precise control over the timing and sequence of enabling or disabling specific channels within PMIC 102. However, these sequences are fixed, and while they can be efficient when a specific channel is available for enabling, controller 114 must wait until an unused time slot has expired and been incremented before PMIC 102 can initiate the enabling of that channel.

[0048] An alternative and potentially more efficient method for implementing the power-up process of device 100 is the dynamic method. The dynamic method involves enabling channels in a predetermined order, but wherein the channels are enabled as quickly as possible after an earlier channel in the power-up sequence has been enabled and has reached its regulated voltage.

[0049] Figure 3 This is a flowchart depicting a method 300 that can be implemented by controller 114 to perform a dynamic power-on operation of device 100. At block 302, a dynamic power-on operation is initiated. In one or more embodiments, the dynamic power-on operation is initiated by a signal typically sent by the master PMIC state machine when transitioning from a shutdown state to an on state. The power-on mode will typically be determined by a one-time programmable bit (OTP) of the PMIC. In the example startup operation, the device is powered on for the first time. A predefined configuration is decoded, wherein the configuration specifies the device's default sequence, voltage, and operating mode. The device may include input / output pins that can be used (e.g., via applying a specific voltage) to initiate a power-on event at the system level. At block 304, controller 114 is configured to access memory 116 to determine which channels of PMIC 102 have the lowest dynamic sequence number indicating that channel (or channels) should be enabled. In the example of Table 1 above, this would correspond to channels “REG1” and “GPIO2”. After these channels are enabled, controller 114 performs two operations in parallel. At block 306, controller 114 is configured to perform a lookup of memory 116 to determine which channels have the next highest sequence value. In various embodiments, this may involve controller 114 performing a binary lookup of all dynamic sequence numbers in a table of memory 116 to determine the next sequence number associated with a channel that is not yet enabled.

[0050] If no additional channel is identified at box 206, method 200 ends. However, if a channel is found, the channel is identified and provided as input to box 310, as described below.

[0051] In parallel, at block 308, controller 114 is configured to monitor the channels enabled in the preceding block (block 304 or block 310 described below) to determine whether those enabled channels have reached their respective regulation conditions.

[0052] Once the enabled channel has reached its regulation conditions, controller 114 is configured at box 310 to enable the new channel identified at box 206.

[0053] With these new channels enabled, method 200 returns to boxes 308 and 306 to monitor the newly enabled channels and identify any other channels to be enabled.

[0054] Therefore, as Figure 3 As shown in the flowchart, in the dynamic method, new channels in the power sequence are identified as quickly as possible (i.e., at box 206) and activated after a previous channel has reached its corresponding regulation condition. Thus, method 200 does not... Figure 2 As observed in the time-based power-up procedure depicted in the flowchart, a fixed time delay is applied between channel activations. This dynamic approach can be beneficial because it can be difficult to accurately predict how long a particular channel will take to reach regulation, meaning many power-up sequences are conservative and implement large delays between channel activations. Variations in channel startup times can be attributed to many factors, including system faults / errors, as well as process, voltage, and temperature variations that affect voltage ramp-up times.

[0055] Figure 4 It is depicted in the example PMIC (e.g., Figure 1 A diagram illustrating how channels can be enabled in the PMIC 102 according to the dynamic sequencing method of the present invention. Figure 4 In the diagram, multiple trajectory lines 408 depict the states of various channels 402 within the PMIC 102. The horizontal axis represents time. It should be noted that these channels and their specific power-on and power-off sequences correspond to the list in Table 1 above. On the horizontal axis, region 404 represents a portion of the power-on sequence in the timeline, while region 406 represents the power-off sequence.

[0056] exist Figure 4 In this configuration, each channel is associated with a specific trajectory line (trajectory lines 408a-408i). When trajectory line 408 has a low value, this indicates that the corresponding channel is in a disabled state, and when trajectory line 408 has a high value, this indicates that the corresponding channel is in a enabled state. The slope of trajectory line 408 between its high and low states indicates how long it takes for that particular channel to be fully enabled and in a regulated state, or conversely, how long it takes for that channel to be completely disabled and discharged.

[0057] like Figure 4As described herein, during the power-on process (specified by region 404), a dynamic method of channel sequencing is utilized (e.g., based on...). Figure 3 Method 300). As shown in traces 408a and 408g, channels REG1 and GPIO2 are the first channels (as specified by region 404) enabled as part of the power-up process (attributed to the corresponding sequence numbers of the channels in Table 1 above). When these channels have been fully enabled and have reached their regulation conditions, channel REG2 is enabled (see trace 408b). This process continues until all channels with specific sequence numbers have been enabled in the sequence specified in Table 1 above.

[0058] refer to Figure 4 The various trajectory lines clearly show that different channels require different amounts of time to enable. For example, as indicated by the slope of trajectory line 408c at region 410, channel REG3 transitions from its disabled state to its fully enabled state extremely quickly. Even faster, as indicated by the step size variation in the corresponding trajectory line 408 for that channel, various I / O channels can be enabled. In contrast, channel REG5 requires a considerable amount of time to fully enable, as indicated by the smaller slope of trajectory line 408e for that channel at region 412.

[0059] As discussed above in relation to method 300, the dynamic algorithm is therefore configured to take into account the time differences required to enable different channels by monitoring each enabled channel to detect when that channel has reached its regulation condition. Once the controller 114 of PMIC 102 determines that a channel has been regulated, the next channel in the sequence can be enabled as quickly as possible.

[0060] In contrast to the dynamic method used to perform power-on operations (e.g., indicated by region 404), the PMIC 102 is configured to utilize a fixed-time-based method in power-down operations (i.e., region 406). This may be preferred because, for example, due to the low voltage involved, it may be difficult to monitor a particular channel to determine when it is completely deactivated. Therefore, the dynamic method may not be suitable for power-down operations. Consequently, and as... Figure 4 As reflected in the table above, PMIC 102 is configured to implement a time-based method for channel deactivation during power-down operations. Channels can be deactivated in the reverse order of their initial activation, according to the sequence presented in the third column of Table 1 above. In this case, the time slot assignment associated with each channel is selected (in conjunction with the process by which PMIC 102 decrements the current time slot value) to implement a sufficient delay to ensure that channels in the sequence are fully deactivated before later channels in the sequence are deactivated. This is reflected in… Figure 4 In region 406, as part of the power-down operation, the timeline transition iterates through each available time slot number.

[0061] During operation of PMIC 102, as described above, memory 116 is configured to store control values ​​in one or more memory registers associated with specific sequence values. Memory 116 may also store an indication of whether a channel is enabled or disabled for each available channel. During operation of PMIC 102 (and the larger device 100 in general), these various values ​​may be dynamically updated at any time via appropriate control signals sent to memory 116 from controller 114. However, typically, any such modifications to these values ​​will occur outside of active power transition sequences (e.g., power-on or power-off sequences). Therefore, memory 116 and any registers therein may include terminals configured (e.g., from controller 114) to receive signals indicating power-on or power-off state transitions, and signals that may be configured to cause PMIC 102 to implement an immediate shutdown procedure in which all device regulators are simultaneously deactivated (e.g., in the event of a severe device failure or thermal problem). Such an immediate shutdown procedure may be triggered if the safety controller (not shown) of device 100 determines that such shutdown is necessary.

[0062] In various configurations, the PMIC 102 is configured to operate in several different power transition states, including power-on, standby transition, running transition, and power-off. Operation in each state may involve the PMIC 102 performing a sequenced operation as described herein to bring all channels online.

[0063] Typically, the operation of PMIC 102 is controlled according to a finite state machine, which is configured to cause PMIC 102 to transition between its various operating modes (e.g., idle, power-on operation, power-off operation, power state transition operation). Initially, depending on the selected mode, in time-based power-on operation (e.g., according to...), the PMIC 102 transitions between various operating modes. Figure 2 (method) or dynamic power-on operation (e.g., according to) Figure 3 The power-on operation is performed in a method. In some embodiments, the state of a customer-configurable one-time programmable (OTP) bit can be modified to determine whether a dynamic or time-based startup operation is performed.

[0064] Figure 5 This describes a controller configured to perform time-based and dynamic power-on and power-off operations as disclosed herein (e.g., Figure 1 A block diagram of the functional components of the controller 114.

[0065] The controller 500 includes a central core 502 configured to implement the functions of the controller 500. The controller 500 also includes an input terminal 504 configured to receive an input signal that can be transmitted through an input signal filter 505, the input signal filter 505 being configured to process the input signal (e.g., via a set of special functions or other filters and processors) to generate an input signal usable by the central core 502. Similarly, the controller 500 includes an output terminal 506 configured to generate an output signal of the controller 500. The output terminal 506 is connected to an output signal filter 508 configured to process the output signal (e.g., via a set of special functions or other filters and processors), after which the signal is output at the output terminal 506.

[0066] Central core 502 includes components configured to dynamically identify the PMIC (e.g., Figure 1 The PMIC 102 can be implemented, for example, by implementing Figure 3 The dynamic counter 510 for the enabled channel sequence is located in block 306. The central core 502 includes a highest timeslot logic function 512 configured to identify the highest timeslot number associated with the enabled channel in the PMIC. Thus, as part of the PMIC controller's power-down operation, the PMIC controller can utilize the highest timeslot logic function 512 to implement, for example, identifying the first timeslot number (i.e., the highest timeslot number associated with the active channel) to initiate a time-based power-down operation.

[0067] The dynamic counter 510 and the highest time slot logic function 512 are both connected to register group 514 (e.g., contained in, for example...). Figure 1 In memory such as memory 116, register group 514 identifies for each available time slot in the PMIC whether the time slot is associated with an enabled or disabled channel, or whether the time slot is not used (and therefore can be skipped in dynamic operation).

[0068] Figure 6 This is a circuit diagram depicting a system configured to selectively enable and / or disable a PMIC channel during dynamic power-on operation according to this disclosure. System 600 includes a dynamic counter 602 configured to perform all or part of the dynamic power-on operation. Dynamic counter 602 is configured to receive a set of available sequence numbers 604 as input. Dynamic counter 602 is configured to increment through the set of available sequence numbers and output the value of the available sequence numbers at an output terminal 608 connected to a first input terminal of comparator 610. Simultaneously, sequence register 606 is configured to output a set of assigned sequence numbers to a second terminal of comparator 610. The comparator output goes high when the assigned sequence number equals the current sequence number output at terminal 608 of dynamic counter 602.

[0069] The output signal is provided to the enable control terminals of latches 612 and 614. Latch 612 is configured to produce an output at its non-inverting output (Q) equal to the output of AND gate 616 when the input at its enable control terminal is high (i.e., the output of comparator 610 is high). AND gate 616 is configured to produce a high output value when the value of the to_shutdown pin is low (which is inverted before being provided to the first input of AND gate 616) and the value of the to_run pin is high. Thus, latch 612 produces a high output value when the channel associated with the current serial number should be powered on, and a low value when the channel associated with the current serial number should be powered off.

[0070] In latch 612, when the input at the enable control terminal of latch 612 is high (i.e., the output of comparator 610 is high), it is configured to produce an output at its non-inverting output (Q) equal to the output of AND gate 618. AND gate 618 is configured to produce a high output value when the value of the to_shutdown pin is low (it is inverted before being provided to the first input of AND gate 616) and the value of to_stby is high. Thus, latch 612 produces a high output value when the channel associated with the current serial number should be placed in standby mode, and a low value when the channel associated with the current serial number should be powered down.

[0071] The output of latch 612 is provided as the input of AND gate 620, which produces a high output when the output of latch 612 is high and the value of cfg_run_en is high (indicating that a dynamic sequence operation is running).

[0072] The output of latch 614 is provided as the input of AND gate 622, which produces a high output when the output of latch 614 is high and the value of cfg_stby_en is high (indicating that a dynamic sequence operation is running to put the channel into standby mode).

[0073] The outputs of AND gates 620 and 622 are provided to OR gate 623. Thus, when the output of AND gate 620 or AND gate 622 goes high, system 600 generates the output signal seq_enable at output terminal 624.

[0074] Return to reference Figure 1 After device 100 is fully powered on (by performing a time-based power-on operation or a dynamic power-on operation via PMIC 102), future transitions between states will typically trigger time-based operations, such as power-down operations or transitions to standby mode or some other power state.

[0075] When the PMIC moves to the power-off state, the controller can begin its own power-off operation. The largest programming time slot (i.e., the highest time slot number associated with the PMIC channel) is calculated and will be the starting point of the power-down sequence. The sequencer then performs a timing-based sequencing operation in a countdown manner from its starting point. Once the process reaches the last time slot (i.e., time slot number 0), a configurable power-off delay can occur. The sequencer can also be configured to wait for a subset of the regulators to complete the ramp-up of that subset. Once both delay conditions are met, the controller can indicate that it has successfully powered down and return to its idle state.

[0076] To implement dynamic power-on operation, the controller 114 of the PMIC 102 includes a dynamic counter subsystem, which can be configured to operate in both static and dynamic modes upon power-on. If set to static mode, the dynamic counter is configured to start counting upwards by one time slot number (e.g., by adjusting for time slots). Figure 2 The method iterates through the available time slot numbers over time, with a programmed delay between each time slot value iteration. If, for a given time slot value, memory 116 stores configuration data indicating that a specific channel or channel group should be enabled for that time slot value, then that channel or channel group can be enabled when the current time slot value of the counter matches that time slot number. In this type of time-based power-on operation, no time slot values ​​are skipped, and the power-on operation iterates through all time slot numbers sequentially. A power-on operation is performed after all time slot values ​​have been processed.

[0077] However, if the counter is set to dynamic mode, the counter will start by jumping to the lowest time slot. Once the lowest time slot is reached, the enable bit for that time slot will be set, and the counter will begin counting using any possible skips (e.g., according to...). Figure 3 (Method). This counting can continue until the next lowest time slot is reached, and then the counting will be paused until it is confirmed that the channel associated with the current time slot has been successfully powered on and regulated. This process is repeated until a fault occurs or all time slots have been successfully powered on.

[0078] In its dynamic mode, the dynamic counter is configured to determine the sequence of channels to be enabled based on predefined sequence numbers. Specifically, while a power-on operation is in progress, the dynamic counter is configured to identify the next highest sequence number in that defined set of sequence numbers (e.g., as shown in Table 1 above). The dynamic counter can be configured to implement sequence number skipping by rounding the remaining sequence numbers to the nearest multiple of a power of two. In some embodiments, an XOR logic network can be implemented to determine which bits differ between the current count value and (e.g., in Table 1 above) the remaining sequence numbers in the channel power-on sequence. For each sequence number associated with a channel that has not yet been powered on, multiples that can be safely rounded to powers of 2 can be determined without skipping the time slot.

[0079] For example, when traversing a sequence number that can be a 6-digit value, the next sequence number in the entire sequence number group can be determined by comparing a subset of the sequence number's bits, such as those corresponding to the nearest multiples of 32, 16, 8, etc. (e.g., bits 5, 4, 3, etc. of the sequence number). These "safely rounded" versions of the sequence number can then be compared with each other, and the largest non-enabled "safely rounded" version of the sequence number is used to determine the next sequence number. For example, if two non-enabled channels remain during power-on operation, and the bit difference between the corresponding sequence numbers of said channels is at bits 4 and 5, then the most significant bits of the two sequence numbers (e.g., bits 1, 2, 3, and 4) are the same and can be determined without comparison to determine which sequence number is the next in the sequence. Thus, the dynamic counter can determine which of the two remaining sequence numbers is the next sequence number by comparing only bits 4 and 5. Therefore, for each 2 n The sequence number value, where n is less than the number of bits in the sequence value. If there is a bit difference somewhere between the nth bit and the most significant bit, it can be safely rounded up to 2. n The next multiple of . Compare the safe rounding target for each time slot, and the final rounding target will be the largest power of two that all remaining time slots are considered to be safely rounded up. The counter will be rounded up to this value, and the process will be repeated until an occupied time slot is reached. When the counter is given an initial value of 0, this process ensures that unpowered time slots are not ignored when the counter is rounded up.

[0080] In other words, when determining the next sequence number in a set of sequence numbers, it is not necessary to compare the positions of the same bits across all sequence numbers to determine the next most significant sequence number. For illustration, if the sequence number in a particular PMIC is limited by an 8-bit value, the maximum possible sequence number is 255 (decimal). However, if the corresponding PMIC is only configured to use a total of 127 (decimal) time slots, the first bit (i.e., the most significant bit) of the 8-bit sequence number will always have a value of '0'. Therefore, the MSB of the sequence number can be ignored in this case when determining the next sequence number.

[0081] In various embodiments of the PMIC 102, and specifically in its dynamic counter component, this algorithm can also be used to find the dynamic starting point of the lowest possible slot number that can be used in the power-down sequence. In this case, the maximum slot number associated with a particular PMIC 102 channel can be determined by setting the initial counter value to 0 and performing the algorithm on the inverse of each slot value. Once this value is reached, it is loaded into a counter that begins a simple countdown sequence. In various embodiments, this method allows for faster counting than simple incrementing while avoiding the large area cost of direct skipping. Since this counting also occurs in parallel with the ramp-up of the slots, it is effectively masked by the much longer ramp-up time of the voltage regulator. The O(log(n)) lookup time allows for efficient scaling for larger slot values.

[0082] In some aspects, the technology described herein relates to a power management integrated circuit, the power management integrated circuit comprising: a power input terminal; a plurality of power output terminals, wherein each of the power output terminals is associated with a channel among a plurality of channels; a memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each channel among the plurality of channels; and a controller configured to: receive a control input indicating that a power-on operation should be performed; determine a power-on mode based on the configuration stored in the memory; and perform the dynamic power-on operation by means of the power-on mode indicating a dynamic power-on operation. Power-on operation: Identify a first channel among the plurality of channels associated with a first dynamic sequence number that is the lowest dynamic sequence number among the plurality of dynamic sequence numbers, enable the first channel, monitor the first channel to determine whether the first channel is in a first regulated state, and while monitoring the first channel, identify a second channel among the plurality of channels associated with a second dynamic sequence number among the plurality of dynamic sequence numbers; when the power-on mode indicates a time-based power-on operation: cause a time slot counter to traverse the plurality of time slot numbers; and when the current value of the time slot counter is equal to the time slot number associated with a third channel among the plurality of channels in the configuration data, enable the third channel.

[0083] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to enable a second channel after determining that a first channel is in a first regulated state.

[0084] In some respects, the techniques described herein relate to a power management integrated circuit in which a controller is configured to wait for a predetermined time slot duration at each iteration of a time slot counter.

[0085] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine that a second dynamic sequence number is the next highest dynamic sequence number following a first dynamic sequence number among the plurality of dynamic sequence numbers.

[0086] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine that the second dynamic sequence number is the next highest dynamic sequence number by comparing a first subset of binary values ​​in the second dynamic sequence number with a second subset of binary values ​​in the next highest dynamic sequence number.

[0087] In some aspects, the technology described herein relates to a power management integrated circuit, the power management integrated circuit comprising: a power input terminal; a plurality of power output terminals, wherein each of the power output terminals is associated with a channel among a plurality of channels; a memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each channel among the plurality of channels; and a controller configured to perform a dynamic device power-on operation by: determining a first channel among the plurality of channels associated with a first dynamic sequence number that is the lowest dynamic sequence number among the plurality of dynamic sequence numbers, enabling the first channel, monitoring the first channel to determine whether the first channel is in a first regulated state, determining a second channel among the plurality of channels associated with a second dynamic sequence number among the plurality of dynamic sequence numbers while monitoring the first channel, determining that the first channel is in the first regulated state, and enabling the second channel.

[0088] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to perform a time-based power-on operation by causing a timeslot counter to traverse the plurality of timeslot numbers; and enabling the third channel when the current value of the timeslot counter is equal to the timeslot number associated with the third channel of the plurality of channels in the configuration data.

[0089] In some respects, the techniques described herein relate to a power management integrated circuit in which a controller is configured to wait for a predetermined time slot duration at each iteration of a time slot counter.

[0090] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine that a second dynamic sequence number is the next highest dynamic sequence number following a first dynamic sequence number among the plurality of dynamic sequence numbers.

[0091] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine that the second dynamic sequence number is the next highest dynamic sequence number by comparing a first subset of binary values ​​in the second dynamic sequence number with a second subset of binary values ​​in the next highest dynamic sequence number.

[0092] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine a second channel by performing a binary search of multiple dynamic sequence numbers.

[0093] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine a third channel among a plurality of channels associated with a first dynamic sequence number, and to enable said third channel.

[0094] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to enable a third channel while enabling a first channel.

[0095] In some respects, the technology described herein relates to a power management integrated circuit in which a controller is configured to determine that a third channel is in a second regulated state before the second channel is enabled.

[0096] In some respects, the technology described herein relates to a power management integrated circuit in which multiple channels include at least one general-purpose input / output channel.

[0097] In some aspects, the technology described herein relates to a method comprising: determining a first channel among a plurality of channels of a power management integrated circuit that is associated with a first dynamic serial number in the memory of the power management integrated circuit, wherein the first dynamic serial number is the lowest dynamic serial number among the plurality of dynamic serial numbers; enabling the first channel; monitoring the first channel to determine whether the first channel is in a first regulated state of a specified voltage value; while monitoring the first channel, determining a second channel among the plurality of channels that is associated with a second dynamic serial number among the plurality of dynamic serial numbers; determining that the first channel is in the first regulated state; and enabling the second channel.

[0098] In some respects, the techniques described herein relate to a method that further includes determining that a second dynamic sequence number is the next highest dynamic sequence number following a first dynamic sequence number among the plurality of dynamic sequence numbers.

[0099] In some respects, the techniques described herein relate to a method that further includes determining that the second dynamic sequence number is the next highest dynamic sequence number by comparing a first subset of binary values ​​in the second dynamic sequence number with a second subset of binary values ​​in the next highest dynamic sequence number.

[0100] In some respects, the technology described herein relates to a method that further includes: determining a third channel among the plurality of channels associated with a first dynamic sequence number; and enabling the third channel.

[0101] In some aspects, the techniques described herein relate to a method that further includes enabling a third channel while enabling a first channel. Those skilled in the art will understand that aspects of this disclosure can be embodied as systems, processes, methods, and / or program products. Therefore, aspects of this disclosure can take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects (which may be generally referred to herein as "circuit," "circuit system," "module," or "system"). Furthermore, aspects of this disclosure can take the form of program products embodied in one or more computer-readable storage media on which computer-readable program code is embodied. (However, any combination of one or more computer-readable media may be utilized. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium.)

[0102] Computer-readable storage media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, biological, atomic, or semiconductor systems, devices, controllers, or apparatuses, or any suitable combination thereof, wherein the computer-readable storage medium itself is not a transient signal. More specific examples (a non-exhaustive list) of computer-readable storage media may include: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (“RAM”), read-only memory (“ROM”), erasable programmable read-only memory (“EPROM” or flash memory), optical fiber, portable compressed optical disc read-only memory (“CD-ROM”), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device, controller, or apparatus. Any suitable medium may be used to transmit program code embodied on a computer-readable signal medium, including but not limited to wireless, wires, fiber optic cables, RF, etc., or any suitable combination thereof.

[0103] Computer-readable signal media may include propagated data signals in which computer-readable program code is embodied, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and is capable of transmitting, propagating, or transmitting a program for use by or in conjunction with an instruction execution system, device, controller, or apparatus.

[0104] The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of circuit systems, systems, methods, processes, and program products according to various embodiments of the present disclosure. In this regard, certain blocks in the block diagrams may represent portions of modules, segments, or code comprising one or more executable program instructions for implementing specified logical functions. It should also be noted that in some implementations, the functions marked in the blocks may occur in a non-linear order. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or the blocks may sometimes execute in reverse order.

[0105] Modules implemented in software for execution by various types of processors may, for example, comprise one or more physical or logical blocks of computer instructions, which may be organized, for example, as objects, programs, or functions. However, the executable files of the identified modules need not be physically located together, but may comprise different instructions stored in different locations that, when logically combined, include the module and implement its stated purpose. In practice, a module of executable code may be a single instruction, or many instructions, and may even be distributed across several different code segments in different programs and span several memory devices. Similarly, operational data (e.g., a weighted and / or biased knowledge base described herein) may be identified and represented within modules herein, and may be embodied in any suitable form and organized within any suitable type of data structure. Operational data may be collected as a single dataset or may be distributed across different locations, including across different storage devices. The data may provide electronic signals on a system or network.

[0106] These program instructions may be provided to one or more processors and / or controllers or other programmable data processing devices (e.g., controllers) of a general-purpose computer or a special-purpose computer to produce a machine such that the instructions, which execute via the computer's processor or other programmable data processing device, create a circuit system or manner for implementing the functions / actions specified in one or more boxes of the block diagram.

[0107] It should also be noted that each block of the block diagram, and combinations of blocks within the block diagram, can be implemented by a dedicated hardware-based system (e.g., which may include one or more graphics processing units) or a combination of dedicated hardware and computer instructions that performs the specified function or action. For example, a module can be implemented as hardware circuitry, including custom VLSI circuitry or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, controllers, or other discrete components. Modules can also be implemented in programmable hardware devices such as field-programmable gate arrays, programmable array logic, programmable logic devices, application-specific integrated circuits (ASICs), microcontrollers, system-on-a-chip (SoCs), general-purpose processors, microprocessors, etc.

[0108] Computer program code, i.e. instructions, for performing the operations of various aspects of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, Python, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.

[0109] These program instructions may also be stored in a computer-readable storage medium, which can direct a computer system, other programmable data processing equipment, controller or other means to function in a particular manner, causing the instructions stored in the computer-readable medium to produce an article of writing, which includes instructions that implement the functions / actions specified in one or more blocks of the block diagram.

[0110] Program instructions may also be loaded onto a computer, other programmable data processing apparatus, controller or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, provide for performing a process for carrying out a function / action specified in one or more boxes of the block diagram.

[0111] The specific implementation methods described above are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments.

[0112] As used herein, the term “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary should not be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0113] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply a sequence or order.

[0114] As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data mode, current, or quantity exists. Furthermore, two or more nodes can be implemented using a single physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even if received or output at a common node).

[0115] The preceding description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly connected to (or directly connected to) another element, and not necessarily mechanically. Similarly, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly connected to (or directly or indirectly connected to, electrically or otherwise) another element, and not necessarily mechanically. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0116] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the described embodiments or embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A power management integrated circuit, characterized in that, include: Power input terminal; Multiple power output terminals, wherein each of the power output terminals is associated with a channel in a plurality of channels; A memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each of the plurality of channels; as well as The controller is configured to: Receive control input indicating that a power-on operation should be performed; The power-on mode is determined based on the configuration stored in the memory; When the power-on mode indicates a dynamic power-on operation, the dynamic power-on operation is performed in the following manner: A first channel is identified from the plurality of channels and associated with a first dynamic sequence number, wherein the first dynamic sequence number is the lowest dynamic sequence number among the plurality of dynamic sequence numbers. Enable the first channel. Monitor the first channel to determine whether the first channel is in the first regulated state, and While monitoring the first channel, a second channel is identified that is associated with a second dynamic sequence number among the plurality of channels. When the power-on mode indicates a time-based power-on operation: The time slot counter iterates through the multiple time slot numbers; and The third channel is enabled when the current value of the time slot counter is equal to the time slot number associated with the third channel among the plurality of channels in the configuration data.

2. The power management integrated circuit according to claim 1, characterized in that, The controller is configured to enable the second channel after determining that the first channel is in the first regulated state.

3. The power management integrated circuit according to claim 1, characterized in that, The controller is configured to wait for a predetermined time slot duration during each iteration of the time slot counter.

4. The power management integrated circuit according to claim 1, characterized in that, The controller is configured to determine that the second dynamic sequence number is the next highest dynamic sequence number after the first dynamic sequence number among the plurality of dynamic sequence numbers.

5. The power management integrated circuit according to claim 4, characterized in that, The controller is configured to determine that the second dynamic sequence number is the next highest dynamic sequence number by comparing a first subset of binary values ​​in the second dynamic sequence number with a second subset of binary values ​​in the next highest dynamic sequence number.

6. A power management integrated circuit, characterized in that, include: Power input terminal; Multiple power output terminals, wherein each of the power output terminals is associated with a channel in a plurality of channels; A memory configured to store configuration data, the configuration data identifying a timeslot number among a plurality of timeslot numbers and a dynamic sequence number among a plurality of dynamic sequence numbers for each of the plurality of channels; as well as The controller is configured to perform the power-on operation of the dynamic device in the following manner: A first channel is identified from the plurality of channels and associated with a first dynamic sequence number, wherein the first dynamic sequence number is the lowest dynamic sequence number among the plurality of dynamic sequence numbers. Enable the first channel. Monitor the first channel to determine whether the first channel is in the first regulated state. While monitoring the first channel, a second channel is identified that is associated with a second dynamic sequence number among the plurality of channels. Determine that the first channel is in the first regulated state, and Enable the second channel.

7. The power management integrated circuit according to claim 6, characterized in that, The controller is configured to perform a time-based power-on operation in the following manner: The time slot counter iterates through the multiple time slot numbers; and The third channel is enabled when the current value of the time slot counter is equal to the time slot number associated with the third channel among the plurality of channels in the configuration data.

8. The power management integrated circuit according to claim 6, characterized in that, The controller is configured to determine that the second dynamic sequence number is the next highest dynamic sequence number after the first dynamic sequence number among the plurality of dynamic sequence numbers.

9. The power management integrated circuit according to claim 6, characterized in that, The controller is configured to: Determine the third channel among the plurality of channels that is associated with the first dynamic sequence number, and Enable the third channel.

10. A method, characterized in that, include: A first channel among multiple channels of a power management integrated circuit is identified and associated with a first dynamic serial number in the memory of the power management integrated circuit, wherein the first dynamic serial number is the lowest dynamic serial number among multiple dynamic serial numbers. Enable the first channel. Monitor the first channel to determine whether the first channel is in a first regulated state with a specified voltage value. While monitoring the first channel, a second channel is identified that is associated with a second dynamic sequence number among the plurality of channels. Determine that the first channel is in the first regulated state, and Enable the second channel.

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