A clock phase synchronization circuit

Abstract

This invention discloses a clock phase synchronization circuit, belonging to the field of integrated circuit design technology. The circuit includes: a phase difference detection module, a filtering module, a control window module, a sampler, and a control latch module. The phase difference detection module detects the phase difference between the frequency division signals of the first and second clock paths and outputs a signal; the filtering module filters out the high-frequency components of the signal; the control window module outputs a reset trigger signal when the alignment enable signal is valid; the sampler synchronously generates a differential reset control signal; the control latch module is located in the frequency divider of the second path and resets its output clock phase according to the differential reset control signal. This clock phase synchronization circuit utilizes two configuration ports to precisely control the clock phase relationship, quickly achieving clock phase synchronization of different clock paths under frequency division conditions, while maintaining excellent clock synchronization accuracy.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and specifically relates to a clock phase synchronization circuit. Background Technology

[0002] In the clock path design circuit of high-speed SERDES, multiple clock paths are typically included. To reduce system power consumption, some paths can be disabled under normal operating conditions. However, when they need to be re-enabled, due to the presence of clock divider circuits, a phase deviation will occur between the clock of the disabled path and the original path clock. If a complete initialization calibration process is re-executed to ensure clock phase alignment, it will not only be time-consuming and severely affect the system response speed, but also generate significant performance overhead during frequent low-power state transitions, failing to meet the requirements of modern high-speed communication systems for rapid recovery and real-time monitoring. Summary of the Invention

[0003] The purpose of this invention is to provide a clock phase synchronization circuit that uses two configuration ports to precisely control the clock phase relationship, quickly completes clock phase synchronization of different clock paths under frequency division, and maintains excellent clock synchronization accuracy, thereby solving the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a clock phase synchronization circuit, applied to a clock circuit phase synchronization system including a first clock path and a second clock path, the circuit comprising:

[0005] The phase difference detection module has a first input terminal connected to the frequency divider output terminal of the first clock path and a second input terminal connected to the frequency divider output terminal of the second clock path. It is used to detect the phase difference between the two frequency divider clock signals and output the corresponding phase difference signal.

[0006] A filtering module, whose input is connected to the output of the phase difference detection module, is used to filter the received phase difference signal to remove high-frequency components.

[0007] The control window module has its first input terminal connected to the output terminal of the filter module, and its second input terminal receiving the external alignment enable signal RELEASE_ALIGN. When the alignment enable signal RELEASE_ALIGN is valid, it outputs a reset trigger signal RST.

[0008] The sampler has its input connected to the output of the control window module and its clock connected to the system reference clock. It is used to synchronously sample the reset trigger signal RST and generate a pair of differential reset control signals RST_N and RST_P with complementary logic states.

[0009] The control latch module is provided in a set, including a first control latch module disposed in the first clock path and a second control latch module disposed in the frequency divider of the second clock path.

[0010] The control terminal of the second control latch module receives the differential reset control signals RST_N and RST_P, and its clock input terminal is connected to the original clock signal of the second clock path. It is used to reset the phase of the output frequency-divided clock signal to a predetermined state that is synchronized with the frequency-divided clock signal of the first clock path according to the differential reset control signals RST_N and RST_P.

[0011] Preferably, the phase difference detection module is an XOR gate circuit, and its output signal is a high-frequency pulse signal characterizing the phase difference between the two input clocks.

[0012] Preferably, the filtering module is a low-pass filter.

[0013] Preferably, when the alignment enable signal RELEASE_ALIGN is valid, the control window module allows the signal from the filtering module to pass through and outputs it as the reset trigger signal RST.

[0014] Preferably, the sampler is a D flip-flop or a synchronization stage composed of D flip-flops.

[0015] Preferably, the control latch module includes at least one mode circuit, the mode circuit including:

[0016] An inverter, whose input terminal serves as the clock input terminal CLK_IN of the control latch module;

[0017] The first-level tri-state gate has its input connected to the output of the inverter, and its output serves as the clock output CLK_OUT of the control latch module.

[0018] The input of the second-stage tri-state gate is connected to the output of the first-stage tri-state gate;

[0019] PMOS transistor PM2 and NMOS transistor NM2 are connected in series between the power supply voltage VDD and ground VSS, and their common connection point M is connected to the control node of the first-stage tri-state gate and the second-stage tri-state gate.

[0020] The gates of the PMOS transistor PM2 and the NMOS transistor NM2 are controlled by the differential reset control signals RST_N and RST_P, respectively, to pull the potential of the control node to a fixed level during the reset phase, thereby turning off the first-stage tri-state gate and outputting a predetermined level at the clock output terminal; after the reset phase ends, the first-stage tri-state gate resumes normal operation, and the clock output terminal follows the phase of the input clock.

[0021] Preferably, the mode circuit includes a pull-up mode circuit and a pull-down mode circuit;

[0022] In the pull-up mode circuit, the gate of the PMOS transistor PM2 is connected to the power supply voltage VDD, and the gate of the NMOS transistor NM2 receives the differential reset control signal RST_P. When the differential reset control signal RST_P is high and the differential reset control signal RST_N is low, the NMOS transistor NM2 is turned on, pulling the control node M down to a low level, thereby forcibly pulling the clock output terminal CLK_OUT low.

[0023] In the pull-down mode circuit, the gate of the PMOS transistor PM2 receives the differential reset control signal RST_N, and the gate of the NMOS transistor NM2 is grounded to VSS. When the differential reset control signal RST_P is high and the differential reset control signal RST_N is low, the PMOS transistor PM2 is turned on, pulling the control node M to a high level, thereby forcibly pulling the clock output terminal CLK_OUT high.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] The clock phase fast alignment circuit of the present invention can quickly complete the synchronization of clock phases of different paths under frequency division, shorten the alignment time required for low power switching; maintain high-precision synchronization and reduce performance overhead; the sampler has strong adaptability, the loop is stable, and the system response speed and reliability are improved. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the clock circuit phase synchronization system of the present invention.

[0027] Figure 2 This is the circuit diagram of DIV_CTRL_LATCH of the present invention.

[0028] Figure 3 This is a timing diagram of the clock circuit phase synchronization system of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0030] Figure 1This is a schematic diagram of a clock circuit phase synchronization system. In this system, two different clock paths output multiphase signals, which are then sent to a frequency divider. Due to the characteristics of the frequency divider, its output signal may have a phase deviation. The principle of clock phase synchronization is as follows: First, the frequency-divided signals of the two paths are XORed to obtain a signal X containing phase difference information. Then, a filter is used to filter out high-frequency components in the XOR result, reducing the speed requirement of the sampler. In ALIGN_WINDOW, a control signal RELEASE_ALIGN is used to control the release of X, and the sampler is used for synchronization, outputting RST_N and RST_P and sending them back to DIV_CTRL_LATCH in the DIVIDER module to reset the clock phase. The entire feedback loop achieves real-time phase synchronization in this way.

[0031] Figure 2 This is the circuit diagram of the DIV_CTRL_LATCH circuit of the present invention. The core function of this circuit is to reset the phase of the input clock using differential control signals RST_N and RST_P. Figure 2 As shown, the DIV_CTRL_LATCH circuit has two modes: UP and DOWN. The input and output are differential clock signals. In the UP circuit (pull-up mode circuit), the gates of PM2 and NM2 are connected to VDD and RST_P respectively. When RST_P is high and RST_N is low, it enters the reset state, the first-stage tri-state gate is closed, point M is pulled down to low level by NM2, and CLK_OUT outputs a low level. When RST_P transitions from high to low and RST_N transitions from low to high, the first-stage tri-state gate starts to work normally. CLK_IN is output to CLK_OUT after passing through a buffer (inverter), and the output follows the phase of CLK_IN at the current moment. Similarly, in the DOWN circuit (pull-down mode circuit), the gates of PM2 and NM2 are connected to RST_N and VSS respectively. When RST_P is high and RST_N is low, CLK_OUT outputs a high level. When RST_P transitions from high to low and RST_N transitions from low to high, CLK_OUT follows the phase of CLK_IN at the current moment.

[0032] Depend on Figure 3As shown, after clock path 2 is turned off and then powered on again, even with the same phase codeword, the clock phase output after frequency division may deviate due to the lack of phase initialization. The frequency division outputs of path 1 and path 2 are XORed to obtain a pulse signal X containing phase difference information. Considering that the Sampler may not be able to accurately synchronize the high-speed signal X under PVT, X is low-pass filtered to obtain Y. In fact, the RESET operation of the frequency division circuit does not need to be performed in high-speed scenarios. When the system needs phase alignment, RELEASE_ALIGN is set from 0 to 1, and ALIGN_WINDOW outputs an RST signal. After synchronization by the sampler X, the RST_N and RST_P signals required by DIV_CTRL_LATCH are obtained. This signal is used to reset the phase of DIVIDER2. To ensure the stability of the loop, the RST signal must complete all the above operations within 1 / 2 of the frequency division clock cycle; otherwise, the RST signal may act on different cycles, leading to phase alignment failure.

[0033] The clock phase fast alignment circuit of the present invention can quickly complete the synchronization of clock phases of different paths under frequency division, shorten the alignment time required for low power switching; maintain high-precision synchronization and reduce performance overhead; the sampler has strong adaptability, the loop is stable, and the system response speed and reliability are improved.

[0034] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0035] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A clock phase synchronization circuit, characterized in that, A clock circuit phase synchronization system comprising a first clock path and a second clock path is applied, the circuit comprising: The phase difference detection module has a first input terminal connected to the frequency divider output terminal of the first clock path and a second input terminal connected to the frequency divider output terminal of the second clock path. It is used to detect the phase difference between the two frequency divider clock signals and output the corresponding phase difference signal. A filtering module, whose input is connected to the output of the phase difference detection module, is used to filter the received phase difference signal to remove high-frequency components. The control window module has its first input terminal connected to the output terminal of the filter module, and its second input terminal receiving the external alignment enable signal RELEASE_ALIGN. When the alignment enable signal RELEASE_ALIGN is valid, it outputs a reset trigger signal RST. The sampler has its input connected to the output of the control window module and its clock connected to the system reference clock. It is used to synchronously sample the reset trigger signal RST and generate a pair of differential reset control signals RST_N and RST_P with complementary logic states. The control latch module is provided in a set, including a first control latch module disposed in the first clock path and a second control latch module disposed in the frequency divider of the second clock path. The control terminal of the second control latch module receives the differential reset control signals RST_N and RST_P, and its clock input terminal is connected to the original clock signal of the second clock path. It is used to reset the phase of the output frequency-divided clock signal to a predetermined state that is synchronized with the frequency-divided clock signal of the first clock path according to the differential reset control signals RST_N and RST_P.

2. The clock phase synchronization circuit according to claim 1, characterized in that, The phase difference detection module is an XOR gate circuit, and its output signal is a high-frequency pulse signal that represents the phase difference between the two input clocks.

3. A clock phase synchronization circuit according to claim 1, characterized in that, The filtering module is a low-pass filter.

4. A clock phase synchronization circuit according to claim 1, characterized in that, When the alignment enable signal RELEASE_ALIGN is valid, the control window module allows signals from the filtering module to pass through and outputs them as the reset trigger signal RST.

5. A clock phase synchronization circuit according to claim 1, characterized in that, The sampler is a D flip-flop or a synchronization stage composed of D flip-flops.

6. A clock phase synchronization circuit according to claim 1, characterized in that, The control latch module includes at least one mode circuit, the mode circuit including: An inverter, whose input terminal serves as the clock input terminal CLK_IN of the control latch module; The first-level tri-state gate has its input connected to the output of the inverter, and its output serves as the clock output CLK_OUT of the control latch module. The input of the second-stage tri-state gate is connected to the output of the first-stage tri-state gate; PMOS transistor PM2 and NMOS transistor NM2 are connected in series between the power supply voltage VDD and ground VSS, and their common connection point M is connected to the control node of the first-stage tri-state gate and the second-stage tri-state gate. The gates of the PMOS transistor PM2 and the NMOS transistor NM2 are controlled by the differential reset control signals RST_N and RST_P, respectively, to pull the potential of the control node to a fixed level during the reset phase, thereby turning off the first-stage tri-state gate and outputting a predetermined level at the clock output terminal; after the reset phase ends, the first-stage tri-state gate resumes normal operation, and the clock output terminal follows the phase of the input clock.

7. A clock phase synchronization circuit according to claim 6, characterized in that, The mode circuit includes a pull-up mode circuit and a pull-down mode circuit; In the pull-up mode circuit, the gate of the PMOS transistor PM2 is connected to the power supply voltage VDD, and the gate of the NMOS transistor NM2 receives the differential reset control signal RST_P. When the differential reset control signal RST_P is high and the differential reset control signal RST_N is low, the NMOS transistor NM2 is turned on, pulling the control node M down to a low level, thereby forcibly pulling the clock output terminal CLK_OUT low. In the pull-down mode circuit, the gate of the PMOS transistor PM2 receives the differential reset control signal RST_N, and the gate of the NMOS transistor NM2 is grounded to VSS. When the differential reset control signal RST_P is high and the differential reset control signal RST_N is low, the PMOS transistor PM2 is turned on, pulling the control node M to a high level, thereby forcibly pulling the clock output terminal CLK_OUT high.

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