Circuit board and manufacturing method thereof

Abstract

The invention discloses a circuit board and a manufacturing method thereof. The circuit board comprises a substrate layer, a circuit layer, a conductive bump and an insulating medium layer. The circuit layer is arranged on the surface of the base material layer, and the circuit layer comprises a welding pad; the conductive bump is located on the surface, deviating from the base material layer, of the welding pad; the conductive bumps and the welding pads are coated with the insulating dielectric layer; a groove is formed in the exposed face, away from the base material layer, of the insulating medium layer, the groove is arranged around the conductive protruding block, and part of the peripheral face of the conductive protruding block is exposed in the groove.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a circuit board and a method for manufacturing the same. Background Technology

[0002] In existing technologies, raised copper pillars are typically formed on the surface of a circuit board, and solder paste is printed on the copper pillars for hot-press soldering. Current methods for manufacturing copper pillars involve applying dry film, creating openings, and electroplating on the circuit board substrate. However, copper pillars formed in this way can become uneven due to uneven current density distribution during electroplating or the inability to properly smooth the dry film applied to the substrate surface, thus failing to meet current soldering and packaging requirements.

[0003] In addition, since the copper pillars extend beyond the substrate surface after electroplating, they are not effectively protected during subsequent circuit board processes, which can lead to the copper pillars falling off.

[0004] In addition, during hot-press soldering, the copper pillars have limited capacity to absorb solder paste, and the solder paste tends to flow outwards, forming solder paste bridges and causing short circuits. Summary of the Invention

[0005] In view of this, this application provides a circuit board that can solve the above-mentioned technical problems and a method for manufacturing the same.

[0006] A circuit board includes a substrate layer, a circuit layer, conductive bumps, and an insulating dielectric layer. The circuit layer is disposed on the surface of the substrate layer and includes solder pads. The conductive bumps are located on the surface of the solder pads facing away from the substrate layer. The insulating dielectric layer covers the conductive bumps and the solder pads. The exposed surface of the insulating dielectric layer facing away from the substrate layer has a groove, the groove surrounding the conductive bumps, and a portion of the outer peripheral surface of the conductive bumps is exposed in the groove.

[0007] Furthermore, the circuit board provided in this application also includes a protective layer that covers the surface of the insulating dielectric layer away from the substrate layer, and covers the surfaces of the substrate layer and the circuit layer exposed on the insulating dielectric layer.

[0008] Furthermore, the orthographic projection of the groove along the thickness direction of the circuit board is located within the solder pad.

[0009] Furthermore, the insulating dielectric layer fills the gaps between the conductive bumps and the gaps between the solder pads, and is connected to the substrate layer.

[0010] Furthermore, along the thickness direction of the circuit board, the ratio of the bonding depth between the insulating dielectric layer and the conductive bump to the height of the conductive bump is 1 / 3 to 2 / 3.

[0011] This application also provides a method for manufacturing a circuit board, including the following steps:

[0012] A substrate is provided, the substrate comprising a substrate layer and a conductor layer;

[0013] The conductor layer is fabricated to form a circuit layer, the circuit layer including solder pads;

[0014] Conductive bumps are formed on the surface of the solder pads that are away from the substrate layer;

[0015] An insulating dielectric layer is formed on the surface of the circuit layer opposite to the substrate layer. The insulating dielectric layer covers the conductive bumps and the solder pads. The insulating dielectric layer is connected to the substrate layer and fills the gaps between the conductive bumps and the gaps between the solder pads.

[0016] The insulating dielectric layer covering the conductive bumps is polished to expose the surface of the conductive bumps that faces away from the solder pads;

[0017] A groove is formed in the insulating dielectric layer around the conductive bump, exposing part of the outer peripheral surface of the conductive bump.

[0018] Furthermore, before the step of "polishing the insulating dielectric layer covering the conductive bumps to expose the surface of the conductive bumps facing away from the solder pads", the following step is also included: pressing a cover film onto the opposite sides of the substrate layer to form a protective layer, the protective layer covering a portion of the circuit layer.

[0019] Furthermore, "forming an insulating dielectric layer on the surface of the circuit layer opposite to the substrate layer, the insulating dielectric layer enclosing the conductive bumps and the solder pads" specifically includes:

[0020] A metal sheet is provided, with through grooves on the metal sheet corresponding to the areas where the solder pads and conductive bumps are located. The metal sheet is fitted onto the circuit layer, so that the conductive bumps and the solder pads are exposed from the through grooves. An insulating dielectric material is laid in the through grooves, so that the insulating dielectric material covers the conductive bumps and the solder pads. After curing, the insulating dielectric material is cured to form an insulating dielectric layer, which encapsulates the conductive bumps and the solder pads.

[0021] Furthermore, the orthographic projection of the groove along the thickness direction of the circuit board is located within the solder pad.

[0022] Furthermore, along the thickness direction of the circuit board, the ratio of the bonding depth between the insulating dielectric layer and the conductive bump to the height of the conductive bump is 1 / 3 to 2 / 3.

[0023] The insulating dielectric layer of the circuit board provided in this application can reliably fix the conductive bumps to the substrate layer, reducing the risk of conductive bump detachment. Unlike the prior art that reduces the risk of solder paste bridging short circuit by increasing the spacing between solder pads, the grooves provided on the insulating dielectric layer of the circuit board provided in this application can hold excess solder paste, thereby improving the risk of solder paste bridging short circuit. Furthermore, it does not require a large spacing between solder pads to hold excess solder paste, thus reducing the spacing between solder pads, achieving a denser arrangement of solder pads, and improving the space utilization of the circuit board. Attached Figure Description

[0024] Figure 1 This is a cross-sectional schematic diagram of a conductive structure formed on a substrate according to an embodiment of this application.

[0025] Figure 2 In order to be in Figure 1 The diagram shows a cross-sectional view of the structure in which the circuit layer and solder pads are formed.

[0026] Figure 3 In order to be in Figure 2 A schematic cross-sectional view of the structure shown, in which conductive bumps are formed.

[0027] Figure 4 In order to be in Figure 3 A schematic diagram of a cross-section on the structure shown, in which an insulating dielectric layer is formed.

[0028] Figure 5 In order to be in Figure 4 A schematic diagram of a cross-section on the structure shown, in which a protective layer is formed.

[0029] Figure 6 for Figure 5 A schematic diagram of the cross-section of the insulating dielectric layer and conductive bumps on the structure shown after polishing.

[0030] Figure 7 for Figure 6 A top view of the area containing the insulating dielectric layer, grooves, and conductive bumps.

[0031] Explanation of main component symbols

[0032]

[0033] Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of the embodiments of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other.

[0035] The following description sets forth numerous specific details to provide a thorough understanding of the embodiments of the present invention. The described embodiments are only a part of, and not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the embodiments of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the invention pertain. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention.

[0037] Please see Figures 1 to 7 One embodiment of this application provides a method for manufacturing a circuit board 100, comprising the following steps:

[0038] Step S1, please refer to Figure 1 A substrate 10 is provided, the substrate 10 including a substrate layer 11 and a conductor layer 12 disposed on a surface 11a of the substrate layer 11. The conductor layer 12 may be disposed on one surface 11a or two opposite surfaces 11a of the substrate layer 11. In this embodiment, the conductor layer 12 is disposed on two opposite surfaces 11a of the substrate layer 11.

[0039] The substrate layer 11 has electrical insulating properties, and its material can be selected from at least one of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and prepregs containing glass fiber and epoxy resin. This application does not impose any special limitations on the material of the substrate layer 11.

[0040] The conductor layer 12 has electrical conductivity, and its material can be selected from at least one of copper, silver, aluminum, etc. This application does not impose any special restrictions on the material of the conductor layer 12. In this embodiment, the conductor layer 12 is made of copper, that is, the substrate 10 is a double-sided copper-clad laminate.

[0041] For step S2, please refer to [link / reference]. Figure 1 A conductive structure 20 is formed that penetrates the substrate layer 11 and electrically connects the two conductor layers 12.

[0042] The conductive structure 20 can be a conductive hole or a conductive pillar. The conductive structure 20 can be formed by: making an opening in the substrate 10 to form a blind hole that penetrates the substrate layer 11 and a conductor layer 12, and then electroplating the blind hole to form a conductive hole, or electroplating the blind hole to fill it to form a conductive pillar.

[0043] It is understandable that when the substrate 10 is a single-sided copper-clad laminate, step S2 can be omitted.

[0044] Step S3, please refer to Figure 2 The conductor layer 12 is fabricated to form a circuit layer 13, which includes solder pads 16. The fabrication methods include, but are not limited to, laser etching or ink printing.

[0045] For step S4, please refer to [link / reference]. Figure 3 Conductive bumps 20 are formed on the surface of the solder pad 16 facing away from the substrate layer 11. The conductive bumps 20 can be cylindrical, cubic, or cuboid in shape. The number of conductive bumps 20 can be set according to actual needs. In this embodiment, a dry film is laminated on the surface of the circuit layer 13 facing away from the substrate layer 11. The dry film is exposed and developed to expose the portion of the circuit layer 13 where the conductive bumps 20 are to be formed. Then, the conductive bumps 20 are formed by electroplating on the exposed circuit layer 13. Finally, the dry film is removed. In this embodiment, the conductive bumps are cylindrical, and the number of conductive bumps is two.

[0046] The height of the conductive bump 20 can be 15–70 μm, and the diameter of the conductive bump 20 can be 100–200 μm. In this embodiment, the height of the conductive bump 20 is 50 μm, and the diameter of the conductive bump 20 is 125 μm. In this embodiment, the thickness of the conductive bump is selected as 12 μm, which corresponds to a minimum theoretical pad spacing of 335 μm. This is just an example; this application does not limit the height, diameter, thickness of the conductive bump 20, or the spacing of the pads 16.

[0047] For step S5, please refer to [link / reference]. Figure 4 An insulating dielectric layer 30 is formed on the surface of the circuit layer 13 opposite to the substrate layer 11. The insulating dielectric layer 30 covers the conductive bumps 20 and the solder pads 16. The insulating dielectric layer 30 is connected to the substrate layer 11 and also fills the gaps between the conductive bumps 20 and the gaps between the solder pads 16. In this way, the conductive bumps 20 can be firmly fixed on the substrate 10, preventing the conductive bumps 20 from falling off in subsequent processes.

[0048] In this embodiment, the method of "forming an insulating dielectric layer 30 on the surface of the circuit layer 13 away from the substrate layer 11" specifically includes:

[0049] A metal sheet is provided, with through grooves on the metal sheet corresponding to the areas where the solder pads 16 and conductive bumps 20 are located. The metal sheet is fitted onto the circuit layer 13, so that the conductive bumps 20 and solder pads 16 are exposed from the through grooves. Powdered or granular insulating dielectric material is filled into the through grooves. Finally, in a vacuum environment, heat melting and scraping or flattening are performed to remove gaps, so that the insulating dielectric material covers the conductive bumps 20 and solder pads 16, and reliably fills the gaps between the conductive bumps 20 and between the solder pads 16 and the circuit layer 13. After curing, the insulating dielectric material solidifies to form an insulating dielectric layer 30, thereby firmly fixing the conductive bumps 20 to the solder pads 16 and the substrate layer 11. The metal sheet can be made of materials such as copper, stainless steel, or aluminum, and the thickness of the metal sheet is designed according to the height of the conductive bumps. The insulating dielectric material can be at least one of BI resin, ABF resin, epoxy resin, polypropylene (PP), polyethylene terephthalate (PET), or polyolefin. Among them, BI resin refers to the resin obtained by reacting BMI resin (bismaleimide resin) and CE resin (triazine resin), and ABF resin refers to the resin whose structure is composed of three repeating units: phenylene, alkyl, and fluorine groups.

[0050] In other embodiments, an insulating dielectric layer 30 may be formed by repeatedly scraping resin ink and baking between the conductive bump 20 and the solder pad 16, and between the solder pad 16 and the circuit layer 13, so that the insulating dielectric layer 30 can fill the above-mentioned area and reach a preset height, so that the insulating dielectric layer 30 covers the conductive bump 20 and the solder pad 16.

[0051] Step S6, please refer to Figure 5 A protective layer 40 is formed on the surface of the insulating dielectric layer 30 facing away from the substrate layer 11 and on the surface of the circuit layer 13 facing away from the substrate layer 11. The protective layer 40 covers the entire surface of the insulating dielectric layer 30 facing away from the substrate layer 11, and also covers the surfaces of the substrate layer 11 and the circuit layer 13 exposed on the insulating dielectric layer 30. The material of the protective layer 40 may be selected from at least one of polyimide (PI) and polyvinyl chloride (PVC). This application does not impose any special limitations on the material of the protective layer 40.

[0052] In this embodiment, a cover layer (CVL) is laminated onto the side of the insulating dielectric layer 30 opposite to the substrate layer 11. The cover layer covers the insulating dielectric layer 30 and fills the gaps on the surface of the circuit layer 13. A cover layer is also laminated onto the other side of the substrate layer 11. The cover layer is then cured to form a protective layer 40. The cover layer comprises two material layers stacked on top of each other, one of which is a polyvinyl chloride layer and the other is a polyimide layer. Other insulating materials can also be used for the protective layer 40; this application does not limit the material of the protective layer 40.

[0053] For step S7, please refer to [link / reference]. Figure 6 The insulating dielectric layer 30 covering the conductive bumps 20 and the conductive bumps 20 are polished to expose the surface of the conductive bumps 20 facing away from the solder pads 16, making the surface of each conductive bump 20 facing away from the circuit layer 13 flush. This ensures the flatness and height consistency of the conductive bumps 20, preventing them from being affected by uneven dry film or uneven current density during electroplating. Polishing can be performed using physical methods such as mechanical grinding or ceramic roller brushes, achieving high precision, with the height tolerance of each conductive bump controlled within ±5μm after polishing. In this embodiment, the surface of the insulating dielectric layer 30 facing away from the circuit layer 13 is also flush with the surface of each conductive bump 20 facing away from the circuit layer 13.

[0054] Step S8, please refer to Figure 6 and Figure 7 A groove 50 is formed in the insulating dielectric layer 30, exposing a portion of the outer peripheral surface of the conductive bump 20. The groove 50 is arranged around the periphery of the conductive bump 20. The groove 50 is used to store excess solder paste and prevent excess solder paste from flowing outwards during soldering, forming solder paste bridges and causing short circuits.

[0055] The groove 50 can be formed using processes such as laser engraving or mechanical milling. The shape of the groove 50 can be annular or square. The number of grooves 50 can be set according to the number of conductive bumps 20. In this embodiment, the grooves 50 are formed by laser engraving, the grooves 50 are annular in shape, and there are two grooves 50.

[0056] The orthographic projection of the groove 50 along the thickness direction of the circuit board 100 lies within the solder pad 16. The depth of the groove 50 is greater than or equal to one-third and less than or equal to two-thirds of the height of the conductive bump 20. This ensures that the groove 50 has sufficient space to store excess solder paste, preventing solder bridging and short circuits, and preventing excess solder paste from affecting adjacent conductive bumps 20 and the circuit layer 13. Therefore, it eliminates the need for excessively large solder pad spacing to prevent solder bridging and short circuits, allowing for a smaller spacing between the solder pads 16 and a denser arrangement of the pads 16, which is beneficial for miniaturization of the circuit board 100 while ensuring the stability of the conductive bumps 20. This application does not limit the specific values ​​of the depth and diameter of the groove 50.

[0057] After the groove 50 is formed, along the thickness direction of the circuit board 100, the ratio of the bonding depth between the insulating dielectric layer 30 and the conductive bump 20 to the height of the conductive bump 20 is 1 / 3 to 2 / 3, which helps to ensure that the conductive bump 20 is always firmly fixed by the insulating dielectric layer 30. It can be understood that the bonding depth between the insulating dielectric layer 30 and the conductive bump 20 refers to the height of the conductive bump 20 covered by the insulating dielectric layer 30, calculated from the bottom surface of the conductive bump 20.

[0058] Please see Figure 6 This application also provides a circuit board 100, including a substrate layer 11, a circuit layer 13, conductive bumps 20, and an insulating dielectric layer 30. The circuit layer 13 is disposed on the surface of the substrate layer 11 and includes solder pads 16. The conductive bumps 20 are located on the surface of the solder pads 16 facing away from the substrate layer 11. The insulating dielectric layer 30 covers a portion of the outer peripheral surface of the conductive bumps 20 and the solder pads 16, and fills the gaps between the conductive bumps 20 and the gaps between the solder pads 16, and is connected to the substrate layer 11. A groove 50 is disposed on the exposed surface of the insulating dielectric layer 30 and surrounds the conductive bumps 20, and a portion of the outer peripheral surface of the conductive bumps 20 is exposed in the groove 50. In this embodiment, the circuit board 100 further includes a protective layer 40, which covers a portion of the insulating dielectric layer 30 and a portion of the circuit layer 30.

[0059] In some embodiments, the orthographic projection of the groove 50 along the thickness direction of the circuit board 100 is located within the solder pad 16, so that the groove 50 can store excess solder paste during soldering, and avoids the groove 50 being too wide to occupy the space of the adjacent conductive bump 20, thus avoiding affecting the adjacent conductive bump 20.

[0060] In some embodiments, along the thickness direction of the circuit board 100, the ratio of the bonding depth between the insulating dielectric layer 30 and the conductive bump 20 to the height of the conductive bump 20 is 1 / 3 to 2 / 3, so that the conductive bump 20 is always securely fixed by the insulating dielectric layer 30.

[0061] The circuit board 100 of this application has an insulating dielectric layer 30. The grooves 50 on the insulating dielectric layer 30 can hold excess solder paste, thereby improving the risk of short circuit due to solder paste bridging. Furthermore, there is no need to reserve a large spacing between the solder pads 16 to hold excess solder paste, thus reducing the spacing between the solder pads 16 and achieving a denser arrangement of the solder pads 16, thereby improving the space utilization of the circuit board 100.

[0062] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A circuit board, characterized in that, include: Substrate layer; A circuit layer is disposed on the surface of the substrate layer, the circuit layer including solder pads; A conductive bump, wherein the conductive bump is located on the surface of the solder pad opposite to the substrate layer; An insulating dielectric layer covers the conductive bump and the solder pad; the exposed surface of the insulating dielectric layer away from the substrate layer has a groove, the groove is arranged around the conductive bump, and a portion of the outer peripheral surface of the conductive bump is exposed in the groove.

2. The circuit board as described in claim 1, characterized in that, The circuit board further includes a protective layer that covers the surface of the insulating dielectric layer away from the substrate layer, and covers the surfaces of the substrate layer and the circuit layer exposed on the insulating dielectric layer.

3. The circuit board as described in claim 1, characterized in that, The orthographic projection of the groove along the thickness direction of the circuit board is located within the solder pad.

4. The circuit board as described in claim 1, characterized in that, The insulating dielectric layer fills the gaps between the conductive bumps and the gaps between the solder pads, and is connected to the substrate layer.

5. The circuit board as described in claim 1, characterized in that, Along the thickness direction of the circuit board, the ratio of the bonding depth between the insulating dielectric layer and the conductive bump to the height of the conductive bump is 1 / 3 to 2 / 3.

6. A method for manufacturing a circuit board, characterized in that, Includes the following steps: A substrate is provided, the substrate comprising a substrate layer and a conductor layer; The conductor layer is fabricated to form a circuit layer, the circuit layer including solder pads; Conductive bumps are formed on the surface of the solder pads that are away from the substrate layer; An insulating dielectric layer is formed on the surface of the circuit layer opposite to the substrate layer. The insulating dielectric layer covers the conductive bumps and the solder pads. The insulating dielectric layer is connected to the substrate layer and fills the gaps between the conductive bumps and the gaps between the solder pads. The insulating dielectric layer covering the conductive bumps is polished to expose the surface of the conductive bumps that faces away from the solder pads; A groove is formed in the insulating dielectric layer to expose part of the outer peripheral surface of the conductive bump.

7. The method for manufacturing a circuit board as described in claim 6, characterized in that, Before the step of "polishing the insulating dielectric layer covering the conductive bumps to expose the surface of the conductive bumps facing away from the solder pads", the following step is also included: pressing a cover film onto the opposite sides of the substrate layer to form a protective layer, the protective layer covering a portion of the circuit layer.

8. The method for manufacturing a circuit board as described in claim 6, characterized in that, "Forming an insulating dielectric layer on the surface of the circuit layer opposite to the substrate layer, wherein the insulating dielectric layer encloses the conductive bumps and the solder pads" specifically includes: A metal sheet is provided, with through grooves on the metal sheet corresponding to the areas where the solder pads and conductive bumps are located. The metal sheet is fitted onto the circuit layer, so that the conductive bumps and the solder pads are exposed from the through grooves. An insulating dielectric material is laid in the through grooves, so that the insulating dielectric material covers the conductive bumps and the solder pads. After curing, the insulating dielectric material is cured to form an insulating dielectric layer, which encapsulates the conductive bumps and the solder pads.

9. The method for manufacturing a circuit board as described in claim 6, characterized in that, The orthographic projection of the groove along the thickness direction of the circuit board is located within the solder pad.

10. The method for manufacturing a circuit board as described in claim 6, characterized in that, Along the thickness direction of the circuit board, the ratio of the bonding depth between the insulating dielectric layer and the conductive bump to the height of the conductive bump is 1 / 3 to 2 / 3.

Images