Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device includes gate lines each having a pair of main gate portions and a bridge portion; a dummy channel structure passing through the gate line in a vertical direction; and local word line cutting structures passing through respective local regions of the gate lines in a vertical direction and intermittently extending in a first direction to define a width of the bridge portion in the first direction, in which the dummy channel structure includes: a first normal dummy channel structure facing the local word line cutting structures in a second direction, each of the first and second terminals has a center on an imaginary straight line extending in the first direction; and at least one offset dummy channel structure facing the bridge portion in the second direction and having a center located at a position shifted from the imaginary straight line toward the bridge portion in the second direction.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0108969, filed on August 14, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices and electronic systems including such semiconductor devices, and more specifically, to semiconductor devices including non-volatile vertical memory devices and electronic systems including such semiconductor devices. Background Technology

[0004] To meet the needs of semiconductor devices capable of storing large amounts of data and electronic systems including such semiconductor devices, a semiconductor device including a vertical memory device is proposed, which includes memory cells arranged in three dimensions to increase the data storage capacity of the semiconductor device. Summary of the Invention

[0005] The present invention provides a semiconductor device having a structure configured to prevent (and / or) damage even as integration density increases in semiconductor devices comprising 3D arranged memory cells, during the manufacturing process of the semiconductor device.

[0006] Or reduce potential structural defects such as pattern collapse to ensure reliability and improve electronic properties.

[0007] The present invention also provides an electronic system including a semiconductor device having a structure configured to ensure reliability and improve electronic properties even as integration density increases in a semiconductor device including memory cells arranged in three dimensions. This is achieved by preventing (and / or reducing) potential structural defects such as pattern collapse during the manufacturing process of the semiconductor device.

[0008] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a plurality of gate lines overlapping each other in a vertical direction, each of the plurality of gate lines having a pair of main gate portions and a bridging portion connecting the pair of main gate portions to each other; a plurality of pseudo-channel structures passing through the plurality of gate lines in a vertical direction; and a partial word line dicing structure passing through corresponding partial regions of the plurality of gate lines in a vertical direction, the partial word line dicing structure extending intermittently in a first horizontal direction such that the width of the bridging portion is defined by the partial word line dicing structure in the first horizontal direction, wherein the plurality of pseudo-channel structures include A first pseudo-channel structure group, comprising a first pseudo-channel structure extending in a first horizontal direction, the first pseudo-channel structure being adjacent to a local word line cutting structure, and the first pseudo-channel structure group comprising: a first normal pseudo-channel structure facing the local word line cutting structure in a second horizontal direction orthogonal to the first horizontal direction, each of the first normal pseudo-channel structures having a center on an imaginary first straight line extending in the first horizontal direction; and at least one offset pseudo-channel structure facing the bridging portion in the second horizontal direction, and having a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction.

[0009] According to another aspect of the present invention, a semiconductor device is provided, comprising: a plurality of gate lines extending across a memory cell region, a pseudo-channel region, and a connection region, the memory cell region, the pseudo-channel region, and the connection region being sequentially arranged in a first horizontal direction within a memory cell block, the plurality of gate lines overlapping each other in a vertical direction; a plurality of channel structures passing through the plurality of gate lines in a vertical direction within the memory cell region; a plurality of pseudo-channel structures passing through the plurality of gate lines in a vertical direction within the pseudo-channel region; a pair of word line cut structures extending longitudinally in the first horizontal direction and defining the width of the memory cell block in a second horizontal direction, the second horizontal direction being orthogonal to the first horizontal direction; and a partial word line cut structure located between the pair of word line cut structures, the partial word line cut structure passing through a corresponding portion of the plurality of gate lines in a vertical direction. The region extends intermittently in a first horizontal direction, wherein each of the plurality of gate lines includes: a pair of main gate portions that respectively contact a pair of word line cut structures; and a bridging portion that connects the pair of main gate portions to each other in the pseudo-channel region, the bridging portion having a width defined by the local word line cut structure in the first horizontal direction, the plurality of pseudo-channel structures in the pseudo-channel region including: a first pseudo-channel structure group that includes a first pseudo-channel structure in a row adjacent to the local word line cut structure in the first horizontal direction, and the first pseudo-channel structure group including: a first normal pseudo-channel structure facing the local word line cut structure in a second horizontal direction, each of the first normal pseudo-channel structures having a center on an imaginary first straight line extending in the first horizontal direction; and an offset pseudo-channel structure facing the bridging portion in the second horizontal direction and having a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction.

[0010] According to another aspect of the present invention, an electronic system is provided, comprising: a main substrate; a semiconductor device disposed on the main substrate; and a controller disposed on the main substrate and electrically connected to the semiconductor device, wherein the semiconductor device comprises: a plurality of gate lines overlapping each other in a vertical direction; a plurality of pseudo-channel structures passing through the plurality of gate lines in a vertical direction; and partial word line dicing structures passing through corresponding partial regions of the plurality of gate lines in a vertical direction and extending intermittently in a first horizontal direction, the plurality of pseudo-channel structures including a first pseudo-channel structure group, the first... The pseudo-channel structure group includes a first pseudo-channel structure in a row extending in a first horizontal direction, the first pseudo-channel structure being adjacent to a local word line cutting structure, and the first pseudo-channel structure group includes: a first normal pseudo-channel structure facing the local word line cutting structure in a second horizontal direction orthogonal to the first horizontal direction, each of the first normal pseudo-channel structures having a center on an imaginary first straight line extending in the first horizontal direction; and at least one offset pseudo-channel structure facing the bridging portion in the second horizontal direction, and having a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction. Attached Figure Description

[0011] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a semiconductor device according to some embodiments;

[0013] Figure 2 This is a plan view illustrating a schematic planar structure of a portion of a memory cell array of a semiconductor device according to some embodiments;

[0014] Figure 3 This is a schematic perspective view of a portion of a semiconductor device according to some embodiments;

[0015] Figure 4 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to some embodiments;

[0016] Figure 5A It is shown Figure 2 A plan view of an example construction of region EX1;

[0017] Figure 5B It is shown Figure 2 A plan view of an example of the construction of region EX2;

[0018] Figure 6 It is shown Figure 2 A plan view of an example of the construction of region EX3;

[0019] Figure 7 It is along Figure 5A The line Y1-Y1' intercepted Figure 5A A cross-sectional view of region EX1;

[0020] Figure 8 It is along Figure 5A The line Y2-Y2' intercepted Figure 5A A cross-sectional view of region EX1;

[0021] Figure 9 It is along Figure 6 The line X1-X1' intercepts Figure 6 A cross-sectional view of region EX3;

[0022] Figure 10 yes Figure 5A A magnified planar view of region EX4;

[0023] Figures 11 to 18 These are plan views of semiconductor devices according to some embodiments;

[0024] Figure 19 This is a schematic diagram illustrating an electronic system including semiconductor devices according to some embodiments;

[0025] Figure 20 This is a schematic diagram illustrating an electronic system including semiconductor devices according to an embodiment;

[0026] Figure 21 This is a schematic cross-sectional view of a semiconductor package according to some embodiments;

[0027] Figure 22 This schematically illustrates a cross-sectional view of a semiconductor package according to some embodiments; and

[0028] Figures 23A to 34 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments, and specifically, Figure 23A , Figure 24A , Figure 25A , Figure 28A and Figure 31A It is shown according to a series of processes and along Figure 5A A cross-sectional view of some components in the region corresponding to the section intercepted by line Y1-Y1'. Figure 28B and Figure 31B It is shown according to a series of processes and along Figure 5A A cross-sectional view of some components in the region corresponding to the section intercepted by line Y2-Y2', and Figure 23B , Figure 24B , Figure 25B , Figure 26 , Figure 27 , Figure 28C , Figure 29 , Figure 30 , Figure 31C , Figure 32 , Figure 33 and Figure 34 It is shown according to a series of processes and along Figure 6 A cross-sectional view of some components in the region corresponding to the section intercepted by line X1-X1'. Detailed Implementation

[0029] In the following description, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same components are indicated by the same reference numerals throughout the specification, and their repeated description may be omitted.

[0030] The embodiments described are merely examples, and various modifications can be made from such embodiments. In the drawings, the dimensions of components may be exaggerated for ease of explanation. Additionally, when the terms "approximately" or "substantially" are used in conjunction with numerical and / or geometric terms in this specification, the numerical values ​​intended to be associated include manufacturing tolerances (e.g., ±10%) around the stated values. Furthermore, regardless of whether numerical and / or geometric terms are modified to "approximately" or "substantially," it will be understood that these values ​​should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometries.

[0031] In addition to the orientations depicted in the accompanying drawings, spatial relative terms such as “above,” “below,” and / or similar directional terms are intended to cover different orientations of the device during use or operation, and the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein are interpreted accordingly.

[0032] Figure 1 This is a block diagram of a semiconductor device 100 according to some embodiments.

[0033] Reference Figure 1 The semiconductor device 100 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple pads MT. Each of the multiple pads MT may include multiple memory cell blocks BLK1, BLK2, ..., and BLKp. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKp may include multiple memory cells. The multiple memory cell blocks BLK1, BLK2, ..., or BLKp may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL, respectively. In this document, the memory cell array 20 may also be referred to as a memory cell array MCA.

[0034] The peripheral circuitry 30 may include a line decoder 32, a page buffer 34, a data input / output circuitry 36, control logic 38, and a common source line driver 39. The peripheral circuitry 30 may also include various circuits, such as voltage generation circuits for generating the various voltages required for the operation of the semiconductor device 100, error correction circuits for correcting errors in the data read from the memory cell array 20, input / output interfaces, etc.

[0035] The memory cell array 20 can be connected to the row decoder 32 via word lines WL, serial select lines SSL, and ground select lines GSL, and can be connected to the page buffer 34 via bit lines BL. In the memory cell array 20, each of the multiple memory cells included in the multiple memory cell blocks BLK1, BLK2, ..., and BLKp can include flash memory cells. The memory cell array 20 can include a 3D memory cell array. The 3D memory cell array can include multiple NAND strings, and each of the multiple NAND strings can include multiple memory cells respectively connected to multiple vertically stacked word lines WL.

[0036] The peripheral circuit 30 can be configured to receive address ADDR, command CMD and control signal CTRL from outside the semiconductor device 100, and can be configured to transmit data DATA to and receive data DATA from outside the semiconductor device 100.

[0037] The row decoder 32 can be configured to select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKp in response to an address ADDR from outside the semiconductor device 100, and can be configured to select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can be configured to deliver a voltage for performing memory operations to the word line WL of the selected memory cell block.

[0038] Page buffer 34 can be connected to memory cell array 20 via bit line BL. Page buffer 34 can be configured to apply a voltage to bit line BL according to the voltage of data DATA to be stored in memory cell array 20 during a write driver operation, and can be configured to read data DATA stored in memory cell array 20 during a read operation as a sense amplifier operation. Page buffer 34 can be operated according to control signal PCTL provided by control logic 38.

[0039] Data input / output circuitry 36 can be connected to page buffer 34 via multiple data lines DLs. During programming operations, data input / output circuitry 36 can receive data DATA from memory controller (not shown) based on column address C_ADDR provided by control logic 38, and can provide programming data DATA to page buffer 34. During read operations, data input / output circuitry 36 can provide read data DATA stored in page buffer 34 to memory controller based on column address C_ADDR provided by control logic 38.

[0040] Data input / output circuitry 36 can transmit addresses or commands input to it to control logic 38 or line decoder 32. In at least some embodiments, peripheral circuitry 30 may also include electrostatic discharge (ESD) circuitry (not shown) and / or pull-up / pull-down drivers (not shown).

[0041] Control logic 38 can be configured to receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can be configured to provide row address R_ADDR to row decoder 32 and column address C_ADDR to data input / output circuitry 36. Control logic 38 can be configured to generate various internal control signals for the semiconductor device 100 in response to the control signal CTRL. For example, when performing memory operations such as programming or erasing operations, control logic 38 can adjust the levels of the voltages provided to word line WL and bit line BL, respectively.

[0042] The common source line driver 39 can be connected to the memory cell array 20 via the common source line CSL. The common source line driver 39 can apply a common source voltage (e.g., power supply voltage) or ground voltage to the common source line CSL based on the control signal CTRL_BIAS of the control logic 38.

[0043] Figure 2 This is a plan view illustrating a portion of the memory cell array 20 of a semiconductor device 100 according to some embodiments.

[0044] Reference Figure 2 The memory cell array 20 may include four pads MT, each arranged in one of the four quadrants of the rectangular region. Each of the four pads MT may include a memory cell region MEC, a pair of pseudo-channel regions DA arranged on both sides of the memory cell region MEC relative to the first horizontal direction (X direction), and a connection region CON arranged on one side of the memory cell region MEC relative to the first horizontal direction (X direction). One of the pair of pseudo-channel regions DA may be arranged between the memory cell region MEC and the connection region CON.

[0045] Figure 3 This is a schematic perspective view of a portion of a semiconductor device 100 according to some embodiments.

[0046] Reference Figure 3 The semiconductor device 100 may include a cell array structure CAS and a peripheral circuit structure PCS that overlap each other in the vertical direction (Z direction). The cell array structure CAS can be compared with a reference... Figure 1 and Figure 2 The described memory cell array 20 corresponds to this. The peripheral circuit structure PCS can be compared with the reference. Figure 1 The peripheral circuit 30 described corresponds to this.

[0047] In the CAS cell array structure, each of the multiple pads MT can include multiple memory cell blocks BLK1, BLK2, ..., and BLKp. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKp can include memory cells arranged in 3D.

[0048] Figure 4 This is an equivalent circuit diagram of the memory cell array 20 of the semiconductor device 100 according to some embodiments. Figure 4 An equivalent circuit diagram of a vertical NAND flash memory device with a vertical channel structure is shown.

[0049] Reference Figure 4 The memory cell array 20 may include multiple memory cell strings MS. The memory cell array 20 may include multiple bit lines BL (e.g., BL1, BL2, ..., and BLm), multiple word lines WL (e.g., WL1, WL2, ..., WLn-1 and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. The multiple memory cell strings MS may be formed between the multiple bit lines BL and the common source line CSL. Although... Figure 4 An example is shown where each of a plurality of memory cell strings (MS) includes one ground select line (GSL) and two string select lines (SSL), but the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0050] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be a region where the source regions of the multiple ground select transistors GST are connected together.

[0051] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Each of the multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to the word line WL.

[0052] Figure 5A It is shown Figure 2 A plan view of an example construction of region EX1. Figure 5B It is shown Figure 2 A plan view of an example of the construction of region EX2, and Figure 6 It is shown Figure 2 A plan view of an example of the construction of region EX3. Figure 7 It is along Figure 5A The line Y1-Y1' intercepted Figure 5A A cross-sectional view of region EX1. Figure 8 It is along Figure 5A The line Y2-Y2' intercepted Figure 5A A cross-sectional view of region EX1, and Figure 9 It is along Figure 6 The line X1-X1' intercepts Figure 6 A cross-sectional view of region EX3. Figure 10 yes Figure 5A A magnified plan view of region EX4. (Refer to...) Figures 5A to 10 The semiconductor device 100 is described in more detail.

[0053] Reference Figures 5A to 10 The cell array structure CAS of semiconductor device 100 may include multiple board common source lines 110 (see...). Figure 7 and Figure 8 ) and the memory cell block BLK arranged on each board common source line 110 (see Figure 5A , Figure 5B and Figure 6 The memory cell block BLK can be compared with a reference. Figure 1 and Figure 3 This describes a corresponding memory cell block BLK1, BLK2, ..., and BLKp. The peripheral circuit structure PCS (see...) Figure 7 , Figure 8 and Figure 9 The common source line 110 can be placed below the board common source line 110. The cell array structure CAS of the memory cell block BLK can be arranged to overlap with the peripheral circuit structure PCS in the vertical direction (Z direction), and the board common source line 110 is located between the cell array structure CAS of the memory cell block BLK and the peripheral circuit structure PCS.

[0054] The memory cell block BLK of the CAS (Computer-Aided Array) structure may include a pseudo-channel region DA, a memory cell region MEC, other pseudo-channel regions DA, and a connection region CON arranged sequentially in the first horizontal direction (X direction). The memory cell block BLK may also include a memory stack structure MST that extends across the memory cell region MEC, the pseudo-channel region DA, and the connection region CON in the first horizontal direction (X direction).

[0055] A memory cell block (BLK) may include multiple gate lines 130 arranged on a common source line 110 extending across the memory cell region (MEC), a pair of pseudo-channel regions (DA), and a connection region (CON). The multiple gate lines 130 may be stacked with spacing between them in the vertical direction (Z-direction) to overlap each other in the vertical direction (Z-direction). In each of the multiple memory stack structures (MST), the multiple gate lines 130 may constitute a gate stack (GS). Figure 1 The ground select line GSL, multiple word lines WL, and string select line SSL are shown.

[0056] In the connection region CON, the area occupied by multiple gate lines 130 in the XY plane can gradually decrease as the distance from the common source line 110 increases. In the memory cell region MEC and the pair of pseudo-channel regions DA, the areas occupied by multiple gate lines 130 in the XY plane can be substantially equal or substantially similar, regardless of the distance from the common source line 110.

[0057] In each of the plurality of gate lines 130, one edge portion in the first horizontal direction (X direction) may form a connection region CON, and the other edge portions in the first horizontal direction (X direction) may form a pseudo-channel region DA.

[0058] like Figures 5A to 8 As shown, multiple word line cut structures WLC1 extending longitudinally in the first horizontal direction (X direction) within the memory cell region MEC, pseudo-channel region DA, and connection region CON can be arranged on the board common source line 110. The multiple word line cut structures WLC1 can be spaced apart from each other in the second horizontal direction (Y direction). A memory cell block BLK can be arranged between adjacent pairs of word line cut structures WLC1 within the multiple word line cut structures WLC1. The multiple word line cut structures WLC1 can be arranged sequentially on both sides of the memory cell block BLK in the second horizontal direction (Y direction) to define the width of the memory cell block BLK in the second horizontal direction (Y direction).

[0059] A local word line dicing structure WLC2 extending longitudinally in the first horizontal direction (X direction) can be arranged in a memory cell block BLK. The local word line dicing structure WLC2 can pass through corresponding local regions of multiple gate lines 130 in the vertical direction (Z direction) between a pair of word line dicing structures WLC1 defining a memory cell block BLK, and can have a shape that extends intermittently in the first horizontal direction (X direction) in a plan view. For example, the local word line dicing structure WLC2 can include multiple regions spaced apart from each other in the first horizontal direction (X direction).

[0060] like Figure 5A , Figure 5B and Figure 10 As shown, in a memory cell block BLK, each of the plurality of gate lines 130 may include a pair of main gate portions MGPs respectively contacting a pair of adjacent word line cut structures WLC1, and a bridging portion WLE connecting the pair of main gate portions MGPs to each other. In the pseudo-channel region DA, the bridging portion WLE in each of the plurality of gate lines 130 of a memory cell block BLK can connect the pair of main gate portions MGPs to each other. The bridging portion WLE may have a width defined by the local word line cut structure WLC2 in a first horizontal direction (X direction).

[0061] In the memory cell block BLK, some regions of each of the multiple gate lines 130 may be spaced apart or separated from each other in a second horizontal direction (Y direction) by a local word line dicing structure WLC2. Each of the word line dicing structure WLC1 and the local word line dicing structure WLC2 may include an insulating structure. The insulating structure may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k materials, etc. In some embodiments, the insulating structure may include, but is not limited to, a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, a SiCN film, or a combination thereof. In some embodiments, at least a portion of the insulating structure may include an air gap. As used herein, the term "air" refers to the atmosphere or other gases that may be present during the manufacturing process.

[0062] like Figure 7 , Figure 8 and Figure 9 As shown, the cell array structure CAS may include a common source line 110 arranged in the memory cell region MEC, a first conductive plate 114 and a second conductive plate 118, an insulating plate 112 arranged in the connection region CON, and a memory stack structure MST.

[0063] like Figure 7 and Figure 8As shown, in the memory cell region (MEC) and the pseudo-channel region (DA), the first conductive plate 114, the second conductive plate 118, and the memory stack structure (MST) can be stacked on the board common source line 110 in the stated order. The board common source line 110, the first conductive plate 114, and the second conductive plate 118 can perform the function of supplying current to the common source line (CSL) of the vertical memory cells included in the cell array structure (CAS). Figure 9 As shown, in the connection region CON, the edge portions of the insulating plate 112, the second conductive plate 118, and the multiple gate lines 130 can be stacked on the common source line 110 of the plate in the order stated.

[0064] In some embodiments, the common source line 110 may include a semiconductor material such as polycrystalline silicon. Each of the first conductive plate 114 and the second conductive plate 118 may include a conductive material (e.g., a zero-bandgap material), such as a doped polycrystalline silicon film, a metal film, or a combination thereof. The metal film may include, but is not limited to, tungsten (W).

[0065] The memory stack structure (MST) may include a gate stack GS. The gate stack GS may include multiple gate lines 130 extending parallel to each other in the horizontal direction and overlapping each other in the vertical direction (Z direction). Each of the multiple gate lines 130 may include a conductive material, such as a metal, a metal silicide, an impurity-doped semiconductor, and / or combinations thereof. For example, each of the multiple gate lines 130 may include a metal (such as tungsten, nickel, cobalt, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, or combinations thereof.

[0066] A first insulating film 132 may be disposed between the second conductive plate 118 and the plurality of gate lines 130, and between each of the plurality of gate lines 130. The uppermost gate line 130 among the plurality of gate lines 130 may be covered by the first insulating film 132. The first insulating film 132 may include an insulator such as silicon oxide.

[0067] In the memory cell region MEC, pseudo-channel region DA, and connection region CON, multiple word line cut structures WLC1 can be arranged on the board common source line 110, and local word line cut structures WLC2 can be arranged between a pair of word line cut structures WLC1 defining a memory cell block BLK. The word line cut structures WLC1 can extend continuously longitudinally in the first horizontal direction (X direction), and the local word line cut structures WLC2 can extend intermittently longitudinally in the first horizontal direction (X direction).

[0068] In a memory cell block BLK, multiple gate lines 130 constituting a gate stack GS can be stacked such that they overlap each other in the vertical direction (Z direction). The multiple gate lines 130 constituting a gate stack GS may include those already referenced. Figure 1 The description includes the ground select line GSL, the word line WL, and the string select line SSL.

[0069] like Figure 7 As shown, the two gate lines 130 located at the top of the plurality of gate lines 130 can each be separated in the second horizontal direction (Y direction) by a string select line cut structure SSLC, and the gate lines 130 separated in this way can form a reference. Figure 1 The described string select line SSL. Although Figure 7 An example is shown where two string select wire cut structures (SSLCs) are formed in a gate stack (GS), but the inventive concept is not limited thereto. Figure 7 The example shown is illustrated. For instance, a string select wire-cut structure (SSLC) can be formed in a gate stack (GS). The SSLC may include an insulating film. In some embodiments, the SSLC may include an insulating film comprising an oxide film, a nitride film, or a combination thereof. In some embodiments, at least a portion of the SSLC may include an air gap.

[0070] like Figure 7 , Figure 8 and Figure 9 As shown, the peripheral circuit structure PCS may include a substrate 52, a plurality of peripheral circuits on the substrate 52, and a multilayer wiring structure MWS for connecting the plurality of peripheral circuits to each other or connecting the plurality of peripheral circuits to components in the memory cell region MEC.

[0071] Substrate 52 may include a semiconductor substrate. For example, substrate 52 may include Si, Ge, or SiGe. An active region AC may be defined in substrate 52 by a device isolation film 54. A plurality of transistors TR constituting a plurality of peripheral circuits may be formed on the active region AC. Each of the plurality of transistors TR may include a gate PG and a plurality of ion-implanted regions PSD formed on both sides of the gate PG in the active region AC. Each of the plurality of ion-implanted regions PSD may constitute a source region or a drain region.

[0072] The peripheral circuits of the PCS can include references. Figure 1 The peripheral circuitry 30 described includes various circuits. For example, the peripheral circuitry of the peripheral circuitry structure PCS may include multiple peripheral circuits. Figure 1 The row decoder 32, page buffer 34, data input / output circuit 36, control logic 38, and common source line driver 39 are shown.

[0073] The multilayer wiring structure (MWS) of the peripheral circuit structure (PCS) may include multiple wiring layers ML60, ML61, and ML62 and multiple contacts MC60, MC61, and MC62. At least some of the multiple wiring layers ML60, ML61, and ML62 may be configured to be electrically connected to transistors TR. The multiple contacts MC60, MC61, and MC62 may be configured to connect multiple transistors TR to some selected from the multiple wiring layers ML60, ML61, and ML62, respectively. Each of the multiple wiring layers ML60, ML61, and ML62 and the multiple contacts MC60, MC61, and MC62 may include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, each of the multiple wiring layers ML60, ML61, and ML62 and the multiple contacts MC60, MC61, and MC62 may include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0074] like Figure 9 As shown, the conductive landing pad LP can be disposed on a portion of the uppermost wiring layer ML62 among multiple wiring layers ML60, ML61, and ML62. The conductive landing pad LP can include polysilicon. The multiple transistors TR, the multilayer wiring structure MWS, and the conductive landing pad LP included in the peripheral circuit structure PCS can be covered by an interlayer dielectric 70. The interlayer dielectric 70 can include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof. A board common source line 110 can be disposed on the interlayer dielectric 70. The board common source line 110, the insulating plate 112, the first conductive plate 114, and the second conductive plate 118 can each extend horizontally to cover the peripheral circuit structure PCS.

[0075] like Figure 9 As shown, in some areas of the connection region CON, multiple through openings 120H can be formed to pass through the board common source line 110, the insulating plate 112, and the second conductive plate 118 in the vertical direction (Z direction). Each of the multiple through openings 120H can be filled with an insulating plug 120. The insulating plug 120 may include an insulating film, such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0076] like Figure 7 As shown, in the memory cell region (MEC), multiple channel structures 140 can pass through multiple gate lines 130, multiple first insulating films 132, a second conductive plate 118, a first conductive plate 114, and a common source line 110 in the vertical direction (Z direction). The multiple channel structures 140 can be arranged at specific intervals in a first horizontal direction (X direction) and a second horizontal direction (Y direction) to be spaced apart from each other. Figure 5A and Figure 5B As shown, multiple channel structures 140 can be arranged in a honeycomb structure in a plan view, with each channel structure 140 arranged sequentially at the interior center and corresponding vertices of an imaginary hexagon. Each of the multiple channel structures 140 may include a gate dielectric film 142, a channel region 144, a buried insulating film 146, and a drain region 148.

[0077] The gate dielectric film 142 may include a tunneling dielectric film, a charge storage film, and a barrier dielectric film formed on the channel region 144 in the stated order. The tunneling dielectric film may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film is a region capable of storing electrons that have passed through the tunneling dielectric film from the channel region 144, and may include, for example, silicon nitride, boron nitride, silicon boron nitride, impurity-doped polysilicon, or combinations thereof. The barrier dielectric film may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant greater than that of silicon oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0078] like Figure 7 As shown, the first conductive plate 114 may extend through a portion of the gate dielectric film 142 in a horizontal direction (X direction and / or Y direction) to contact the channel region 144. The gate dielectric film 142 may include a portion disposed at a level higher than the first conductive plate 114 and covering the sidewalls of the channel region 144, and a portion disposed at a level lower than the first conductive plate 114 and covering the lower surface of the channel region 144. The channel region 144 may be spaced apart from the board common source line 110, and the gate dielectric film 142 is located between the channel region 144 and the board common source line 110. The sidewalls of the channel region 144 may contact the first conductive plate 114 and may be configured to be electrically connected to the first conductive plate 114.

[0079] like Figure 7 As shown, the channel region 144 may be cylindrical. The channel region 144 may comprise doped or undoped polysilicon. A buried insulating film 146 may fill the internal space of the channel region 144. The buried insulating film 146 may comprise an insulating material. For example, the buried insulating film 146 may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the buried insulating film 146 may be omitted. In this case, the channel region 144 may have a cylindrical structure without internal space.

[0080] Drain regions 148 may include a doped polysilicon film. Multiple drain regions 148 may be insulated from each other by a first upper insulating film UL1. In the memory cell region (MEC), multiple channel structures 140 and the first upper insulating film UL1 may be covered by a second upper insulating film UL2.

[0081] The string select wire-cut structure SSLC can pass through the first upper insulating film UL1, the second upper insulating film UL2, and the third upper insulating film UL3 in the vertical direction (Z direction). The upper surfaces of the string select wire-cut structure SSLC, the upper surfaces of the word wire-cut structures WLC1 and WLC2, and the upper surface of the third upper insulating film UL3 can extend at approximately the same vertical level. The fourth upper insulating film UL4 and the fifth upper insulating film UL5 can be formed sequentially on the string select wire-cut structure SSLC, the word wire-cut structures WLC1 and WLC2, and the third upper insulating film UL3 in the order stated. Each of the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, and the fifth upper insulating film UL5 may include an oxide film, a nitride film, or a combination thereof.

[0082] like Figure 7 As shown, in the memory cell region MEC of the memory stack structure MST, multiple bit lines BL can be arranged on the fifth upper insulating film UL5. The multiple bit lines BL can extend parallel to each other in the second horizontal direction (Y direction). Multiple channel structures 140 can be connected to the multiple bit lines BL via multiple contact plugs 176 passing through the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, and the fifth upper insulating film UL5, respectively.

[0083] As in Figure 9 As shown, in the connection region CON, the insulating plate 112 and the second conductive plate 118 can be stacked sequentially on the common source line 110 in the stated order. The insulating plate 112 may include a multilayer insulating film, which includes a first insulating film 112A, a second insulating film 112B, and a third insulating film 112C stacked sequentially on the common source line 110 in the stated order. In some embodiments, the first insulating film 112A and the third insulating film 112C may each include a silicon oxide film, and the second insulating film 112B may include a silicon nitride film.

[0084] In the connection region CON, each of the multiple gate lines 130 may include a gate pad portion 130A having a thickness in the vertical direction (Z direction) greater than the thickness of other portions of the gate line 130. The gate pad portion 130A of the gate line 130 may be located in the edge portion of the gate line 130 furthest from the memory cell region MEC. Although Figure 9Only the gate pad portions 130A included in one end of some of the multiple gate lines 130 are shown, but... Figure 9 The gate line 130, shown as not having a gate pad portion 130A, may include a gate line arranged in a manner not present in the gate pad portion 130A. Figure 9 Gate pad portion 130A is shown in the other portions.

[0085] In the connection region CON, the edge portions of each of the plurality of gate lines 130 and the plurality of first insulating films 132 may be covered by an interlayer dielectric 138. The interlayer dielectric 138 may include, but is not limited to, a silicon oxide film.

[0086] like Figure 9 As shown, multiple memory cell contacts (MCCs) can be arranged in the connection region CON. Each of the multiple memory cell contacts (MCCs) can be arranged in a vertical via H1 passing through at least some of the interlayer dielectric 138, multiple gate lines 130, and multiple first insulating films 132. Each of the multiple memory cell contacts (MCCs) can pass through at least one gate line 130, at least one first insulating film 132, insulating plug 120, and conductive landing pad LP in the vertical direction (Z direction), and can be connected to each of the multiple wiring layers ML62 selected from the multiple wiring layers ML60, ML61, and ML62 in the multilayer wiring structure MWS of the peripheral circuit structure PCS.

[0087] Each of the plurality of memory cell contacts (MCCs) may be electrically connected to each gate line 130 selected from the plurality of gate lines 130, and may not be electrically connected to the other gate lines 130 except for one selected gate line 130. Each of the plurality of memory cell contacts (MCCs) may contact a gate pad portion 130A of each gate line 130 selected from the plurality of gate lines 130, and may be connected to a selected gate line 130 via the gate pad portion 130A. The memory cell contacts (MCCs) in the vertical hole H1 may be horizontally spaced from the other gate lines 130 except for one selected gate line 130. An insulating ring 152 may be disposed between the memory cell contacts (MCCs) and the gate lines 130 not connected to the memory cell contacts (MCCs). In some embodiments, the insulating ring 152 may include, but is not limited to, a silicon oxide film.

[0088] like Figure 5A , Figure 5B , Figure 6 , Figure 7 and Figure 9 As shown, multiple pseudo-channel structures D140 can be arranged in the pseudo-channel region DA and the connecting region CON. Figure 8As shown, in the pseudo-channel region DA, each of the plurality of pseudo-channel structures D140 can pass through multiple gate lines 130 and multiple first insulating films 132 in the vertical direction (Z direction). Figure 9 As shown, in the connection region CON, each of the plurality of dummy channel structures D140 can pass through at least some of the interlayer dielectric 138, the plurality of gate lines 130, and the plurality of first insulating films 132. In the connection region CON, each of the plurality of dummy channel structures D140 can pass through at least one of the plurality of gate lines 130. In the connection region CON, each of the plurality of dummy channel structures D140 can pass through at least one gate line 130, at least one first insulating film 132, the second conductive plate 118, and the insulating plate 112 in the vertical direction (Z direction), and can pass through a portion of the plate common source line 110 in the vertical direction (Z direction).

[0089] Similar to channel structure 140, each of the plurality of pseudo-channel structures D140 may include a gate dielectric film 142, a channel region 144, a buried insulating film 146, and a drain region 148; however, the planar dimensions of each of the plurality of pseudo-channel structures D140 may be larger than the planar dimensions of channel structure 140. In some embodiments, the plurality of pseudo-channel structures D140 may each include a silicon oxide plug. Figure 5A , Figure 5B , Figure 6 , Figure 7 and Figure 9 The number and arrangement of the pseudo-channel structures D140 shown are merely examples, and the inventive concept is not limited thereto. Multiple pseudo-channel structures D140 can be arranged differently in various locations selected within the memory stack structure MST in the pseudo-channel region DA and the connection region CON.

[0090] like Figure 9 As shown, in the connection region CON, the interlayer dielectric 138 can be covered by the first upper insulating film UL1. Figure 8 and Figure 9 As shown, in the pseudo-channel region DA and the connection region CON, the corresponding drain regions 148 of the plurality of pseudo-channel structures D140 can be insulated from each other by the first upper insulating film UL1. In the pseudo-channel region DA and the connection region CON, the plurality of pseudo-channel structures D140 and the first upper insulating film UL1 can be covered by the second upper insulating film UL2.

[0091] like Figure 9As shown, conductive plate contacts 164 can be arranged in the connection area CON. Conductive plate contacts 164 can extend vertically (Z-direction) through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the second conductive plate 118, and the insulating plate 112 to the common source line 110. The sidewalls of conductive plate contacts 164 can be covered by insulating spacers 162. A fourth upper insulating film UL4 can cover the upper surface of each of the conductive plate contacts 164 and the insulating spacers 162.

[0092] Multiple memory cell contacts (MCCs) can pass through the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, and the fourth upper insulating film UL4. The upper surface of each of the multiple memory cell contacts (MCCs) can be covered by the fifth upper insulating film UL5 and the sixth upper insulating film UL6.

[0093] The conductive plate contact 164 can be connected to one of the multiple upper wiring layers UML via contact plugs 172 passing through the fourth upper insulating film UL4 and the fifth upper insulating film UL5. The multiple upper wiring layers UML can be arranged at the same (or substantially similar) vertical level as the multiple bit lines BL arranged in the memory cell region MEC. The spaces between each of the multiple upper wiring layers UML and between each of the multiple bit lines BL can be filled with a sixth upper insulating film UL6. The sixth upper insulating film UL6 may comprise an oxide film, a nitride film, or a combination thereof.

[0094] Multiple memory cell contacts (MCCs), conductive plate contacts (164), multiple contact plugs (172), and multiple upper wiring layers (UMLs) may each include conductive materials such as tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof.

[0095] In the connection area CON, the board common source line 110, the insulating plate 112, the first conductive plate 114 and the second conductive plate 118 can extend in the horizontal direction (XY plane direction) to cover the peripheral circuit structure PCS.

[0096] Each of the multiple memory cell contacts (MCCs) can be configured to be connected to at least one peripheral circuit selected from the multiple peripheral circuits via a multilayer wiring structure (MWS) of the peripheral circuit structure (PCS). Although Figure 7 , Figure 8 and Figure 9 An example of a multilayer wiring structure (MWS) including three wiring layers in the vertical direction (Z direction) is shown, but the inventive concept is not limited thereto. For example, a multilayer wiring structure (MWS) may include two wiring layers or four or more wiring layers.

[0097] although Figure 6 The diagram illustrates a configuration in which multiple memory cell contacts (MCCs) are arranged in a row along a straight line in a first horizontal direction (X direction), but the inventive concept is not limited thereto. The planar placement configuration of each of the multiple memory cell contacts (MCCs) can be chosen differently without departing from the scope of the inventive concept.

[0098] like Figure 5A , Figure 5B and Figure 10 As shown, in the pseudo-channel region DA, multiple pseudo-channel structures D140 may include a first pseudo-channel structure group (e.g., Figure 10 The first pseudo-channel structure group GX1 shown includes first pseudo-channel structures arranged in a row in a first horizontal direction (X direction) adjacent to the local word line cutting structure WLC2. The first pseudo-channel structure belonging to the first pseudo-channel structure group GX1 among a plurality of pseudo-channel structures D140 may include: a first normal pseudo-channel structure DN1 facing and adjacent to the local word line cutting structure WLC2 in a second horizontal direction (Y direction); and an offset pseudo-channel structure SD1 facing and adjacent to the bridging portion WLE in the second horizontal direction (Y direction). The first normal pseudo-channel structures DN1 of the first pseudo-channel structure group GX1 may each have a center on an imaginary first straight line extending in the first horizontal direction (X direction) and may be arranged in a row in the first horizontal direction. The offset pseudo-channel structure SD1 may be arranged to be shifted from the imaginary first straight line toward the bridging portion WLE in the second horizontal direction (Y direction). That is, in the plan view, the center of the offset pseudo-channel structure SD1 can be located away from the imaginary first line and closer to the bridging portion WLE than to the imaginary first line.

[0099] In addition, such as Figure 5A , Figure 5B and Figure 10 As shown, in the pseudo-channel region DA, multiple pseudo-channel structures D140 may include a second pseudo-channel structure group (e.g., Figure 10 The second pseudo-channel structure group (GY1) shown includes second pseudo-channel structures arranged in a row along an imaginary second straight line extending across the bridging portion WLE of each of the plurality of gate lines 130 in a second horizontal direction (Y direction). The second pseudo-channel structures belonging to the second pseudo-channel structure group GY1 among the plurality of pseudo-channel structures D140 may include two offset pseudo-channel structures SD1 and a second normal pseudo-channel structure DN2, the second normal pseudo-channel structure DN2 being further away from the bridging portion WLE than the offset pseudo-channel structures SD1.

[0100] like Figure 10As detailed in the diagram, in each of a pair of main gate portions MGPs, the minimum distance between the offset pseudo-channel structure SD1 and the second normal pseudo-channel structure DN2 that is closest to the offset pseudo-channel structure SD1 in the second horizontal direction (Y direction) can be greater than the minimum distance between two adjacent second normal pseudo-channel structures DN2 in the second horizontal direction (Y direction). Therefore, in each of a pair of main gate portions MGPs, the minimum distance L2 between the center of the offset pseudo-channel structure SD1 and the center of the second normal pseudo-channel structure DN2 that is closest to the offset pseudo-channel structure SD1 in the second horizontal direction (Y direction) can be greater than the minimum distance L1 between the centers of two adjacent second normal pseudo-channel structures DN2 in the second horizontal direction (Y direction).

[0101] The minimum offset distance AD2 or AD3 between the offset pseudo-channel structure SD1 and the local word line cut structure WLC2 can be selected from a range of ±0.5 nm from the normal minimum distance AD1 between the local word line cut structure WLC2 and each of the first normal pseudo-channel structures DN1 belonging to the first pseudo-channel structure group GX1. For example, when the normal minimum distance AD1 is selected from a range of approximately 210 nm to approximately 250 nm, the minimum offset distance AD2 or AD3 can be selected from a range of approximately 209.5 nm to approximately 250.5 nm.

[0102] The minimum distance L3 between the centers of the two offset pseudo-channel structures SD1 belonging to the second pseudo-channel structure group GY1 can be equal to or greater than the minimum distance L2 between the center of the offset pseudo-channel structure SD1 and the center of the second normal pseudo-channel structure DN2 that is closest to the offset pseudo-channel structure SD1.

[0103] In the planar diagram, the pseudo-channel structures D140, excluding the second pseudo-channel structure of the second pseudo-channel structure group GY1, can be arranged at regular pitches in the first horizontal direction (X direction) and the second horizontal direction (Y direction) to form a matrix array structure. That is, in the pseudo-channel region DA, the pseudo-channel structure D140 positioned facing the local word line cutting structure WLC2 in the second horizontal direction (Y direction) can be arranged at regular pitches in the first horizontal direction (X direction) and the second horizontal direction (Y direction) to form a matrix array structure. For example, as... Figure 5A and Figure 10As shown, in the pseudo-channel region DA, multiple pseudo-channel structures D140 may include a normal pseudo-channel structure group GN1. The normal pseudo-channel structure group GN1 includes a third pseudo-channel structure. The third pseudo-channel structure is arranged between the local word line cut structure WLC2 and each of the pair of word line cut structures WLC1 to pass through at least one main gate portion MGP selected from a pair of main gate portions MGPs of each of the multiple gate lines 130 in the vertical direction (Z direction). In the plan view, the third pseudo-channel structure of the normal pseudo-channel structure group GN1 may be arranged with a regular pitch in the first horizontal direction (X direction) and the second horizontal direction (Y direction) to form a matrix array structure.

[0104] According to reference Figures 1 to 10 The semiconductor device 100 described, in a pseudo-channel region DA including a plurality of pseudo-channel structures D140 supporting a plurality of gate lines 130 and a plurality of first insulating films 132, an offset pseudo-channel structure SD1 among the plurality of pseudo-channel structures D140 facing and adjacent to the bridging portion WLE in the second horizontal direction (Y direction) may not be in the arrangement rules of the first normal pseudo-channel structure DN1, the first normal pseudo-channel structures DN1 being arranged in a row in the first horizontal direction (X direction), and may be arranged to be shifted in the second horizontal direction (Y direction) from an imaginary first straight line passing through the center of each of the first normal pseudo-channel structures DN1 toward the bridging portion WLE. Therefore, even when the planar area of ​​the bridging portion WLE of each of the plurality of gate lines 130 arranged in a straight line in the first horizontal direction (X direction) together with the intermittently longitudinally extending local word line cut structures WLC2 in the first horizontal direction (X direction) is relatively large, the bridging portion WLE of each of the plurality of gate lines 130 in each of the plurality of first insulating films 132, as well as the local region overlapping with the bridging portion WLE in the vertical direction (Z direction), can be stably supported by the offset pseudo-channel structure SD1. Furthermore, during the manufacturing process of the semiconductor device 100, before the formation of the plurality of gate lines 130, structural defects such as pattern collapse can be mitigated and / or prevented, in which the local region overlapping with the region corresponding to the bridging portion WLE in each of the plurality of first insulating films 132 collapses, and thus the reliability and electrical characteristics of the semiconductor device 100 can be improved.

[0105] Figures 11 to 18 These are plan views illustrating semiconductor devices 100A, 200, 300, 300A, 400, 500, 500A, and 600 according to some embodiments. Figures 11 to 18 The same reference numerals in the figures respectively indicate as follows: Figures 1 to 10 The same components are mentioned here, and their differences are discussed here and there, while for the sake of brevity, repeated descriptions can be omitted.

[0106] Reference Figure 11 The semiconductor device 100A includes a plurality of pseudo-channel structures D140A arranged in the pseudo-channel region DA.

[0107] In addition to the following, multiple pseudo-channel structures D140A have similar characteristics to the reference. Figures 5A to 10 The multiple pseudo-channel structures D140 described are substantially identical (and / or substantially similar) in construction: the multiple pseudo-channel structures D140A arranged in the pseudo-channel region DA of the semiconductor device 100A include a first pseudo-channel structure group GX1A and a second pseudo-channel structure group GY1A. The first pseudo-channel structure group GX1A includes a first pseudo-channel structure arranged in a row in a first horizontal direction (X direction) adjacent to the local word line cut structure WLC2. The second pseudo-channel structure group GY1A includes a second pseudo-channel structure arranged in a row in a second horizontal direction (Y direction) across the bridging portion WLE of each of the multiple gate lines 130.

[0108] The first pseudo-channel structure belonging to the first pseudo-channel structure group GX1A among multiple pseudo-channel structures D140A may include a first normal pseudo-channel structure DN1A facing the local word line cutting structure WLC2 in the second horizontal direction (Y direction), and an offset pseudo-channel structure SD1A facing and adjacent to the bridging portion WLE in the second horizontal direction (Y direction). The first normal pseudo-channel structures DN1A of the first pseudo-channel structure group GX1A may each have a center on an imaginary first straight line extending in the first horizontal direction (X direction), and may be arranged in a row in the first horizontal direction (X direction). The offset pseudo-channel structure SD1A may be arranged to be shifted from the imaginary first straight line toward the bridging portion WLE in the second horizontal direction (Y direction). That is, in a plan view, the center of the offset pseudo-channel structure SD1A may be arranged at a position offset from the imaginary first straight line to be closer to the bridging portion WLE than to the imaginary first straight line.

[0109] In a planar view, the offset pseudo-channel structure SD1A may have a shape in which its dimension in the second horizontal direction (Y direction) is larger than its dimension in the first horizontal direction (X direction). In some embodiments, the offset pseudo-channel structure SD1A may have an elliptical planar shape. In a planar view, the dimension of the offset pseudo-channel structure SD1A in the second horizontal direction (Y direction) may be larger than the dimension in the second horizontal direction (Y direction) of each of the first normal pseudo-channel structures DN1A in the first pseudo-channel structure group GX1A.

[0110] Furthermore, in the pseudo-channel region DA, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY1A among the multiple pseudo-channel structures D140A may include two offset pseudo-channel structures SD1A and a second normal pseudo-channel structure DN2A, with the second normal pseudo-channel structure DN2A being further away from the bridging portion WLE than the two offset pseudo-channel structures SD1A.

[0111] In the plan view, the dimension of the offset pseudo-channel structure SD1A in the second horizontal direction (Y direction) can be greater than the dimension of each of the second normal pseudo-channel structures DN2A in the second pseudo-channel structure group GY1A in the second horizontal direction (Y direction). The minimum distance between the offset pseudo-channel structure SD1A and the second normal pseudo-channel structure DN2A that is closest to the offset pseudo-channel structure SD1A in the second horizontal direction (Y direction) can be greater than the minimum distance between two adjacent second normal pseudo-channel structures DN2A in the second horizontal direction (Y direction). Therefore, the minimum distance L2A between the center of the offset pseudo-channel structure SD1A and the center of the second normal pseudo-channel structure DN2A that is closest to the offset pseudo-channel structure SD1A can be greater than the minimum distance L1 between two adjacent second normal pseudo-channel structures DN2A in the second horizontal direction (Y direction).

[0112] The minimum offset distance AD2A or AD3A between the offset pseudo-channel structure SD1A and the local word line cut structure WLC2 can be selected from the range of ±0.5nm between the local word line cut structure WLC2 and each of the first normal pseudo-channel structures DN1A belonging to the first pseudo-channel structure group GX1A.

[0113] The minimum distance L3A between the centers of the two offset pseudo-channel structures SD1A belonging to the second pseudo-channel structure group GY1A can be equal to or greater than the minimum distance L2A between the center of the offset pseudo-channel structure SD1A and the center of the second normal pseudo-channel structure DN2A that is closest to the offset pseudo-channel structure SD1A.

[0114] As described above, the more detailed construction of the first normal pseudo-channel structure DN1A in the first pseudo-channel structure group GX1A and the second normal pseudo-channel structure DN2A in the second pseudo-channel structure group GY1A can be found in other respects with reference to [reference]. Figure 10 The more detailed construction of the first normal pseudo-channel structure DN1 and the second normal pseudo-channel structure DN2 is the same (and / or substantially similar).

[0115] Reference Figure 12The semiconductor device 200 includes a plurality of pseudo-channel structures D240 arranged in the pseudo-channel region DA.

[0116] In addition to the following, multiple pseudo-channel structures D240 have similar characteristics to the reference. Figures 5A to 10 The multiple pseudo-channel structures D140 described are substantially identical (or substantially similar) in construction: the multiple pseudo-channel structures D240 arranged in the pseudo-channel region DA of the semiconductor device 200 include a second pseudo-channel structure group GY2, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE across each of the multiple gate lines 130 in a second horizontal direction (Y direction).

[0117] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY2 among the multiple pseudo-channel structures D240 may include two offset pseudo-channel structures SD2 facing the bridging portion WLE and adjacent to the bridging portion WLE in the second horizontal direction (Y direction).

[0118] In the planar view, in each of a pair of main gate portions MGPs, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY2 may include an offset pseudo-channel structure SD2 and a second normal pseudo-channel structure DN22, the second normal pseudo-channel structure DN22 being further away from the bridging portion WLE than the offset pseudo-channel structure SD2. In each of the pair of main gate portions MGPs, the offset pseudo-channel structure SD2 and the second normal pseudo-channel structure DN22 arranged in a row in the second horizontal direction (Y direction) may be arranged with a regular pitch in the second horizontal direction (Y direction). That is, in a main gate portion MGP, the center-to-center distance L22 between two adjacent offset pseudo-channel structures SD2 and second normal pseudo-channel structures DN22 may be constant.

[0119] The center-to-center distance L23 of the two offset pseudo-channel structures SD2, which are included in the second pseudo-channel structure group GY2 and are spaced apart from each other in the second horizontal direction (Y direction) and whose bridging portion WLE is located therebetween, can be greater than the center-to-center distance L22 of the two adjacent pseudo-channel structures DN22 in the second normal pseudo-channel structure DN22 in the second horizontal direction (Y direction).

[0120] Reference Figure 13 In addition to the following, the semiconductor device 300 has the same characteristics as the referenced device. Figures 1 to 10The semiconductor device 300 described is substantially the same (or substantially similar) in construction as the semiconductor device 100: The semiconductor device 300 includes a local word line dicing structure WLC32 and a plurality of pseudo-channel structures D340. The local word line dicing structure WLC32 passes through corresponding local regions of a plurality of gate lines 130 in the vertical direction (Z direction) and has a shape that extends intermittently in a first horizontal direction (X direction) in a plan view. The plurality of pseudo-channel structures D340 are arranged in pseudo-channel regions DA to pass through the plurality of gate lines 130 in the vertical direction (Z direction). Each of the plurality of gate lines 130 may include a bridging portion WLE3 connecting a pair of main gate portions MGPs to each other, and the bridging portion WLE3 may have a width defined by the local word line dicing structure WLC32 in the first horizontal direction (X direction). The local word line dicing structure WLC32 and the plurality of pseudo-channel structures D340 respectively have the same configuration as referenced... Figures 5A to 10 The described local word line cut structure WLC2 and the plurality of pseudo-channel structures D140 have the same (or substantially similar) construction. However, the plurality of pseudo-channel structures D340 arranged in the pseudo-channel region DA of the semiconductor device 300 include a second pseudo-channel structure group GY3, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE3 spanning each of the plurality of gate lines 130 in the second horizontal direction (Y direction).

[0121] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY3 among the multiple pseudo-channel structures D340 may include four offset pseudo-channel structures SD31 that face the bridging portion WLE3 and are adjacent to the bridging portion WLE3 in the second horizontal direction (Y direction).

[0122] In the plan view, in each of a pair of main gate portions MGP, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY3 may include two offset pseudo-channel structures SD31 and a second normal pseudo-channel structure DN23, the second normal pseudo-channel structure DN23 being further away from the bridging portion WLE3 than the two offset pseudo-channel structures SD31.

[0123] In each of the pair of main gate portions MGPs, the minimum distance in the second horizontal direction (Y direction) between the offset pseudo-channel structure SD31 and the second normal pseudo-channel structure DN23 that is closest to the offset pseudo-channel structure SD31 can be greater than the minimum distance between two adjacent second normal pseudo-channel structures DN23 in the second horizontal direction (Y direction). Therefore, in each of the pair of main gate portions MGPs, the minimum distance L32 in the second horizontal direction (Y direction) between the center of the offset pseudo-channel structure SD31 and the center of the second normal pseudo-channel structure DN23 that is closest to the offset pseudo-channel structure SD31 can be greater than the minimum distance L1 between the centers of two adjacent second normal pseudo-channel structures DN23 in the second horizontal direction (Y direction).

[0124] Among the four offset pseudo-channel structures SD31 belonging to the second pseudo-channel structure group GY3, the corresponding centers of the two offset pseudo-channel structures SD31 arranged in a row in the second horizontal direction (Y direction) can be arranged on a straight line extending in the second horizontal direction (Y direction). The minimum distance L33 between the centers of the two offset pseudo-channel structures SD31 on the straight line in the second horizontal direction (Y direction) can be equal to or greater than the minimum distance L32 between the center of the offset pseudo-channel structure SD31 and the center of the second normal pseudo-channel structure DN23 that is closest to the offset pseudo-channel structure SD31 in the second horizontal direction (Y direction).

[0125] The centers of the two offset pseudo-channel structures SD31 arranged in a row in the first horizontal direction (X direction) among the four offset pseudo-channel structures SD31 belonging to the second pseudo-channel structure group GY3 can be arranged on a straight line extending in the first horizontal direction (X direction).

[0126] Semiconductor device 300 has a minimum offset distance AD32 or AD33 between the offset pseudo-channel structure SD31 and the local word line cut structure WLC32. Semiconductor device 300 also has a normal minimum distance AD1 between the local word line cut structure WLC32 and the pseudo-channel structure D340, which faces and is closest to the local word line cut structure WLC32 in the second horizontal direction (Y direction). The minimum offset distance AD32 or AD33 can be selected from a range of ±0.5 nm from the normal minimum distance AD1.

[0127] Reference Figure 14 Semiconductor device 300A has the same characteristics as the reference. Figure 13The semiconductor device 300A described has the same (or substantially similar) construction. However, the semiconductor device 300A includes a plurality of pseudo-channel structures D340A arranged in the pseudo-channel region DA.

[0128] Multiple pseudo-channel structures D340A have similar characteristics to the reference Figure 13 The described multiple pseudo-channel structures D340 have the same (or substantially similar) construction. However, the multiple pseudo-channel structures D340A arranged in the pseudo-channel region DA of the semiconductor device 300A include a second pseudo-channel structure group GY3A, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE3 spanning each of the multiple gate lines 130 in the second horizontal direction (Y direction).

[0129] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY3A among the multiple pseudo-channel structures D340A may include four offset pseudo-channel structures SD31A that face and are adjacent to the bridging portion WLE3 in the second horizontal direction (Y direction).

[0130] In the plan view, in each of a pair of main gate portions MGP, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY3A may include two offset pseudo-channel structures SD31A and a second normal pseudo-channel structure DN23A, the second normal pseudo-channel structure DN23A being further away from the bridging portion WLE3 than the two offset pseudo-channel structures SD31A.

[0131] In the plan view, the offset pseudo-channel structure SD31A may have a shape in which its dimension in the second horizontal direction (Y direction) is larger than its dimension in the first horizontal direction (X direction). In some embodiments, the offset pseudo-channel structure SD31A may have an elliptical planar shape. In the plan view, the dimension of each of the four offset pseudo-channel structures SD31A belonging to the second pseudo-channel structure group GY3A in the second horizontal direction (Y direction) may be larger than the dimension of each of the second normal pseudo-channel structures DN23A in the second horizontal direction (Y direction).

[0132] The minimum distance in the second horizontal direction (Y direction) between the offset pseudo-channel structure SD31A and the second normal pseudo-channel structure DN23A, where the second normal pseudo-channel structure DN23A is closest to the offset pseudo-channel structure SD31A, can be greater than the minimum distance in the second horizontal direction (Y direction) between two adjacent second normal pseudo-channel structures DN23A. Therefore, the minimum distance L32A in the second horizontal direction (Y direction) between the center of the offset pseudo-channel structure SD31A and the center of the second normal pseudo-channel structure DN23A, where the second normal pseudo-channel structure DN23A is closest to the offset pseudo-channel structure SD31A, can be greater than the minimum distance L1 between the centers of two adjacent second normal pseudo-channel structures DN23A in the second horizontal direction (Y direction).

[0133] Semiconductor device 300A has a minimum offset distance AD32A or AD33A between the offset pseudo-channel structure SD31A and the local word line dicing structure WLC32. Semiconductor device 300A also has a normal minimum distance AD1 between the local word line dicing structure WLC32 and the pseudo-channel structure D340A, which faces and is closest to the local word line dicing structure WLC32 in the second horizontal direction (Y direction). The minimum offset distance AD32A or AD33A can be selected from a range of ±0.5 nm from the normal minimum distance AD1.

[0134] Among the four offset pseudo-channel structures SD31A belonging to the second pseudo-channel structure group GY3A, the centers of the two offset pseudo-channel structures SD31A arranged in a row in the second horizontal direction (Y direction) can be arranged on a straight line extending in the second horizontal direction (Y direction). The minimum distance L33A between the centers of the two offset pseudo-channel structures SD31A on the straight line in the second horizontal direction (Y direction) can be equal to or greater than the minimum distance L32A between the center of the offset pseudo-channel structure SD31A and the center of the second normal pseudo-channel structure DN23A closest to the offset pseudo-channel structure SD31A.

[0135] The centers of the two offset pseudo-channel structures SD31A arranged in a row in the first horizontal direction (X direction) among the four offset pseudo-channel structures SD31A belonging to the second pseudo-channel structure group GY3A can be arranged on a straight line extending in the first horizontal direction (X direction).

[0136] Reference Figure 15 The semiconductor device 400 has a reference Figure 13The semiconductor device 300 described has the same (or substantially similar) construction. However, the semiconductor device 400 includes a plurality of pseudo-channel structures D440 arranged in the pseudo-channel region DA.

[0137] Multiple pseudo-channel structures D440 have similar characteristics to the reference. Figure 13 The described multiple pseudo-channel structures D340 have substantially the same (or substantially similar) construction. However, the multiple pseudo-channel structures D440 arranged in the pseudo-channel region DA of the semiconductor device 400 include a second pseudo-channel structure group GY4, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE3 spanning each of the multiple gate lines 130 in the second horizontal direction (Y direction).

[0138] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY4 among the multiple pseudo-channel structures D440 may include four offset pseudo-channel structures SD4 facing and adjacent to the bridging portion WLE3 in the second horizontal direction (Y direction).

[0139] In the plan view, in each of a pair of main gate portions MGPs, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY4 may include two offset pseudo-channel structures SD4 and a second normal pseudo-channel structure DN24, the second normal pseudo-channel structure DN24 being further away from the bridging portion WLE3 than the offset pseudo-channel structure SD4. In each of a pair of main gate portions MGPs, the offset pseudo-channel structures SD4 and the second normal pseudo-channel structure DN24 arranged in a row in the second horizontal direction (Y direction) may be arranged with a regular pitch in the second horizontal direction (Y direction). That is, in one main gate portion MGP, the center-to-center distance L42 between two adjacent offset pseudo-channel structures SD4 and the second normal pseudo-channel structure DN24 may be constant.

[0140] The center-to-center distance L43 of the two offset pseudo-channel structures SD4, which are included in the second pseudo-channel structure group GY4 and are spaced apart from each other in the second horizontal direction (Y direction) and in which the bridging portion WLE3 is located, can be greater than the center-to-center distance L42 of the two normal pseudo-channel structures DN24 that are adjacent to each other in the second horizontal direction (Y direction).

[0141] Reference Figure 16 The semiconductor device 500 has the same characteristics as the reference. Figures 1 to 10The semiconductor device 500 described has the same (or substantially similar) construction as the semiconductor device 100. However, the semiconductor device 500 includes: a local word line dicing structure WLC52 that passes through corresponding local regions of a plurality of gate lines 130 in a vertical direction (Z direction) and has a shape that extends intermittently in a first horizontal direction (X direction); and a plurality of pseudo-channel structures D540 arranged in pseudo-channel regions DA to pass through the plurality of gate lines 130 in a vertical direction (Z direction). Each of the plurality of gate lines 130 may include a bridging portion WLE5 connecting a pair of main gate portions MGPs to each other, and the bridging portion WLE5 may have a width defined by the local word line dicing structure WLC52 in the first horizontal direction (X direction). The local word line dicing structure WLC52 and the plurality of pseudo-channel structures D540 each have a construction similar to the referenced... Figures 5A to 10 The described local word line cut structure WLC2 and the plurality of pseudo-channel structures D140 have the same (or substantially similar) construction. However, the plurality of pseudo-channel structures D540 arranged in the pseudo-channel region DA of the semiconductor device 500 include a second pseudo-channel structure group GY5, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE5 spanning each of the plurality of gate lines 130 in the second horizontal direction (Y direction).

[0142] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY5 among the multiple pseudo-channel structures D540 may include six offset pseudo-channel structures SD51 that face and are adjacent to the bridging portion WLE5 in the second horizontal direction (Y direction).

[0143] In the plan view, in each of a pair of main gate portions MGP, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY5 may include three offset pseudo-channel structures SD51 and a second normal pseudo-channel structure DN25, the second normal pseudo-channel structure DN25 being further away from the bridging portion WLE5 than the three offset pseudo-channel structures SD51.

[0144] In each of the pair of main gate portions MGPs, the minimum distance in the second horizontal direction (Y direction) between the offset pseudo-channel structure SD51 and the second normal pseudo-channel structure DN25 that is closest to the offset pseudo-channel structure SD51 can be greater than the minimum distance between two adjacent second normal pseudo-channel structures DN25 in the second horizontal direction (Y direction). Therefore, in each of the pair of main gate portions MGPs, the minimum distance L52 in the second horizontal direction (Y direction) between the center of the offset pseudo-channel structure SD51 and the center of the second normal pseudo-channel structure DN25 that is closest to the offset pseudo-channel structure SD51 can be greater than the minimum distance L1 between the centers of two adjacent second normal pseudo-channel structures DN25 in the second horizontal direction (Y direction).

[0145] Among the six offset pseudo-channel structures SD51 belonging to the second pseudo-channel structure group GY5, the corresponding centers of two offset pseudo-channel structures SD51 arranged in a row in the second horizontal direction (Y direction) can be arranged on a straight line extending in the second horizontal direction (Y direction). The minimum distance L53 between the centers of the two offset pseudo-channel structures SD51 on the straight line in the second horizontal direction (Y direction) can be equal to or greater than the minimum distance L52 between the center of the offset pseudo-channel structure SD51 and the center of the second normal pseudo-channel structure DN25 that is closest to the offset pseudo-channel structure SD51 in the second horizontal direction (Y direction).

[0146] The centers of the three offset pseudo-channel structures SD51 arranged in a row in the first horizontal direction (X direction) among the six offset pseudo-channel structures SD51 belonging to the second pseudo-channel structure group GY5 can be arranged on a straight line extending in the first horizontal direction (X direction).

[0147] Semiconductor device 500 has a minimum offset distance AD52 or AD53 between an offset pseudo-channel structure SD51 and a local word line cut structure WLC52. Semiconductor device 500 also has a normal minimum distance AD1 between the local word line cut structure WLC52 and a pseudo-channel structure D540 that faces and is closest to the local word line cut structure WLC52 in the second horizontal direction (Y direction). The minimum offset distance AD52 or AD53 can be selected from a range of ±0.5 nm from the normal minimum distance AD1.

[0148] Reference Figure 17 Semiconductor device 500A has the same characteristics as the reference. Figure 16The semiconductor device 500A described has the same (or substantially similar) construction. However, the semiconductor device 500A includes a plurality of pseudo-channel structures D540A arranged in the pseudo-channel region DA.

[0149] Multiple pseudo-channel structures D540A have similar characteristics to the reference Figure 16 The described multiple pseudo-channel structures D540 have the same (or substantially similar) construction. However, the multiple pseudo-channel structures D540A arranged in the pseudo-channel region DA of the semiconductor device 500A include a second pseudo-channel structure group GY5A, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE5 spanning each of the multiple gate lines 130 in the second horizontal direction (Y direction).

[0150] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY5A among the multiple pseudo-channel structures D540A may include six offset pseudo-channel structures SD51A that face and are adjacent to the bridging portion WLE5 in the second horizontal direction (Y direction).

[0151] In the plan view, in each of a pair of main gate portions MGP, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY5A may include three offset pseudo-channel structures SD51A and a second normal pseudo-channel structure DN25A, the second normal pseudo-channel structure DN25A being further away from the bridging portion WLE5 than the three offset pseudo-channel structures SD51A.

[0152] In the plan view, the offset pseudo-channel structure SD51A may have a shape in which its dimension in the second horizontal direction (Y direction) is larger than its dimension in the first horizontal direction (X direction). In some embodiments, the offset pseudo-channel structure SD51A may have an elliptical planar shape. In the plan view, the dimension of each of the six offset pseudo-channel structures SD51A belonging to the second pseudo-channel structure group GY5A in the second horizontal direction (Y direction) may be larger than the dimension of each of the second normal pseudo-channel structures DN25A in the second horizontal direction (Y direction).

[0153] The minimum distance in the second horizontal direction (Y direction) between the offset pseudo-channel structure SD51A and the second normal pseudo-channel structure DN25A that is closest to the offset pseudo-channel structure SD51A can be greater than the minimum distance between two adjacent second normal pseudo-channel structures DN25A in the second horizontal direction (Y direction). Therefore, the minimum distance L52A in the second horizontal direction (Y direction) between the center of the offset pseudo-channel structure SD51A and the center of the second normal pseudo-channel structure DN25A that is closest to the offset pseudo-channel structure SD51A can be greater than the minimum distance L1 between the centers of two adjacent second normal pseudo-channel structures DN25A in the second horizontal direction (Y direction).

[0154] Semiconductor device 500A has a minimum offset distance AD52A or AD53A between the offset pseudo-channel structure SD51A and the local word line dicing structure WLC52. Semiconductor device 500A also has a normal minimum distance AD1 between the local word line dicing structure WLC52 and the pseudo-channel structure D540A, which faces and is closest to the local word line dicing structure WLC52 in the second horizontal direction (Y direction). The minimum offset distance AD52A or AD53A can be selected from ±0.5 nm of the normal minimum distance AD1.

[0155] Among the six offset pseudo-channel structures SD51A belonging to the second pseudo-channel structure group GY5A, the centers of the two offset pseudo-channel structures SD51A arranged in a row in the second horizontal direction (Y direction) can be arranged on a straight line extending in the second horizontal direction (Y direction). The minimum distance L53A between the centers of the two offset pseudo-channel structures SD51A on the straight line in the second horizontal direction (Y direction) can be equal to or greater than the minimum distance L52A between the center of the offset pseudo-channel structure SD51A and the center of the second normal pseudo-channel structure DN25A that is closest to the offset pseudo-channel structure SD51A in the second horizontal direction (Y direction).

[0156] The centers of the three offset pseudo-channel structures SD51A arranged in a row in the first horizontal direction (X direction) among the six offset pseudo-channel structures SD51A belonging to the second pseudo-channel structure group GY5A can be arranged on a straight line extending in the first horizontal direction (X direction).

[0157] Reference Figure 18 The semiconductor device 600 has the same characteristics as the reference. Figure 16The semiconductor device 500 described has the same (or substantially similar) construction. However, the semiconductor device 600 includes a plurality of pseudo-channel structures D640 arranged in the pseudo-channel region DA.

[0158] Multiple pseudo-channel structures D640 have similar characteristics to the reference Figure 16 The described multiple pseudo-channel structures D540 have the same (or substantially similar) construction. However, the multiple pseudo-channel structures D640 arranged in the pseudo-channel region DA of the semiconductor device 600 include a second pseudo-channel structure group GY6, which includes a second pseudo-channel structure arranged in a row with bridging portions WLE5 spanning each of the multiple gate lines 130 in the second horizontal direction (Y direction).

[0159] The second pseudo-channel structure belonging to the second pseudo-channel structure group GY6 among the multiple pseudo-channel structures D640 may include six offset pseudo-channel structures SD6 facing and adjacent to the bridging portion WLE5 in the second horizontal direction (Y direction).

[0160] In the plan view, in each of a pair of main gate portions MGPs, the second pseudo-channel structure belonging to the second pseudo-channel structure group GY6 may include three offset pseudo-channel structures SD6 and a second normal pseudo-channel structure DN26, the second normal pseudo-channel structure DN26 being further away from the bridging portion WLE5 than the offset pseudo-channel structures SD6. In each of a pair of main gate portions MGPs, the offset pseudo-channel structures SD6 and the second normal pseudo-channel structures DN26 arranged in a row in the second horizontal direction (Y direction) may be arranged with a regular pitch in the second horizontal direction (Y direction). That is, in one main gate portion MGP, the center-to-center distance L62 between two adjacent offset pseudo-channel structures SD6 and the second normal pseudo-channel structure DN26 may be constant.

[0161] The center-to-center distance L63 of the two offset pseudo-channel structures SD6, which are included in the second pseudo-channel structure group GY6 and are spaced apart from each other in the second horizontal direction (Y direction) and in which the bridging portion WLE5 is located, can be greater than the center-to-center distance L62 of the two normal pseudo-channel structures DN26 that are adjacent to each other in the second horizontal direction (Y direction).

[0162] According to reference Figures 11 to 18 The semiconductor devices 100A, 200, 300, 300A, 400, 500, 500A and 600 described are consistent with the reference. Figures 1 to 10Similar to the described semiconductor device 100, even when the planar area of ​​the bridging portion WLE, WLE3, or WLE5 of each of the plurality of gate lines 130 is relatively large, in each of the plurality of first insulating films 132, the bridging portion WLE, WLE3, or WLE5 of each of the plurality of gate lines 130, and the local region overlapping with the bridging portion WLE, WLE3, or WLE5 in the vertical direction (Z direction) can also be stably supported by the offset pseudo-channel structures SD1A, SD2, SD31, SD31A, SD4, SD51, SD51A, SD52, or SD6. Furthermore, during the manufacturing process of each of the semiconductor devices 100A, 200, 300, 300A, 400, 500, 500A, and 600, before the formation of the plurality of gate lines 130, structural defects such as pattern collapse can be mitigated and / or prevented. In pattern collapse, a local area in each of the plurality of first insulating films 132 collapses, overlapping with the area corresponding to the bridging portion WLE, WLE3, or WLE5. Therefore, the reliability and electrical characteristics of each of the semiconductor devices 100A, 200, 300, 300A, 400, 500, 500A, and 600 can be improved.

[0163] Figure 19 This is a schematic diagram illustrating an electronic system including a semiconductor device according to some embodiments.

[0164] Reference Figure 19 According to some embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may include a storage device having one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may include a solid-state drive (SSD) device having at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0165] Semiconductor device 1100 may include a non-volatile memory device. For example, semiconductor device 1100 may include a reference... Figures 1 to 18The semiconductor device 1100 is a NAND flash memory device comprising at least one of the structures of semiconductor devices 100, 100A, 200, 300, 300A, 400, 500, 500A, and 600. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may include peripheral circuitry including a decoder circuit 1110, a page buffer 1120, and logic circuitry 1130. The second structure 1100S may include a memory cell structure including a bit line BL, a common source line CSL, multiple word lines WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and multiple memory cell strings CSTR between the bit line BL and the common source line CSL. The first structure 1100F and the second structure 1100S may, for example, be respectively associated with... Figure 1 The peripheral circuit 30 corresponds to the memory cell array 20.

[0166] In the second structure 1100S, each of the plurality of memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The corresponding numbers of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 may be modified differently depending on the embodiment.

[0167] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Multiple lower gate lines (i.e., LL1 and LL2) may be the gate electrodes of lower transistors LT1 and LT2, respectively. A word line WL may be the gate electrode of a memory cell transistor MCT, and multiple upper gate lines (i.e., UL1 and UL2) may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0168] The common source line CSL, multiple gate down lines (i.e., LL1 and LL2), multiple word lines WL, and multiple gate up lines (i.e., UL1 and UL2) can be electrically connected to the decoder circuit 1110 via multiple first connection wiring lines 1115 extending from inside the first structure 1100F to the second structure 1100S. Multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connection wiring lines 1125 extending from inside the first structure 1100F to the second structure 1100S.

[0169] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130.

[0170] Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output connection wiring lines 1135 extending from inside the first structure 1100F to the second structure 1100S.

[0171] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0172] Processor 1210 can control all operations of electronic system 1000, including controller 1200. Processor 1210 can operate via specific firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to multiple memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from multiple memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted via NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When receiving control commands from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0173] Figure 20 This is a schematic perspective view of an electronic system including semiconductor devices according to an embodiment.

[0174] Reference Figure 20 According to some embodiments, the electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via a plurality of wiring patterns 2005 formed on the main substrate 2001. The semiconductor package 2003 may be and / or include data storage space.

[0175] The main substrate 2001 may include a connector 2006 having a plurality of pins to be coupled to an external host. The number of pins and the arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI High Speed), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some embodiments, the electronic system 2000 may be operated by power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0176] The controller 2002 can be configured to write data to or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0177] DRAM 2004 can be a buffer memory configured to mitigate the speed difference between an external host and semiconductor package 2003. For example, DRAM 2004 in electronic system 2000 can operate as a cache memory and can provide space for temporary data storage during control operations on semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0178] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, a bonding layer 2300 on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 disposed on the package substrate 2100 to cover the plurality of semiconductor chips 2200 and the connection structure 2400.

[0179] The package substrate 2100 may include a printed circuit board having a plurality of package-on-pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2210. The input / output pads 2210 may be coupled to... Figure 19 The input / output pads 1101 correspond to this. Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. Each of the plurality of semiconductor chips 2200 may include references Figures 1 to 18 At least one of the structures of the described semiconductor devices 100, 100A, 200, 300, 300A, 400, 500, 500A and 600.

[0180] In some embodiments, the connection structure 2400 may include bonding leads that electrically connect input / output pads 2210 and package-on-package pads 2130 to each other. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via bonding leads and may be electrically connected to the package-on-package pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of via a bonding lead type connection structure 2400.

[0181] In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insert substrate different from the main substrate 2001 and may be interconnected with each other via wiring formed on the insert substrate.

[0182] Figure 21 This is a schematic cross-sectional view of a semiconductor package according to some embodiments. Figure 21 Showing according to along Figure 20 The cross section intercepted by line II-II' Figure 20 A more detailed description of the semiconductor package 2003.

[0183] Reference Figure 21 In semiconductor package 2003, package substrate 2100 may include a printed circuit board. Package substrate 2100 may include package substrate body 2120 and a plurality of package pads 2130 disposed on the upper surface of package substrate body 2120 (see See...). Figure 20The package includes multiple lower pads 2125 disposed on or exposed through the lower surface of the package substrate 2120, and multiple internal wiring lines 2135 disposed inside the package substrate 2120 to electrically connect multiple upper pads 2130 to multiple lower pads 2125. The multiple upper pads 2130 can be electrically connected to multiple connection structures 2400, respectively. The multiple lower pads 2125 can be connected to multiple conductive connection units 2800, respectively. Figure 20 Multiple wiring patterns 2005 on the main substrate 2001 of the electronic system 2000 shown.

[0184] Each of the plurality of semiconductor chips 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 stacked on the semiconductor substrate 3010 in the stated order. The first structure 3100 may include a peripheral circuit region having a plurality of peripheral wiring lines 3110. The second structure 3200 may include a common source line 3205, a gate stack 3210 on the common source line 3205, a channel structure 3220 through the gate stack 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line electrically connected to the gate stack 3210 via a contact CTS (i.e., ...). Figure 19 The gate connection wiring line 3250 of the WL). As described above, each of the plurality of semiconductor chips 2200 may include a reference. Figures 1 to 18 At least one of the structures of the described semiconductor devices 100, 100A, 200, 300, 300A, 400, 500, 500A and 600.

[0185] Each of the plurality of semiconductor chips 2200 may include a through-wiring line 3245 electrically connected to a plurality of peripheral wiring lines 3110 of the first structure 3100 and extending into the interior of the second structure 3200. The through-wiring line 3245 may be disposed outside the gate stack 3210. In some embodiments, the semiconductor package 2003 may further include a through-wiring line passing through the gate stack 3210. Each of the plurality of semiconductor chips 2200 may also include input / output pads electrically connected to the plurality of peripheral wiring lines 3110 of the first structure 3100 (i.e., Figure 20 (of 2210).

[0186] Figure 22 This is a schematic cross-sectional view of a semiconductor package according to some embodiments. Figure 22 Showing along Figure 20 The cross-sectional structure of a portion of the semiconductor package 2003A corresponding to the section cut by line II-II'. Figure 22 In, such as Figure 21 The same reference numerals in the figures denote the same components, and their differences are discussed accordingly. For the sake of brevity, repeated descriptions may be omitted.

[0187] Reference Figure 22 In the semiconductor package 2003A, the semiconductor chip 2200A may each include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding manner.

[0188] The first structure 4100 may include a peripheral circuit region having peripheral wiring lines 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 passing through the gate stack structure 4210, and word lines electrically connected to the memory channel structure 4220 and the gate stack structure 4210, respectively. Figure 19 The second bonding structure 4250 of the WL). For example, the second bonding structure 4250 can be electrically connected to the bit line 4240 of the memory channel structure 4220 and electrically connected to the word line (i.e., WL). Figure 19 The gate connection wiring of the WL is electrically connected to the memory channel structure 4220 and the word line (i.e., Figure 19 (WL). The first bonding structure 4150 of the first structure 4100 may contact and bond to the second bonding structure 4250 of the second structure 4200. The bonding portion of the first bonding structure 4150 and the second bonding structure 4250 may include, for example, copper (Cu).

[0189] The second structure 4200 may include a reference Figures 1 to 18 At least one of the described semiconductor devices 100, 100A, 200, 300, 300A, 400, 500, 500A and 600.

[0190] Next, a method for manufacturing a semiconductor device according to some embodiments will be described in detail.

[0191] Figures 23A to 34 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments. More specifically, Figure 23A , Figure 24A , Figure 25A , Figure 28A and Figure 31A It is shown according to a series of processes and along Figure 5AA cross-sectional view of some components in the region corresponding to the section intercepted by line Y1-Y1'. Figure 28B and Figure 31B It is shown according to a series of processes and along Figure 5A A cross-sectional view of some components in the region corresponding to the section intercepted by line Y2-Y2', and Figure 23B , Figure 24B , Figure 25B , Figure 26 , Figure 27 , Figure 28C , Figure 29 , Figure 30 , Figure 31C , Figure 32 , Figure 33 and Figure 34 It is shown according to a series of processes and along Figure 6 A cross-sectional view of some components in the region corresponding to the section intercepted by line X1-X1'. (Refer to...) Figures 23A to 34 Description of manufacturing reference Figures 1 to 10 An example of a method for describing the semiconductor device 100. Figures 23A to 34 In, such as Figures 1 to 10 The same reference numerals in the figures denote the same components, and their differences are discussed accordingly. For the sake of brevity, repeated descriptions may be omitted.

[0192] Reference Figure 23A and Figure 23B This can form a peripheral circuit structure PCS including a substrate 52, multiple transistors TR, a multilayer wiring structure MWS, multiple conductive landing pads LP, and an interlayer dielectric 70. Each of the multiple conductive landing pads LP can be arranged to contact the memory cell contacts MCC (see [link to relevant documentation]). Figure 9 The position corresponds to the layer. An interlayer dielectric 70 can be formed such that the interlayer dielectric 70 covers the uppermost of the multiple wiring layers ML62, which are ML60, ML61 and ML62.

[0193] Reference Figure 24A and Figure 24B , can Figure 23A and Figure 23B A common source line 110 is formed on the resulting product, and an insulating plate 112 and a second conductive plate 118 may be formed in the order stated above, such that the insulating plate 112 and the second conductive plate 118 cover the common source line 110. The insulating plate 112 may include an insulating film with a multilayer structure having a first insulating film 112A, a second insulating film 112B, and a third insulating film 112C.

[0194] Next, as Figure 24BAs shown, a plurality of through openings 120H can be formed in a portion of the connection region CON so that the plurality of through openings 120H pass through the board common source line 110, the insulating plate 112 and the second conductive plate 118, and a plurality of insulating plugs 120 can be formed so that the plurality of insulating plugs 120 respectively fill the plurality of through openings 120H.

[0195] Reference Figure 25A and Figure 25B In the memory cell region (MEC) and the connection region (CON), a plurality of first insulating films 132 and a plurality of second insulating films 134 may be alternately stacked on the second conductive plate 118 and the insulating plug 120. In at least one embodiment, the plurality of first insulating films 132 may each comprise a silicon oxide film, and the plurality of second insulating films 134 may each comprise a silicon nitride film. Some of the plurality of second insulating films 134 may be used to ensure the formation of [the structure / structure] in subsequent processes. Figure 7 , Figure 8 and Figure 9 The space of the multiple gate lines 130 shown.

[0196] Reference Figure 26 Having already experienced reference Figure 25A and Figure 25B In the product obtained by the described process, an etch stop film 136 may be formed to cover the uppermost of a plurality of first insulating films 132, and then a portion of each of the plurality of first insulating films 132 and the plurality of second insulating films 134 in the connection region CON is removed via, for example, a photolithography process to form a stepped structure ST, in which the ends of each of the plurality of first insulating films 132 and the plurality of second insulating films 134 have a gradually decreasing width in the horizontal direction away from the board common source line 110.

[0197] Reference Figure 27 Having already experienced reference Figure 26 In the product obtained from the described process, a third insulating film 134R may be formed on the end of each of the plurality of second insulating films 134 constituting the stepped structure ST. The third insulating film 134R may include, for example, a silicon nitride film.

[0198] although Figure 27 The diagram shows third insulating films 134R formed on the ends of some of the plurality of second insulating films 134, but the third insulating film 134 is shown on the ends of some of the plurality of second insulating films 134. Figure 27 The second insulating film 134, shown as not being covered by the third insulating film 134R, may have a non-covered portion. Figure 27 The other part is shown but covered by the third insulating film 134R.

[0199] In some embodiments, in order to form a third insulating film 134R at the end of each of the plurality of second insulating films 134, an initial third insulating film may be formed such that the initial third insulating film covers the portion that has undergone reference. Figure 26 The process described describes the entire surface of the resulting product, and then a portion of the initial third insulating film can be removed to form the third insulating film 134R, and atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD) processes can be used.

[0200] An interlayer dielectric 138 can be formed such that the interlayer dielectric 138 covers the resulting product formed on the ends of each of the plurality of second insulating films 134 as described above. During the formation of the interlayer dielectric 138, the etch stop film 136 can be removed by performing a chemical mechanical polishing (CMP) process to planarize the upper surface of the interlayer dielectric 138, and as a result, the uppermost of the plurality of first insulating films 132 can be exposed around the interlayer dielectric 138. Next, a first upper insulating film UL1 can be formed such that the first upper insulating film UL1 covers the uppermost first insulating film 132 and the upper surface of each of the interlayer dielectrics 138.

[0201] Reference Figure 28A , Figure 28B and Figure 28C Multiple channel structures 140 and multiple pseudo-channel structures D140 can be formed. The multiple channel structures 140 extend longitudinally in the vertical direction (Z direction) through the first upper insulating film UL1, multiple first insulating films 132, and multiple second insulating films 134 in the memory cell region MEC. The multiple pseudo-channel structures D140 extend longitudinally in the vertical direction (Z direction) through the first upper insulating film UL1, multiple first insulating films 132, multiple second insulating films 134, and interlayer dielectric 138 in the pseudo-channel region DA and the connection region CON. Figure 28B In the pseudo-channel region DA shown, it can be referenced Figure 5A , Figure 5B and Figure 10 The described arrangement structure forms multiple pseudo-channel structures D140.

[0202] Reference Figure 29 You can refer to what you have already experienced Figure 28A , Figure 28B and Figure 28C The product obtained from the described process has a second upper insulating film UL2 formed on it, and then a plurality of vertical holes H1 can be formed in the connection area CON of the memory cell block BLK. The conductive landing pads LP of the peripheral circuit structure PCS can be exposed at the lower surface of each of the plurality of vertical holes H1.

[0203] Each of the plurality of vertical holes H1 can pass through one of the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the third insulating film 134R, the plurality of second insulating films 134, the plurality of first insulating films 132, the insulating plug 120, and a portion of the interlayer dielectric 70 of the peripheral circuit structure PCS in the vertical direction (Z direction).

[0204] Next, by etching the corresponding portions of the second insulating film 134 and the third insulating film 134R exposed in each of the plurality of vertical holes H1, the horizontal width of each of the plurality of vertical holes H1 can be expanded, thereby forming a plurality of recessed spaces ID. In some of the plurality of recessed spaces ID, only the second insulating film 134 in the second insulating film 134 and the third insulating film 134R can be exposed, while in some of the plurality of recessed spaces ID, both the second insulating film 134 and the third insulating film 134R can be exposed together.

[0205] Reference Figure 30 In executing the reference Figure 29 Following the described process, in the connection region CON of the memory cell block, among the plurality of recessed spaces ID connected to each of the plurality of vertical holes H1, the recessed spaces ID exposing the second insulating film 134 can be filled with an insulating ring 152, and the recessed spaces ID exposing both the second insulating film 134 and the third insulating film 134R can be filled with a sacrificial insulating ring 154. The insulating ring 152 may comprise a silicon oxide film. The sacrificial insulating ring 154 may comprise a material that is the same as (or substantially similar to) the second insulating film 134. For example, the sacrificial insulating ring 154 may comprise, for example, a silicon nitride film.

[0206] In some embodiments, a process may be performed such that an insulating ring 152 is first formed in a recessed space ID exposing a second insulating film 134 in each of a plurality of vertical holes H1, and subsequently a sacrificial insulating ring 154 is formed in a recessed space ID exposing both the second insulating film 134 and the third insulating film 134R in each of the plurality of vertical holes H1. In some embodiments, an etch-stop insulating pad (not shown) may be disposed between the second insulating film 134 and the insulating ring 152. The etch-stop insulating pad may comprise a silicon nitride film.

[0207] Next, the interior of each of the plurality of vertical holes H1 can be filled with insulating spacer 156 and sacrificial plug 158. In some embodiments, insulating spacer 156 may comprise silicon oxide and sacrificial plug 158 may comprise polysilicon, but the inventive concept is not limited thereto.

[0208] Reference Figure 31A , Figure 31B and Figure 31CA third upper insulating film UL3 can be formed to cover multiple insulating spacers 156, multiple sacrificial plugs 158, and the corresponding upper surfaces of the second upper insulating film UL2 in the memory cell region MEC, the pseudo-channel region DA, and the connection region CON.

[0209] In the resulting product in which the third upper insulating film UL3 is formed, a plurality of serial select line holes can be formed by etching the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, some of the plurality of first insulating films 132, and some of the plurality of second insulating films 134 in the memory cell region MEC, and a serial select line cut structure SSLC can be formed to fill the plurality of serial select line holes.

[0210] Multiple word line cut holes WCH can be formed through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, multiple first insulating films 132, multiple second insulating films 134, the second conductive plate 118, and the insulating plate 112 in the memory cell region MEC, the pseudo-channel region DA, and the connection region CON to expose the board common source line 110.

[0211] In the memory cell region MEC and the pseudo-channel region DA, the insulating plate 112 can be selectively removed through the internal space of each of the multiple word line cutting holes WCH, and the resulting empty space can be filled with the first conductive plate 114. The insulating plate 112 can be retained in the connection region CON. While removing the insulating plate 112 in the memory cell region MEC and the pseudo-channel region DA, a portion of the gate dielectric film 142 (adjacent to the insulating plate 112) of each of the multiple pseudo-channel structures D140 in the memory cell region MEC and the pseudo-channel region DA can be removed together with the insulating plate 112, and as a result, the first conductive plate 114 can pass horizontally through a portion of the gate dielectric film 142 and contact the channel region 144.

[0212] In the memory cell region (MEC), pseudo-channel region (DA), and connection region (CON), multiple gate lines 130 can replace multiple second insulating films 134, third insulating films 134R, and sacrificial insulating rings 154 within the internal space of each of multiple word line cut-through holes (WCH). In each of the multiple gate lines 130, the relatively thick end obtained by replacing both the sacrificial insulating ring 154 and the second insulating film 134 and third insulating film 134R that contact the sacrificial insulating ring 154 can form a gate pad portion 130A.

[0213] As described above, while replacing multiple second insulating films 134, third insulating films 134R, and sacrificial insulating rings 154 with multiple gate lines 130, after first removing the multiple second insulating films 134, third insulating films 134R, and sacrificial insulating rings 154, and before forming the multiple gate lines 130, the spaces between each of the multiple first insulating films 132 that already exist are kept empty. Specifically, in the pseudo-channel region DA, because compared to other regions of the pseudo-channel region DA, the bridging portion WLE of each of the multiple gate lines 130 is to be formed (see...). Figure 5A , Figure 5B and Figure 10 The space has a relatively large planar area, so in each of the plurality of first insulating films 132, in the vertical direction (Z direction) it forms a bridging portion WLE (see Figure 5A , Figure 5B and Figure 10 Locally overlapping areas of the space may be prone to collapse. However, according to the present invention, in the pseudo-channel region DA, an offset pseudo-channel structure SD1 (see [reference]) faces and is adjacent to the bridging portion WLE in the second horizontal direction (Y direction). Figure 10 The first normal pseudo-channel structure DN1 is not included in the arrangement rules of the first horizontal direction (X direction). For example, the offset pseudo-channel structure SD1 can be arranged to be shifted from the imaginary first straight line toward the bridging portion WLE in the second horizontal direction (Y direction), the imaginary first straight line passing through the corresponding center of the first normal pseudo-channel structure DN1.

[0214] Therefore, even when the planar area of ​​the bridging portion WLE of each of the plurality of gate lines 130 is relatively large, the bridging portion WLE of each of the plurality of gate lines 130, and the local region in each of the plurality of first insulating films 132 that overlaps with the bridging portion WLE in the vertical direction (Z direction), can be stably supported by the offset pseudo-channel structure SD1. Thus, during the process of manufacturing the semiconductor device 100, before the formation of the plurality of gate lines 130, structural defects such as pattern collapse can be prevented and / or the likelihood of such structural defects occurring, in which the local region in each of the plurality of first insulating films 132 that overlaps with the region corresponding to the bridging portion WLE collapses, can be prevented.

[0215] After forming the first conductive plate 114 and the multiple gate lines 130, some of the multiple word line cut holes WCH can be filled with word line cut structures WLC1, and some other word line cut holes WCH can be filled with local word line cut structures WLC2. The width of the memory cell block BLK in the second horizontal direction (Y direction) can be defined by the multiple word line cut structures WLC1.

[0216] Reference Figure 32 In the connection area CON of the memory cell block BLK, a hole PH can be formed through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the second conductive plate 118 and the insulating plate 112 to expose the common source line 110 of the plate, and then, an insulating spacer 162 and a conductive plate contact 164 can be formed in the hole PH in the order stated.

[0217] Reference Figure 33 You can refer to what you have already experienced Figure 32 The process described results in the formation of a fourth upper insulating film UL4 on the product. A portion of each of the fourth upper insulating film UL4 and the third upper insulating film UL3 is then removed, thereby exposing the insulating spacer 156 and the sacrificial plug 158. The interior of each of the plurality of vertical holes H1 can then be emptied by removing the exposed insulating spacer 156 and the sacrificial plug 158.

[0218] Next, by etching the conductive landing pads LP exposed on the lower surface of each of the multiple vertical holes H1, the length of each of the multiple vertical holes H1 in the vertical direction (Z direction) can be increased, and the wiring layer ML62 of the multilayer wiring structure MWS of the peripheral circuit structure PCS can be exposed on the lower surface of each of the multiple vertical holes H1.

[0219] Reference Figure 34 ,exist Figure 33 In the resulting product, multiple memory cell contacts (MCCs) can be formed to fill multiple vertical holes (H1) in the connection region (CON).

[0220] Next, as Figures 7 to 9 As shown, it can be Figure 34A fifth upper insulating film UL5 is formed on the resulting product, and contact plugs 172 and multiple contact plugs 176 can be formed thereon. Contact plugs 172 pass through the fifth upper insulating film UL5 and the fourth upper insulating film UL4 in the connection region CON and are connected to the conductive plate contact 164. Multiple contact plugs 176 pass through the fifth upper insulating film UL5, the fourth upper insulating film UL4, the third upper insulating film UL3 and the second upper insulating film UL2 in the memory cell region MEC and are respectively connected to the drain regions 148 of multiple channel structures 140.

[0221] Next, multiple upper wiring layers UML can be formed on the fifth upper insulating film UL5 in the connection region CON, and multiple bit lines BL can be formed on the fifth upper insulating film UL5 in the memory cell region MEC. Furthermore, a sixth upper insulating film UL6 can be formed to fill the spaces between each of the multiple upper wiring layers UML and between each of the multiple bit lines BL.

[0222] Although it has been referenced Figures 23A to 34 Describes manufacturing reference Figures 1 to 10 The method of the semiconductor device 100 described herein, however, will be understood by those skilled in the art to be different without departing from the spirit and scope of the inventive concept. Figures 23A to 34 The described method can be modified and changed in various ways to create a reference. Figures 11 to 18 The semiconductor devices described are 100A, 200, 300, 300A, 400, 500, 500A and 600, as well as semiconductor devices with various structures modified and altered therefrom.

[0223] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Multiple gate lines that overlap each other in the vertical direction, each of the multiple gate lines having a pair of main gate portions and a bridging portion connecting the pair of main gate portions to each other; Multiple pseudo-channel structures, the multiple pseudo-channel structures passing through the multiple gate lines in the vertical direction; as well as A partial word line dicing structure passes through corresponding local regions of the plurality of gate lines in the vertical direction, the partial word line dicing structure extending intermittently in a first horizontal direction such that the width of the bridging portion is defined by the partial word line dicing structure in the first horizontal direction. The plurality of pseudo-channel structures includes a first pseudo-channel structure group, which includes a first pseudo-channel structure in a row extending in the first horizontal direction. The first pseudo-channel structure is adjacent to the local word line cutting structure. The first pseudo-channel structure group includes: A first normal pseudo-channel structure faces the local word line cutting structure in a second horizontal direction orthogonal to the first horizontal direction. Each of the first normal pseudo-channel structures has a center on an imaginary first straight line extending in the first horizontal direction. At least one offset pseudo-channel structure, the at least one offset pseudo-channel structure facing the bridging portion in the second horizontal direction, and having a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction.

2. The semiconductor device according to claim 1, wherein, The plurality of pseudo-channel structures further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The at least one offset pseudo-channel structure is located in one of the main gate portions of the pair of main gate portions, and A second normal pseudo-channel structure is located within the main gate portion, and the distance between the second normal pseudo-channel and the bridging portion is greater than the distance between the at least one offset pseudo-channel structure and the bridging portion. The minimum distance between the at least one offset pseudo-channel structure and the second normal pseudo-channel structure closest to the at least one offset pseudo-channel structure is greater than the minimum distance between two second normal pseudo-channel structures that are adjacent to each other in the second horizontal direction.

3. The semiconductor device according to claim 1, wherein, The plurality of pseudo-channel structures further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The at least one offset pseudo-channel structure is located in one of the main gate portions of the pair of main gate portions, and A second normal pseudo-channel structure is located within the main gate portion, and the distance between the second normal pseudo-channel and the bridging portion is greater than the distance between the at least one offset pseudo-channel structure and the bridging portion. The at least one offset pseudo-channel structure and the second normal pseudo-channel structure are arranged at a regular pitch in the second horizontal direction.

4. The semiconductor device according to claim 1, wherein, The minimum offset distance between the at least one offset pseudo-channel structure and the local word line cut structure is within ±0.5 nm of the average minimum distance between the local word line cut structure and each of the first normal pseudo-channel structures adjacent to the local word line cut structure.

5. The semiconductor device according to claim 1, wherein, In the plan view, the width of the at least one offset pseudo-channel structure in the second horizontal direction is greater than its length in the first horizontal direction.

6. The semiconductor device according to claim 1, wherein, In the plan view, the width of the at least one offset pseudo-channel structure in the second horizontal direction is greater than the width of each of the first normal pseudo-channel structures in the first pseudo-channel structure group in the second horizontal direction.

7. The semiconductor device according to claim 1, wherein, The plurality of pseudo-channel structures further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The at least one offset pseudo-channel structure is arranged in one of the main gate portions selected from the pair of main gate portions, and A second normal pseudo-channel structure is arranged in one of the selected main gate portions. The distance between the second normal pseudo-channel structure and the bridging portion is greater than the distance between the at least one offset pseudo-channel structure and the bridging portion, and In the plan view, the width of the at least one offset pseudo-channel structure in the second horizontal direction is greater than the length of each of the second normal pseudo-channel structures in the second pseudo-channel structure group in the second horizontal direction.

8. The semiconductor device according to claim 1, wherein, The plurality of pseudo-channel structures include a group of normal pseudo-channel structures, the group of normal pseudo-channel structures including a third pseudo-channel structure that passes through a main gate portion selected from each of the pair of main gate portions of the plurality of gate lines in the vertical direction, and In the plan view, the third pseudo-channel structure in the normal pseudo-channel structure group is in a matrix array structure.

9. The semiconductor device according to claim 1, wherein, The plurality of pseudo-channel structures further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure in the second pseudo-channel structure group includes the at least one offset pseudo-channel structure, and In the planar diagram, the other pseudo-channel structures that are different from the second pseudo-channel structure are arranged in a matrix array structure.

10. The semiconductor device according to claim 1, wherein, The first pseudo-channel structure group includes a plurality of offset pseudo-channel structures, which face the bridging portion in the second horizontal direction and are shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction. The respective centers of the plurality of offset pseudo-channel structures are located on a straight line extending in the first horizontal direction.

11. A semiconductor device, comprising: Multiple gate lines extend across a memory cell region, a pseudo-channel region, and a connection region. The memory cell region, the pseudo-channel region, and the connection region are arranged sequentially in a first horizontal direction within a memory cell block. The multiple gate lines overlap each other in the vertical direction. Multiple channel structures, wherein the multiple channel structures pass through the multiple gate lines in the vertical direction in the memory cell region; Multiple pseudo-channel structures, wherein the multiple pseudo-channel structures pass through the multiple gate lines in the vertical direction in the pseudo-channel region; A pair of word line cutting structures, the pair of word line cutting structures extending longitudinally in the first horizontal direction and defining the width of the memory cell block in the second horizontal direction, the second horizontal direction being orthogonal to the first horizontal direction; as well as A partial word line cut structure is located between the pair of word line cut structures, the partial word line cut structure passing through corresponding local regions of the plurality of gate lines in the vertical direction and extending intermittently in the first horizontal direction. Each of the plurality of gate lines includes: A pair of main gate portions, which respectively contact the pair of word line cut structures, and A bridging portion that connects the pair of main gate portions to each other in the pseudo-channel region, the bridging portion having a width defined by the local word line cut structure in the first horizontal direction. The plurality of pseudo-channel structures in the pseudo-channel region includes a first pseudo-channel structure group, the first pseudo-channel structure group including a first pseudo-channel structure in a row adjacent to the local word line cutting structure in the first horizontal direction, and The first pseudo-channel structure group includes: A first normal pseudo-channel structure, which faces the local word line cutting structure in the second horizontal direction, each of the first normal pseudo-channel structures having a center on an imaginary first straight line extending in the first horizontal direction, and An offset pseudo-channel structure faces the bridging portion in the second horizontal direction and has a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction.

12. The semiconductor device according to claim 11, wherein, The plurality of pseudo-channel structures in the pseudo-channel region further includes a second pseudo-channel structure group, the second pseudo-channel structure group including a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The offset pseudo-channel structure, and Second normal pseudo-channel structure, The distance between the second normal pseudo-channel structure and the bridging portion is greater than the distance between the offset pseudo-channel structure and the bridging portion, and The minimum distance between the offset pseudo-channel structure and the second normal pseudo-channel structure that is closest to the offset pseudo-channel structure is greater than the minimum distance between two adjacent second normal pseudo-channel structures.

13. The semiconductor device according to claim 11, wherein, The plurality of pseudo-channel structures in the pseudo-channel region further includes a second pseudo-channel structure group, the second pseudo-channel structure group including a second pseudo-channel structure on an imaginary second straight line extending across the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The offset pseudo-channel structure, and Second normal pseudo-channel structure, The distance between the second normal pseudo-channel and the bridging portion is greater than the distance between the offset pseudo-channel structure and the bridging portion, and The offset pseudo-channel structure and the second normal pseudo-channel structure are arranged at regular pitch in the second horizontal direction.

14. The semiconductor device according to claim 11, wherein, The minimum offset distance between the offset pseudo-channel structure and the local word line cut structure is within ±0.5 nm of the average minimum distance between the local word line cut structure and each of the first normal pseudo-channel structures adjacent to the local word line cut structure.

15. The semiconductor device according to claim 11, wherein, In the plan view, the width of the offset pseudo-channel structure in the second horizontal direction is greater than the length of the offset pseudo-channel structure in the first horizontal direction.

16. The semiconductor device according to claim 11, wherein, In the plan view, the width of the offset pseudo-channel structure in the second horizontal direction is greater than the width of each of the first normal pseudo-channel structures in the first pseudo-channel structure group in the second horizontal direction.

17. The semiconductor device according to claim 11, wherein, The plurality of pseudo-channel structures in the pseudo-channel region further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on a row of an imaginary second straight line extending along the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure group includes: The offset pseudo-channel structure, and Second normal pseudo-channel structure, The distance between the second normal pseudo-channel structure and the bridging portion is greater than the distance between the offset pseudo-channel structure and the bridging portion, and In the plan view, the width of the offset pseudo-channel structure in the second horizontal direction is greater than the length of each of the second normal pseudo-channel structures in the second pseudo-channel structure group in the second horizontal direction.

18. The semiconductor device according to claim 11, wherein, The plurality of pseudo-channel structures in the pseudo-channel region include a group of normal pseudo-channel structures, the group of normal pseudo-channel structures including a third pseudo-channel structure located between each of the partial word line cut structure and each of the pair of word line cut structures, the third pseudo-channel structure passing through a main gate portion selected from each of the pair of main gate portions of the plurality of gate lines in the vertical direction, and In the plan view, the third pseudo-channel structure in the normal pseudo-channel structure group is in a matrix array structure.

19. The semiconductor device according to claim 11, wherein, The plurality of pseudo-channel structures in the pseudo-channel region further includes a second pseudo-channel structure group, the second pseudo-channel structure group comprising a second pseudo-channel structure on a row of an imaginary second straight line extending along the bridging portion of each of the plurality of gate lines in the second horizontal direction. The second pseudo-channel structure in the second pseudo-channel structure group includes the offset pseudo-channel structure, and In the planar diagram, the other pseudo-channel structures that are different from the second pseudo-channel structure are arranged in a matrix array structure.

20. An electronic system comprising: Main substrate; A semiconductor device located on the main substrate; as well as A controller, located on the main substrate and electrically connected to the semiconductor device, The semiconductor device includes: Multiple gate lines that overlap each other in the vertical direction; Multiple pseudo-channel structures, the multiple pseudo-channel structures passing through the multiple gate lines in the vertical direction, and A partial word line cut structure, which passes through corresponding local regions of the plurality of gate lines in the vertical direction and extends intermittently in the first horizontal direction, the plurality of pseudo-channel structures including a first pseudo-channel structure group, the first pseudo-channel structure group including a first pseudo-channel structure in a row extending in the first horizontal direction, the first pseudo-channel structure being adjacent to the partial word line cut structure, and The first pseudo-channel structure group includes: A first normal pseudo-channel structure faces the local word line cutting structure in a second horizontal direction orthogonal to the first horizontal direction. Each of the first normal pseudo-channel structures has a center on an imaginary first straight line extending in the first horizontal direction. At least one offset pseudo-channel structure faces the bridging portion in the second horizontal direction and has a center located at a position shifted from the imaginary first straight line toward the bridging portion in the second horizontal direction.

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