Transistor structure and preparation method thereof
By forming an isolation layer on the side of the buried channel region away from the substrate surface, the problem of difficult-to-control boron implantation diffusion in BCPMOS devices is solved, resulting in a wider process window and more stable device performance.
Patent Information
- Application Number
- CN202511714985.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-03-03
AI Technical Summary
The performance of existing BCPMOS devices is easily affected by P-type implanted ions. Diffusion after boron implantation is difficult to control, which leads to a narrowing of the process window and makes it difficult to further reduce device noise.
An isolation layer is formed on the side of the buried channel region away from the substrate surface. The diffusion of the channel is suppressed by the isolation layer, and the depth and width of the channel are controlled. The diffusion of boron ions is suppressed by forming an isolation layer such as a nitrogen implantation layer.
This effectively broadens the process window, improves the electrical performance of the device, reduces the contact between the channel and the Si-O surface states, and enhances the design reliability and performance stability of the device.
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Figure CN121604484A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a transistor structure and its fabrication method. Background Technology
[0002] Signal chain products are increasingly demanding in terms of device noise, but the noise of surface-mount devices is limited by Si-O surface states, making further reduction difficult. Si-O surface states refer to additional energy states at the interface between silicon (Si) and silicon dioxide (O, with silicon dioxide being a common gate oxide material), arising from various physical and chemical factors. These states significantly impact semiconductor device performance, especially noise characteristics. Si-O surface states trap and release charge carriers, and this random trapping and release process generates additional noise that interferes with the transmission and processing of weak signals, limiting the device's application in high-precision signal processing. Buried channel PMOS (BCPMOS) technology, which fabricates conductive channels far from the surface, overcomes the performance limitations imposed by surface states by reducing the physical contact between the channel and Si-O surface states through its innovative buried-channel structure. However, BCPMOS device performance is susceptible to the effects of p-type implanted ions (boron), as diffusion after boron implantation is difficult to control, leading to a narrowing of the process window.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] To address the problems in the prior art, the purpose of this application is to provide a transistor structure and its fabrication method. Based on the advantages of the buried channel of buried channel devices, the diffusion of the channel is suppressed by the isolation layer, the depth and width of the buried layer of the channel are better controlled, a wider process window is obtained, and the buried channel devices are more easily opened from the designed buried channel.
[0005] This application provides a transistor structure, including:
[0006] Substrate;
[0007] A well region, located within the substrate, comprising doped ions of a first conductivity type;
[0008] An embedded channel region is located within the well region, and the channel region includes doped ions of a second conductivity type;
[0009] An isolation layer is located on the side of the buried trench region facing away from the substrate;
[0010] A gate structure is located on the surface of the substrate.
[0011] In some embodiments, an epitaxial layer is further included between the buried channel region and the gate structure, the epitaxial layer comprising doped ions of a second conductivity type.
[0012] In some embodiments, the doped ion of the first conductivity type is an N-type ion, and the doped ion of the second conductivity type is a P-type ion.
[0013] In some embodiments, the isolation layer is a nitrogen-injected layer.
[0014] In some embodiments, the width of the isolation layer is the same as the width of the embedded trench area.
[0015] In some embodiments, the system further includes a source region and a drain region located within the well region and distributed on both sides of the buried trench region, wherein the depth of the source region and the drain region is greater than the depth of the isolation layer.
[0016] This application also provides a method for fabricating a transistor structure, used to fabricate the transistor structure described in the claims, the method comprising the following steps:
[0017] Provide a substrate;
[0018] The substrate is implanted with ions of a first conductivity type to form a well region within the substrate, the well region comprising dopant ions of the first conductivity type;
[0019] The well region is implanted with ions of a second conductivity type to form a buried channel region in the substrate, the buried channel region comprising dopant ions of the second conductivity type;
[0020] An isolation layer is formed on the side of the embedded trench region facing away from the substrate.
[0021] A gate structure is formed on the surface of the substrate.
[0022] In some embodiments, forming an isolation layer on the side of the buried trench region facing away from the substrate includes the following steps:
[0023] Nitrogen ion implantation is performed on the substrate to form a nitrogen implantation layer on the side of the buried trench region away from the surface of the substrate, which serves as the isolation layer.
[0024] In some embodiments, before forming the gate structure on the surface of the substrate, the following steps are further included:
[0025] An epitaxial layer is formed on the side of the buried trench region facing the substrate using an epitaxial growth process, and the epitaxial layer includes doped ions of a second conductivity type.
[0026] The gate structure is formed on the surface of the epitaxial layer.
[0027] In some embodiments, after forming the gate structure on the surface of the substrate, the following steps are further included:
[0028] Ion implantation of a second conductivity type is performed on opposite sides of the gate structure to form source and drain regions located on both sides of the buried channel region, wherein the depth of the source and drain regions is greater than the depth of the isolation layer.
[0029] The transistor structure and its fabrication method provided in this application have the following advantages:
[0030] By adopting this application, a buried channel region is formed in the well region, which is far away from the substrate surface. This reduces the contact between the channel and the Si-O surface states from a physical perspective. It fully utilizes the advantages of the buried channel in buried channel devices. An isolation layer is formed on the surface side of the buried channel region away from the substrate. The diffusion of the buried channel region is suppressed by the isolation layer, which better controls the depth and width of the buried channel region, resulting in a wider process window. This makes it easier to start the buried channel device from the designed buried channel, effectively widening the process and device electrical performance window of the buried channel device well region implantation and its reverse doping implantation.
[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0033] Figure 1 This is a schematic diagram of a transistor structure according to an embodiment of this application;
[0034] Figure 2 This is a flowchart of a method for fabricating a transistor structure according to an embodiment of this application;
[0035] Figure 3 This is a schematic diagram of a substrate and a well region formed according to an embodiment of this application;
[0036] Figure 4This is a schematic diagram of an embodiment of the present application showing the formation of an embedded trench area and an isolation layer within the trap area;
[0037] Figure 5 This is a schematic diagram of the formation of an epitaxial layer according to an embodiment of this application;
[0038] Figure 6 This is a schematic diagram of the formation of a gate structure according to an embodiment of this application;
[0039] Figure 7 It is a channel conduction state diagram obtained from simulation experiments of an existing transistor structure;
[0040] Figure 8 This is a channel conduction state diagram of the transistor structure of this application obtained through simulation experiments. Detailed Implementation
[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The words “or” and “or” in the specification may mean “and” or “or”. Spatial relation terms such as “…above” are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “…above” will be oriented “…below” other elements or features. Therefore, the exemplary term “…above” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. Although “first” or “second,” etc., are used in this specification to denote certain features, this is merely indicative of function and not a limitation on the number or importance of the specific features.
[0043] While existing buried channel devices reduce the physical contact between the channel and Si-O surface states by burying the channel away from the surface, their performance is susceptible to the effects of p-type implanted ions (boron). Specifically, boron diffusion after implantation is difficult to control, leading to a narrowing of the process window. In subsequent high-temperature process steps after channel formation, boron ions gain energy with increasing temperature and migrate randomly within the silicon lattice, causing the originally precisely doped region to widen and deepen. If diffusion becomes uncontrolled, the channel size may exceed the design range, ultimately affecting device performance or even causing failure. Therefore, this application provides a novel transistor structure that forms an isolation layer on the surface side of the buried channel away from the substrate. This isolation layer suppresses channel diffusion, better controlling the depth and width of the buried layer, resulting in a wider process window and making it easier to start the buried channel from the designed buried channel.
[0044] like Figure 1 As shown, this application provides a transistor structure, including: a substrate 100; a well region 300 located within the substrate 100, the well region 300 including doped ions of a first conductivity type; a buried channel region 400 located within the well region 300, the buried channel region 400 including doped ions of a second conductivity type; and an isolation layer 500 located on the side of the buried channel region 400 opposite to the surface of the substrate 100, where the surface of the substrate 100 refers to... Figure 1 The upper surface of substrate 100 in the viewpoint, Figure 1 From the perspective of [the image source], the isolation layer 500 is located below the buried channel region 400, and the isolation layer 500 is in direct contact with the lower surface of the buried channel region 400; the gate structure 700 is located on the surface of the substrate 100. The gate structure 700 includes a gate dielectric layer, a gate conductive layer, and isolation sidewalls. Figure 1 The gate structure 700 is shown only as an example.
[0045] By adopting the transistor structure of this application, a buried channel region 400 is formed in the well region 300, which keeps the channel region 400 away from the surface of the substrate 100. This reduces the contact between the channel and the Si-O surface states from a physical perspective, making full use of the advantages of the buried channel of the buried channel device. An isolation layer 500 is formed on the side of the buried channel region 400 away from the surface of the substrate 100. The isolation layer 500 is used to suppress the diffusion of the buried channel region 400, and better control the depth and width of the buried channel region 400, resulting in a wider process window. This makes it easier to start the buried channel device from the designed buried channel, effectively widening the process and device electrical performance window of the buried channel device well region implantation and its anti-doping implantation.
[0046] In this embodiment, the first conductivity type of doped ion is an N-type ion, the second conductivity type of doped ion is a P-type ion, and the substrate 100 is a P-type substrate. The well region formed in the substrate 100 is an N-type well region, and the transistor structure is a BC PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) device. In another embodiment, the first conductivity type of doped ion is a P-type ion, the second conductivity type of doped ion is an N-type ion, the substrate 100 is an N-type substrate, and the well region formed in the substrate 100 is a P-type well region. The transistor structure is a BC NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) device, which also falls within the scope of protection of this application.
[0047] like Figure 1 As shown, the transistor structure further includes an epitaxial layer 600 located between the buried channel region 400 and the gate structure 700. The epitaxial layer 600 contains doped ions of a second conductivity type. The transistor structure also includes a source region 800 and a drain region 900 located within the well region 300 and distributed on both sides of the buried channel region 400. The depths of the source region 800 and the drain region 900 are both greater than the depth of the isolation layer 500; that is, the bottoms of the source region 800 and the drain region 900 are closer to the bottom surface of the substrate than the bottom of the isolation layer 500. The surfaces of the source region 800 and the drain region 900 are flush with the surface of the epitaxial layer 600 facing away from the buried channel region 400. The epitaxial layer 600 covers the surface of the buried channel region 400, meaning the epitaxial layer 600 is in direct contact with the surface of the buried channel region 400.
[0048] In this embodiment, the isolation layer 500 is a nitrogen-implanted layer, formed by nitrogen ion implantation into the well region 300. The width of the isolation layer 500 is substantially the same as the width of the buried channel region 400. The nitrogen isolation layer effectively suppresses the diffusion of the buried channel region 400, allowing for better control of its depth and width. Taking a PMOS transistor structure as an example, the diffusion of boron ions in silicon requires continuous lattice interstices or vacancies as migration channels. The high density of the nitrogen isolation layer cuts off these migration channels, effectively creating a physical barrier in the direction of boron ion diffusion, thus effectively suppressing boron ion diffusion and achieving effective control over the width and depth of the buried channel region 400.
[0049] In this embodiment, the substrate 100 also includes multiple isolation structures 200, with an active region between two adjacent isolation structures 200, and a buried channel region 400 located within the active region. The core function of the isolation structure is to achieve electrical isolation and physical demarcation between adjacent active regions, ensuring that each active region can work independently without interference from adjacent regions. It is a key structure for ensuring the function, performance, and reliability of the device.
[0050] like Figure 2 As shown in the embodiments of this application, a method for fabricating a transistor structure is also provided, for fabricating the transistor structure described in the claims, the method comprising the following steps:
[0051] S100: Provides a substrate;
[0052] S200: Ion implantation of a first conductivity type is performed on the substrate to form a well region in the substrate, the well region comprising dopant ions of the first conductivity type;
[0053] In this embodiment, prior to forming the well region, an isolation structure is formed on the substrate, with the area for forming the well region defined between every two adjacent isolation structures;
[0054] The formation process of the well region includes: coating a photoresist on the surface of the substrate, exposing the area to be implanted based on a photomask, and then performing well region IMP (Ion Implantation Process) to form the well region of the transistor structure.
[0055] S300: Ion implantation of a second conductivity type is performed on the well region to form a buried channel region in the substrate, wherein the buried channel region includes dopant ions of the second conductivity type;
[0056] In this embodiment, the well region is implanted with ions of the second conductivity type by anti-doping layer implantation to form a buried channel region in the substrate. The buried channel region includes doped ions of the second conductivity type. The buried channel region is far away from the substrate surface, which reduces the contact between the channel and the Si-O surface states from a physical perspective, and can reduce the impact of the Si-O surface states on the device performance to a certain extent.
[0057] S400: An isolation layer is formed on the side of the buried trench area away from the surface of the substrate;
[0058] S500: A gate structure is formed on the surface of the substrate; wherein the gate structure includes a gate dielectric layer, a gate conductive layer, and an isolation sidewall.
[0059] By employing the transistor structure fabrication method of this application, a buried channel region is formed in the well region, which keeps the channel region away from the substrate surface. This reduces the contact between the channel and the Si-O surface states from a physical perspective, fully utilizing the advantages of the buried channel in buried channel devices. An isolation layer is formed on the surface side of the buried channel region away from the substrate, and the diffusion of the buried channel region is suppressed by the isolation layer. This allows for better control of the depth and width of the buried channel region, resulting in a wider process window. This makes it easier for buried channel devices to be activated from the designed buried channel, effectively broadening the process and device electrical performance window for well region implantation and reverse doping implantation in buried channel devices.
[0060] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the transistor structure is a PMOS structure; or, the first conductivity type is P-type, the second conductivity type is N-type, and the transistor structure is an NMOS structure.
[0061] In this embodiment, the isolation layer is a nitrogen-implanted layer. Step S400: Forming an isolation layer on the side of the buried trench region facing away from the substrate includes the following steps:
[0062] Nitrogen ion implantation is performed on the substrate to form a nitrogen implantation layer on the side of the buried trench region facing away from the substrate surface, serving as the isolation layer. The width of the isolation layer is substantially the same as the width of the buried trench region. The nitrogen isolation layer effectively suppresses diffusion in the buried trench region, allowing for better control of the depth and width of the buried trench region.
[0063] In this embodiment, before step S500: forming the gate structure on the surface of the substrate, the following step is further included: forming an epitaxial layer on the side of the buried channel region facing the surface of the substrate using an epitaxial growth process, wherein the epitaxial layer includes doped ions of a second conductivity type. The gate structure is formed on the surface of the epitaxial layer. The epitaxial layer covers the surface of the buried channel region, that is, the epitaxial layer is in direct contact with the surface of the buried channel region.
[0064] In this embodiment, after step S500: the gate structure is formed on the surface of the substrate, the following step is further included:
[0065] Ion implantation of a second conductivity type is performed on opposite sides of the gate structure to form source and drain regions located on both sides of the buried channel region. The depth of the source and drain regions is greater than the depth of the isolation layer, meaning that the bottom of the source and drain regions is closer to the bottom surface of the substrate than the bottom of the isolation layer. The surfaces of the source and drain regions are flush with the surface of the epitaxial layer on the side opposite to the buried channel region.
[0066] The following is combined Figures 3-6 and Figure 1This application describes in detail the fabrication process of a transistor structure according to a specific embodiment.
[0067] Figure 3 This is a schematic diagram illustrating the provision of a substrate and the formation of a well region according to an embodiment of this application. Corresponding to steps S100 and S200, a substrate 100 is provided, an isolation structure 200 is formed in the substrate 100, and ion implantation of a first conductivity type is performed on the substrate 100 to form a well region 300 within the substrate 100. The well region 300 includes doped ions of the first conductivity type. Taking a BC PMOS as an example, a P-type substrate is provided, and N-type ion implantation is performed on the P-type substrate to form an N-type well region. Specifically, the formation process of the N-type well region 300 includes: coating a photoresist on the surface of the substrate 100, exposing the area to be implanted into the N-well using a photomask, and then performing N-well IMP implantation to form the N-well of the PMOS.
[0068] Figure 4 This is a schematic diagram illustrating the formation of a buried channel region and an isolation layer within a well region according to an embodiment of this application. Corresponding to steps S300 and S400, ion implantation of a second conductivity type is performed on the well region 300 to form a buried channel region 400 within the substrate 100. The buried channel region 400 includes dopant ions of the second conductivity type. An isolation layer 500 is formed on the side of the buried channel region 400 facing away from the surface of the substrate 100. Taking the fabrication of a PMOS device with a nitrogen-implanted isolation layer as an example, P-type ion implantation is performed on the N-well to form a P-type buried channel region within the substrate, and nitrogen ion implantation is performed on the N-well, forming a nitrogen-implanted layer on the side of the buried channel region facing away from the surface of the substrate. The step of forming the buried channel region 400 includes: performing ion implantation of a second conductivity type on the well region 300 through anti-doping layer implantation to form the buried channel region 400 within the substrate 100. The steps to form a nitrogen implantation layer include nitrogen doping implantation, suppressing boron (B) atom diffusion, and widening the process window.
[0069] Figure 5 This is a schematic diagram of the formation of an epitaxial layer according to an embodiment of this application. An epitaxial growth process is used on the side of the buried trench region 400 facing the surface of the substrate 100 (i.e., Figure 5 An epitaxial layer 600 is formed above the buried channel region 400 in the view, and the epitaxial layer 600 includes doped ions of a second conductivity type. In this embodiment, the epitaxial layer 600 directly covers the surface of the buried channel region 400 and is in direct contact with the surface of the buried channel region 400.
[0070] Figure 6This is a schematic diagram illustrating the formation of a gate structure according to an embodiment of this application. A gate structure 700 is formed on the surface of the epitaxial layer 600. Further, ion implantation of a second conductivity type is performed on opposite sides of the gate structure 700 to form a source region 800 and a drain region 900 located on both sides of the buried channel region, thus obtaining... Figure 1 The transistor structure shown is such that the depths of the source region 800 and the drain region 900 are both greater than the depth of the isolation layer 500, meaning that the bottoms of the source region 800 and the drain region 900 are closer to the bottom surface of the substrate 100 than the bottom of the isolation layer 500.
[0071] Figure 7 It is a channel conduction state diagram obtained through simulation experiments of an existing transistor structure. Figure 8 This is a channel conduction state diagram of the transistor structure of this application obtained through simulation experiments. Specifically, Figure 7 and Figure 8 The corresponding TCAD (Technology Computer-Aided Design) simulation of the BC PMOS shows the channel conduction status in the Vth on state. Figure 7 The orange portion inside the red circle represents the conductive channel of a transistor structure in existing technology. Figure 8 The orange portion within the red circle represents the conduction channel of the transistor structure in this application. (Comparison is needed.) Figure 7 and Figure 8 It can be seen that by using the nitrogen implantation layer as an isolation layer to suppress boron diffusion, this application can better control the width and depth of the P-type buried layer, obtain better device performance, and thus obtain a wider process window, making it easier to start the buried channel device from the designed buried channel, effectively widening the process and device electrical performance window of the buried channel device well region implantation and its reverse doping implantation.
[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.
Claims
1. A transistor structure, characterized in that, include: Substrate; A well region, located within the substrate, comprising doped ions of a first conductivity type; An embedded channel region is located within the well region, and the channel region includes doped ions of a second conductivity type; An isolation layer is located on the side of the buried trench region facing away from the substrate; A gate structure is located on the surface of the substrate.
2. The transistor structure according to claim 1, characterized in that, It also includes an epitaxial layer located between the buried channel region and the gate structure, wherein the epitaxial layer includes doped ions of a second conductivity type.
3. The transistor structure according to claim 1, characterized in that, The doped ions of the first conductivity type are N-type ions, and the doped ions of the second conductivity type are P-type ions.
4. The transistor structure according to claim 1, characterized in that, The isolation layer is a nitrogen-injected layer.
5. The transistor structure according to claim 1, characterized in that, The width of the isolation layer is the same as the width of the buried trench area.
6. The transistor structure according to claim 1, characterized in that, It also includes a source region and a drain region located within the well region and distributed on both sides of the buried trench region, wherein the depth of the source region and the drain region is greater than the depth of the isolation layer.
7. A method for fabricating a transistor structure, characterized in that, The method for fabricating the transistor structure according to any one of claims 1 to 6 comprises the following steps: Provide a substrate; The substrate is implanted with ions of a first conductivity type to form a well region within the substrate, the well region comprising dopant ions of the first conductivity type; The well region is implanted with ions of a second conductivity type to form a buried channel region in the substrate, the buried channel region comprising dopant ions of the second conductivity type; An isolation layer is formed on the side of the embedded trench region facing away from the substrate. A gate structure is formed on the surface of the substrate.
8. The method for fabricating a transistor structure according to claim 7, characterized in that, Forming an isolation layer on the side of the buried trench region away from the substrate includes the following steps: Nitrogen ion implantation is performed on the substrate to form a nitrogen implantation layer on the side of the buried trench region away from the surface of the substrate, which serves as the isolation layer.
9. The method for fabricating a transistor structure according to claim 7, characterized in that, Before forming the gate structure on the surface of the substrate, the following steps are also included: An epitaxial layer is formed on the side of the buried trench region facing the substrate using an epitaxial growth process, and the epitaxial layer includes doped ions of a second conductivity type. The gate structure is formed on the surface of the epitaxial layer.
10. The method for fabricating a transistor structure according to claim 7, characterized in that, After forming the gate structure on the surface of the substrate, the following steps are also included: Ion implantation of a second conductivity type is performed on opposite sides of the gate structure to form source and drain regions located on both sides of the buried channel region, wherein the depth of the source and drain regions is greater than the depth of the isolation layer.