Layered reset control system of switching module

Abstract

The invention provides a layered reset control system of a switching module. The layered reset control system comprises a monitoring logic circuit and a microprocessor, the monitoring logic circuit is configured to receive reset request signals from at least two independent reset sources and perform logical operation on the reset request signals to generate a first reset control signal output to the switch chip layer and / or the bus interface layer; the microprocessor is configured to monitor the working state of the optical module layer and / or the network physical layer chip, and trigger and generate a second reset control signal for the optical module layer and / or the network physical layer chip based on the working state; wherein at least two of the switching chip layer, the bus interface layer, the optical module layer and the network physical layer form a controlled multi-level function level in the switching module, and the monitoring logic circuit and the microprocessor cooperate to realize discrete reset control of the multi-level function level. According to the system provided by the invention, rapid isolation and recovery of a fault unit are realized through layered precise reset, and global interruption of the system is avoided.

Description

Technical Field

[0001] This disclosure generally relates to the field of reliability design technology for aerospace electronic equipment, and specifically to a hierarchical reset control system for a switching module. Background Technology

[0002] In high-reliability applications such as aerospace, high-speed data exchange modules are the key hardware foundation for achieving interconnectivity within the system. Their reset management system undertakes the core functions of status monitoring, anomaly recovery, and security isolation, directly affecting the reliability and continuity of the entire mission system.

[0003] However, existing reset management schemes suffer from a fundamental flaw: insufficient granularity in triggering and controlling reset operations. When a specific sub-unit within a switching module (such as an optical module for a single communication channel or a network physical layer chip) fails, commonly used reset mechanisms cannot specifically isolate and restore that faulty unit. Instead, they inevitably affect or even trigger the reset of the entire switching module or the upstream system. This system-wide reset pattern forces the interruption of all normally functioning communication links, causing system-level service disruptions and failing to meet the extreme requirements of localized fault handling and service continuity in high-reliability application scenarios. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a hierarchical reset control system for a switching module to solve the above problems.

[0005] This application provides a hierarchical reset control system for a switching module, including: a monitoring logic circuit and a microprocessor; The monitoring logic circuit is configured to receive reset request signals from at least two independent reset sources and perform logical operations on the reset request signals to generate a first reset control signal output to the switching chip layer and / or bus interface layer. The microprocessor is configured to monitor the operating state of the optical module layer and / or the network physical layer chip, and trigger the generation of a second reset control signal for the optical module layer and / or the network physical layer chip based on the operating state. The switching module comprises at least two of the switching chip layer, the bus interface layer, the optical module layer, and the network physical layer chip, forming a controlled multi-level functional hierarchy. The monitoring logic circuit and the microprocessor work together to implement discrete reset control of the multi-level functional hierarchy.

[0006] According to the technical solution provided in the embodiments of this application, the multi-functional layer further includes a global layer, which responds to an externally input global reset signal.

[0007] According to the technical solution provided in the embodiments of this application, the monitoring logic circuit includes at least one multi-input AND gate logic device, which is configured to output a valid first reset control signal when any one of the multiple reset request signals it receives is at a valid level.

[0008] According to the technical solution provided in the embodiments of this application, the at least two independent reset sources are selected from at least two of the following sources: power-on reset source provided by the power-on reset chip, strategy reset source provided by the microprocessor, master control reset source provided by the external master control unit, and manual trigger reset source.

[0009] According to the technical solution provided in the embodiments of this application, the power-on reset source is provided by a reset management chip, which is configured to output a power-on reset signal to the monitoring logic circuit and / or the microprocessor after detecting that the system is powered on and the power supply is stable.

[0010] According to the technical solution provided in the embodiments of this application, the microprocessor monitors the working status of the optical module layer by receiving hardware alarm signals actively reported by the optical module layer; the microprocessor monitors the working status of the network physical layer chip by periodically reading the link status register of the network physical layer chip through the bus interface.

[0011] According to the technical solution provided in the embodiments of this application, the microprocessor is further configured to execute the following control flow: For the optical module layer, when a hardware alarm signal is received, the corresponding optical module or optical module group is reset, and the alarm is verified after the reset. If the alarm continues, the fault is accumulated and reported. For network physical layer chips, when the link disconnection state is detected to last for more than a first preset time, the corresponding chip is reset, and the link is verified after the reset. If the link is not restored, the fault is accumulated and reported.

[0012] According to the technical solution provided in the embodiments of this application, the fault accumulation and reporting includes: counting reset attempts for the same fault event, and when the count reaches a preset number, reporting fault information containing device identifier and fault location code through the communication interface.

[0013] According to the technical solution provided in the embodiments of this application, the microprocessor is further configured to monitor the internal state of the switching chip layer based on the switching strategy, and when the internal state meets the preset reset conditions, generate a strategy reset request signal for the switching chip layer, and output the signal as one of the at least two independent reset sources to the monitoring logic circuit.

[0014] According to the technical solution provided in the embodiments of this application, the system is integrated into a fully domestically produced high-speed optical fiber switching module, wherein the switching chip layer is implemented by an SDI3210 switching chip, the microprocessor is implemented by a GD32F450 series microcontroller, the bus interface layer is a PCIe bus, the optical module layer is implemented by a JM048L series optical module, and the network physical layer chip is implemented by a CH395Q series chip; Compared with existing technologies, the advantages of this application are as follows: By setting up an architecture where the monitoring logic circuit and the microprocessor work together, discrete and precise reset control of multiple functional levels within the switching module is achieved. The monitoring logic circuit can integrate requests from at least two independent reset sources, ensuring that any valid request can trigger a critical reset of the switching chip or bus interface, improving the reliability and timeliness of the reset response; the microprocessor directly triggers the reset intelligently based on the actual working state of the optical module or network physical layer chip, realizing a shift from passive polling to active, real-time status response. The collaboration of both enables the system to precisely limit the reset operation to the fault level, effectively avoiding the phenomenon of a global reset of the entire machine due to a local fault in traditional solutions, greatly shortening the system recovery time, and significantly improving the overall reliability and availability of the switching module. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of the hierarchical reset control system for the switching module provided in this application; Figure 2 This is a schematic diagram of a multi-level functional hierarchy; Figure 3 This is a block diagram of the switching module. Figure 4 This is a structural diagram of the GD32F450 monitoring and management unit; Figure 5 This is a schematic diagram of the JMAX6390 reset chip circuit. Figure 6 This is a schematic diagram of the structure of a dual 4-channel AND gate CD4082 logic monitoring circuit.

[0016] The reference numerals are: 10: monitoring logic circuit; 20: microprocessor. Detailed Implementation

[0017] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Please refer to Figures 1-6 This embodiment provides a hierarchical reset control system for a switching module, including: a monitoring logic circuit 10 and a microprocessor 20; The monitoring logic circuit 10 is configured to receive reset request signals from at least two independent reset sources and perform logical operations on the reset request signals to generate a first reset control signal output to the switching chip layer and / or bus interface layer. The microprocessor 20 is configured to monitor the operating state of the optical module layer and / or the network physical layer chip, and trigger the generation of a second reset control signal for the optical module layer and / or the network physical layer chip based on the operating state. The switching module comprises at least two of the switching chip layer, the bus interface layer, the optical module layer, and the network physical layer chip, forming a controlled multi-level functional hierarchy. The monitoring logic circuit 10 and the microprocessor 20 work together to implement discrete reset control of the multi-level functional hierarchy.

[0020] Specifically, the hierarchical reset control system for the switching module provided in this embodiment is mainly applied to domestically produced high-speed fiber optic switching modules in the aerospace electronic equipment field. It fundamentally solves the technical problem of local faults causing global interruptions in traditional reset schemes, achieving rapid recovery through precise isolation of faulty units, thus ensuring the continuity and reliability of system tasks. This system consists of a collaborative control architecture comprised of monitoring logic circuit 10 and microprocessor 20, combined with... Figures 1 to 6The hardware connections shown enable discrete reset control of multiple functional layers within the switching module. These controlled layers include the switching chip layer, bus interface layer, optical module layer, and network physical layer (PHY) chip. Each layer operates independently yet collaboratively, providing a structural foundation for precise reset. The monitoring logic circuit 10 is built using dual 4-way AND gate logic devices CD4082SA as the core logic operation unit. Its main function is to receive reset request signals from at least two independent reset sources, perform logic operations to generate a first reset control signal, and output it to the switching chip layer and bus interface layer respectively. The switching chip layer uses a domestically produced SDI3210 switching chip, and the bus interface layer is a PCIe bus. The corresponding first reset control signals are SDI3210_RST_N and PCIE_RST_N, respectively. The microprocessor 20 uses a domestically produced GD32F450 series microcontroller as the status... The monitoring and partial reset control core monitors the working status of the optical module layer and network physical layer chips in real time through a hardware interface. The optical module layer uses JM048L series optical modules and is divided into three groups according to channels. The network physical layer chips use CH395Q series chips. The microprocessor 20 generates a second reset control signal based on the monitored working status, including JM048T_01_RST_N, JM048T_02_RST_N, and JM048T_03_RST_N for the optical module groups, and CH395_01_RST_N and CH395_02_RST_N for the PHY chips.

[0021] The collaborative working mode of the monitoring logic circuit 10 and the microprocessor 20 ensures the accuracy and hierarchical isolation of the reset operation. When an anomaly occurs in the switching chip layer or the bus interface layer, the monitoring logic circuit 10 logically integrates the received reset request signals, and the generated first reset control signal only acts on the target layer, without interfering with the normal operation of other functional layers such as the optical module layer and the network physical layer chip. When an anomaly occurs in the optical module layer or the network physical layer chip, the microprocessor 20 generates a second reset control signal based on the real-time monitored status data, and performs a reset operation only on the faulty optical module group or PHY chip, avoiding affecting the core switching functions of the switching chip layer and the bus interface layer. This design effectively abandons the global reset mode of traditional solutions where a single fault affects the entire system. By strictly limiting the reset operation to the fault level, the impact of reset on the overall system operation is greatly reduced. At the same time, the multi-source reset request response mechanism of the monitoring logic circuit 10 and the real-time status monitoring capability of the microprocessor 20 significantly improve the reliability and timeliness of the reset control, making the system more adaptable in high-reliability application scenarios such as aerospace, and successfully solving the core defect of insufficient reset granularity in traditional technologies.

[0022] Furthermore, the multi-functional layer also includes a global layer that responds to an externally input global reset signal.

[0023] Specifically, in this embodiment, the multi-functional layer, based on the switching chip layer, bus interface layer, optical module layer, and network physical layer chip, further includes a global layer. The core function of this layer is to respond to externally input global reset signals, providing overall system reset protection, while complementing the local reset functions of other functional layers, thus improving the system reset control architecture. Combined with... Figure 1 The principle block diagram of the switching module and Figure 4 The hardware connection relationship of the GD32F450 monitoring and management unit is as follows: the global layer reset signal mainly includes the externally input top-level reset signal and the global reset signal generated by the processor. In addition, a manually triggered global reset signal is also set, forming a multi-path global reset triggering mechanism.

[0024] The global layer's response logic is clearly defined. When the system receives an externally input top-level reset signal or a global reset signal generated by the processor, it immediately sets the reset state of all functional layers, achieving a synchronous reset of the entire switching module. This ensures that the system can quickly return to its initial state in scenarios requiring a complete reboot. Manually triggered global reset signals are implemented via jumpers or buttons, providing operators with an emergency reset mechanism to handle system anomalies in special circumstances. The global layer's design satisfies the need for overall system reset in scenarios such as aerospace, without affecting the local reset functions of other layers. This allows the system to accurately isolate and handle local faults while quickly resolving overall anomalies through a global reset when needed, balancing the precision and comprehensiveness of reset control and further enhancing the system's adaptability and reliability in complex application environments.

[0025] Furthermore, the monitoring logic circuit 10 includes at least one multi-input AND gate logic device, which is configured to output a valid first reset control signal when any one of the multiple reset request signals it receives is at a valid level.

[0026] Specifically, in this embodiment, the multi-input AND gate logic device used in the monitoring logic circuit is a dual 4-channel AND gate chip CD4082SA, and its hardware connection relationship is shown in Figure 6. This device, as the core operation unit of the monitoring logic circuit, can efficiently realize the logic processing of multiple reset request signals and the generation of the first reset control signal. Combining the reset control requirements of the switching chip layer and the PCIe bus layer, the dual 4-channel AND gate chip CD4082SA is divided into two independent logic operation channels, corresponding to the reset control of the two levels respectively, ensuring that the generation of reset signals at each level does not interfere with each other, further improving the accuracy of reset control.

[0027] For the switching chip layer, one operation channel of the dual 4-way AND gate chip CD4082SA receives three active-low reset request signals from different independent reset sources. When any one of these signals is active, the operation channel immediately outputs an active-low SDI3210_RST_N signal as the first reset control signal, triggering a reset of the switching chip layer. For the PCIe bus layer, the other operation channel also receives three active-low reset request signals, following the same logic: any active input triggers an active-low PCIe_RST_N signal, thus triggering a reset of the PCIe bus layer. This configuration design, where any active input triggers an active output, ensures a delay-free response to the reset request signals, avoiding reset failures caused by abnormal transmission of a single reset source signal. It also simplifies the logic operation process, reduces circuit complexity, and allows the monitoring logic circuit to maintain high reliability while possessing good stability, providing solid hardware support for rapid fault recovery at both the switching chip layer and the PCIe bus layer.

[0028] Furthermore, the at least two independent reset sources are selected from at least two of the following sources: a power-on reset source provided by the power-on reset chip, a strategy reset source provided by the microprocessor 20, a master control reset source provided by the external master control unit, and a manual trigger reset source.

[0029] Specifically, in this embodiment, the monitoring logic circuit receives at least two independent reset sources, selected from a combination of the power-on reset source provided by the power-on reset chip, the strategy reset source provided by the microprocessor, the master control reset source provided by the external master control unit, and the manually triggered reset source. Each reset source establishes a stable connection with the monitoring logic circuit through hardware circuitry to ensure reliable transmission of the reset request signal. Figure 3 JMAX6390 reset chip circuit and Figure 6 The monitoring logic circuit structure includes a power-on reset source implemented by the JMAX6390 reset chip, which outputs reset request signals for the switching chip layer and the PCIe bus layer; a strategy reset source generated by the GD32F450 microprocessor, which outputs corresponding reset request signals according to the system switching status; an external main control unit is a Com-E interface motherboard, which outputs main control reset request signals through its protocol processing and status monitoring functions; and a manual trigger reset source, which provides an emergency reset trigger path through jumper or button design, with the corresponding reset request signal directly connected to the signal input terminal of the monitoring logic circuit.

[0030] Each independent reset source provides dedicated reset request signals for the switching chip layer and the PCIe bus layer, forming a multi-dimensional reset triggering mechanism. The monitoring logic circuit can flexibly select at least two reset sources to work in combination according to the actual application scenario. This multi-source selection design can avoid the failure of the reset function due to the failure of a single reset source, ensuring that the target level reset can be triggered in a timely manner under different abnormal scenarios. For example, the system relies on the power-on reset source during the power-on phase, the strategy reset source and the master control reset source during normal operation, and the manual trigger reset source can be used in emergency situations. The redundant configuration and flexible combination of multiple reset sources significantly improve the reliability and adaptability of reset control, allowing the system to cope with the complex operating conditions in aerospace applications and further ensuring the stable operation of the switching module.

[0031] Furthermore, the power-on reset source is provided by a reset management chip, which is configured to output a power-on reset signal to the monitoring logic circuit 10 and / or the microprocessor 20 after detecting that the system is powered on and the power supply is stable.

[0032] Specifically, in this embodiment, the power-on reset source is implemented using the JMAX6390 reset management chip, and its hardware circuit structure is as follows: Figure 3 As shown, this chip establishes a stable connection with the system power supply circuit, monitoring logic circuit, and microprocessor, undertaking the core task of resetting and triggering the system during power-up. When the VCC power supply of the switching module starts to power on, and the voltage gradually rises and meets the preset voltage establishment conditions, the JMAX6390 reset management chip starts working and then outputs a clean power-on reset signal.

[0033] The power-on reset signals are transmitted to the monitoring logic circuit 10 and the microprocessor 20, respectively. The power-on reset signals output to the monitoring logic circuit include 6390_3210_RST_N for the switching chip layer and 6390_PCIE_RST_N for the PCIe bus layer. The power-on reset signal output to the microprocessor is GD32_Global_RST_N. This design ensures that the switching chip layer, PCIe bus layer, and microprocessor can synchronously enter the reset state during the initial power-on phase, avoiding hardware conflicts or functional abnormalities caused by inconsistent startup timings at different levels. Furthermore, the clean power-on reset signal has a stable pulse width of 1000ms, providing ample time for each hardware level to complete initialization, significantly improving the reliability and stability of the system's power-on startup and laying a solid foundation for subsequent normal operation.

[0034] Furthermore, the microprocessor 20 monitors the working status of the optical module layer by receiving hardware alarm signals actively reported by the optical module layer; the microprocessor 20 monitors the working status of the network physical layer chip by periodically reading the link status register of the network physical layer chip through the bus interface.

[0035] Specifically, in this embodiment, the microprocessor monitors the operating status of the optical module layer using an active response design, combined with... Figure 3 The hardware connection relationship of the GD32F450 monitoring and management unit is shown. The JM048L series optical modules at the optical module layer monitor the working status of the internal lasers in real time. When the optical power of any channel is lower than a preset threshold, the optical module will actively generate a hardware alarm signal and report it to the microprocessor. These hardware alarm signals correspond to three groups of optical modules, namely JM048T_01_ALERT_N, JM048T_02_ALERT_N, and JM048T_03_ALERT_N. The microprocessor receives these signals in real time through a dedicated pin, without the need for additional periodic polling, ensuring the immediate capture of abnormal states of the optical modules and effectively solving the problem of easily missing transient faults under the traditional polling method.

[0036] For monitoring the operational status of network physical layer chips, the microprocessor employs a periodic reading method. It establishes a communication connection with the CH395Q series PHY chip via the SPI bus interface, reading the link status bit in the PHY_STATUS register of the PHY chip every 20 milliseconds. This periodic monitoring design not only reliably acquires link status data but also avoids the high resource consumption caused by frequent queries. It directly determines whether the link is in a normal connection state through register data, providing accurate status information for subsequent reset triggering. Two monitoring methods are adapted to the operating characteristics of the optical module and the PHY chip respectively, achieving targeted optimization for different levels of status monitoring, improving the overall reliability and efficiency of monitoring, and providing solid data support for hierarchical reset control.

[0037] Furthermore, the microprocessor 20 is also configured to execute the following control flow: For the optical module layer, when a hardware alarm signal is received, the corresponding optical module or optical module group is reset, and the alarm is verified after the reset. If the alarm continues, the fault is accumulated and reported. For network physical layer chips, when the link disconnection state is detected to last for more than a first preset time, the corresponding chip is reset, and the link is verified after the reset. If the link is not restored, the fault is accumulated and reported.

[0038] Specifically, in this embodiment, the microprocessor's control flow for the optical module layer is closely integrated with the status monitoring stage, combined with the attached... Figure 3The hardware connection relationship shown indicates that when the microprocessor receives a hardware alarm signal reported by the optical module layer, it immediately locates the corresponding optical module group, generates and sends the corresponding second reset control signal, and performs a reset operation on the faulty group. After the reset operation is completed, the microprocessor continuously monitors the hardware alarm signal status of the group. If the alarm signal disappears, it indicates that the fault has been recovered, and the microprocessor immediately clears the fault count of the group and restores its normal working state. If the alarm signal is not cleared after the reset is released, it indicates that the fault persists, and the microprocessor accumulates the fault count and triggers the reset operation again to ensure that recoverable faults are fully attempted.

[0039] For the control flow of the network physical layer chip, the first preset duration is set to 100 milliseconds. When the microprocessor periodically reads the PHY_STATUS register through the SPI interface and detects that the link disconnection state of a certain CH395Q chip has lasted for 100 milliseconds, it immediately sends the corresponding second reset control signal to that chip. After the reset is completed, the microprocessor continues to monitor the link status register data. If the link returns to a normal connection state, the working status information of that port is updated to maintain normal system communication; if the link is still disconnected, the microprocessor starts the fault accumulation process and prepares for subsequent fault reporting operations. This closed-loop control process of "reset-verification-accumulation" ensures that faults can be recovered in a timely and effective manner, while avoiding unnecessary reporting due to momentary faults or misjudgments. This significantly improves the system's accuracy and reliability in handling local faults, providing strong support for business continuity in aerospace scenarios.

[0040] Furthermore, the fault accumulation and reporting includes: counting reset attempts for the same fault event, and when the count reaches a preset number, reporting fault information containing device identifier and fault location code through the communication interface.

[0041] Specifically, in this embodiment, the fault accumulation and reporting functions are closely integrated with the reset attempt process. Independent counting mechanisms are established for fault events at the optical module layer and network physical layer chips, with a preset count of three attempts to ensure sufficient attempts and reasonable definition of fault recovery. For the optical module layer, if the hardware alarm signal remains unresolved after three reset operations for a group of optical modules, the microprocessor determines that the group of optical modules has a persistent fault, stops repeated resets, and initiates the reporting process. For the network physical layer chips, if the link of a CH395Q chip fails to recover after a reset, and the accumulated reset attempts reach three, fault reporting is also triggered to avoid invalid resets consuming system resources.

[0042] The reporting process is implemented through dual communication interfaces, Eth0 and Eth1, ensuring the reliability of the reporting channel. The reported fault information includes two core components: first, the device MAC address, serving as a device identifier and enabling rapid location of the faulty switching module; second, the fault location code, with different fault locations corresponding to unique codes. For example, the code for a failure in the T01 group (channels 0-11) of optical modules is 0x10, the code for a failure in the PHY01 chip is 0x20, and other fault locations also have corresponding unique codes. This reporting design, which includes both device identification and fault location codes, completely solves the problem of traditional fault reports lacking clear identification, allowing maintenance personnel to quickly and accurately locate faulty devices and specific faulty units, significantly shortening fault diagnosis and repair time, and further improving the maintainability and stability of the system in high-reliability aerospace scenarios.

[0043] Furthermore, the microprocessor 20 is also configured to monitor the internal state of the switching chip layer based on the switching strategy, and when the internal state meets the preset reset conditions, generate a strategy reset request signal for the switching chip layer, and output the signal as one of the at least two independent reset sources to the monitoring logic circuit 10.

[0044] Specifically, in this embodiment, the microprocessor performs real-time monitoring of the internal state of the switching chip layer based on the switching strategy, combined with the attached... Figure 2 The hardware connection relationship of the GD32F450 monitoring and management unit is shown. During normal system operation, the microprocessor continuously maintains the routing table and monitors the port register status, cache status, packet drop status, and interrupt indications caused by various events in real time. It comprehensively covers the key status dimensions of the switching chip during operation and ensures accurate perception of internal anomalies.

[0045] The preset reset conditions are explicitly defined by the system switching strategy. When the microprocessor detects that any of the aforementioned internal status indicators has reached the preset reset threshold, it immediately generates a policy reset request signal GD32_3210_RST_N for the switching chip layer. This signal, as one of at least two independent reset sources, is directly output to the dual 4-way AND gate CD4082SA of the monitoring logic circuit, participating in logic operations together with other reset request signals such as the power-on reset source and the master control reset source. This design allows the reset triggering of the switching chip layer not only to respond to external anomalies but also to adapt to the dynamic requirements of the system switching strategy. When the switching state does not meet the requirements of routing table maintenance or data transmission, a reset can be actively triggered to restore normal switching function, significantly improving the targeting and flexibility of reset control and further ensuring the stable operation of the core functions of the switching module.

[0046] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A hierarchical reset control system for a switching module, the system comprising: Comprising: a monitoring logic circuit (10) and a microprocessor (20); the monitoring logic circuit (10) is configured to receive reset request signals from at least two independent reset sources and perform logical operation on the reset request signals to generate a first reset control signal output to the switching chip layer and / or the bus interface layer; the microprocessor (20) is configured to monitor the working state of the optical module layer and / or the network physical layer chip and trigger a second reset control signal for the optical module layer and / or the network physical layer chip based on the working state; wherein at least two of the switching chip layer, the bus interface layer, the optical module layer and the network physical layer chip constitute a multi-level functional hierarchy controlled in the switching module, and the monitoring logic circuit (10) and the microprocessor (20) cooperatively implement separate reset control of the multi-level functional hierarchy.

2. The hierarchical reset control system of a switching module according to claim 1, wherein, The multi-functional hierarchy further comprises a global layer which responds to an externally input global reset signal.

3. The hierarchical reset control system of a switch module according to claim 1, wherein, The monitoring logic circuit (10) comprises at least one multi-input AND gate logic device configured to output a valid first reset control signal when any of the multiple reset request signals it receives is at a valid level.

4. The hierarchical reset control system of a switching module according to claim 1 or 3, characterized in that, The at least two independent reset sources are selected from at least two of the following sources: a power-on reset source provided by a power-on reset chip, a policy reset source provided by the microprocessor (20), a master reset source provided by an external master control unit, and a manually triggered reset source.

5. The hierarchical reset control system of claim 4, wherein, The power-on reset source is provided by a reset management chip configured to output a power-on reset signal to the monitoring logic circuit (10) and / or the microprocessor (20) after detecting system power-on and stable power supply.

6. The hierarchical reset control system of a switch module of claim 1, wherein, The microprocessor (20) monitors the working state of the optical module layer by receiving a hardware alarm signal actively reported by the optical module layer; and monitors the working state of the network physical layer chip by periodically reading a link state register of the network physical layer chip through a bus interface.

7. The hierarchical reset control system of a switching module according to claim 6, wherein, The microprocessor (20) is further configured to perform the following control process: For the optical module layer, when a hardware alarm signal is received, a reset of the corresponding optical module or optical module group is triggered, and after the reset, it is verified whether the alarm is eliminated, and if the alarm persists, fault accumulation and reporting are performed; For the network physical layer chip, when it is monitored that the link disconnection state lasts for more than a first preset time length, a reset of the corresponding chip is triggered, and after the reset, it is verified whether the link is restored, and if not, fault accumulation and reporting are performed.

8. The hierarchical reset control system of claim 7, wherein, The fault accumulation and reporting includes counting the number of reset attempts for the same fault event, and when the count reaches a preset number, fault information containing device identification and fault location code is reported through a communication interface.

9. The hierarchical reset control system of a switch module of claim 1, wherein, The microprocessor (20) is further configured to monitor an internal state of the switch chip layer based on the switching policy, and when the internal state meets a preset reset condition, generate a policy reset request signal for the switch chip layer and output the signal as one of the at least two independent reset sources to the monitoring logic circuit (10).

10. The hierarchical reset control system of a switch module of claim 1, wherein, The system is integrated in a nationalization high-speed optical fiber switching module, wherein the switch chip layer is implemented by an SDI3210 switch chip, the microprocessor (20) is implemented by a GD32F450 series microcontroller, the bus interface layer is a PCIe bus, the optical module layer is implemented by a JM048L series optical module, and the network physical layer chip is implemented by a CH395Q series chip.

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