Method for preparing optical chip by using wafer

Abstract

The invention provides a method for preparing an optical chip by using a wafer, and relates to the technical field of integrated photon chip manufacturing, and the method comprises the steps: forming a deep etching window in the front surface of the wafer, and carrying out the etching from an optical chip protection layer to the interior of an optical chip substrate in the thickness direction based on the deep etching window, so as to expose the side surface of an optical interface, a bottom step is formed on the edge of the optical chip substrate; turning over the wafer subjected to the deep etching process, arranging a back etching area on the optical chip substrate on the back of the wafer, and etching from the optical chip substrate to a preset position based on the back etching area so as to form a top step which shrinks inwards in the horizontal direction relative to the bottom step on the edge of the optical chip substrate; thinning the whole wafer subjected to the back etching process to a set thickness; and finally, segmenting the thinned wafer along the scribing line to obtain a plurality of optical chips which expose the side surfaces of the optical interfaces and have step-shaped end surface morphology.

Description

Technical Field

[0001] This invention relates to the field of integrated photonic chip manufacturing technology, and in particular to a method for fabricating optical chips using wafers. Background Technology

[0002] With the rapid development of information technology, the demand for data transmission bandwidth and energy efficiency is exploding. Silicon photonics technology optical chips, with their advantages of CMOS (Complementary Metal Oxide Semiconductor) compatibility, low loss, and high integration, have become the mainstream platform for on-chip and inter-chip optical interconnects. As the core carrier for realizing optoelectronic convergence, optical chips have significant strategic importance in fields such as data centers, high-performance computing, and 5G communications.

[0003] In the current development of integrated photonic chips, end-to-end horizontal direct coupling places extremely high demands on end-face morphology, surface finish, alignment accuracy, and post-packaging thermal stability. Existing processes typically involve directly cutting the two ends of the chip flat, or only performing deep etching on the front side to expose the optical interface; the latter leaves a bottom step on the end face, which can easily lead to problems such as misalignment of the optical port, excessive gaps, and obstructed heat dissipation when interfacing with heterogeneous chips of different shapes, making it difficult to simultaneously achieve low-loss coupling and high-reliability packaging.

[0004] Meanwhile, the lack of unified and repeatable control over step height and chip thickness makes optical path matching and loss extremely sensitive to packaging errors and temperature changes, resulting in insufficient coupling efficiency and long-term stability. Summary of the Invention

[0005] In view of the above problems, the present invention provides a method for fabricating optical chips using wafers, which improves the compatibility and stability of coupling between various heterogeneous optical chips while maintaining wafer yield and mechanical strength, realizes wafer-level flexible configuration of optical chip end-face morphology parameters, and has the capability of customizing optical chip end-faces for mass production.

[0006] This invention provides a method for fabricating optical chips using a wafer. The method includes: a deep etching process, in which a deep etching window is formed on the optical chip protective layer on the front side of the wafer according to the designed optical chip width and the layout of the optical interface of the photonic functional layer of the optical chip; etching from the optical chip protective layer along the thickness direction to the interior of the optical chip substrate based on the deep etching window to expose the side of the optical interface and form a bottom step at the edge of the optical chip substrate; a back etching process, in which the wafer after the deep etching process is flipped over, and a back etching area is formed on the optical chip substrate on the back side of the wafer; etching from the back etching area to a predetermined position to form a top step at the edge of the optical chip substrate, and the top step is horizontally contracted inward relative to the bottom step; a chip thinning process, in which the entire wafer after the back etching process is thinned to a set thickness; and finally, the thinned wafer is divided along a dicing line to obtain multiple optical chips with exposed optical interface sides and stepped end face morphology.

[0007] According to an embodiment of the present invention, the optical chip substrate includes silicon-on-insulator; the photonic functional layer of the optical chip includes a waveguide layer and a metal layer, the waveguide layer material includes single-crystal silicon, silicon nitride, and lithium niobate, the metal layer material includes titanium nitride and platinum; and the optical chip protective layer material includes silicon oxide.

[0008] According to embodiments of the present invention, both the deep etching process and the back etching process include deep reactive ion etching; the chip thinning process includes chemical mechanical polishing.

[0009] According to an embodiment of the present invention, the predetermined location is within the optical chip substrate.

[0010] According to an embodiment of the present invention, the deep etching window and the back etching area are independent configurable parameters used to customize the stepped end face morphology of the optical chip.

[0011] According to an embodiment of the present invention, the back etching process uses the bottom step as a reference, so that the length and thickness of the top step meet the end-to-end coupling requirements with other optical chips.

[0012] According to an embodiment of the present invention, the deep etching window is aligned with or adjacent to the optical interface, so that the vertical end face of the optical chip obtained after segmentation is coplanar with the exposed side face of the optical interface, or the distance between the vertical end face and the exposed side face of the optical interface is less than a preset threshold.

[0013] According to an embodiment of the present invention, the back-side etching region has a lateral etching width greater than that of the deep etching window on the optical chip, and is aligned with the deep etching window at the edge of the optical chip, so as to ensure that the top step has a predetermined shrinkage amount relative to the bottom step in the direction from the edge of the optical chip toward its interior.

[0014] According to an embodiment of the present invention, the back etching region adopts a staggered layout, so that each optical chip obtained after dicing has only one back etching region, so as to maintain the overall mechanical strength of the wafer while forming the top step and avoid the wafer from breaking before dicing.

[0015] According to embodiments of the present invention, the optical chip includes an active optical chip and a passive optical chip.

[0016] According to an embodiment of the present invention, the optical interface is used to import external light or export internal light from the optical chip; the optical interface includes an insulated tapered coupler.

[0017] Compared with the prior art, the method for fabricating optical chips using wafers provided by the present invention has at least the following beneficial effects:

[0018] By employing a combined front and back etching and wafer thinning process, the configurable and reproducible geometry parameters of the end-face steps are achieved at the wafer level. This ensures that the optical interface is exposed coplanarly or adjacently after wafer dicing, facilitating direct horizontal coupling between multiple chips end-to-end. This improves mode matching, reduces insertion loss, and provides favorable placement and heat dissipation paths for circuits and heat sinks in the coupling region, thereby enhancing the thermal stability and long-term reliability after packaging. This method is simple, yields high output, and is suitable for the mass production of both active and passive optical chips. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A flowchart illustrating a method for fabricating an optical chip using a wafer according to an embodiment of the present invention is shown schematically.

[0021] Figure 2 The front and back surface topography of a wafer according to an embodiment of the present invention are schematically illustrated.

[0022] Figure 3 This schematically illustrates a process flow diagram along the wafer thickness direction of a method for fabricating an optical chip using a wafer according to an embodiment of the present invention.

[0023] Figure 4 The diagram illustrates a predetermined amount of contraction of the top step relative to the bottom step in the direction from the edge of the optical chip toward its interior, according to an embodiment of the present invention.

[0024] Figure 5 The diagram illustrates a structure in which an optical chip fabricated using a wafer fabrication method according to an embodiment of the present invention is coupled and aligned with other optical chips.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1-Optical interface; 2-Wafer; 3-Optical chip; 4-Optical chip width; 5-Deep etching width; 6-Backside etching area; 7-Bottom step; 8-Top step; 9-Thin film circuit; 10-Heat sink; 11-Active optical chip; 12-Optical chip with customizable end face morphology; 13-Passive optical chip;

[0027] a- Deep etching process; b- Backside etching process; c- Wafer thinning process. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0030] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0031] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of the present invention. Throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding the present invention.

[0032] Figure 1 A flowchart illustrating a method for fabricating an optical chip using a wafer according to an embodiment of the present invention is shown schematically. Figure 2 The front and back surface topography of a wafer according to an embodiment of the present invention are schematically illustrated. Figure 3 The diagram illustrates an operation flowchart along the wafer thickness direction of a method for fabricating an optical chip using a wafer according to an embodiment of the present invention.

[0033] like Figures 1 to 3 As shown, in this embodiment of the invention, the method for fabricating an optical chip using a wafer may include steps S110 to S140.

[0034] Step S110: Deep etching process a: On the optical chip protective layer 23 located on the front side of wafer 2, a deep etching window 5 is opened according to the layout of the optical chip width 4 and the optical interface 1 of the optical chip photonic functional layer 22. Based on the deep etching window 5, the optical chip protective layer 23 is etched into the interior of the optical chip substrate 21 along the thickness direction to expose the side of the optical interface 1, and a bottom step 7 is formed at the edge of the optical chip substrate 21.

[0035] Wafer 2 is the substrate material for manufacturing semiconductor devices such as chips. It is typically a thin disk made of ultra-high purity semiconductor materials (such as silicon) and includes: an optical chip substrate 21, an optical chip photonic functional layer 22 located on the optical chip substrate 22, and an optical chip protective layer 23 covering the optical chip photonic functional layer 22. Specifically, the optical chip substrate 21 is the bottom layer of the optical chip 3, serving as the mechanical support for the entire chip and ensuring the structural stability of the entire chip; the optical chip photonic functional layer 22 is a complex system composed of various materials and structures, used to realize all the functions of the optical chip; the optical chip protective layer 23 is one or more thin films that are covered on top of the photonic functional layer 22 after its fabrication, providing protection for the optical chip and improving its reliability.

[0036] For example, the optical chip substrate 21 includes, but is not limited to, silicon-on-insulator.

[0037] For example, the photonic functional layer 22 of the optical chip includes, but is not limited to, a waveguide layer and a metal layer. The waveguide layer material includes, but is not limited to, single-crystal silicon, silicon nitride, and lithium niobate, and the metal layer material includes, but is not limited to, titanium nitride and platinum.

[0038] For example, the material of the optical chip protective layer 23 includes, but is not limited to, silicon oxide.

[0039] A deep etching window 5 aligned with the optical interface 1 is provided on the front side of wafer 2. Specifically, the deep etching window 5 is arranged according to the layout of the optical chip width 4 and the optical interface 1 of the photonic functional layer 22 of the optical chip.

[0040] The optical interface 1 is located within the photonic functional layer 22 of each optical chip 3 and is used to import external light or export internal light from the optical chip 3. In some embodiments, the optical interface 1 includes, but is not limited to, an insulated tapered coupler.

[0041] In some embodiments, the deep etching window 5 is aligned with or adjacent to the optical interface 1, such that the vertical end face of the resulting optical chip 3 is coplanar with the exposed side face of the optical interface 1, or the distance between the vertical end face and the exposed side face of the optical interface 1 is less than a preset threshold. For example, the preset threshold can be set to 2µm.

[0042] By making the vertical end face of the optical chip 3 coplanar or adjacent to the exposed side of the optical interface 1, fast and accurate optical alignment can be achieved during packaging docking, which can significantly improve coupling efficiency. At the same time, the optimized mechanical structure enhances the long-term stability of the package.

[0043] Step S120: Backside etching process b, the wafer 2 that has undergone deep etching process a is flipped, and a backside etching region 6 is formed on the optical chip substrate 21 located on the back side of the wafer 2. Based on the backside etching region 6, the backside etching region 6 is etched from the optical chip substrate 21 to a predetermined position to form a top step 8 at the edge of the optical chip substrate 21, and the top step 8 is made to shrink inward in the horizontal direction relative to the bottom step 7.

[0044] A back-side etching area 6 is provided on the back side of the wafer, which is misaligned with the deep etching window 5.

[0045] In some embodiments, the back etched area 6 adopts a staggered layout, so that each optical chip 3 obtained after slicing has only one back etched area 6, so as to maintain the overall mechanical strength of the wafer 2 while forming the top step 8, and avoid the wafer 2 from breaking before slicing.

[0046] In some embodiments, the photonic functional layer 22 of the optical chip is used as an anti-etching layer, based on the fact that the back-side etching region 6 is etched from the optical chip substrate 21 to a predetermined position within the optical chip substrate 21. Specifically, the back-side etching process b terminates within the optical chip substrate 21 and does not reach the photonic functional layer 22 of the optical chip, thereby ensuring that the geometric parameters of the top step are uniform and controllable while avoiding damage to the photonic devices in the photonic functional layer 22 of the optical chip.

[0047] In some embodiments, both deep etching process a and back etching process b include deep reactive ion etching.

[0048] Step S130: Chip thinning process c, thinning the entire wafer 2, which has undergone back-side etching process b, to a set thickness.

[0049] When optical chip 3 is horizontally coupled end-to-end with other optical chips, strict requirements are placed on the alignment accuracy between the coupled chips and the stability after packaging.

[0050] At the optical alignment level, the optical waveguides between the coupled chips are required to achieve sub-micron level alignment accuracy in the vertical direction. For example, the lateral alignment error must be less than ±0.5µm and the longitudinal waveguide height difference must be less than ±0.2µm to ensure that the optical signal can be transmitted with low loss through optical interface 1.

[0051] At the packaging level, the chip is required to have thickness parameters that match those of the mating chip and the packaging substrate. The total chip thickness is controlled to match the thermal expansion coefficient of the packaging substrate in order to meet the mechanical stability requirements of the packaging structure. In addition, the chip thickness after thinning must also take into account the stress resistance and long-term reliability requirements of subsequent packaging processes.

[0052] In some embodiments, the entire wafer is thinned to a set thickness using a chip thinning process. The set thickness can be determined according to specific application requirements to meet the optical alignment requirements and packaging requirements for end-to-end horizontal coupling with other optical chips.

[0053] In some embodiments, chip thinning process c includes chemical mechanical polishing.

[0054] Step S140: Finally, the thinned wafer is divided along the dicing line to obtain multiple optical chips 3 with exposed sides of the optical interface 1 and stepped end face morphology.

[0055] For example, wafer 2 can be divided by laser scribing or blade cutting. By precisely controlling the cutting depth and position, the end face morphology of each optical chip 3 can be ensured to be complete and consistent.

[0056] In some embodiments, the optical chip 3 may include an active optical chip and a passive optical chip.

[0057] The multiple optical chips 3 obtained through the aforementioned deep etching process a, back etching process b, chip thinning process c, and wafer dicing exhibit a stepped morphology at their end faces. Specifically, this includes a bottom step 7 close to the photonic functional layer 22, and a top step 8 that tapers laterally inward relative to the bottom step 7. This stepped morphology allows the optical interfaces 1 to be exposed coplanarly or adjacently after the wafer is diced into multiple optical chips 3. This enables rapid and precise optical alignment during packaging, significantly improving coupling efficiency, while also enhancing the long-term stability of the package through optimized mechanical structures. Furthermore, this design allows optical signals to be transmitted directly between chips with extremely low loss, and its stepped structure provides a physical reference for precise positioning, facilitating end-to-end horizontal direct coupling during packaging.

[0058] In some embodiments, the deep etching window 5 and the back etching region 6 are independent configurable parameters used to customize the stepped end face morphology of the optical chip 3.

[0059] For example, in applications requiring high-density integration, a compact stepped structure can be formed by reducing the width of the deep etching window 5 and the shrinkage of the back etching area 6, thereby achieving a tight arrangement of multi-chip arrays within a limited space.

[0060] For example, in laser chip coupling scenarios with high heat dissipation requirements, the etching depth of the back etching area 6 can be increased, and the edge of the deep etching window 5 can be adjusted to maintain a certain distance from the optical interface 1, thereby forming a top step 8 with a large heat dissipation area, providing sufficient mounting space for the heat sink.

[0061] By adjusting the width and position of the deep etching window 5, as well as the shrinkage and etching depth of the back etching area 6, precise control of the optimal end face morphology under different application scenarios can be achieved.

[0062] Figure 4 The diagram illustrates a predetermined amount of contraction of the top step relative to the bottom step in the direction from the edge of the optical chip toward its interior, according to an embodiment of the present invention.

[0063] like Figure 4 As shown, the top step 8 formed by the back etching process b has a predetermined shrinkage amount relative to the bottom step 7 formed by the deep etching process a in the direction from the edge of the optical chip 3 toward its interior.

[0064] For example, the back etching area 6 has a lateral etching width greater than the deep etching window 5 on the optical chip 3, and is aligned with the deep etching window 5 at the edge of the optical chip 3, thereby ensuring that the top step 8 has a predetermined shrinkage amount relative to the bottom step 7 in the direction from the edge of the optical chip 3 toward its interior.

[0065] In some embodiments, the back etching process b takes the bottom step 7 as a reference, so that the length and thickness of the top step 8 meet the requirements for end-to-end coupling with other optical chips.

[0066] For example, by using the bottom step 7 as a unified process reference, the thickness of the top step 8 can be configured to the required compensation thickness for the specific waveguide height of the mating chip, thereby ensuring the precise alignment of the optical interface 1 in the vertical direction; at the same time, the shrinkage length of the top step 8 can be set to an appropriate size according to the electrode layout or heat dissipation structure requirements of the mating chip, reserving the necessary space for package interconnection.

[0067] By combining the parameterized settings with the bottom step 7 as a reference with the back-side etching process b implemented uniformly at the wafer level, the end face morphology of all chips maintains highly consistent geometric features during mass production, and the assembly tolerance between different batches of chips is strictly controlled, thereby significantly improving the alignment reproducibility and coupling consistency of multi-chip packages.

[0068] Figure 5 The diagram illustrates a structure in which an optical chip fabricated using a wafer fabrication method according to an embodiment of the present invention is coupled and aligned with other optical chips.

[0069] like Figure 5 As shown, the optical chip 12 with customizable end-face morphology achieves optical interconnection with the active optical chip 11 and the passive optical chip 13 through end-to-end horizontal direct coupling.

[0070] The end face of the customizable optical chip 12 has a stepped morphology, including a bottom step near the photonic functional layer 22 and a top step 8 that tapers laterally into the chip relative to the bottom step 7. This stepped morphology is uniformly formed through wafer-level front and back co-etching and thinning processes, so that the optical interface 1 is exposed coplanarly or adjacently after slicing, which facilitates alignment with the end faces of the active optical chip 11 and the passive optical chip 13.

[0071] Furthermore, the stepped end-face morphology provides a precise geometric alignment basis for multi-chip coupling. Specifically, the configurability of parameters such as the length, thickness, and shrinkage of the bottom step 7 and the top step 8 ensures optical mode matching between the customizable end-face morphology optical chip 12 and the active optical chip 11 and passive optical chip 13 during mating, thereby reducing insertion loss. Simultaneously, the shrinkage design of the top step 8 reserves space in the coupling area, allowing the integration of auxiliary components such as the thin-film circuit 9 and the heat sink 10. The thin-film circuit 9 can be arranged in the stepped area for electrical interconnection or signal transmission; the heat sink 10 directly contacts the chip end face or adjacent area, providing an efficient heat dissipation path for the coupling area.

[0072] By uniformly controlling the geometric parameters of the bottom step 7 and the top step 8, the alignment tolerance between chips is reduced, and the coupling efficiency is more stable and reliable. Furthermore, the step structure provides an optimized layout for thermal management, and the integration of the heat sink 10 enhances the thermal stability of the coupling area, reducing the impact of thermal stress on optical performance, thereby improving long-term reliability after packaging. This embodiment of the invention significantly improves the compatibility and performance of multi-chip packaging through this customized end-face topography design.

[0073] In summary, the method for fabricating optical chips using wafers provided in this invention achieves precise, reproducible, and customizable edge-face step morphology of the optical chip on the wafer through processes such as front-side deep etching, back-side etching, chip thinning, and wafer dicing. This method not only solves the alignment and gap control challenges in end-to-end coupling of heterogeneous chips but also provides physical space for circuit integration and thermal management through optimized structural design, thereby significantly enhancing the structural strength and long-term thermal stability of the package while improving optical coupling efficiency.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing an optical chip using a wafer, the wafer being a wafer (2) with complete photonic functions, comprising an optical chip substrate (21), an optical chip photonic function layer (22) and an optical chip protective layer (23) stacked in sequence; characterized in that, The method comprises: Deep etching process (a): according to the designed optical chip width (4) and the layout of the optical interface (1) of the optical chip photon functional layer (22), a deep etching window (5) is opened on the optical chip protection layer (23) located on the front surface of the wafer (2), and based on the deep etching window (5), the optical chip substrate (21) is etched from the optical chip protection layer (23) along the thickness direction to expose the side surface of the optical interface (1) and form a bottom step (7) at the edge of the optical chip substrate (21); Back etching process (b): the wafer (2) after the deep etching process (a) is flipped, a back etching area (6) is arranged on the optical chip substrate (21) located on the back surface of the wafer (2), and based on the back etching area (6), the optical chip substrate (21) is etched to a predetermined position to form a top step (8) at the edge of the optical chip substrate (21), and the top step (8) is inwardly retracted relative to the bottom step (7) in the horizontal direction; Chip thinning process (c): the wafer (2) after the back etching process (b) is thinned to a set thickness; Finally, the thinned wafer is segmented along the scribe line to obtain a plurality of optical chips (3) exposing the side surface of the optical interface (1) and having a stepped end surface morphology. 2.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The optical chip substrate (21) comprises silicon on insulator; The optical chip photon functional layer (22) comprises a waveguide layer and a metal layer, the waveguide layer material comprises monocrystalline silicon, silicon nitride and lithium niobate, and the metal layer material comprises titanium nitride and platinum; The optical chip protection layer (23) material comprises silicon oxide. 3.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The deep etching process (a) and the back etching process (b) both comprise deep reactive ion etching; The chip thinning process (c) comprises chemical mechanical polishing. 4.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The predetermined position is inside the optical chip substrate (21). 5.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The deep etching window (5) and the back etching area (6) are independent configurable parameters, which are used to customize the stepped end surface morphology of the optical chip (3). 6.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The back etching process (b) takes the bottom step (7) as a reference, so that the length and thickness of the top step (8) meet the needs of end-to-end coupling with other optical chips. 7.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The deep etching window (5) is aligned with or adjacent to the optical interface (1), so that the vertical end surface of the optical chip (3) obtained after segmentation is coplanar with the exposed side surface of the optical interface (1), or the distance between the vertical end surface and the exposed side surface of the optical interface (1) is less than a preset threshold. 8.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The back etching area (6) has a transverse etching width greater than the deep etching window (5) and is aligned with the deep etching window (5) at the edge of the optical chip (3), so as to ensure that the top step (8) has a predetermined shrinkage relative to the bottom step (7) in the direction from the edge of the optical chip (3) to its interior. 9.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The back etching area (6) is arranged in a staggered manner, so that each light chip (3) obtained after segmentation has only one back etching area (6), so as to maintain the overall mechanical strength of the wafer (2) while forming the top step (8), and avoid the wafer (2) from being broken before segmentation.

10. The method for manufacturing an optical chip using a wafer according to claim 1, wherein The light chip (3) comprises an active light chip and a passive light chip. 11.The method for manufacturing an optical chip using a wafer according to claim 1, wherein, The light interface (1) is used for guiding external light or guiding internal light of the light chip (3); The light interface (1) comprises an adiabatic tapered coupler.

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