Mask plate, pattern forming method and preparation method of semiconductor device

Abstract

The invention provides a mask plate, a pattern forming method and a preparation method of a semiconductor device, and belongs to the technical field of semiconductors, the mask plate comprises at least two pattern areas which are arranged at intervals, and gaps between the pattern areas are pervious to light; the pattern area comprises at least one first pattern area and at least one second pattern area, the area of the first pattern area is smaller than that of the second pattern area, the first pattern area is light-proof, the second pattern area comprises at least two unit patterns which are arranged at intervals, the unit patterns are light-proof, and gaps between the unit patterns are light-permeable; the width of the gap between the unit patterns is between the minimum exposure size of the first photoresist and the minimum exposure size of the second photoresist, and the minimum exposure size of the first photoresist is greater than the minimum exposure size of the second photoresist. In the manufacturing process of the active region, the mask plate can be used as a mask plate of two photoetching processes for forming the trench isolation structure, the pattern density of the isolation layer before planarization is reduced, and the isolation layer can be uniformly planarized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a photomask, a pattern forming method, and a method for fabricating semiconductor devices. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is a process that fabricates devices such as bipolar transistors, CMOS (Complementary Metal-Oxide Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor) on the same chip.

[0003] In BCD technology, LDMOS devices feature a multi-finger structure. This multi-finger structure is achieved through improvements in electric field distribution and conduction performance, primarily used to increase the breakdown voltage (BV) of high-voltage devices and reduce the on-resistance per unit area (Ronsp). In this case, the active region area of ​​LDMOS is typically larger, while the active region area of ​​devices such as MV CMOS (medium-voltage CMOS) and LV CMOS (low-voltage CMOS) does not require such a large area. This results in a significant difference in the active region area between LDMOS devices and other MOS devices. During the active region fabrication process, when filling and planarizing the isolation material within the isolation trench, the significant differences in pattern density lead to uneven planarization and substantial process risks. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a photomask, a pattern forming method, and a semiconductor device fabrication method to solve the problem of high process risk in the active region fabrication process in the prior art.

[0005] This application provides a mask template, comprising at least two spaced-apart graphic areas, with the gap between each graphic area being light-transmitting; The pattern area includes at least one first pattern area and at least one second pattern area. The area of ​​the first pattern area is smaller than the area of ​​the second pattern area. The first pattern area is opaque. The second pattern area includes at least two spaced-apart unit patterns. The unit patterns are opaque, but the gaps between the unit patterns are transparent. The width of the gaps between the unit patterns is between the minimum exposure dimensions of the first photoresist and the second photoresist. The minimum exposure dimension of the first photoresist is greater than the minimum exposure dimension of the second photoresist.

[0006] In some embodiments, the side length of the unit pattern and the width of the gap between the pattern areas are greater than the minimum exposure size of the first photoresist.

[0007] In some embodiments, within each of the second graphic regions, at least some of the gaps between the unit graphics have equal widths.

[0008] In some embodiments, the shape of the unit graphic is at least one of a rectangle, an L-shape, a T-shape, and a cross shape.

[0009] This application also provides a pattern forming method for forming a pattern of the second pattern area of ​​the mask template, including: At least two spaced-apart square shapes are randomly generated within the second graphic area; and, The side lengths of at least two sides of at least a portion of the block pattern are increased or decreased to form the unit pattern, until the width of the gap between the unit patterns is between the minimum exposure size of the first photoresist and the second photoresist.

[0010] In some embodiments, the side length of the block graphic is 1 / m of the minimum side length of the second graphic area, where m is 15~25.

[0011] In some embodiments, the number of the block graphics is q, q≤p, where p is the value of 4 / m of the maximum side length of the second graphic area rounded down.

[0012] In some embodiments, after increasing or decreasing the side length of at least two sides of at least a portion of the block graphic, the overlapping or side-length-touching block graphics form a unit graphic.

[0013] In some embodiments, the four block graphics are arranged in a cross shape, with two block graphics in the same row staggered in the row direction, two block graphics in the same column staggered in the column direction, and two adjacent block graphics in the circumferential direction having opposite sides. A unit graphic is added in the gap between the four block graphics.

[0014] This application also provides a method for fabricating a semiconductor device, comprising: A first photoresist layer is formed on a substrate using a first photoresist, and the first photoresist layer is patterned using the photomask. Using the patterned first photoresist layer as a mask, a portion of the substrate is etched to form an isolation trench within the substrate; The patterned first photoresist layer is removed, and an isolation layer is formed, which covers the substrate and fills the isolation trench; A second photoresist layer is formed on the isolation layer using a second photoresist, and the second photoresist layer is patterned using the photomask. Using the patterned second photoresist layer as a mask, a portion of the thickness of the isolation layer is etched; and, Flatten the isolation layer.

[0015] In some embodiments, the surface of the isolation layer is undulated to give the isolation layer protrusions and recesses, a portion of the thickness of the isolation layer is etched, and when etching a portion of the thickness of the isolation layer, etching is performed downward from a portion of the protrusions and all of the recesses of the isolation layer, and after etching a portion of the thickness of the isolation layer, the bottom surface of the recesses is higher than the top surface of the isolation trench; and; Flatten the isolation layer and stop at the bottom surface of the recess.

[0016] In some embodiments, the semiconductor device is a BCD device, which includes an LDMOS transistor and other MOS transistors besides the LDMOS transistor. The isolation trench defines the active regions of the LDMOS transistor and the other MOS transistors, and the area of ​​the active region of the LDMOS transistor is larger than the area of ​​the active regions of the other MOS transistors.

[0017] This application provides a photomask, a pattern forming method, and a method for fabricating a semiconductor device. The photomask includes at least two spaced-apart patterned regions, with the gap between each patterned region being light-transmitting. Each patterned region includes at least one first patterned region and at least one second patterned region. The area of ​​the first patterned region is smaller than the area of ​​the second patterned region, and the first patterned region is opaque. The second patterned region includes at least two spaced-apart unit patterns, which are opaque. The gap between the unit patterns is light-transmitting, and the width of the gap between the unit patterns is between the minimum exposure dimensions of the first photoresist and the second photoresist. The minimum exposure dimension of the first photoresist is greater than the minimum exposure dimension of the second photoresist. An unexpected effect of this application is that, in the active region process, the photomask in this application can serve as the photomask for the two photolithography processes that form the trench isolation structure, and different patterns can be formed in the first photoresist layer and the second photoresist layer, thereby reducing the pattern density of the isolation layer before planarization, enabling the isolation layer to be planarized uniformly, reducing process risks, increasing the process window, and using the same photomask for the two photolithography processes, saving costs, and having strong feasibility without requiring process modifications. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the first mask template.

[0019] Figure 2This is a schematic diagram of the second mask template.

[0020] Figure 3 This is a schematic diagram of a structure in which a first mask layer and a third photoresist layer are sequentially formed on a first substrate.

[0021] Figure 4 This is a schematic diagram of the structure used to pattern the third photoresist layer using the first photomask.

[0022] Figure 5 A schematic diagram of a structure formed by etching a portion of the first mask layer and the first substrate to create a first isolation trench.

[0023] Figure 6 A schematic diagram of a structure for depositing an isolation material on a first substrate to form a first isolation layer.

[0024] Figure 7 A schematic diagram of the structure for forming a fourth photoresist layer on the first isolation layer.

[0025] Figure 8 This is a schematic diagram of the structure used to pattern the fourth photoresist layer using the second photomask.

[0026] Figure 9 This is a schematic diagram of a structure in which a portion of the first isolation layer is etched using the patterned fourth photoresist layer as a mask.

[0027] Figure 10 This is a schematic diagram of the structure after the fourth photoresist layer has been patterned and removed.

[0028] Figure 11 This is a schematic diagram of the structure for planarizing the first isolation layer.

[0029] Figure 12 This is a schematic diagram of the structure of a mask template provided in an embodiment of this application.

[0030] Figure 13 This is a schematic diagram of the structure of a unit graphic provided in an embodiment of this application.

[0031] Figure 14 A flowchart of a graphic forming method provided in an embodiment of this application.

[0032] Figure 15 This is a schematic diagram illustrating the random generation of block graphics within a second graphic area, as provided in an embodiment of this application.

[0033] Figure 16 This is a schematic diagram illustrating how a portion of a block graphic is enlarged to form a unit graphic, according to an embodiment of this application.

[0034] Figure 17 and Figure 18Two schematic diagrams illustrating the addition of a unit graphic within the gap between unit graphics, as provided in one embodiment of this application.

[0035] Figure 19 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0036] Figure 20 This is a schematic diagram of a structure in which a mask layer and a first photoresist layer are formed on a substrate, according to an embodiment of this application.

[0037] Figure 21 This is a schematic diagram of a structure for patterning a first photoresist layer using a photomask, provided as an embodiment of this application.

[0038] Figure 22 This is a schematic diagram of a portion of the depth of the etching mask layer and substrate provided in an embodiment of this application.

[0039] Figure 23 This is a schematic diagram of a structure for removing the first photoresist layer and forming an isolation layer, provided in an embodiment of this application.

[0040] Figure 24 This is a schematic diagram of a structure in which a second photoresist layer is formed on an isolation layer, according to an embodiment of this application.

[0041] Figure 25 This is a schematic diagram of a structure for patterning a second photoresist layer using a photomask, provided as an embodiment of this application.

[0042] Figure 26 This is a schematic diagram of a structure provided in an embodiment of the present application, showing the etching of a partial depth of the isolation layer using a patterned second photoresist layer as a mask.

[0043] Figure 27 This is a schematic diagram of the structure of the second photoresist layer after removing the patterning, provided in an embodiment of this application.

[0044] Figure 28 This is a schematic diagram of the surface structure of the grinding isolation layer provided in an embodiment of this application.

[0045] The attached figures are labeled as follows: 111-First patterned area; 112-Second patterned area; 1121-Unit pattern; 1120-Block pattern; 110-Substrate; 210-Mask layer; 311-First photoresist layer; 410-Isolation trench; AA11-First active area; AA21-Second active area; 510-Isolation layer; 312-Second photoresist layer; 101-Small area patterned area; 102-Large area patterned area; 103-Supplementary patterned area; 100-First substrate; 200-First mask layer; 301-Third photoresist layer; 302-Fourth photoresist layer; 400-First isolation trench; AA1-First active area; AA2-Second active area; 500-First isolation layer. Detailed Implementation

[0046] In the active region fabrication process, to improve the uniformity of the planarization process and reduce process risks when planarizing the isolation material, an additional photolithography and etching process can be added before planarizing the isolation material to reduce the difference in pattern density. That is, two photolithography and etching processes are used to form the trench isolation structure, with different photomasks for each photolithography process.

[0047] Specifically, Figure 1 This is a schematic diagram of the first mask template, as shown below. Figure 1 As shown, the first mask includes at least two spaced-apart patterned areas, with light passing through the gap between the patterned areas. The patterned areas include a small-area patterned area 101 and a large-area patterned area 102. Figure 1 The diagram shows six small-area graphic areas 101 and four large-area graphic areas 102. The area of ​​the small-area graphic areas 101 is smaller than that of the large-area graphic areas 102. Both the small-area graphic areas 101 and the large-area graphic areas 102 are opaque. Figure 2 This is a schematic diagram of the second mask template. Figure 2 The short dashed line in the diagram represents the position of the small-area graphic area 101, and the long dashed line represents the position of the large-area graphic area 102. Figure 2 As shown, the second mask also includes at least one supplementary graphic area 103. The number and position of the supplementary graphic areas 103 correspond one-to-one with the number and position of the large area graphic areas 102. The area of ​​the supplementary graphic areas 103 is smaller than the area of ​​the large area graphic areas 102.

[0048] Figures 3-11 This is a schematic diagram of a trench isolation structure formed using a first mask template and a second mask template.

[0049] like Figure 3 As shown, firstly, a first mask layer 200 and a third photoresist layer 301 are sequentially formed on the first substrate 100. The first mask layer 200 covers the first substrate 100, and the third photoresist layer 301 covers the first mask layer 200.

[0050] like Figure 4As shown, the third photoresist layer 301 is patterned using the first photomask. The position where the third photoresist layer 301 is removed corresponds to the position where the gap between the patterned areas on the first photomask is located, and the position where the third photoresist layer 301 is retained corresponds to the positions where the small area patterned area 101 and the large area patterned area 102 are located.

[0051] like Figure 5 As shown, using the patterned third photoresist layer 301 as a mask, the first mask layer 200 is etched, thereby transferring the pattern on the third photoresist layer 301 onto the first mask layer 200. Then, a portion of the depth of the first substrate 100 is etched to form a first isolation trench 400, used to define the active region within the first substrate 100. After forming the first isolation trench 400, the third photoresist layer 301 can be removed.

[0052] It is understandable that the isolation trench can define at least a small area active region AA1 and a large area active region AA2 within the first substrate 100. The area of ​​the small area active region AA1 is smaller than the area of ​​the large area active region AA2. In this case, the large area active region AA2 can be used as the active region of the LDMOS device, while the small area active region AA1 can be used as the active region of other MOS devices.

[0053] like Figure 6 As shown, an isolation material is deposited on a first substrate 100 to form a first isolation layer 500. The first isolation layer 500 covers the first substrate 100 and fills the first isolation trench 400. The first isolation layer 500 replicates the morphology of the previous layer; therefore, the surface of the first isolation layer 500 is undulating, and it is subsequently necessary to planarize the surface of the first isolation layer 500 while reducing its thickness. Figure 6 As can be seen, the surface of the first isolation layer 500 has protrusions, which are located above the small active area AA1 and the large active area AA2. The large active area AA2 has a larger area, and the area of ​​the protrusion above the large active area AA2 is also larger. This results in a difference in pattern density. If the first isolation layer 500 is directly planarized, it will lead to uneven planarization process and greater process risk.

[0054] Based on this, such as Figure 7 As shown, a fourth photoresist layer 302 is formed on the first isolation layer 500, and the fourth photoresist layer 302 covers the surface of the first isolation layer 500.

[0055] like Figure 8As shown, the fourth photoresist layer 302 is patterned using the second photomask. The location where the fourth photoresist layer 302 is removed corresponds to the location of the supplementary pattern area 103 on the second photomask. That is, the patterned fourth photoresist layer 302 exposes a portion of the first isolation layer 500 above the large-area active region AA2.

[0056] like Figure 9 As shown, using the patterned fourth photoresist layer 302 as a mask, a portion of the depth of the first isolation layer 500 is etched.

[0057] like Figure 10 As shown, the patterned fourth photoresist layer 302 is removed. At this time, since the first isolation layer 500 above the large-area active region AA2 is etched, it is equivalent to turning the large-area protrusions above the large-area active region AA2 into small-area protrusions, making the area of ​​the protrusions on the surface of the first isolation layer 500 more uniform and reducing the difference in pattern density.

[0058] like Figure 11 As shown, the first isolation layer 500 is planarized. At this time, the first isolation layer 500 can be planarized more uniformly, reducing process risks.

[0059] Although the above process can improve the uniformity of the first isolation layer 500 when planarizing, it requires two photolithography and etching processes to form the trench isolation structure, and the two photolithography processes require different photomasks, resulting in higher costs.

[0060] Based on this, this application provides a photomask, a pattern forming method, and a method for fabricating a semiconductor device. The photomask includes at least two spaced-apart patterned regions, with the gap between each patterned region being transparent. Each patterned region includes at least one first patterned region and at least one second patterned region. The area of ​​the first patterned region is smaller than the area of ​​the second patterned region, and the first patterned region is opaque. The second patterned region includes at least two spaced-apart unit patterns, which are opaque, while the gap between the unit patterns is transparent. The width of the gap between the unit patterns is between the minimum exposure dimensions of the first photoresist and the second photoresist, and the minimum exposure dimension of the first photoresist is greater than the minimum exposure dimension of the second photoresist. An unexpected effect of this application is that, in the active region process, the photomask in this application can serve as the photomask for the two photolithography processes that form the trench isolation structure, and different patterns can be formed in the first photoresist layer and the second photoresist layer, thereby reducing the pattern density of the isolation layer before planarization, enabling the isolation layer to be planarized uniformly, reducing process risks, increasing the process window, and using the same photomask for the two photolithography processes, saving costs, and having strong feasibility without requiring process modifications.

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] Figure 12 This is a schematic diagram of the structure of a mask template provided in an embodiment of this application, as shown below. Figure 12 As shown, the photomask includes at least two spaced-apart graphic areas, wherein each graphic area includes at least one first graphic area 111 and at least one second graphic area 112, and the area of ​​the first graphic area 111 is smaller than the area of ​​the second graphic area 112. Figure 12 The diagram shows six first graphic areas 111 and four second graphic areas 112, but the number of first graphic areas 111 and second graphic areas 112 should not be limited thereto. In some embodiments, there can be multiple first graphic areas 111 and multiple second graphic areas 112. Multiple first graphic areas 111 can be grouped together and arranged in an array, and multiple second graphic areas 112 can also be grouped together and arranged in an array.

[0063] Furthermore, the gaps between each graphic area are translucent; that is, the gaps between two adjacent first graphic areas 111, the gaps between two adjacent second graphic areas 112, and the gaps between adjacent first graphic areas 111 and second graphic areas 112 are all translucent. The first graphic areas 111 are opaque, and the second graphic areas 112 include at least two spaced-apart unit graphics 1121, which are also opaque. The gaps between the unit graphics 1121 are translucent. In general, on the photomask, the unit graphics 1121 and the first graphic areas 111 are opaque, while other areas are translucent.

[0064] Figure 13 This is a structural schematic diagram of unit pattern 1121 provided in an embodiment of this application, combined with... Figure 12 and Figure 13As shown, the width d of the gap between the unit patterns 1121 is between the minimum exposure size of the first photoresist and the second photoresist. That is, the width d of the gap between the unit patterns 1121 is greater than the minimum exposure size of the second photoresist and less than the minimum exposure size of the first photoresist. When the first photoresist is exposed using a mask, because the width d of the gap between the unit patterns 1121 is less than the minimum exposure size of the first photoresist, the position of the first photoresist corresponding to the gap d between the unit patterns 1121 cannot be effectively exposed and will not be washed away during development. Therefore, a corresponding effective pattern cannot be formed on the first photoresist. Conversely, when the second photoresist is exposed using a mask, because the width d of the gap between the unit patterns 1121 is greater than the minimum exposure size of the second photoresist, the second photoresist between the gaps d between the unit patterns 1121 can be effectively exposed and can be easily washed away during development. A corresponding effective pattern can be formed on the second photoresist through the gap d between the unit patterns 1121.

[0065] In some embodiments, the unit graphic 1121 is a graphic formed by expanding / shrinking / overlapping the square graphic 1120. Therefore, the shape of the unit graphic 1121 can be at least one of rectangle, L-shape, T-shape and cross shape.

[0066] Furthermore, the side length of the unit pattern 1121 is greater than the minimum exposure size of the first photoresist, and naturally also greater than the minimum exposure size of the second photoresist. This ensures that when the first and second photoresists are exposed using a photomask, each unit pattern 1121 can be effectively exposed, thus forming corresponding effective patterns on both the first and second photoresists. Similarly, the width of the gap between the pattern areas is also greater than the minimum exposure size of the first photoresist, and naturally also greater than the minimum exposure size of the second photoresist. This ensures that when the first photoresist is exposed using a photomask, the gap between the pattern areas can be effectively exposed, thus forming corresponding effective patterns on the first photoresist.

[0067] It should be noted that within each second pattern area 112, at least some of the gaps between the unit patterns 1121 have equal widths. That is to say, the width of the gaps between the unit patterns 1121 can be equal everywhere, or the width of the gaps between the unit patterns 1121 may not be equal everywhere. However, the width of each gap between the unit patterns 1121 must be between the minimum exposure size of the first photoresist and the second photoresist.

[0068] Based on this, this application also provides a graphic forming method for forming the graphic of the second graphic area 112 of the above-mentioned mask template. Figure 14 A flowchart of a graphic forming method provided in an embodiment of this application, such as Figure 14 As shown, the methods for forming the graphic include: Step S100: Randomly generate at least two spaced square shapes 1120 within the second graphic area 112; and, Step S200: Increase or decrease the side length of at least two sides of at least a portion of the block pattern 1120 to form a unit pattern 1121, until the width of the gap between the unit patterns 1121 is between the minimum exposure size of the first photoresist and the second photoresist.

[0069] Figure 15 This is a schematic diagram illustrating the random generation of a block graphic 1120 within a second graphic area 112, as provided in an embodiment of this application. (See diagram below.) Figure 15 As shown, in step S100, at least two spaced square shapes 1120 are randomly generated within the second graphic area 112 using a random number function. The square shapes 1120 are rectangular, and their side length and number can be preset. For example, the side length of the square shape 1120 can be set to 1 / 20 of the minimum side length of the second graphic area 112, and the number of square shapes 1120 can be 16. The random number function will automatically generate 16 square shapes 1120 within the second graphic area 112, each with a side length of 1 / 20 of the minimum side length of the second graphic area 112. The edge of each square shape 1120 will not extend beyond the edge of the second graphic area 112.

[0070] In some embodiments, the side length of the block graphic 1120 can be 1 / m of the minimum side length of the second graphic area 112, where m is 15~25.

[0071] In some embodiments, the number of block graphics 1120 is q, q≤p, where p is the value of 4 / m of the maximum side length of the second graphic area 112 rounded down, that is, 2≤q≤4 / m rounded down. This ensures that the second graphic area 112 can accommodate all the block graphics 1120.

[0072] Next, step S200 is performed to increase or decrease the side length of at least two sides of at least a portion of the block shape 1120 to form a unit shape 1121. Figure 16 This is a schematic diagram illustrating how a portion of the block graphic 1120 is enlarged to form a unit graphic 1121, according to an embodiment of this application. Figure 16 The image shows four square shapes 1120, with the dashed boxes representing the enlarged areas of the corresponding square shape 1120. For example... Figure 16As shown, assuming the gap between the two square patterns 1120 in the first row is too small (less than the minimum exposure size of the second photoresist), the side length of the upper left square pattern 1120 remains unchanged, while the side lengths of the top and bottom sides of the upper right square pattern 1120 are reduced, so that the gap between the two square patterns 1120 in the first row meets the requirement (between the minimum exposure sizes of the first and second photoresists); assuming the gap between the two square patterns 1120 in the second row is too large (greater than the minimum exposure size of the first photoresist), and the gap between the two square patterns 1120 in the first column... The gap between the two square patterns 1120 in the second column and the 20th column is also too large (greater than the minimum exposure size of the first photoresist). In this case, the left and right side lengths and the top side length of the lower left square pattern 1120 can be increased, and the top and bottom side lengths and the left and right side lengths of the lower right square pattern 1120 can be increased, so that the gap width between the two square patterns 1120 in the second row and the gap width between the two square patterns 1120 in the first column and the two square patterns 1120 in the second column both meet the requirements (between the minimum exposure sizes of the first and second photoresists).

[0073] Of course, Figure 16 The method of increasing or decreasing the side length of the four square patterns 1120 to form unit patterns 1121 is not limited to the above-mentioned method. As long as the side length of the square patterns 1120 is changed so that the spacing between the unit patterns 1121 is between the minimum exposure size of the first photoresist and the second photoresist, it is acceptable.

[0074] It should be noted that the unit graphic can be the square graphic 1120 itself (some square graphics 1120 may not have changed side length), or it can be a graphic formed by increasing or decreasing the side length of the square graphic 1120. It can also be a graphic formed by at least two square graphics 1120 that overlap or have their side lengths in contact after the side lengths of at least two sides of the square graphic 1120 have increased or decreased. Therefore, the shape of the unit graphic 1121 can be at least one of rectangle (including square), L-shape, T-shape and cross shape.

[0075] Figure 17 and Figure 18 Two schematic diagrams illustrating the addition of a unit pattern 1121 within the gap between unit patterns 1121, as provided in one embodiment of this application. For example... Figure 17 and Figure 18As shown, in some cases, the four square patterns 1120 may be arranged in a cross shape, with two square patterns 1120 in the same row staggered in the row direction and two square patterns 1120 in the same column staggered in the column direction. Furthermore, adjacent square patterns 1120 in the circumferential direction have opposite sides. In this case, the gap between the four square patterns 1120 is usually relatively large, but it is not suitable to increase the side length of these four square patterns 1120 (the four square patterns 1120 will be combined into a single unit pattern 1121). In this case, the side length of the four square patterns 1120 remains unchanged, and a single unit pattern 1121 can be added within the gap between the four square patterns 1120, so that the width of the gap between any two unit patterns 1121 is within the minimum exposure size of the first photoresist and the second photoresist. In addition, the added unit pattern 1121 can be an isolated pattern (such as...). Figure 17 (As shown in the dashed box in the image), the edges of the added unit graphic 1121 can also contact the edges of other block graphics 1120, thus merging into a single unit graphic 1121 (as shown in the dashed box in the image). Figure 18 (as shown in the dashed box in the image).

[0076] Based on this, this application also provides a method for fabricating a semiconductor device, which may be, for example, a BCD device, which may include an LDMOS transistor with a relatively large active area and other MOS transistors with relatively small active areas. Figure 19 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown below. Figure 19 As shown, the method for fabricating a semiconductor device includes: Step 01: Form a first photoresist layer 311 on the substrate 110 using the first photoresist, and pattern the first photoresist layer 311 using a photomask; Step 02: Using the patterned first photoresist layer 311 as a mask, etch a portion of the depth of the substrate 110 to form an isolation trench 410 within the substrate 110; Step 03: Remove the patterned first photoresist layer 311 and form an isolation layer 510. The isolation layer 510 covers the substrate 110 and fills the isolation trench 410. Step 04: Form a second photoresist layer 312 on the isolation layer 510 using the second photoresist, and pattern the second photoresist layer 312 using a photomask; Step 05: Using the patterned second photoresist layer 312 as a mask, etch a portion of the thickness of the isolation layer 510; and, Step 06: Flatten the isolation layer 510.

[0077] Figures 20-28This is a schematic diagram of the structure corresponding to the corresponding steps of the method for fabricating a semiconductor device provided in an embodiment of this application. Next, it will be discussed in conjunction with... Figures 20-28 The method for fabricating the semiconductor device provided in this application is described in detail.

[0078] like Figure 20 As shown, in step S01, a mask layer 210 is formed on the substrate 110, covering the substrate 110. The material of the mask layer 210 can be silicon oxide or similar materials. Then, a first photoresist is spin-coated onto the mask layer 210 and cured, thereby forming a first photoresist layer 311 on the mask layer 210, covering the mask layer 210. That is, the material of the first photoresist layer 311 is the first photoresist.

[0079] like Figure 21 As shown, a photomask is used to pattern the first photoresist layer 311. Theoretically, the removal of the first photoresist layer 311 should correspond to the light-transmitting areas on the photomask, i.e., the gaps between patterned areas and the gaps between unit patterns 1121. However, since the width of the gaps between unit patterns 1121 is smaller than the minimum exposure size of the first photoresist, i.e., smaller than the minimum exposure size of the first photoresist layer 311, when patterning the first photoresist layer 311, the position of the first photoresist layer 311 corresponding to the gap d between unit patterns 1121 cannot be effectively exposed, thus failing to form a corresponding effective pattern on the first photoresist. The gaps between patterned areas are used to define the position of the isolation trench 410, and their width is usually larger (greater than the minimum exposure size of the first photoresist). Therefore, when patterning the first photoresist layer 311, the position of the first photoresist layer 311 corresponding to the gap between patterned areas can be effectively exposed, thereby forming a corresponding effective pattern on the first photoresist.

[0080] like Figure 22 As shown, in step S02, using the patterned first photoresist layer 311 as a mask, the mask layer 210 is etched to transfer the pattern on the first photoresist layer 311 onto the mask layer 210. Afterwards, a portion of the substrate 110 is etched to form an isolation trench 410 within the substrate 110. The isolation trench 410 is used to define the active region within the substrate 110.

[0081] It is understood that the isolation trench 410 can define at least one first active region AA11 and at least one second active region AA21 within the substrate 110. The area of ​​the first active region AA11 corresponds to the area of ​​the first patterned region 111, and the area of ​​the second active region AA21 corresponds to the area of ​​the second patterned region 112. Since the area of ​​the first patterned region 111 is smaller than the area of ​​the second patterned region 112, the area of ​​the first active region AA11 is also smaller than the area of ​​the second active region AA21. In this case, the second active region AA21 can be used as the active region of the LDMOS transistor, and the first active region AA11 can be used as the active region of other MOS transistors.

[0082] like Figure 23 As shown, in step S03, the first photoresist layer 311 is removed, and an isolation material is deposited on the substrate 110 to form an isolation layer 510. The isolation layer 510 covers the substrate 110 and fills the isolation trench 410. The isolation layer 510 is relatively thick and replicates the morphology of the previous layer; therefore, the surface of the isolation layer 510 has undulations. Subsequently, it is necessary to planarize the surface of the isolation layer 510 and reduce its thickness. Figure 23 As can be seen, the surface undulation of the isolation layer 510 at this time gives the surface of the isolation layer 510 protrusions and depressions. The protrusions are located above the first active region AA11 and the second active region AA21, and the depressions are located above the isolation trench 410. Since the area of ​​the second active region AA21 is larger, the area of ​​the protrusions above the second active region AA21 is also larger. The area of ​​the first active region AA11 is smaller (and usually more dense), and the area of ​​the protrusions above the first active region AA11 is also smaller (and also more dense). This produces a difference in pattern density. If the isolation layer 510 is directly planarized, it will lead to uneven planarization process and greater process risk.

[0083] like Figure 24 As shown, in step S04, a second photoresist is spin-coated onto the isolation layer 510 and then cured, thereby forming a second photoresist layer 312 on the isolation layer 510, which covers the isolation layer 510. That is, the material of the second photoresist layer 312 is the second photoresist.

[0084] like Figure 25As shown, the second photoresist layer 312 is patterned using a photomask. Theoretically, the areas where the second photoresist layer 312 is removed should correspond to the light-transmitting areas on the photomask, i.e., the gaps between patterned areas and the gaps between unit patterns 1121. Since the width of the gaps between unit patterns 1121 is greater than the minimum exposure size of the second photoresist, i.e., greater than the minimum exposure size of the second photoresist layer 312, when patterning the second photoresist layer 312, the positions of the second photoresist layer 312 corresponding to the gaps between patterned areas and the gaps d between unit patterns 1121 can be effectively exposed. Therefore, corresponding effective patterns can be formed on the second photoresist layer 312. At this time, a portion of the isolation layer 510 above the second active region AA21 and above the isolation trench 410 is exposed.

[0085] like Figure 26 As shown, using the patterned second photoresist layer 312 as a mask, a portion of the depth of the isolation layer 510 is etched. It should be noted that the partial depth of etching the isolation layer 510 is actually etched downwards along a portion of the protrusions (specifically the protrusions above the second active region AA21) and the recesses of the isolation layer 510. However, after etching, the bottom surface of the recesses needs to be higher than the top surface of the isolation layer 510.

[0086] like Figure 27 As shown, the patterned second photoresist layer 312 is removed. At this time, since the isolation layer 510 above the second active region AA21 is etched, it is equivalent to breaking down the large area of ​​protrusions above the second active region AA21 into small area protrusions, making the area of ​​the protrusions on the surface of the isolation layer 510 more uniform and reducing the difference in pattern density.

[0087] like Figure 28 As shown, the surface of the isolation layer 510 is ground to planarize the isolation layer 510. The grinding can stop at the bottom surface of the recess. At this time, since the pattern density of the isolation layer 510 is relatively uniform, the isolation layer 510 can be planarized uniformly, reducing process risks.

[0088] In summary, one embodiment of this application provides a photomask, a pattern forming method, and a method for fabricating a semiconductor device. The photomask includes at least two spaced-apart pattern regions, with the gap between each pattern region being light-transmitting. Each pattern region includes at least one first pattern region 111 and at least one second pattern region 112. The area of ​​the first pattern region 111 is smaller than the area of ​​the second pattern region 112, and the first pattern region 111 is opaque. The second pattern region 112 includes at least two spaced-apart unit patterns 1121, which are opaque. The gap between the unit patterns 1121 is light-transmitting, and the width of the gap between the unit patterns 1121 is between the minimum exposure dimensions of the first photoresist and the second photoresist. The minimum exposure dimension of the first photoresist is greater than the minimum exposure dimension of the second photoresist. An unexpected effect of this application is that, in the active region process, the photomask in this application can serve as the photomask for the two photolithography processes that form the trench isolation structure, and different patterns can be formed in the first photoresist layer 311 and the second photoresist layer 312, thereby reducing the pattern density of the isolation layer 510 before planarization, so that the isolation layer 510 can be planarized uniformly, reducing process risks and increasing the process window. At the same time, the two photolithography processes use the same photomask, saving costs and having strong feasibility, without the need to modify the process.

[0089] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0090] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0091] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0092] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A mask plate, characterized by, The patterned mask plate comprises at least two spaced apart patterned areas, and a gap between each of the patterned areas is transparent to light; The patterned areas comprise at least one first patterned area and at least one second patterned area, the first patterned area has an area smaller than that of the second patterned area, the first patterned area is opaque to light, the second patterned area comprises at least two spaced apart unit patterns, the unit patterns are opaque to light, the gap between the unit patterns is transparent to light, and the width of the gap between the unit patterns is between the minimum exposure size of the first photoresist and the minimum exposure size of the second photoresist, the minimum exposure size of the first photoresist is greater than the minimum exposure size of the second photoresist.

2. The mask plate according to claim 1, wherein The side length of the unit pattern and the width of the gap between the patterned areas are greater than the minimum exposure size of the first photoresist.

3. The mask plate according to claim 1, wherein In each of the second patterned areas, the width of at least part of the gap between the unit patterns is equal.

4. The mask plate of claim 1, wherein, The shape of the unit pattern is at least one of a rectangle, an L shape, a T shape, and a cross shape.

5. A pattern forming method for forming a pattern of the second pattern area of the mask blank according to any one of claims 1 to 4, characterized by, The method comprises: Randomly generating at least two spaced apart square patterns in the second patterned area; And, Increasing or decreasing the side length of at least two edges of at least part of the square patterns to form the unit patterns until the width of the gap between the unit patterns is between the minimum exposure size of the first photoresist and the minimum exposure size of the second photoresist.

6. The pattern forming method according to claim 5, wherein The side length of the square pattern is 1 / m of the minimum side length of the second patterned area, and m is 15-25.

7. The pattern forming method according to claim 6, wherein The number of the square patterns is q, and q≤p, p is the value of 4 / m of the maximum side length of the second patterned area rounded down.

8. The pattern forming process according to claim 5, wherein After increasing or decreasing the side length of at least two edges of at least part of the square patterns, the square patterns that overlap or have edge contact form one unit pattern.

9. The pattern forming process according to claim 5, wherein Four of the square patterns are distributed in a cross shape, two of the square patterns in the same row are arranged in a staggered manner in the row direction, two of the square patterns in the same column are arranged in a staggered manner in the column direction, and the edges of the two square patterns adjacent to each other in the circumferential direction have a facing portion, and a unit pattern is added in the gap between the four square patterns.

10. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming a first photoresist layer on a substrate using a first photoresist, and patterning the first photoresist layer using the mask plate according to any one of claims 1-4; etching a part of the depth of the substrate to form an isolation trench in the substrate using the patterned first photoresist layer as a mask; removing the patterned first photoresist layer, and forming an isolation layer covering the substrate and filling the isolation trench; forming a second photoresist layer on the isolation layer using a second photoresist, and patterning the second photoresist layer using the mask plate; etching a part of the thickness of the isolation layer using the patterned second photoresist layer as a mask; and planarizing the isolation layer.

11. The method of producing a semiconductor device according to Claim 10, wherein The isolation layer is etched to have a surface relief, so that the isolation layer has protrusions and recesses, a partial thickness of the isolation layer is etched, when etching the partial thickness of the isolation layer, the partial protrusions and all of the recesses of the isolation layer are etched downward, after etching the partial thickness of the isolation layer, the bottom surface of the recesses is higher than the top surface of the isolation trench; and The isolation layer is planarized and stopped at the bottom surface of the recesses.

12. The method of producing a semiconductor device according to Claim 10 or 11, wherein The semiconductor device is a BCD device, the BCD device includes an LDMOS tube and other MOS tubes except the LDMOS tube, the isolation trench defines active regions of the LDMOS tube and the other MOS tubes, and the area of the active region of the LDMOS tube is greater than the area of the active region of the other MOS tubes.

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