Synchronization method, device, equipment, readable storage medium and program product of instructions

Abstract

The application discloses a synchronization method and device of instructions, equipment, a readable storage medium and a program product. When a target address carried by write permission exception information matches a preset write permission address, an operating system kernel modifies a permission attribute of the target address to have write permission and not have execution permission, a central processing unit writes a target instruction into a data cache; execution permission exception information is acquired; in the case that a target address in the execution permission exception information matches a preset execution permission address, a data cache cleaning instruction is called, a central processing unit is triggered to write a target instruction of the target address into a storage unit, an instruction cache invalidation instruction is called to invalidate the instruction cache; the permission attribute of the target address is modified to not have write permission and have execution permission, and when a user state program system subsequently executes the target instruction of the target address, the user state program can execute valid instructions, the consumption of human resource cost is reduced, and the synchronization efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method, apparatus, device, computer-readable storage medium, and computer program product for synchronizing instructions. Background Technology

[0002] Dynamically modifying code instructions refers to a user-space program updating code instructions during execution. Common application scenarios include self-modifying code instructions and dynamically generated code instructions. Self-modifying code instructions modify code instructions already loaded into storage units during runtime. By rewriting the instruction content, the user-space program can change its execution flow or behavior. Dynamically generated code instructions dynamically generate new code instructions based on specific rules or inputs during runtime, and then compile or interpret them for execution. This capability allows user-space programs to self-adjust, customize behavior, or dynamically extend functionality according to specific needs. Both self-modifying and dynamically generated code instructions involve writing code instructions into storage units with executable permissions during runtime, and then executing the instructions in those storage units.

[0003] However, after a user-mode program rewrites its code instructions, it cannot execute them directly. This is because most modern CPUs have caches, including a data cache (D-cache) and an instruction cache (I-cache). When writing instructions, they are not usually written directly to memory; instead, they are first written to the data cache, and only when the data cache is cleared are they written to memory. Similarly, when executing instructions, they are not fetched directly from memory; instead, they are first fetched from the instruction cache and executed. Only if the corresponding instruction cache is invalid will the instruction be fetched from memory. In many CPU architectures, such as the ARMv7 architecture, the data cache and instruction cache are not directly synchronized. This causes problems for applications with dynamic code modifications: instructions are written to the data cache, and then instructions from the instruction cache are executed, but the actual valid instructions cannot be fetched from the instruction cache.

[0004] In existing technologies, for this situation, users typically need to manually call the cache operation interface to clear the data cache and invalidate the instruction cache before rewriting the instructions into the memory unit so that the user-mode program can execute valid instructions. However, different CPU architectures may require different cache operation interfaces, which means users need to understand the relevant information before calling the cache operation interface to perform the above operations. This not only consumes a lot of human resources but is also inefficient. Summary of the Invention

[0005] This application provides a method, apparatus, device, computer-readable storage medium, and computer program product for synchronizing instructions, which can reduce the consumption of human resources costs and improve synchronization efficiency.

[0006] In a first aspect, embodiments of this application provide a method for synchronizing instructions, applied to an operating system kernel, the method comprising: Get write permission exception information. Write permission exception information is information generated by the central processing unit when a user-mode program writes a target instruction to the target address in the memory area. If the target address carried in the write permission exception message matches the preset write permission address, the permission attribute of the target address is modified to have write permission but no execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address into the data cache. Obtain execution permission exception information. Execution permission exception information is information generated by the central processing unit when a user-mode program executes a target instruction at a target address. If the target address carried in the execution permission exception information matches the preset execution permission address, the data cache cleanup instruction is invoked, triggering the central processing unit to write the target instruction at the target address in the data cache to the storage unit, and the instruction cache invalidation instruction is invoked to invalidate the instruction cache, so that when the user-mode program system executes the target instruction, the central processing unit is triggered to update the original instruction at the target address in the instruction cache to the target instruction. Modify the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0007] In one possible implementation, before obtaining write permission exception information, the method further includes: Receive memory allocation requests for write and execute permissions from user-mode programs; In response to a memory allocation request, allocate a memory area for the user-mode program system; Record the memory area's preset write permission address has write permission, and the preset execute permission address has execute permission; Map the permission attribute of the preset write permission address to "no write permission".

[0008] In one possible implementation, the preset write permission address of the record memory area has write permission, and the preset execute permission address has execute permission, including: The memory pages containing multiple sub-preset write permission addresses in the preset write permission address of the memory area have write permission, and the memory pages containing multiple sub-preset execution permission addresses in the preset execution permission address have execution permission. The capacity of the memory page is the preset capacity. If the target address carried in the write permission exception message matches the preset write permission address, modify the permission attributes of the target address to have write permissions but not execute permissions, including: If the target address carried in the write permission exception message matches the target sub-preset write permission address among multiple sub-preset write permission addresses, the permission attribute of the memory page where the target sub-preset write permission address is located will be modified to have write permission but not execute permission. Modify the target address's permission attributes to have execute permission but no write permission, including: Modify the permission attributes of the memory page containing the target sub-preset write permission address to have no write permission but have execute permission.

[0009] In one possible implementation, after triggering the central processing unit to write the target instruction at the target address in the data cache to the memory unit, the method further includes: The original instruction at the target address in the instruction cache is marked as invalid, so that when the user-mode program system executes the target instruction at the target address, it triggers the central processing unit to fetch the instruction from the memory unit.

[0010] In one possible implementation, the method further includes: Record the frequency of write commands to the target address within a preset time period; If the frequency exceeds a preset threshold, disable the caching property.

[0011] Secondly, embodiments of this application provide a method for synchronizing instructions, applied to a user-mode program system, the method comprising: When a target instruction is written to the target address in the memory area, and the CPU detects a write operation exception, it generates a write permission exception message. The operating system kernel obtains the write permission exception message. If the target address carried in the write permission exception message matches the preset write permission address, it modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area. The CPU writes the target instruction at the target address to the data cache. When the target instruction at the target address is executed, if the CPU detects an execution operation abnormality, it generates an execution permission exception message. The operating system kernel obtains the execution permission exception message. If the target address carried in the execution permission exception message matches the preset execution permission address, it calls the data cache cleanup instruction, triggering the CPU to write the target instruction at the target address in the data cache to the memory unit, and calls the instruction cache invalidation instruction to invalidate the instruction cache. This allows the CPU to update the original instruction in the instruction cache to the target instruction when the user-mode program system executes the target instruction, and to modify the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0012] In one possible implementation, the method further includes, before writing the target instruction to the target address of the memory region: Send a memory request with write and execute permissions to the operating system kernel so that the operating system kernel can respond to the memory request, allocate a memory area for the user-mode program system, record that the preset write permission address of the memory area has write permission, and the preset execute permission address has execute permission, and map the permission attribute of the preset write permission address to not have write permission.

[0013] Thirdly, embodiments of this application provide an instruction synchronization device applied to an operating system kernel, the device comprising: The acquisition module is used to acquire write permission exception information. Write permission exception information is information generated by the central processing unit when the user-mode program system writes the target instruction to the target address in the memory area. The modification module is used to modify the permission attributes of the target address to have write permission but not execute permission when the target address carried in the write permission exception information matches the preset write permission address, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address to the data cache. The acquisition module is also used to acquire execution permission exception information, which is information generated by the central processing unit when a user-mode program executes a target instruction at a target address. The trigger module is used to call the data cache cleanup instruction when the target address carried in the execution permission exception information matches the preset execution permission address. This triggers the central processing unit to write the target instruction at the target address in the data cache to the storage unit and calls the instruction cache invalidation instruction to invalidate the instruction cache. This is so that when the target instruction is executed in the user-mode program system, the central processing unit is triggered to update the original instruction at the target address in the instruction cache to the target instruction. The modification module is also used to change the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0014] Fourthly, embodiments of this application provide an instruction synchronization device applied to a user-mode program system, the device comprising: The write module is used to write target instructions to the target address in the memory area. If the central processing unit detects a write operation abnormality, it generates write permission exception information. The operating system kernel obtains the write permission exception information. If the target address carried in the write permission exception information matches the preset write permission address, it modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write target instructions to the target address in the memory area. The central processing unit writes the target instruction at the target address to the data cache. The execution module is used to execute the target instruction at the target address. When the CPU detects an execution operation abnormality, it generates an execution permission exception message. The operating system kernel obtains the execution permission exception message. If the target address carried in the execution permission exception message matches the preset execution permission address, it calls the data cache cleanup instruction, triggering the CPU to write the target instruction at the target address in the data cache to the storage unit. It also calls the instruction cache invalidation instruction to invalidate the instruction cache. This allows the CPU to update the original instruction in the instruction cache to the target instruction when the user-mode program system executes the target instruction, and to modify the permission attribute of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0015] Fifthly, embodiments of this application provide an electronic device, the device comprising: A processor and a memory storing computer program instructions; a method for synchronizing instructions that implement any of the above when the processor executes the computer program instructions.

[0016] Sixthly, embodiments of this application provide a computer storage medium on which computer program instructions are stored, and a synchronization method for implementing instructions that are executed by a processor when the computer program instructions are executed.

[0017] In a seventh aspect, embodiments of this application provide a computer program product, wherein when the instructions in the computer program product are executed by the processor of an electronic device, a synchronization method enables the electronic device to execute any of the instructions described above.

[0018] The method, apparatus, device, computer-readable storage medium, and computer program product for instruction synchronization in this application include: An operating system kernel acquires write permission exception information, which is information generated by the central processing unit (CPU) when a user-mode program system writes a target instruction to a target address in memory; if the target address carried in the write permission exception information matches a preset write permission address, the permission attribute of the target address is modified to have write permission but no execute permission, so that the user-mode program system continues to write the target instruction to the target address in memory, and the CPU writes the target instruction at the target address to a data cache; An execution permission exception information is acquired, which is information generated by the CPU when the user-mode program system executes the target instruction at the target address; if the target address carried in the execution permission exception information matches a preset execution permission address, a data cache cleanup instruction is invoked, triggering the CPU to write the target instruction at the target address in the data cache to a storage unit, and an instruction to invalidate the instruction cache is invoked, invalidating the instruction cache, so that when the user-mode program system executes the target instruction, the CPU is triggered to update the original instruction at the target address in the instruction cache to the target instruction; the permission attribute of the target address is modified to have no write permission but have execute permission, so that the user-mode program system continues to execute the target instruction at the target address. This involves dynamically modifying the write and execute permissions of the target address in the memory area through the operating system kernel, synchronizing the instructions written in the data cache to the storage unit and instruction cache, so that user-mode programs can execute valid instructions without the user having to manually call the cache operation interface, thereby reducing the consumption of human resources and improving synchronization efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a method for synchronizing instructions according to an embodiment of this application; Figure 2 This is a flowchart illustrating a method for synchronizing instructions provided in another embodiment of this application; Figure 3 This is a flowchart illustrating a method for synchronizing instructions provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of a synchronization device for instructions applied to the operating system kernel, provided in another embodiment of this application; Figure 5 This is a schematic diagram of the structure of a synchronization device for instructions applied to a user-mode program system provided in another embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0021] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0022] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0023] Dynamically modifying code instructions refers to a user-space program updating code instructions during execution. Common application scenarios include self-modifying code instructions and dynamically generated code instructions. Self-modifying code instructions modify code instructions already loaded into memory during runtime. By rewriting the instruction content, the user-space program can change its execution flow or behavior. Dynamically generated code instructions dynamically generate new code instructions based on specific rules or input during runtime, and then compile or interpret them for execution. This capability allows user-space programs to self-adjust, customize behavior, or dynamically extend functionality according to specific needs. Both self-modifying and dynamically generated code instructions involve writing code instructions into memory locations with executable permissions during runtime, and then executing the instructions in those memory locations. For example, this might involve writing and executing operations on a specific memory block, potentially requiring repeated modification and execution of code instructions.

[0024] However, after a user-mode program rewrites its code instructions, it cannot execute them directly. This is because most modern CPUs have caches, including a data cache (D-cache) and an instruction cache (I-cache). When writing instructions, they are not usually written directly to memory; instead, they are first written to the data cache, and only when the data cache is cleared are they written to memory. Similarly, when executing instructions, they are not fetched directly from memory; instead, they are first fetched from the instruction cache and executed. Only if the corresponding instruction cache is invalid will the instruction be fetched from memory. In many CPU architectures, such as the ARMv7 architecture, the data cache and instruction cache are not directly synchronized. This causes problems for applications with dynamic code modifications: instructions are written to the data cache, and then instructions from the instruction cache are executed, but the actual valid instructions cannot be fetched from the instruction cache.

[0025] In existing technologies, for this situation, users typically need to manually call the cache operation interface to clear the data cache, invalidate the instruction cache, and then rewrite the instructions into the memory unit, or call other specific interfaces to trigger instruction synchronization before the user-space program can execute valid instructions. However, different CPU architectures may require different cache operation interfaces, which means users need to understand the relevant information before calling the cache operation interface to perform the above operations. This not only consumes a lot of human resources but is also inefficient.

[0026] It's important to note that, taking the Linux operating system as an example, Linux provides several interfaces for users to call when dynamically modifying code in user-space programs. For instance, for the Central Processing Unit (CPU) of Advanced RISC Machines (ARM) architecture, a cache clearing function interface is provided. After modifying instructions, users need to manually call the cache clearing function interface to clear the specified data cache and invalidate the specified instruction cache before jumping to the specified address to execute code instructions. However, the cache clearing function interface (clear_cache) is not a universal standard C library interface. This interface is implemented internally by the gcc compiler, so it depends on the compiler; there is no standardized interface, and the interface may differ across different architectures or platforms. For example, some architectures or platforms may use the cacheflush interface, and its parameters and semantics may differ.

[0027] To address the problems of existing technologies, embodiments of this application provide a method, apparatus, device, computer-readable storage medium, and computer program product for instruction synchronization. Embodiments of this application dynamically modify the write and execute permissions of the target address in the memory region through the operating system kernel, synchronizing instructions written in the data cache to the storage unit and the instruction cache. This allows user-mode programs to execute valid instructions without requiring users to manually call the cache operation interface, thereby reducing the consumption of human resources and improving synchronization efficiency.

[0028] The method for synchronizing instructions provided in the embodiments of this application will be described in detail below.

[0029] like Figure 1 As shown, the instruction synchronization method provided in this application embodiment includes the following steps S110 to S170.

[0030] S110, The user-mode program system writes the target instruction to the target address in the memory area.

[0031] In some embodiments, the user-mode program system is a program system running in user-mode. Based on the actual needs of the program, the user-mode program system writes the generated target instructions byte-by-byte sequentially into the target address of the allocated memory area via a memory write interface. The target instructions are valid code instructions.

[0032] It should be noted that before the user-mode program system writes the target instruction to the target address in the memory area, the operating system kernel has already allocated a memory area for the user-mode program system, but the target address of the user-mode program system has no write permission.

[0033] S120. The operating system kernel obtains write permission exception information. The write permission exception information is the information generated by the central processing unit when the user-mode program system writes the target instruction to the target address in the memory area.

[0034] In some embodiments, the target address of the user-mode program system has no write permission. When the user-mode program system writes a target instruction to the target address in the memory area, the central processing unit detects the write operation and verifies whether the permission attributes include write permission. However, if the target address of the user-mode program system has no write permission, a write permission exception will be triggered, generating write permission exception information.

[0035] In some embodiments, the operating system kernel obtains write permission exception information through the central processing unit. Upon obtaining write permission exception information, the operating system kernel enters the write permission exception handling process.

[0036] S130. If the target address carried in the write permission exception information matches the preset write permission address, the operating system kernel modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address into the data cache.

[0037] In some embodiments, the operating system kernel records a preset write-permission address, which is a virtual address. During the write permission exception handling process, the operating system kernel matches the target address carried in the write permission exception message with the preset write permission address. If the target address matches, the operating system kernel modifies the permission attributes of the target address to have write permission but not execute permission, allowing the user-mode program system to continue writing target instructions to the target address in the memory area.

[0038] Modifying the permission attributes of the target address refers to remapping the abnormal virtual address (i.e., the target address) with the physical address. At this time, the mapping will have write permissions but no execute permissions.

[0039] In some embodiments, after the operating system kernel modifies the permission attributes of the target address to have write permissions but not execute permissions, it can return to the target address that previously triggered the write permission exception in the user-mode program system and continue the write operation. Since the user-mode program system now has write permissions for the target address, it can write data normally. While the user-mode program system continues to write the target instruction to the target address in the memory area, the central processing unit writes the target instruction at the target address to the data cache.

[0040] S140, User-mode program system executes the target instruction at the target address.

[0041] In some embodiments, when a user-mode program system needs to execute a target instruction, it executes the target instruction at the target address in the instruction cache. It should be noted that when the user-mode program system writes the target instruction to the target address in memory, the operating system kernel modifies the permission attributes of the target address to have write permissions but not execute permissions. Therefore, the CPU will detect an anomaly when execution is triggered.

[0042] S150, The operating system kernel obtains execution permission exception information. Execution permission exception information is information generated by the central processing unit when a user-mode program executes a target instruction at a target address.

[0043] In some embodiments, the execution permission exception information is generated by the CPU when the user-mode program system executes the target instruction at the target address. When the user-mode program system executes the target instruction written to the target address, the CPU detects the execution operation of the user-mode program system and verifies whether the permission attributes include execution permission. However, if the permission attribute of the target address of the user-mode program system is not execution permission, an execution permission exception is triggered, generating execution permission exception information.

[0044] In some embodiments, the operating system kernel obtains execution permission exception information through the central processing unit. Upon obtaining this information, the operating system kernel enters the execution permission exception handling process.

[0045] S160. When the target address carried in the execution permission exception information matches the preset execution permission address, the operating system kernel calls the data cache cleanup instruction, which triggers the central processing unit to write the target instruction at the target address in the data cache to the memory unit, and calls the instruction cache invalidation instruction to invalidate the instruction cache, so that when the user-mode program system executes the target instruction, it triggers the central processing unit to update the original instruction at the target address in the instruction cache to the target instruction.

[0046] In some embodiments, the operating system kernel records a preset execution permission address, which is a virtual address. During the execution permission exception handling process, the operating system kernel matches the target address carried in the execution permission exception information with the preset execution permission address. If the target address matches, a data cache cleanup instruction is invoked, triggering the central processing unit to write the target instruction at the target address in the data cache to the storage unit.

[0047] In some embodiments, the storage unit includes a synchronization point storage unit. When a synchronization point storage unit is present, the target instruction at the target address in the data cache is written to the synchronization point storage unit. Here, the synchronization point storage unit can be understood as a second-level cache, while the data cache and instruction cache are first-level caches.

[0048] In some embodiments, the storage unit includes memory. In the absence of a second-level cache, the target instruction at the target address in the data cache is written into memory.

[0049] In some embodiments, during the execution permission exception handling process, the operating system kernel invokes an instruction cache invalidation instruction, thereby invalidating the instruction cache. Since the user-mode program system needs to execute the target instruction, the central processing unit is triggered to update the original instruction at the target address in the instruction cache with the target instruction, based on the target instruction already written to the target address in the memory unit.

[0050] S170, The operating system kernel modifies the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0051] In some embodiments, the operating system kernel records a preset execution permission address, which is a virtual address. During the execution permission exception handling process, the operating system kernel matches the target address carried in the execution permission exception information with the preset execution permission address. If the target address matches, the operating system kernel modifies the permission attributes of the target address to have no write permission but have execute permission, allowing the user-mode program system to continue executing the target instruction at the target address.

[0052] Modifying the permission attributes of the target address refers to remapping the abnormal virtual address (i.e., the target address) with the physical address. At this time, the mapping is no write permission, but execute permission is granted.

[0053] In some embodiments, after the operating system kernel modifies the permission attributes of the target address to have execute permission but no write permission, it returns to the target address that previously triggered the execution permission exception in the user-mode program system and continues the execution operation. Since execute permission is now available, the user-mode program system can execute the target instructions normally.

[0054] It should be noted that the operating system kernel modifies the permission attributes of the target address to have execute permission but no write permission. This is so that when the user-mode program writes instructions to the target address in memory again after the target instructions are modified, a write operation exception is triggered, thereby achieving synchronization of the modified instructions.

[0055] In some embodiments, if the user-mode program system repeatedly modifies and executes instructions, the preceding steps S110~S170 will be repeatedly triggered. Specifically: the first write operation after execution will trigger a write exception, at which point write permissions will be granted and execution permissions will be disabled; the first execution operation after write will trigger an execution exception, at which point execution permissions will be granted and write permissions will be disabled. This operation is similar to a ping-pong game, except that during the ping-pong process, it is also necessary to clear the data cache and invalidate the instruction cache each time execution permissions are granted, updating the original instruction at the target address in the instruction cache to the target instruction. In this way, without the user-mode program system needing to explicitly call the cache operation interface, the operating system automatically detects write and execution operations, invalidates the instruction cache and synchronizes instructions at appropriate times, ensuring that the user-mode program system can obtain the latest instructions and execute them correctly each time it modifies them.

[0056] This application embodiment dynamically modifies the write and execute permissions of the target address in the memory area through the operating system kernel, and synchronizes the instructions written in the data cache to the storage unit and the instruction cache, so that user-mode programs can execute valid instructions without the user having to manually call the cache operation interface, thereby reducing the consumption of human resources costs and improving synchronization efficiency.

[0057] In some embodiments, such as Figure 2 As shown, before S110 above, the method may also include S101 to S104.

[0058] S101, The user-mode program system sends a memory request for write and execute permissions to the operating system kernel.

[0059] In some embodiments, if a user-mode program system wants to use the dynamic code modification function, it needs to request memory with write and execute permissions. That is, the user-mode program system can send a memory request request with write and execute permissions to the operating system kernel through the standard mmap interface.

[0060] Having write permissions is for writing instructions; having execute permissions is for executing newly written instructions.

[0061] S102. The operating system kernel responds to the memory request and allocates a memory area for the user-mode program system.

[0062] In some embodiments, after receiving a memory request from a user-mode program, the operating system kernel allocates a memory region for the user-mode program in response to the request. Memory allocation includes allocating virtual memory and physical memory, and mapping virtual memory to physical memory.

[0063] S103, The operating system kernel records that the preset write permission address of the memory area has write permission, and the preset execute permission address has execute permission.

[0064] In some embodiments, the operating system kernel records the permissions of the requested virtual memory area, including that the memory area has write permissions at a preset write permission address and execute permissions at a preset execute permission address.

[0065] S104. The operating system kernel maps the permission attribute of the preset write permission address to "not having write permission".

[0066] In some embodiments, when mapping virtual memory to physical memory, the operating system kernel maps the permission attribute of a preset write permission address to not having write permission.

[0067] In this embodiment of the application, write permissions are disabled during the memory area allocation stage, which allows the operating system to detect user write operations in subsequent stages and execute the corresponding exception handling process when appropriate.

[0068] In some embodiments, S103 may specifically include: The operating system kernel records that the memory pages containing multiple sub-preset write permission addresses in the preset write permission address range have write permissions, and the memory pages containing multiple sub-preset execution permission addresses in the preset execution permission address range have execution permissions. The capacity of the memory page is the preset capacity. Specifically, S130 mentioned above may include: If the target address carried in the write permission exception message matches the target sub-preset write permission address among multiple sub-preset write permission addresses, the operating system kernel will modify the permission attributes of the memory page where the target sub-preset write permission address is located to have write permission but not execute permission. Specifically, S170 mentioned above may include: The operating system kernel modifies the permission attributes of the memory page located at the target's default write permission address to have execute permission but no write permission.

[0069] In this embodiment, each time mapping permissions are modified, virtual memory and physical memory are typically operated on a page-by-page basis. This means modifying the permissions of the memory page containing the address that triggered the exception, i.e., the target address. The memory page size is a preset size, for example, 4KB.

[0070] It is understandable that modifying the permission attributes of the memory page where the target sub-preset write permission address is located to have write permission but no execute permission or no write permission but execute permission means remapping the memory page where the virtual address is located to the memory page where the physical address is located.

[0071] In some embodiments, when an execution permission exception occurs, during cache-related operations, memory barrier instructions (such as data synchronization barrier instructions and instruction synchronization barrier instructions) can also be executed to force the CPU to strictly follow the execution order of memory operations, ensure the consistency of cached data, and prevent abnormal remnants and logical errors caused by instruction reordering.

[0072] In this embodiment of the application, when recording write permissions and execution permissions and handling operational anomalies, the recording and processing are performed on a page-by-page basis. This avoids the large consumption of storage and computing resources caused by recording and processing on a byte-by-byte basis, thus saving resource costs.

[0073] In some embodiments, after S160 described above, the method may further include: The operating system kernel marks the original instruction at the target address in the instruction cache as invalid, so that when the user-mode program executes the target instruction at the target address, it triggers the central processing unit to fetch the instruction from the memory unit.

[0074] In this embodiment, when the user-mode program system executes the target instruction at the target address, the central processing unit fetches the instruction from the memory unit.

[0075] This embodiment of the application marks the original instruction at the target address in the instruction cache as invalid. This prevents the user-mode program from retrieving the instruction from the cache when it needs to execute the target instruction. Instead, it fetches the instruction from the corresponding memory location. Since the data in the memory location has been updated to the latest instruction, the user-mode program can execute the newly written instruction normally. This triggers the central processing unit to fetch the instruction from the corresponding memory location, reducing instruction cache synchronization steps and saving resources.

[0076] In some embodiments, such as Figure 3 As shown, the method also includes steps S210 to S220.

[0077] S210: The operating system kernel records the frequency of write instructions to the target address within a preset time period.

[0078] In some embodiments, the operating system kernel includes a monitoring unit for write and execution operations. The operating system kernel uses the monitoring unit to record the frequency of write instructions to a target address within a preset time period.

[0079] In some embodiments, the operating system kernel may also use a monitoring unit to record the frequency of instructions executed at a target address within a preset time period.

[0080] S220: When the frequency exceeds a preset threshold, the operating system kernel disables the cache attribute.

[0081] In some embodiments, if the frequency exceeds a preset threshold, it can be considered that the user is frequently modifying instructions at the target address, and the operating system kernel disables the caching attribute of that target address. Disabling the caching attribute of the target address refers to disabling the caching attribute in the mapping relationship between virtual and physical addresses; for example, setting the cache attribute to non-cache.

[0082] In some embodiments, the operating system kernel records the frequency of write instructions to the memory page containing the target address within a preset time period. If the frequency exceeds a preset threshold, the cache attribute of the memory page containing the target address is disabled.

[0083] In this embodiment of the application, if the user-mode program system modifies its code very frequently, using a cache will not significantly improve system performance. In fact, it may even negatively impact performance due to the frequent maintenance of cache correctness. In this case, the caching strategy is automatically adjusted by disabling the cache attribute. With this setting, writing instructions to or reading instructions from the target address will not go through the cache. After modifying the instructions, the new instructions can be executed directly and normally, improving the efficiency of writing and executing new instructions.

[0084] In this embodiment of the application, for scenarios involving dynamic code modification, a general automatic instruction synchronization function is implemented in the operating system kernel. This eliminates the need for operating system developers to rely on specific compiler features, thereby improving the flexibility of operating system development. It also eliminates the need for operating system users to worry about when to call interfaces and which interfaces to call, thereby improving system usability. Furthermore, it ensures that instructions are synchronized only when necessary, i.e., by using delayed refresh, and only operating on the cache of necessary areas when actually accessed. This reduces unnecessary operations, thereby improving the efficiency of the operating system and reducing jitter.

[0085] This application's embodiments are applicable to users writing valid instructions and executing instructions on allocated memory; it is suitable for both single writes and executions, as well as repeated writes and executions. After handling write permission exceptions, the user-mode program system can perform write operations normally on the target address; after handling execution permission exceptions, the user-mode program system can perform execution operations normally on the target address. Throughout the process, there is no need for the user to explicitly call the cache operation interface or indirectly trigger the instruction synchronization interface. The operating system kernel automatically synchronizes instructions, and may even disable cache attributes, eliminating the need for cache maintenance and improving synchronization efficiency.

[0086] Based on the instruction synchronization method provided in the above embodiments, this application also provides specific implementations of an instruction synchronization device. Please refer to the following embodiments.

[0087] See Figure 4 The instruction synchronization device 300 provided in this application embodiment is applied to the operating system kernel, and the device 300 includes: The acquisition module 310 is used to acquire write permission exception information. The write permission exception information is the information generated by the central processing unit when the user-mode program system detects whether the execution time of the target instruction has been reached and obtains the detection result. If the detection result is that the execution time of the target instruction has been reached, the central processing unit executes the target instruction at the target address. Modification module 320 is used to modify the permission attribute of the target address to have write permission but not execute permission when the target address carried in the write permission exception information matches the preset write permission address, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address to the data cache. The acquisition module 310 is also used to acquire execution permission exception information, which is information generated by the central processing unit when the user-mode program system executes the target instruction at the target address; Trigger module 330 is used to call a data cache cleanup instruction when the target address carried in the execution permission exception information matches the preset execution permission address, triggering the central processing unit to write the target instruction at the target address in the data cache to the storage unit, and call an instruction to invalidate the instruction cache, so that when the target instruction is executed in the user-mode program system, the central processing unit is triggered to update the original instruction at the target address in the instruction cache to the target instruction. Modification module 320 is also used to modify the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0088] In some embodiments, the device 300 may further include: The receiving module is used to receive memory allocation requests for write and execute permissions sent by the user-mode program system before obtaining write permission exception information; The response module is used to respond to memory allocation requests and allocate memory areas for user-mode programs. The recording module is used to record whether a preset write-permission address in the memory area has write permission and whether a preset execute-permission address has execute permission. The mapping module is used to map the permission attributes of a preset write permission address to a location that does not have write permission.

[0089] In some embodiments, the recording module can specifically be used for: The memory pages containing multiple sub-preset write permission addresses in the preset write permission address of the memory area have write permission, and the memory pages containing multiple sub-preset execution permission addresses in the preset execution permission address have execution permission. The capacity of the memory page is the preset capacity. Modifying module 320 can specifically be used for: If the target address carried in the write permission exception message matches the target sub-preset write permission address among multiple sub-preset write permission addresses, the permission attribute of the memory page where the target sub-preset write permission address is located will be modified to have write permission but not execute permission. Modification module 320 can be used specifically for: Modify the permission attributes of the memory page containing the target sub-preset write permission address to have no write permission but have execute permission.

[0090] In some embodiments, the device 300 may further include: The marking module is used to mark the original instruction at the target address in the instruction cache as invalid after the central processing unit writes the target instruction at the target address in the data cache to the memory unit, so that when the user-mode program system executes the target instruction at the target address, it triggers the central processing unit to fetch the instruction from the memory unit.

[0091] In some embodiments, the device 300 may further include: The recording module is used to record the frequency of write commands to the target address within a preset time period; The shutdown module is used to disable cache attributes when the frequency exceeds a preset threshold.

[0092] See Figure 5 The instruction synchronization device 400 provided in this application embodiment is applied to a user-mode program system. The device 400 includes: The write module 410 is used to write the target instruction to the target address in the memory area. When the central processing unit detects an abnormal write operation, it generates write permission exception information. The operating system kernel obtains the write permission exception information. If the target address carried in the write permission exception information matches the preset write permission address, it modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area. The central processing unit writes the target instruction at the target address to the data cache. The execution module 420 is used to execute the target instruction at the target address. When the central processing unit detects an execution operation abnormality, it generates execution permission exception information. The operating system kernel obtains the execution permission exception information. If the target address carried in the execution permission exception information matches the preset execution permission address, it calls the data cache cleanup instruction, triggering the central processing unit to write the target instruction at the target address in the data cache to the storage unit, and calls the instruction cache invalidation instruction to invalidate the instruction cache. This allows the central processing unit to update the original instruction in the instruction cache to the target instruction when the user-mode program system executes the target instruction, and to modify the permission attribute of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

[0093] In some embodiments, the device 400 may further include: The sending module is used to send a memory request for write permission and execute permission to the operating system kernel before writing the target instruction to the target address in the memory area. The operating system kernel responds to the memory request, allocates a memory area for the user-mode program system, records that the preset write permission address in the memory area has write permission, and the preset execute permission address has execute permission, and modifies the permission attribute of the preset write permission address to not have write permission.

[0094] Each module of the instruction synchronization device provided in this application embodiment can realize the functions of each step of the instruction synchronization method provided above, and can achieve its corresponding technical effects. For the sake of brevity, it will not be described in detail here.

[0095] Based on the same inventive concept, embodiments of this application also provide an electronic device.

[0096] Figure 6 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0097] An electronic device may include a processor 501 and a memory 502 storing computer program instructions.

[0098] Specifically, the processor 501 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0099] Memory 502 may include mass storage for data or instructions. For example, and not limitingly, memory 502 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 502 may include removable or non-removable (or fixed) media. Where appropriate, memory 502 may be internal or external to an electronic device. In a particular embodiment, memory 502 is a non-volatile solid-state memory.

[0100] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.

[0101] The processor 501 implements any of the instruction synchronization methods described in the above embodiments by reading and executing computer program instructions stored in the memory 502.

[0102] In one example, the electronic device may also include a communication interface 503 and a bus 510. Wherein, as... Figure 6 As shown, the processor 501, memory 502, and communication interface 503 are connected through bus 510 and complete communication with each other.

[0103] The communication interface 503 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0104] Bus 510 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Linear Predictive Coding (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (Peripheral Component Interconnect-X, PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VESA Local Bus, VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 510 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application contemplates any suitable bus or interconnection. The electronic device can execute the synchronization method of instructions in the embodiments of this invention, thereby implementing the above-described synchronization method of instructions.

[0105] Furthermore, in conjunction with the instruction synchronization methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the instruction synchronization methods in the above embodiments.

[0106] This application also provides a computer program product in which the instructions, when executed by a processor of an electronic device, cause the electronic device to perform various processes implementing any of the above-described instructions in the synchronization method embodiment.

[0107] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0108] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0109] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0110] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0111] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method of synchronizing instructions, comprising: Applied to the operating system kernel, the method includes: Obtain write permission exception information, which is information generated by the central processing unit when the user-mode program system writes a target instruction to the target address in the memory area; If the target address carried in the write permission exception information matches the preset write permission address, the permission attribute of the target address is modified to have write permission but no execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address into the data cache. Obtain execution permission exception information, wherein the execution permission exception information is information generated by the central processing unit when the user-mode program system executes the target instruction at the target address; If the target address carried in the execution permission exception information matches the preset execution permission address, a data cache cleanup instruction is invoked to trigger the central processing unit to write the target instruction at the target address in the data cache to the storage unit, and an instruction to invalidate the instruction cache is invoked to invalidate the instruction cache, so that when the user-mode program system executes the target instruction, the central processing unit is triggered to update the original instruction at the target address in the instruction cache to the target instruction. The permission attributes of the target address are modified to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

2. The method of claim 1, wherein, Before obtaining write permission exception information, the method further includes: Receive memory request requests for write and execute permissions sent by the user-mode program system; In response to the memory request, a memory area is allocated to the user-mode program system; Record that the preset write permission address of the memory area has write permission, and the preset execute permission address has execute permission; The permission attribute of the preset write permission address is mapped to "no write permission".

3. The method of claim 2, wherein, The record that the preset write permission address of the memory area has write permission and the preset execute permission address has execute permission includes: The memory page containing multiple sub-preset write permission addresses among the preset write permission addresses of the memory area has write permission, and the memory page containing multiple sub-preset execution permission addresses among the preset execution permission addresses has execution permission, wherein the capacity of the memory page is a preset capacity; When the target address carried in the write permission exception information matches a preset write permission address, modifying the permission attribute of the target address to have write permission but not execute permission includes: If the target address carried in the write permission exception information matches the target sub-preset write permission address among the plurality of sub-preset write permission addresses, the permission attribute of the memory page where the target sub-preset write permission address is located is modified to have write permission but not execute permission; The step of modifying the permission attributes of the target address to have execute permission but no write permission includes: Modify the permission attributes of the memory page where the target sub-preset write permission address is located to have no write permission but have execute permission.

4. The method of claim 1, wherein, After triggering the central processing unit to write the target instruction at the target address in the data cache to the memory unit, the method further includes: The original instruction at the target address in the instruction cache is marked as invalid, so that when the user-mode program system executes the target instruction at the target address, it triggers the central processing unit to fetch the instruction from the memory unit.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Record the frequency of write commands to the target address within a preset time period; If the frequency exceeds a preset threshold, the caching attribute is turned off.

6. A method of synchronizing instructions, the method comprising: Applied to user-mode program systems, the method includes: When a target instruction is written to a target address in the memory area, and the central processing unit detects a write operation abnormality, it generates write permission abnormality information. The operating system kernel obtains the write permission abnormality information. If the target address carried in the write permission abnormality information matches a preset write permission address, it modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write the target instruction to the target address in the memory area. The central processing unit writes the target instruction at the target address to the data cache. When the target instruction at the target address is executed, if the CPU detects an execution operation abnormality, it generates execution permission exception information. The operating system kernel obtains the execution permission exception information. If the target address carried in the execution permission exception information matches a preset execution permission address, it calls a data cache cleanup instruction, triggering the CPU to write the target instruction at the target address in the data cache to a storage unit. It also calls an instruction to invalidate the instruction cache, so that when the user-mode program system executes the target instruction, it triggers the CPU to update the original instruction in the instruction cache to the target instruction, and modifies the permission attribute of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

7. The method of claim 6, wherein, Before writing the target instruction to the target address in the memory region, the method further includes: A memory request for write permission and execute permission is sent to the operating system kernel, so that the operating system kernel can respond to the memory request, allocate a memory area for the user-mode program system, record that the preset write permission address of the memory area has write permission, and the preset execute permission address has execute permission, and map the permission attribute of the preset write permission address to not have write permission.

8. An apparatus for synchronizing instructions, comprising: The device is applied to an operating system kernel and includes: The acquisition module is used to acquire write permission exception information, which is the information generated by the central processing unit when the user-mode program system writes the target instruction to the target address in the memory area. The modification module is used to modify the permission attribute of the target address to have write permission but not execute permission when the target address carried in the write permission exception information matches the preset write permission address, so that the user-mode program system can continue to write the target instruction to the target address in the memory area, and the central processing unit writes the target instruction at the target address to the data cache. The acquisition module is also used to acquire execution permission exception information, which is information generated by the central processing unit when the user-mode program system executes the target instruction at the target address; The triggering module is used to, when the target address carried in the execution permission exception information matches the preset execution permission address, call the data cache cleanup instruction to trigger the central processing unit to write the target instruction at the target address in the data cache to the storage unit, and call the instruction cache invalidation instruction to invalidate the instruction cache, so that when the user-mode program system executes the target instruction, the central processing unit is triggered to update the original instruction at the target address in the instruction cache to the target instruction. The modification module is further configured to modify the permission attributes of the target address to have no write permission but have execute permission, so that the user-mode program system can continue to execute the target instruction at the target address.

9. An apparatus for synchronizing instructions, comprising: The device, applied to a user-mode program system, includes: The write module is used to write target instructions to the target address in the memory area. When the central processing unit detects an abnormal write operation, it generates write permission exception information. The operating system kernel obtains the write permission exception information. If the target address carried in the write permission exception information matches the preset write permission address, it modifies the permission attribute of the target address to have write permission but not execute permission, so that the user-mode program system can continue to write target instructions to the target address in the memory area. The central processing unit writes the target instruction at the target address to the data cache. An execution module is used to execute the target instruction at the target address. If the central processing unit (CPU) detects an execution operation abnormality, it generates execution permission exception information. The operating system kernel obtains the execution permission exception information. If the target address carried in the execution permission exception information matches a preset execution permission address, it calls a data cache cleanup instruction, triggering the CPU to write the target instruction at the target address in the data cache to a storage unit. It also calls an instruction to invalidate the instruction cache, thus invalidating it. This ensures that when the user-mode program system executes the target instruction, the CPU updates the original instruction in the instruction cache to the target instruction, and modifies the permission attribute of the target address to have no write permission but have execute permission, allowing the user-mode program system to continue executing the target instruction at the target address.

10. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the instruction synchronization method as described in any one of claims 1-7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the synchronization method of the instructions as described in any one of claims 1-7.

12. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device is able to perform the synchronization method of the instructions as described in any one of claims 1-7.

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