DC error correction circuit applied to V2COT control DC / DC converter

Abstract

The invention discloses a DC error correction circuit applied to a V2COT control DC / DC converter, and the circuit comprises a primary error amplifier A1 which is used for amplifying an error between a feedback voltage VFB and a reference voltage Vref; the band-gap voltage buffer A2 is used for outputting band-gap buffer voltage during soft start; the secondary error amplifier A3 is used for amplifying the error between the output VC1 of the primary error amplifier and the band gap voltage VBG; the reference voltage buffer A4 is used for outputting a reference buffer voltage; and the unity gain driving buffer A5 is used for buffering the output VC1 of the secondary amplifier A3 and outputting the final modulation voltage VC. The feedback voltage VFB and the feedback voltage VC are compared to send out a signal for conducting the high-side power tube, the conducting time is determined by the COT timing module, and therefore output voltage stabilization is achieved. The DC error correction short circuit is easy to integrate, can ensure that the output voltage is highly consistent with a set value, and greatly improves the precision of the output voltage of the DC / DC converter.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, specifically relating to a method applied to V 2 COT controls the DC error correction circuit of the DC / DC converter. Background Technology

[0002] The schematic diagram of a classic buck DC-DC converter based on ripple-based constant on-time (RBCOT) control is shown below. Figure 1 As shown, it mainly consists of energy storage elements (power inductor and capacitor), power switching transistor, load resistor, feedback voltage divider resistor, comparator, COT timer, and driver circuit. Its basic working principle is: the output voltage across the load resistor is divided by a resistor divider to obtain the feedback voltage V. FB Connect the inverting input of the comparator, and then add a reference voltage V. ref When the feedback voltage V is connected to the non-inverting input of the comparator, FB Below the reference voltage V ref When the comparator outputs a signal to turn on the high-side power transistor, the on-time is generated by the COT timer. The logic and driver module generates a pulse waveform to control the high-side power transistor to turn on and off, driving the high-side power transistor and the low-side power transistor to periodically turn on and off. A pulse signal is generated at the switching node SW. This pulse signal is filtered by a low-pass filter composed of a power inductor, output capacitor, and load resistor, thereby obtaining a continuous and regulated output voltage.

[0003] However, the aforementioned RBCOT-based converter relies on a ripple voltage in phase with the inductor current for loop control, requiring an equivalent series resistance (ESR) of the output capacitor. C Greater than a certain value, so that R C The resulting voltage ripple is dominant, causing a large output voltage ripple. This is reflected in the feedback voltage ripple waveform as follows: Figure 2 As shown, the feedback voltage V FB The average value of the waveform and the reference voltage V ref There is a large DC error between the (set average value), which introduces an uncertain DC error value into the output voltage. In addition, the large voltage ripple value reduces the accuracy of the output voltage.

[0004] To improve the aforementioned DC error problem, existing technologies have introduced ripple compensation techniques. Through internal and / or external ripple compensation, the ripple voltage in phase with the inductor current is compensated in the control loop, allowing the use of low-ESR output capacitors. This results in smaller output voltage ripple, and consequently, a smaller DC error between the average value and the reference voltage, thus reducing the DC error of the output voltage to some extent. However, excessive ripple compensation can cause the ramp compensation voltage to replace the inductor current sampling signal as the main component of the comparator, degenerating the current mode into the voltage mode and worsening transient characteristics. Conversely, insufficient ripple compensation can lead to the risk of subharmonic oscillations. A trade-off must be struck regarding the magnitude of the ripple compensation. Furthermore, the DC value of the output voltage still cannot be accurately determined. Therefore, there is an urgent need for a DC error correction scheme that can accurately determine the DC value of the output voltage with an extremely low error compared to the set ideal value. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an application for V 2 COT controls the DC error correction circuit of the DC / DC converter.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] An application to V 2 The DC error correction circuit in the COT-controlled DC / DC converter includes: a primary error amplifier A1, a bandgap voltage buffer A2, a secondary error amplifier A3, a reference voltage buffer A4, and a unity-gain drive buffer A5.

[0008] The primary error amplifier A1 is used to amplify the feedback voltage V. FB With reference voltage V ref The error between;

[0009] The bandgap voltage buffer A2 is used to output a bandgap buffer voltage during soft start to determine the input common-mode voltage of the secondary error amplifier A3;

[0010] The secondary error amplifier A3 is used to convert the primary output error voltage V of the primary error amplifier A1. C1 With bandgap reference voltage V BG The error between them is amplified;

[0011] The reference voltage gain buffer A4 is used to output a reference buffer voltage to determine the output common-mode voltage of the secondary error amplifier A3.

[0012] The unity-gain drive buffer A5 is used to buffer the secondary output error voltage V of the secondary error amplifier A3. C2 And output the final modulation voltage V C;

[0013] Among them, the feedback voltage V FB The final modulation voltage V output by the unity-gain drive buffer A5 C The comparison outputs a signal that turns on the high-side power transistor. The turn-on time is determined by the COT timing module, so that the DC / DC converter outputs a continuous, stable, and accurate regulated voltage.

[0014] In one embodiment, the primary error amplifier A1 includes: an inverter INV1, PMOS transistors P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, PMOS transistor P9, and PMOS transistor P1. 10 PMOS transistor P 11 NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, and NMOS transistor N 10 Resistors R1, R2, R3, R4, and capacitor C1;

[0015] Wherein, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; the source of PMOS transistor P2, the source of PMOS transistor P3, the source of PMOS transistor P4, the source of PMOS transistor P7, the source of PMOS transistor P8, and the source of PMOS transistor P... 10 The sources of PMOS transistors are all connected to the power supply voltage VCC; the gate of PMOS transistor P1 is connected to the first enable inverted signal ENN0; the source of PMOS transistor P1 is connected to the first bias current I. bias1 The drain of PMOS transistor P1 is connected to the upper end of resistor R1, the gate of NMOS transistor N2, and the gate of NMOS transistor N4; the gate of PMOS transistor P2 is connected to the first enable signal ENP0; the drain of PMOS transistor P2 is connected to the drain of PMOS transistor P3 and the drain of NMOS transistor N4; the gate and drain of PMOS transistor P3 are connected together to the drain of NMOS transistor N4 and the gate of PMOS transistor P4; the gate voltage of PMOS transistor P3 is V. b3 The drain of PMOS transistor P4 is connected to the upper ends of resistors R2 and R3; the source of PMOS transistor P5 is connected to the lower end of resistor R2; the gate of PMOS transistor P5 is connected to the reference voltage input terminal V. refThe drain of PMOS transistor P5 is connected to the source of NMOS transistor N6 and the drain of NMOS transistor N7; the source of PMOS transistor P6 is connected to the lower end of resistor R3; the gate of PMOS transistor P6 is connected to the left end of resistor R4 and the upper end of capacitor C1; the drain of PMOS transistor P6 is connected to the source of NMOS transistor N8 and the drain of NMOS transistor N9; the gate of PMOS transistor P7 is connected to the first enable signal ENP0; the drain of PMOS transistor P7 is connected to the drain of PMOS transistor P8; the gate and drain of PMOS transistor P8 are connected together and connected to the source of PMOS transistor P9 and the drain of PMOS transistor P7. 10 The gate of PMOS transistor P9; the gate and drain of PMOS transistor P9 are connected together and connected to the drain of NMOS transistor N6 and PMOS transistor P. 11 The gate of the PMOS transistor; PMOS transistor P 10 The drain of the PMOS transistor is connected to P 11 The source of the PMOS transistor; PMOS transistor P 11 The drain of NMOS transistor N8 is connected to the drain of NMOS transistor N8, the lower end of capacitor C1, and the NMOS transistor N8. 10 The drain of the primary error amplifier A1 is connected to the output terminal V. C1 The source of NMOS transistor N1, the source of NMOS transistor N3, the source of NMOS transistor N5, the source of NMOS transistor N7, the source of NMOS transistor N9, and the source of NMOS transistor N... 10 The source of NMOS transistor N1 is grounded to GND; the gate of NMOS transistor N1 is connected to the first enable inverted signal ENN0; the drain of NMOS transistor N1 is connected to the lower end of resistor R1, the drain of NMOS transistor N2, the gate of NMOS transistor N3, and the gate of NMOS transistor N4; the gate voltage of NMOS transistor N2 is V. b1 The source of NMOS transistor N2 is connected to the drain of N3; the gate voltage of NMOS transistor N3 is V. b2 The gate of NMOS transistor N4 is connected to the gate of NMOS transistor N6 and the gate of NMOS transistor N8; the source of NMOS transistor N4 is connected to the drain of NMOS transistor N5; the gate of NMOS transistor N5 is connected to the gate of NMOS transistor N7 and the gate of NMOS transistor N9; NMOS transistor N... 10 The gate is connected to the enable inverting signal ENN0; the right end of resistor R4 is connected to the feedback voltage input terminal V. FB .

[0016] In one embodiment, the bandgap voltage buffer A2 includes: inverter INV2, inverter INV3, inverter INV4, inverter INV5, and PMOS transistor P. 20 PMOS transistor P 21 PMOS transistor P 22 PMOS transistor P 23 PMOS transistor P 24 PMOS transistor P25 PMOS transistor P 26 NMOS transistor 16 NMOS transistor 17 NMOS transistor 18 NMOS transistor 19 NMOS transistor 20 NMOS transistor 21 NMOS transistor 22 NMOS transistor 23 NMOS transistor 24 NMOS transistor 25 NMOS transistor 26 NMOS transistor 27 NMOS transistor 28 NMOS transistor 29 NMOS transistor 30 Resistors R7, R8, R9, and R 10 Capacitor C2;

[0017] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; ENP1 is the second enable signal input terminal, and ENP1S is the second enable drive signal after ENP1 is double-inverted by inverters INV2 and INV3; ENP2 is the third enable signal input terminal, and ENN2 is the third enable inverted signal after ENP2 is inverted by inverter INV4, and ENP2S is the third enable drive signal after ENP2 is double-inverted by inverters INV4 and INV5; PMOS transistor P 20 The source of the PMOS transistor P 21 The source of the PMOS transistor P 24 The source of the PMOS transistor P 26 The source of the NMOS transistor 22 The drain of the PMOS transistor, the upper end of resistor R7, and the upper end of resistor R8 are all connected to the power supply voltage VCC; PMOS transistor P 20 The gate and drain are connected together and connected to the PMOS transistor P. 21 Gate of NMOS transistor 16 The drain of the PMOS transistor; PMOS transistor P 21 The gate of the PMOS transistor is connected to P 24 The gate of the PMOS transistor; PMOS transistor P 21 The drain of the PMOS transistor is connected to P 22 The source of the PMOS transistor P 23 The source of the PMOS transistor; PMOS transistor P 22 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 22 The drain of the NMOS transistor is connected to the N. 19The drain of the PMOS transistor; PMOS transistor P 23 The gate of the NMOS transistor is connected to the N. 22 The source of the NMOS transistor 25 The source of the NMOS transistor 27 The drain of the PMOS transistor; PMOS transistor P 23 The drain of the NMOS transistor is connected to the N. 20 drain of NMOS transistor N 21 The drain of the PMOS transistor, the upper end of capacitor C2; PMOS transistor P 25 The gate of the PMOS transistor; PMOS transistor P 24 The drain of the PMOS transistor is connected to P 25 The source of the NMOS transistor 22 Gate of NMOS transistor 26 The drain of the PMOS transistor; PMOS transistor P 25 The drain of the PMOS transistor is connected to ground voltage; 26 The gate of the PMOS transistor is connected to the second enable drive signal ENP1S; 26 The drain of the NMOS transistor is connected to the N. 28 The source of the NMOS transistor 29 drain of NMOS transistor N 30 The drain of the NMOS transistor; 18 The source of the NMOS transistor 19 The source of the NMOS transistor 20 The source of the NMOS transistor 26 The source of the NMOS transistor 27 The source of the NMOS transistor, the lower end of resistor R9, and the lower end of capacitor C2 are all grounded to GND; NMOS transistor N 16 The gate of the NMOS transistor is connected to the third enable drive signal ENP2S; 16 The source of the NMOS transistor is connected to the N-terminal. 17 The drain of the NMOS transistor; 17 gate connected to V b1 NMOS transistor N 17 The source of the NMOS transistor is connected to the N-terminal. 18 The drain of the NMOS transistor; 18 gate connected to V b2 NMOS transistor N 19 The gate and drain are connected together and connected to the NMOS transistor N. 20 The gate of the NMOS transistor; 19 The gate voltage is V. b4 NMOS transistor N 21 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 23 The gate is connected to the bandgap voltage input terminal V. BG NMOS transistor N 23The drain of the NMOS transistor is connected to the lower end of resistor R7; NMOS transistor N 23 The source of the NMOS transistor is connected to the N-terminal. 24 The drain of the NMOS transistor; 24 The gate of the NMOS transistor is connected to the first enable signal ENP0; 24 The source of the NMOS transistor is connected to the N-terminal. 25 drain of NMOS transistor N 28 The gate is connected to the output terminal V of the primary error amplifier A1. C1 NMOS transistor N 25 The gate of the NMOS transistor is connected to the third enable signal ENP2; 26 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 27 gate connected to V b4 NMOS transistor N 28 The drain of the NMOS transistor is connected to the lower end of resistor R8; NMOS transistor N 28 The source of the NMOS transistor is connected to the N-terminal. 29 drain of NMOS transistor N 30 The drain of the NMOS transistor; 29 The gate of the NMOS transistor is connected to the second enable drive signal ENP1S; 29 The source of the NMOS transistor is connected to the upper end of R9; 30 The gate of the NMOS transistor is connected to the second enable drive signal ENP1S; 30 The source terminal R 10 The upper end; resistor R 10 The lower end is connected to the feedback voltage input terminal V. FB .

[0018] In one embodiment, the secondary error amplifier A3 includes: a PMOS transistor P 12 PMOS transistor P 13 PMOS transistor P 14 PMOS transistor P 15 PMOS transistor P 16 PMOS transistor P 17 PMOS transistor P 18 PMOS transistor P 19 NMOS transistor 11 NMOS transistor 12 NMOS transistor 13 NMOS transistor 14 NMOS transistor 15 Resistors R5 and R6;

[0019] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P12 The source of the PMOS transistor P 15 The source of the PMOS transistor P 16 The source of the PMOS transistor P 18 The sources of both transistors are connected to the power supply voltage VCC; PMOS transistor P 12 gate connected to V b3 PMOS transistor P 12 The drain of the PMOS transistor is connected to the upper end of resistor R5 and resistor R6; 13 The gate is connected to the output terminal V of the primary error amplifier A1. C1 PMOS transistor P 13 The source of the PMOS transistor is connected to the lower end of resistor R5; PMOS transistor P 13 The drain of the NMOS transistor is connected to the N. 11 The source of the NMOS transistor 12 The drain of the PMOS transistor; PMOS transistor P 14 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 14 The source of the PMOS transistor is connected to the lower end of resistor R6; 14 The drain of the NMOS transistor is connected to the N. 13 The source of the NMOS transistor 14 The drain of the PMOS transistor; PMOS transistor P 15 The gate of the PMOS transistor is connected to the first enable inverting signal ENN0; 15 The drain of the PMOS transistor is connected to P 16 The drain of the PMOS transistor P 17 The source of the PMOS transistor; PMOS transistor P 16 The gate and drain are connected together and connected to the PMOS transistor P. 18 The gate of the PMOS transistor; PMOS transistor P 17 The gate and drain are connected together and connected to the PMOS transistor P. 19 Gate of NMOS transistor 11 The drain of the PMOS transistor; PMOS transistor P 18 The drain of the PMOS transistor is connected to P 19 The source of the PMOS transistor; PMOS transistor P 19 The drain of the NMOS transistor is connected to the N. 13 drain of NMOS transistor N 15 The drain of the circuit is connected in parallel to the output terminal V of the secondary error amplifier. C2 NMOS transistor N 12 The source of the NMOS transistor 14 The source of the NMOS transistor 15 The source of the NMOS transistor is grounded to GND; 11 The gate of the NMOS transistor is connected to the N. 13 The gate is connected to V. b1 NMOS transistor N12 The gate of the NMOS transistor is connected to the N. 14 The gate is connected to V. b2 NMOS transistor N 15 The gate is connected to the first enable inverted signal ENN0.

[0020] In one embodiment, the reference voltage buffer A4 includes: a PMOS transistor P 27 PMOS transistor P 28 PMOS transistor P 29 PMOS transistor P 30 PMOS transistor P 31 PMOS transistor P 32 PMOS transistor P 33 PMOS transistor P 34 NMOS transistor 31 NMOS transistor 32 NMOS transistor 33 NMOS transistor 34 NMOS transistor 35 NMOS transistor 36 NMOS transistor 37 Resistance R 11 Resistance R 12 Resistance R 13 Capacitor C3, capacitor C4;

[0021] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 27 The source of the PMOS transistor P 30 The source of the PMOS transistor P 31 The source of the PMOS transistor P 33 The source and resistor R 11 The upper end of each is connected to the power supply voltage VCC; PMOS transistor P 27 gate connected to V b3 PMOS transistor P 27 The drain of the PMOS transistor is connected to P 28 The source of the PMOS transistor P 29 The source of the PMOS transistor; PMOS transistor P 28 The gate of the NMOS transistor is connected to the N. 35 The source of the NMOS transistor 37 Drain and resistor R 12 The upper end, resistor R 13 The left end of the capacitor and the upper end of capacitor C4; PMOS transistor P 28 The drain of the NMOS transistor is connected to the N. 31 The source of the NMOS transistor 32 The drain of the PMOS transistor; PMOS transistor P29 The gate is connected to the reference voltage input terminal V. ref PMOS transistor P 29 The drain of the NMOS transistor is connected to the N. 33 The source of the NMOS transistor 34 The drain of the PMOS transistor; PMOS transistor P 30 The gate of the PMOS transistor is connected to the first enable signal ENP0; 30 The drain of the PMOS transistor is connected to P 31 The drain of the PMOS transistor P 32 The source of the PMOS transistor; PMOS transistor P 31 The gate and drain are connected together and connected to the PMOS transistor P. 33 The gate of the PMOS transistor; PMOS transistor P 32 The gate and drain are connected together and connected to the PMOS transistor P. 34 Gate of NMOS transistor 31 The drain of the PMOS transistor; PMOS transistor P 33 The drain of the PMOS transistor is connected to P 34 The source of the PMOS transistor; PMOS transistor P 34 The drain of the NMOS transistor is connected to the N. 33 drain of NMOS transistor N 36 drain of NMOS transistor N 35 The gate of the NMOS transistor, the upper end of capacitor C3; NMOS transistor N 32 The source of the NMOS transistor 34 The source of the NMOS transistor 36 The source of the NMOS transistor 37 The source and resistor R 12 The lower ends of capacitors C3, C4, and C5 are all grounded to GND; NMOS transistor N 31 The gate of the NMOS transistor is connected to the N. 33 The gate is connected to V. b1 NMOS transistor N 32 The gate of the NMOS transistor is connected to the N. 34 The gate is connected to V. b2 NMOS transistor N 35 Drain resistor R 11 The lower end; NMOS transistor N 36 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 37 The gate is connected to the first enable inverting signal ENN0; resistor R 13 The right end is connected to the output terminal V of the secondary error amplifier A3. C2 .

[0022] In one embodiment, the unity-gain drive buffer A5 includes: a PMOS transistor P 35 PMOS transistor P36 PMOS transistor P 37 PMOS transistor P 38 PMOS transistor P 39 PMOS transistor P 40 PMOS transistor P 41 PMOS transistor P 42 PMOS transistor P 43 PMOS transistor P 44 PMOS transistor P 45 NMOS transistor 38 NMOS transistor 39 NMOS transistor 40 NMOS transistor 41 NMOS transistor 42 NMOS transistor 43 NMOS transistor 44 NMOS transistor 45 NMOS transistor 46 NMOS transistor 47 NMOS transistor 48 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Capacitor C5, capacitor C6;

[0023] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 36 The source of the PMOS transistor P 37 The source of the PMOS transistor P 38 The source of the PMOS transistor P 41 The source of the PMOS transistor P 42 The source of the PMOS transistor P 44 The source and resistor R 16 The upper end of each is connected to the power supply voltage VCC; PMOS transistor P 35 The gate of the PMOS transistor is connected to the first enable inverting signal ENN0; 35 The source is connected to the second bias current input terminal I. bias2 PMOS transistor P 35 The drain of the NMOS transistor is connected to the N. 39 Gate of NMOS transistor 41 Gate, resistor R 14 The upper end; PMOS transistor P 36 The gate of the PMOS transistor is connected to the first enable signal ENP0; 36 The drain of the PMOS transistor is connected to P 37drain of NMOS transistor N 41 Drain; PMOS transistor P 37 The gate and drain are connected together and connected to the PMOS transistor P. 38 The gate of the PMOS transistor; PMOS transistor P 38 The drain of the PMOS transistor is connected to P 39 The source of the PMOS transistor P 40 The source of the PMOS transistor; PMOS transistor P 39 The gate of the NMOS transistor is connected to the N. 48 The source and resistor R 17 The upper end, resistor R 18 The left end of the capacitor and the upper end of capacitor C6; PMOS transistor P 39 The drain of the NMOS transistor is connected to the N. 45 The source of the NMOS transistor 46 The drain of the PMOS transistor; PMOS transistor P 40 The gate is connected to the output terminal V of the secondary error amplifier A3. C2 PMOS transistor P 40 The drain of the NMOS transistor is connected to the N. 43 The source of the NMOS transistor 44 The drain of the PMOS transistor; PMOS transistor P 41 The gate of the PMOS transistor is connected to the first enable signal ENP0; 41 The drain of the PMOS transistor is connected to P 42 The drain of the PMOS transistor P 43 The source of the PMOS transistor; PMOS transistor P 42 The gate and drain are connected together and connected to the PMOS transistor P. 44 The gate of the PMOS transistor; PMOS transistor P 43 The gate and drain are connected together and connected to the PMOS transistor P. 45 Gate of NMOS transistor 43 The drain of the PMOS transistor; PMOS transistor P 44 The drain of the PMOS transistor is connected to P 45 The source of the PMOS transistor; PMOS transistor P 45 The drain of the NMOS transistor is connected to the N. 45 drain of NMOS transistor N 47 drain of NMOS transistor N 48 Gate, resistor R 15 The upper end; NMOS transistor N 38 The source of the NMOS transistor 40 The source of the NMOS transistor 42 The source of the NMOS transistor 44 The source of the NMOS transistor 46 The source of the NMOS transistor 47 The source and resistor R 17The lower ends of capacitors C5, C6, and C5 are all grounded to GND; NMOS transistor N 38 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 38 The drain of the NMOS transistor is connected to the N. 39 drain of NMOS transistor N 40 Gate of NMOS transistor 42 Gate, resistor R 14 The lower end; NMOS transistor N 39 The source of the NMOS transistor is connected to the N-terminal. 40 The drain of the NMOS transistor; 41 The gate of the NMOS transistor is connected to the N. 43 Gate of NMOS transistor 45 The gate of the NMOS transistor; 41 The source of the NMOS transistor is connected to the N-terminal. 42 The drain of the NMOS transistor; 42 The gate of the NMOS transistor is connected to the N. 44 Gate of NMOS transistor 46 The gate of the NMOS transistor; 47 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 48 Drain resistor R 16 The lower end; resistor R 15 The lower end is connected to the upper end of capacitor C5; resistor R 18 The right end is connected to the final modulated voltage output terminal V. C .

[0024] This invention provides an application to V 2 In a COT-controlled DC / DC converter, the DC error correction circuit uses a primary error amplifier A1 to convert the feedback voltage V... FB With reference voltage V ref The error between the primary and secondary error amplifiers is initially amplified. The bandgap voltage buffer A2 outputs a bandgap buffer voltage during soft-start to determine the input common-mode voltage of the secondary error amplifier A3, preventing large transitions between the primary and secondary error amplifiers A1 and A3. After soft-start, the bandgap voltage buffer A2 clamps the input common-mode voltage of the secondary error amplifier A3; the secondary error amplifier A3 then converts the primary output error voltage V of the primary error amplifier A1... C1 With bandgap reference voltage V BG The error between them is amplified a second time; the reference voltage gain buffer A4 outputs a reference buffer voltage to determine the output common-mode voltage of the secondary error amplifier A3, thereby also accurately determining the DC value of the output voltage; the unity-gain drive buffer A5 buffers the secondary output error voltage V of the secondary error amplifier A3. C2 And output the final modulation voltage VC Feedback voltage V FB and V C The signal to turn on the high-side power transistor is generated by comparison. The turn-on time is determined by the COT timing module, so that the DC / DC converter outputs a continuous, stable and accurate regulated voltage.

[0025] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0026] Figure 1 This is the schematic diagram of a classic RBCOT-controlled buck DC / DC converter;

[0027] Figure 2 This is a waveform diagram of the ripple voltage of an RBCOT-controlled buck DC / DC converter.

[0028] Figure 3 This is an embodiment of the invention provided for application in V 2 Block diagram of DC error correction circuit in COT controlled DC / DC converter;

[0029] Figure 4(a) shows the application of Figure 3 The circuit diagram shown is of a primary error amplifier in a DC error correction circuit.

[0030] Figure 4(b) shows the application of Figure 3 The circuit diagram shown is of a bandgap voltage buffer in a DC error correction circuit.

[0031] Figure 4(c) shows the application of Figure 3 The circuit diagram shown is of a secondary error amplifier in a DC error correction circuit.

[0032] Figure 4(d) shows the application of Figure 3 The circuit diagram shown is of a reference voltage buffer in a DC error correction circuit.

[0033] Figure 4(e) shows the application of Figure 3 The circuit diagram shown is of a unity-gain drive buffer in a DC error correction circuit.

[0034] Figure 5 It is V 2 Schematic diagram of a COT-controlled buck DC / DC converter;

[0035] Figure 6 It is V 2 Waveform of ripple voltage in COT-controlled buck DC / DC converter; Detailed Implementation

[0036] The present invention will now be described in detail with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0037] To achieve a DC error correction scheme that can accurately determine the DC value of the output voltage with extremely low error compared to the set ideal value, embodiments of the present invention provide a scheme applied to V 2 COT control of DC / DC converter DC error correction circuit, such as Figure 3 As shown, the circuit includes: a primary error amplifier A1, a bandgap voltage buffer A2, a secondary error amplifier A3, a reference voltage buffer A4, and a unity-gain drive buffer A5.

[0038] Primary error amplifier A1 is used to amplify the feedback voltage V. FB With reference voltage V ref The error between;

[0039] Bandgap voltage buffer A2 is used to output a bandgap buffer voltage during soft-start to determine the input common-mode voltage of the secondary error amplifier A3, preventing the primary error amplifier A1 and the secondary error amplifier A3 from undergoing large transitions. After soft-start, bandgap voltage buffer A2 clamps the input common-mode voltage of the secondary error amplifier A3. Switch S is an abstraction representing whether the circuit is in the soft-start phase.

[0040] The secondary error amplifier A3 is used to convert the primary output error voltage V of the primary error amplifier A1. C1 With bandgap reference voltage V BG The error between them is amplified;

[0041] The reference voltage gain buffer A4 is used to output a reference buffer voltage to determine the output common-mode voltage of the secondary error amplifier A3; at the same time, it accurately determines the DC value of the output voltage.

[0042] Unity-gain drive buffer A5 is used to buffer the secondary output error voltage V of the secondary error amplifier A3. C2 And output the final modulation voltage V C This facilitates the implementation of subsequent comparator circuits.

[0043] Among them, the feedback voltage V FB The final modulation voltage V output by the unity-gain drive buffer A5 C The comparison outputs a signal that turns on the high-side power transistor. The turn-on time is determined by the COT timing module, so that the DC / DC converter outputs a continuous, stable, and accurate regulated voltage.

[0044] The specific circuit for comparing the feedback voltage VFB with the final modulation voltage and issuing a signal to turn on the high-side power transistor based on the comparison result can be found in existing DC / DC converters, and will not be described again in this embodiment of the invention.

[0045] based on Figure 3 As shown in the DC error correction circuit, the primary error amplifier A1 amplifies the feedback voltage V. FB With reference voltage V ref The error between them; the bandgap voltage buffer A2 outputs a bandgap buffer voltage during soft start to determine the input common-mode voltage of the secondary error amplifier A3; the secondary error amplifier A3 converts the primary output error voltage V of the primary error amplifier A1 into the input common-mode voltage. C1 With bandgap reference voltage V BG The error between them is amplified; the reference voltage gain buffer A4 outputs a reference buffer voltage to determine the output common-mode voltage of the secondary error amplifier A3, and also accurately determines the DC value of the output voltage; the unity-gain drive buffer A5 buffers the secondary output error voltage V of the secondary error amplifier A3. C2 And output the final modulation voltage V C Feedback voltage V FB The final modulation voltage V output by the unity-gain drive buffer A5 C The comparison outputs a signal that turns on the high-side power transistor. The turn-on time is determined by the COT timing module, so that the DC / DC converter outputs a continuous, stable, and accurate regulated voltage.

[0046] In one embodiment, as shown in FIG4(a), the primary error amplifier A1 may include: an inverter INV1, PMOS transistors P1, PMOS transistors P2, PMOS transistors P3, PMOS transistors P4, PMOS transistors P5, PMOS transistors P6, PMOS transistors P7, PMOS transistors P8, PMOS transistors P9, and PMOS transistor P1. 10 PMOS transistor P 11 NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, and NMOS transistor N 10 Resistors R1, R2, R3, R4, and capacitor C1;

[0047] Wherein, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; the source of PMOS transistor P2, the source of PMOS transistor P3, the source of PMOS transistor P4, the source of PMOS transistor P7, the source of PMOS transistor P8, and the source of PMOS transistor P... 10 The sources of PMOS transistors are all connected to the power supply voltage VCC; the gate of PMOS transistor P1 is connected to the first enable inverted signal ENN0; the source of PMOS transistor P1 is connected to the first bias current I. bias1The drain of PMOS transistor P1 is connected to the upper end of resistor R1, the gate of NMOS transistor N2, and the gate of NMOS transistor N4; the gate of PMOS transistor P2 is connected to the first enable signal ENP0; the drain of PMOS transistor P2 is connected to the drain of PMOS transistor P3 and the drain of NMOS transistor N4; the gate and drain of PMOS transistor P3 are connected together to the drain of NMOS transistor N4 and the gate of PMOS transistor P4; the gate voltage of PMOS transistor P3 is V. b3 The drain of PMOS transistor P4 is connected to the upper ends of resistors R2 and R3; the source of PMOS transistor P5 is connected to the lower end of resistor R2; the gate of PMOS transistor P5 is connected to the reference voltage input terminal V. ref The drain of PMOS transistor P5 is connected to the source of NMOS transistor N6 and the drain of NMOS transistor N7; the source of PMOS transistor P6 is connected to the lower end of resistor R3; the gate of PMOS transistor P6 is connected to the left end of resistor R4 and the upper end of capacitor C1; the drain of PMOS transistor P6 is connected to the source of NMOS transistor N8 and the drain of NMOS transistor N9; the gate of PMOS transistor P7 is connected to the first enable signal ENP0; the drain of PMOS transistor P7 is connected to the drain of PMOS transistor P8; the gate and drain of PMOS transistor P8 are connected together and connected to the source of PMOS transistor P9 and the drain of PMOS transistor P7. 10 The gate of PMOS transistor P9; the gate and drain of PMOS transistor P9 are connected together and connected to the drain of NMOS transistor N6 and PMOS transistor P. 11 The gate of the PMOS transistor; PMOS transistor P 10 The drain of the PMOS transistor is connected to P 11 The source of the PMOS transistor; PMOS transistor P 11 The drain of NMOS transistor N8 is connected to the drain of NMOS transistor N8, the lower end of capacitor C1, and the NMOS transistor N8. 10 The drain of the primary error amplifier A1 is connected to the output terminal V. C1 The source of NMOS transistor N1, the source of NMOS transistor N3, the source of NMOS transistor N5, the source of NMOS transistor N7, the source of NMOS transistor N9, and the source of NMOS transistor N... 10 The source of NMOS transistor N1 is grounded to GND; the gate of NMOS transistor N1 is connected to the first enable inverted signal ENN0; the drain of NMOS transistor N1 is connected to the lower end of resistor R1, the drain of NMOS transistor N2, the gate of NMOS transistor N3, and the gate of NMOS transistor N4; the gate voltage of NMOS transistor N2 is V. b1 The source of NMOS transistor N2 is connected to the drain of N3; the gate voltage of NMOS transistor N3 is V. b2 The gate of NMOS transistor N4 is connected to the gate of NMOS transistor N6 and the gate of NMOS transistor N8; the source of NMOS transistor N4 is connected to the drain of NMOS transistor N5; the gate of NMOS transistor N5 is connected to the gate of NMOS transistor N7 and the gate of NMOS transistor N9; NMOS transistor N...10 The gate is connected to the enable inverting signal ENN0; the right end of resistor R4 is connected to the feedback voltage input terminal V. FB .

[0048] In another embodiment, as shown in FIG4(b), the bandgap voltage buffer A2 may include: inverter INV2, inverter INV3, inverter INV4, inverter INV5, and PMOS transistor P 20 PMOS transistor P 21 PMOS transistor P 22 PMOS transistor P 23 PMOS transistor P 24 PMOS transistor P 25 PMOS transistor P 26 NMOS transistor 16 NMOS transistor 17 NMOS transistor 18 NMOS transistor 19 NMOS transistor 20 NMOS transistor 21 NMOS transistor 22 NMOS transistor 23 NMOS transistor 24 NMOS transistor 25 NMOS transistor 26 NMOS transistor 27 NMOS transistor 28 NMOS transistor 29 NMOS transistor 30 Resistors R7, R8, R9, and R 10 Capacitor C2;

[0049] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; ENP1 is the second enable signal input terminal, and ENP1S is the second enable drive signal after ENP1 is double-inverted by inverters INV2 and INV3; ENP2 is the third enable signal input terminal, and ENN2 is the third enable inverted signal after ENP2 is inverted by inverter INV4, and ENP2S is the third enable drive signal after ENP2 is double-inverted by inverters INV4 and INV5; PMOS transistor P 20 The source of the PMOS transistor P 21 The source of the PMOS transistor P 24 The source of the PMOS transistor P 26 The source of the NMOS transistor 22 The drain of the PMOS transistor, the upper end of resistor R7, and the upper end of resistor R8 are all connected to the power supply voltage VCC; PMOS transistor P 20The gate and drain are connected together and connected to the PMOS transistor P. 21 Gate of NMOS transistor 16 The drain of the PMOS transistor; PMOS transistor P 21 The gate of the PMOS transistor is connected to P 24 The gate of the PMOS transistor; PMOS transistor P 21 The drain of the PMOS transistor is connected to P 22 The source of the PMOS transistor P 23 The source of the PMOS transistor; PMOS transistor P 22 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 22 The drain of the NMOS transistor is connected to the N. 19 The drain of the PMOS transistor; PMOS transistor P 23 The gate of the NMOS transistor is connected to the N. 22 The source of the NMOS transistor 25 The source of the NMOS transistor 27 The drain of the PMOS transistor; PMOS transistor P 23 The drain of the NMOS transistor is connected to the N. 20 drain of NMOS transistor N 21 The drain of the PMOS transistor, the upper end of capacitor C2; PMOS transistor P 25 The gate of the PMOS transistor; PMOS transistor P 24 The drain of the PMOS transistor is connected to P 25 The source of the NMOS transistor 22 Gate of NMOS transistor 26 The drain of the PMOS transistor; PMOS transistor P 25 The drain of the PMOS transistor is connected to ground voltage; 26 The gate of the PMOS transistor is connected to the second enable drive signal ENP1S; 26 The drain of the NMOS transistor is connected to the N. 28 The source of the NMOS transistor 29 drain of NMOS transistor N 30 The drain of the NMOS transistor; 18 The source of the NMOS transistor 19 The source of the NMOS transistor 20 The source of the NMOS transistor 26 The source of the NMOS transistor 27 The source of the NMOS transistor, the lower end of resistor R9, and the lower end of capacitor C2 are all grounded to GND; NMOS transistor N 16 The gate of the NMOS transistor is connected to the third enable drive signal ENP2S; 16 The source of the NMOS transistor is connected to the N-terminal. 17 The drain of the NMOS transistor; 17 gate connected to V b1 NMOS transistor N 17 The source of the NMOS transistor is connected to the N-terminal.18 The drain of the NMOS transistor; 18 gate connected to V b2 NMOS transistor N 19 The gate and drain are connected together and connected to the NMOS transistor N. 20 The gate of the NMOS transistor; 19 The gate voltage is V. b4 NMOS transistor N 21 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 23 The gate is connected to the bandgap voltage input terminal V. BG NMOS transistor N 23 The drain of the NMOS transistor is connected to the lower end of resistor R7; NMOS transistor N 23 The source of the NMOS transistor is connected to the N-terminal. 24 The drain of the NMOS transistor; 24 The gate of the NMOS transistor is connected to the first enable signal ENP0; 24 The source of the NMOS transistor is connected to the N-terminal. 25 drain of NMOS transistor N 28 The gate is connected to the output terminal V of the primary error amplifier A1. C1 NMOS transistor N 25 The gate of the NMOS transistor is connected to the third enable signal ENP2; 26 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 27 gate connected to V b4 NMOS transistor N 28 The drain of the NMOS transistor is connected to the lower end of resistor R8; NMOS transistor N 28 The source of the NMOS transistor is connected to the N-terminal. 29 drain of NMOS transistor N 30 The drain of the NMOS transistor; 29 The gate of the NMOS transistor is connected to the second enable drive signal ENP1S; 29 The source of the NMOS transistor is connected to the upper end of R9; 30 The gate of the NMOS transistor is connected to the second enable drive signal ENP1S; 30 The source terminal R 10 The upper end; resistor R 10 The lower end is connected to the feedback voltage input terminal V. FB .

[0050] In yet another embodiment, as shown in FIG4(c), the secondary error amplifier A3 may include: a PMOS transistor P 12 PMOS transistor P 13 PMOS transistor P 14 PMOS transistor P 15 PMOS transistor P16 PMOS transistor P 17 PMOS transistor P 18 PMOS transistor P 19 NMOS transistor 11 NMOS transistor 12 NMOS transistor 13 NMOS transistor 14 NMOS transistor 15 Resistors R5 and R6;

[0051] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 12 The source of the PMOS transistor P 15 The source of the PMOS transistor P 16 The source of the PMOS transistor P 18 The sources of both transistors are connected to the power supply voltage VCC; PMOS transistor P 12 gate connected to V b3 PMOS transistor P 12 The drain of the PMOS transistor is connected to the upper end of resistor R5 and resistor R6; 13 The gate is connected to the output terminal V of the primary error amplifier A1. C1 PMOS transistor P 13 The source of the PMOS transistor is connected to the lower end of resistor R5; PMOS transistor P 13 The drain of the NMOS transistor is connected to the N. 11 The source of the NMOS transistor 12 The drain of the PMOS transistor; PMOS transistor P 14 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 14 The source of the PMOS transistor is connected to the lower end of resistor R6; 14 The drain of the NMOS transistor is connected to the N. 13 The source of the NMOS transistor 14 The drain of the PMOS transistor; PMOS transistor P 15 The gate of the PMOS transistor is connected to the first enable inverting signal ENN0; 15 The drain of the PMOS transistor is connected to P 16 The drain of the PMOS transistor P 17 The source of the PMOS transistor; PMOS transistor P 16 The gate and drain are connected together and connected to the PMOS transistor P. 18 The gate of the PMOS transistor; PMOS transistor P 17 The gate and drain are connected together and connected to the PMOS transistor P. 19 Gate of NMOS transistor 11 The drain of the PMOS transistor; PMOS transistor P 18 The drain of the PMOS transistor is connected to P19 The source of the PMOS transistor; PMOS transistor P 19 The drain of the NMOS transistor is connected to the N. 13 drain of NMOS transistor N 15 The drain of the circuit is connected in parallel to the output terminal V of the secondary error amplifier. C2 NMOS transistor N 12 The source of the NMOS transistor 14 The source of the NMOS transistor 15 The source of the NMOS transistor is grounded to GND; 11 The gate of the NMOS transistor is connected to the N. 13 The gate is connected to V. b1 NMOS transistor N 12 The gate of the NMOS transistor is connected to the N. 14 The gate is connected to V. b2 NMOS transistor N 15 The gate is connected to the first enable inverted signal ENN0.

[0052] In one embodiment, as shown in FIG4(d), the reference voltage buffer A4 may include: a PMOS transistor P 27 PMOS transistor P 28 PMOS transistor P 29 PMOS transistor P 30 PMOS transistor P 31 PMOS transistor P 32 PMOS transistor P 33 PMOS transistor P 34 NMOS transistor 31 NMOS transistor 32 NMOS transistor 33 NMOS transistor 34 NMOS transistor 35 NMOS transistor 36 NMOS transistor 37 Resistance R 11 Resistance R 12 Resistance R 13 Capacitor C3, capacitor C4;

[0053] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 27 The source of the PMOS transistor P 30 The source of the PMOS transistor P 31 The source of the PMOS transistor P 33 The source and resistor R 11 The upper end of each is connected to the power supply voltage VCC; PMOS transistor P 27 gate connected to V b3PMOS transistor P 27 The drain of the PMOS transistor is connected to P 28 The source of the PMOS transistor P 29 The source of the PMOS transistor; PMOS transistor P 28 The gate of the NMOS transistor is connected to the N. 35 The source of the NMOS transistor 37 Drain and resistor R 12 The upper end, resistor R 13 The left end of the capacitor and the upper end of capacitor C4; PMOS transistor P 28 The drain of the NMOS transistor is connected to the N. 31 The source of the NMOS transistor 32 The drain of the PMOS transistor; PMOS transistor P 29 The gate is connected to the reference voltage input terminal V. ref PMOS transistor P 29 The drain of the NMOS transistor is connected to the N. 33 The source of the NMOS transistor 34 The drain of the PMOS transistor; PMOS transistor P 30 The gate of the PMOS transistor is connected to the first enable signal ENP0; 30 The drain of the PMOS transistor is connected to P 31 The drain of the PMOS transistor P 32 The source of the PMOS transistor; PMOS transistor P 31 The gate and drain are connected together and connected to the PMOS transistor P. 33 The gate of the PMOS transistor; PMOS transistor P 32 The gate and drain are connected together and connected to the PMOS transistor P. 34 Gate of NMOS transistor 31 The drain of the PMOS transistor; PMOS transistor P 33 The drain of the PMOS transistor is connected to P 34 The source of the PMOS transistor; PMOS transistor P 34 The drain of the NMOS transistor is connected to the N. 33 drain of NMOS transistor N 36 drain of NMOS transistor N 35 The gate of the NMOS transistor, the upper end of capacitor C3; NMOS transistor N 32 The source of the NMOS transistor 34 The source of the NMOS transistor 36 The source of the NMOS transistor 37 The source and resistor R 12 The lower ends of capacitors C3, C4, and C5 are all grounded to GND; NMOS transistor N 31 The gate of the NMOS transistor is connected to the N. 33 The gate is connected to V. b1 NMOS transistor N 32 The gate of the NMOS transistor is connected to the N. 34The gate is connected to V. b2 NMOS transistor N 35 Drain resistor R 11 The lower end; NMOS transistor N 36 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 37 The gate is connected to the first enable inverting signal ENN0; resistor R 13 The right end is connected to the output terminal V of the secondary error amplifier A3. C2 .

[0054] In another embodiment, as shown in FIG4(e), the unity-gain drive buffer A5 may include: a PMOS transistor P 35 PMOS transistor P 36 PMOS transistor P 37 PMOS transistor P 38 PMOS transistor P 39 PMOS transistor P 40 PMOS transistor P 41 PMOS transistor P 42 PMOS transistor P 43 PMOS transistor P 44 PMOS transistor P 45 NMOS transistor 38 NMOS transistor 39 NMOS transistor 40 NMOS transistor 41 NMOS transistor 42 NMOS transistor 43 NMOS transistor 44 NMOS transistor 45 NMOS transistor 46 NMOS transistor 47 NMOS transistor 48 Resistance R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Capacitor C5, capacitor C6;

[0055] Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 36 The source of the PMOS transistor P 37 The source of the PMOS transistor P 38 The source of the PMOS transistor P 41 The source of the PMOS transistor P 42 The source of the PMOS transistor P 44 The source and resistor R16 The upper end of each is connected to the power supply voltage VCC; PMOS transistor P 35 The gate of the PMOS transistor is connected to the first enable inverting signal ENN0; 35 The source is connected to the second bias current input terminal I. bias2 PMOS transistor P 35 The drain of the NMOS transistor is connected to the N. 39 Gate of NMOS transistor 41 Gate, resistor R 14 The upper end; PMOS transistor P 36 The gate of the PMOS transistor is connected to the first enable signal ENP0; 36 The drain of the PMOS transistor is connected to P 37 drain of NMOS transistor N 41 Drain; PMOS transistor P 37 The gate and drain are connected together and connected to the PMOS transistor P. 38 The gate of the PMOS transistor; PMOS transistor P 38 The drain of the PMOS transistor is connected to P 39 The source of the PMOS transistor P 40 The source of the PMOS transistor; PMOS transistor P 39 The gate of the NMOS transistor is connected to the N. 48 The source and resistor R 17 The upper end, resistor R 18 The left end of the capacitor and the upper end of capacitor C6; PMOS transistor P 39 The drain of the NMOS transistor is connected to the N. 45 The source of the NMOS transistor 46 The drain of the PMOS transistor; PMOS transistor P 40 The gate is connected to the output terminal V of the secondary error amplifier A3. C2 PMOS transistor P 40 The drain of the NMOS transistor is connected to the N. 43 The source of the NMOS transistor 44 The drain of the PMOS transistor; PMOS transistor P 41 The gate of the PMOS transistor is connected to the first enable signal ENP0; 41 The drain of the PMOS transistor is connected to P 42 The drain of the PMOS transistor P 43 The source of the PMOS transistor; PMOS transistor P 42 The gate and drain are connected together and connected to the PMOS transistor P. 44 The gate of the PMOS transistor; PMOS transistor P 43 The gate and drain are connected together and connected to the PMOS transistor P. 45 Gate of NMOS transistor 43 The drain of the PMOS transistor; PMOS transistor P 44 The drain of the PMOS transistor is connected to P 45The source of the PMOS transistor; PMOS transistor P 45 The drain of the NMOS transistor is connected to the N. 45 drain of NMOS transistor N 47 drain of NMOS transistor N 48 Gate, resistor R 15 The upper end; NMOS transistor N 38 The source of the NMOS transistor 40 The source of the NMOS transistor 42 The source of the NMOS transistor 44 The source of the NMOS transistor 46 The source of the NMOS transistor 47 The source and resistor R 17 The lower ends of capacitors C5, C6, and C5 are all grounded to GND; NMOS transistor N 38 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 38 The drain of the NMOS transistor is connected to the N. 39 drain of NMOS transistor N 40 Gate of NMOS transistor 42 Gate, resistor R 14 The lower end; NMOS transistor N 39 The source of the NMOS transistor is connected to the N-terminal. 40 The drain of the NMOS transistor; 41 The gate of the NMOS transistor is connected to the N. 43 Gate of NMOS transistor 45 The gate of the NMOS transistor; 41 The source of the NMOS transistor is connected to the N-terminal. 42 The drain of the NMOS transistor; 42 The gate of the NMOS transistor is connected to the N. 44 Gate of NMOS transistor 46 The gate of the NMOS transistor; 47 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 48 Drain resistor R 16 The lower end; resistor R 15 The lower end is connected to the upper end of capacitor C5; resistor R 18 The right end is connected to the final modulated voltage output terminal V. C .

[0056] Below, based on Figure 3 The circuit block diagrams and various circuit modules shown in Figures 4(a), 4(b), 4(c), 4(d), and 4(e) illustrate the application of the present invention to V... 2 The working principle of the DC error correction circuit in the COT-controlled DC / DC converter is explained:

[0057] The working principle of Embodiment 1 of the present invention is as follows:

[0058] For the primary error amplifier A1 shown in Figure 4(a), when the first enable signal ENP0 is high, PMOS transistor P1 is turned on, and PMOS transistors P2, PMOS transistor P7, NMOS transistor N1, and NMOS transistor N2 are also turned on. 10 When switched off, the circuit begins normal operation. The first bias current I... bias1 The bias current I is provided by an external reference current generation circuit. Resistors R1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, and NMOS transistors N5 form a self-biased cascode current mirror. bias1 Precise replication; PMOS transistors P1 and P2 form a PMOS current mirror, providing suitable bias for the core amplifier circuit; resistors R2 and R3, PMOS transistors P4, P5, P6, P8, P9, and P... 10 PMOS transistor P 11 NMOS transistors N6, N7, N8, and N9 form the core of a folded cascode amplifier. The non-inverting input of the amplifier is connected to the reference voltage V. ref The inverting input terminal is connected to the feedback voltage V. FB It amplifies the difference between the reference voltage and the feedback voltage and outputs the primary error voltage V. C1 .

[0059] Resistor R4 and capacitor C1 form a Type I compensation network for the primary error amplifier. The output node of the primary error amplifier is determined as the dominant pole of the control loop, ensuring that the control loop has sufficient phase margin to stabilize. At the same time, the crossover frequency is made to be about 1 / 10 of the switching frequency, thereby effectively attenuating high-frequency noise.

[0060] Therefore, in this embodiment of the invention, a trade-off between loop gain and bandwidth can be flexibly made by changing the values ​​of resistor R4 and capacitor C1.

[0061] For the bandgap voltage buffer A2, as shown in Figure 4(b), the circuit operates normally when the first enable signal ENP0 is high and the second enable signal is low; when the circuit is in the soft-start phase, the third enable signal ENP2 is high. NMOS transistor N 17 NMOS transistor 18 NMOS transistors N2 and N3 form a current mirror structure to replicate the first bias current I. bias1 As the bias current of the core circuit. PMOS transistor P 20 PMOS transistor P 21To construct a PMOS current mirror, a suitable bias is determined for the core amplifier circuit. The PMOS transistor P... 21 PMOS transistor P 22 PMOS transistor P 23 PMOS transistor P 24 PMOS transistor P 25 NMOS transistor 19 NMOS transistor 20 NMOS transistor 22 NMOS transistor 18 The amplifier is configured such that the non-inverting input terminal is connected to the bandgap voltage V. BG The inverting input of the amplifier is connected to the NMOS transistor N. 22 The source of the NMOS transistor 25 The source of the NMOS transistor 27 The drain of the NMOS transistor forms a unity-gain buffer structure. After the circuit reaches stability, the NMOS transistor N... 22 The source of the NMOS transistor 25 The source of the NMOS transistor 27 The drain voltage of both is V BG NMOS transistor N 23 The gate is also connected to V. BG During soft start, NMOS transistor N 23 Cut-off, NMOS transistor N 24 Operating in the deep linear region, NMOS transistor N 25 The drain voltage is also V BG That is, the output voltage of the bandgap voltage buffer A2 is also V. BG After the soft start is completed, the output voltage of the bandgap voltage buffer A2 is clamped.

[0062] Figure 3 In the block diagram, switch S is an abstraction representing whether the circuit is in the soft-start phase.

[0063] The bandgap voltage buffer A2 determines the output common-mode voltage of the primary error amplifier A1 and the input common-mode voltage of the secondary error amplifier A3 during the soft-start phase, avoiding large transitions for the primary error amplifier A1 and the secondary error amplifier A3, which is beneficial for a smooth transition to the normal amplification state after the soft-start is completed.

[0064] For the secondary error amplifier A3 shown in Figure 4(c), when the first enable signal ENP0 is high, the circuit starts to work normally, and PMOS transistors P3 and P4... 12 This forms a PMOS current mirror, providing a suitable bias for the core circuit. The PMOS transistor P... 12 Resistors R5, R6, and PMOS transistor P 13 PMOS transistor P 14PMOS transistor P 16 PMOS transistor P 17 PMOS transistor P 18 PMOS transistor P 19 NMOS transistor 11 NMOS transistor 12 NMOS transistor 13 NMOS transistor 14 This forms a folded cascode amplifier, with the non-inverting input connected to the output V of the primary error amplifier A1. C1 The inverting input of the amplifier is connected to the bandgap voltage V. BG Amplify the output V of the primary error amplifier A1 C1 With bandgap voltage V BG The error between them is output, and the secondary error voltage V is output. C2 .

[0065] For the reference voltage buffer A4 shown in Figure 4(d), when the first enable signal ENP0 is high, the PMOS transistor P 30 NMOS transistor 36 NMOS transistor 37 Cut off, the circuit is working normally. PMOS transistor P 27 Together with PMOS transistor P3, they form a PMOS current mirror to provide suitable bias for the core circuit. PMOS transistor P... 27 PMOS transistor P 28 PMOS transistor P 29 PMOS transistor P 31 PMOS transistor P 32 PMOS transistor P 33 PMOS transistor P 34 NMOS transistor 31 NMOS transistor 32 NMOS transistor 33 NMOS transistor 34 NMOS transistor 35 Resistance R 11 Resistance R 11 The core amplifier circuit is formed, with the non-inverting input terminal of the amplifier connected to the reference voltage V. ref The inverting input terminal is connected to the NMOS transistor N. 35 The source of the NMOS transistor 37 Drain and resistor R 12 The upper end, resistor R 13 The left end of the resistor and the upper end of capacitor C4 form a buffer structure, and the resistor R 13 The right end is connected to the output of the secondary error amplifier.

[0066] The reference voltage buffer A4 outputs a reference buffer voltage that determines the output common-mode level of the secondary error amplifier, and also determines the final modulation voltage V. C The DC level is fed back as a voltage V in the comparator. FB With the final modulation voltage V C The ripple waveform is as follows Figure 6 As shown, V FB The DC level is very close to the set value.

[0067] The unity-gain drive buffer circuit A5, as shown in Figure 4(e), when the first enable signal ENP0 is high, the PMOS transistor P... 35 Turn on, PMOS transistor P 36 PMOS transistor P 41 NMOS transistor 38 NMOS transistor 47 When switched off, the circuit begins to operate normally. The second bias current I... bias2 Provided by an external reference current generating circuit, resistor R 14 NMOS transistor 39 NMOS transistor 40 NMOS transistor 41 NMOS transistor 42 The self-biased cascode current mirror will bias the second bias current I. bias2 Precise replication; PMOS transistor P 37 PMOS transistor P 38 A PMOS current mirror is formed to provide a suitable bias for the core amplifier circuit; the PMOS transistor P 38 PMOS transistor P 39 PMOS transistor P 40 PMOS transistor P 42 PMOS transistor P 43 PMOS transistor P 44 PMOS transistor P 45 NMOS transistor 43 NMOS transistor 44 NMOS transistor 45 NMOS transistor 46 NMOS transistor 48 The core is a folded cascode amplifier, with its non-inverting input connected to the output V of the secondary error amplifier A3. C2 The inverting input terminal is connected to the NMOS transistor N. 48 The source and resistor R 17 The upper end, resistor R 18 The left end of resistor R18 and the upper end of capacitor C6 form a buffer structure. The right end of resistor R18 outputs the final modulation voltage V. C This facilitates subsequent comparator processing.

[0068] resistor R 15 Together with C5, they form the compensation circuit for the unity-gain drive buffer circuit A5, ensuring that the unity-gain drive buffer circuit A5 has sufficient phase margin to maintain loop stability.

[0069] In summary, the DC error correction circuit for V2COT controlled DC / DC converters provided in this embodiment of the invention has the characteristics of accurately determining the DC value of the DC / DC converter output voltage and increasing the loop gain of the control loop.

[0070] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0071] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0072] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the description of this invention, the word "comprising" does not exclude other components or steps, and "a" or "a" does not exclude a plurality; "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0073] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications or substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method of applying a V 2 A DC error correction circuit in a COT-controlled DC / DC converter, characterized by Comprise: a primary error amplifier A1, a bandgap voltage buffer A2, a secondary error amplifier A3, a reference voltage buffer A4 and a unity gain driver buffer A5. The primary error amplifier A1 is used to preliminarily amplify the error between the feedback voltage V FB and the reference voltage V ref , and output a primary error voltage V C1 ; The bandgap voltage buffer A2 is used to output a bandgap buffer voltage to determine the input common mode voltage of the secondary error amplifier A3 during soft start, preventing the primary error amplifier A1 and the secondary error amplifier A3 from experiencing large transitions. After the soft start is completed, the bandgap voltage buffer A2 clamps the input common mode voltage of the secondary error amplifier A3. The switch S is an abstraction of whether the circuit is in the soft start phase or not; The secondary error amplifier A3 is used to amplify the error between the primary output error voltage V C1 and the bandgap reference voltage V BG and output a secondary error voltage V C2 ; The reference voltage gain buffer A4 is used to output a reference buffer voltage to determine the output common mode voltage of the secondary error amplifier A3; The unit gain drive buffer A5 is used to buffer the secondary output error voltage V C2 and output the final modulation voltage V C ; Wherein, the feedback voltage V FB The final modulation voltage V C The comparison sends the signal to turn on the high-side power tube, and the on time is determined by the COT timing module, so that the DC / DC converter outputs continuous, stable and accurate regulated voltage.

2. The use according to claim 1, applied to V 2 A DC error correction circuit for COT-controlled DC / DC converter, characterized by, The primary error amplifier A1 comprises: an inverter INV1, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P 10 , a PMOS tube P 11 , a NMOS tube N1, a NMOS tube N2, a NMOS tube N3, a NMOS tube N4, a NMOS tube N5, a NMOS tube N6, a NMOS tube N7, a NMOS tube N8, a NMOS tube N9, a NMOS tube N 10 , a resistance R1, a resistance R2, a resistance R3, a resistance R4, a capacitor C1; Wherein, ENP0 is the first enable signal input terminal, ENN0 is the first enable inverse signal after the inversion of ENP0 by the inverter INV1; the source of PMOS tube P2, the source of PMOS tube P3, the source of PMOS tube P4, the source of PMOS tube P7, the source of PMOS tube P8, the source of PMOS tube P 10 all connect to the power supply voltage VCC; the gate of PMOS tube P1 connects to the first enable inverse signal ENN0; the source of PMOS tube P1 connects to the first bias current I bias1 ; the drain of PMOS tube P1 connects to the upper end of resistor R1, the gate of NMOS tube N2, the gate of NMOS tube N4; the gate of PMOS tube P2 connects to the first enable signal ENP0; the drain of PMOS tube P2 connects to the drain of PMOS tube P3, the drain of NMOS tube N4; the gate and the drain of PMOS tube P3 are connected together and connect to the drain of NMOS tube N4, the gate of PMOS tube P4; the gate voltage of PMOS tube P3 is output as V b3 ; the drain of PMOS tube P4 connects to the upper end of resistor R2, the upper end of resistor R3; the source of PMOS tube P5 connects to the lower end of resistor R2; the gate of PMOS tube P5 connects to the reference voltage input terminal V ref ; the drain of PMOS tube P5 connects to the source of NMOS tube N6, the drain of NMOS tube N7; the source of PMOS tube P6 connects to the lower end of resistor R3; the gate of PMOS tube P6 connects to the left end of resistor R4, the upper end of capacitor C1; the drain of PMOS tube P6 connects to the source of NMOS tube N8, the drain of NMOS tube N9; the gate of PMOS tube P7 connects to the first enable signal ENP0; the drain of PMOS tube P7 connects to the drain of PMOS tube P8; the gate and the drain of PMOS tube P8 are connected together and connect to the source of PMOS tube P9, the gate of PMOS tube P 10 ; the gate and the drain of PMOS tube P9 are connected together and connect to the drain of NMOS tube N6, the gate of PMOS tube P 11 ; the drain of PMOS tube P 10 connects to the source of PMOS tube P 11 ; the drain of PMOS tube P 11 connects to the drain of NMOS tube N8, the lower end of capacitor C1, the drain of NMOS tube N 10 , and connects to the output terminal V C1 of the primary error amplifier A1; the source of NMOS tube N1, the source of NMOS tube N3, the source of NMOS tube N5, the source of NMOS tube N7, the source of NMOS tube N9, the source of NMOS tube N 10 The source of the NMOS transistor N1 is connected to the ground voltage GND; the gate of the NMOS transistor N1 is connected to the first inverted enable signal ENN0; the drain of the NMOS transistor N1 is connected to the lower end of the resistor R1, the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, and the gate of the NMOS transistor N4; the gate voltage of the NMOS transistor N2 is output as V b1 ; the source of the NMOS transistor N2 is connected to the drain of N3; the gate voltage of the NMOS transistor N3 is output as V b2 ; the gate of the NMOS transistor N4 is connected to the gate of the NMOS transistor N6 and the gate of the NMOS transistor N8; the source of the NMOS transistor N4 is connected to the drain of the NMOS transistor N5; the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N7 and the gate of the NMOS transistor N9; the gate of the NMOS transistor N 10 is connected to the inverted enable signal ENN0; the right end of the resistor R4 is connected to the feedback voltage input terminal V FB .

3. The use according to claim 1, applied to V 2 A DC error correction circuit for COT-controlled DC / DC converter, characterized by, The bandgap voltage buffer A2 comprises: an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a PMOS tube P 20 , a PMOS tube P 21 , a PMOS tube P 22 , a PMOS tube P 23 , a PMOS tube P 24 , a PMOS tube P 25 , a PMOS tube P 26 , a NMOS tube N 16 , a NMOS tube N 17 , a NMOS tube N 18 , a NMOS tube N 19 , a NMOS tube N 20 , a NMOS tube N 21 , a NMOS tube N 22 , a NMOS tube N 23 , a NMOS tube N 24 , a NMOS tube N 25 , a NMOS tube N 26 , a NMOS tube N 27 , a NMOS tube N 28 , a NMOS tube N 29 , a NMOS tube N 30 , a resistance R7, a resistance R8, a resistance R9, a resistance R 10 , a capacitor C2; Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; ENP1 is the second enable signal input terminal, and ENP1S is the second enable drive signal after ENP1 is double-inverted by inverters INV2 and INV3; ENP2 is the third enable signal input terminal, and ENN2 is the third enable inverted signal after ENP2 is inverted by inverter INV4, and ENP2S is the third enable drive signal after ENP2 is double-inverted by inverters INV4 and INV5; PMOS transistor P 20 The source of the PMOS transistor P 21 The source of the PMOS transistor P 24 The source of the PMOS transistor P 26 The source of the NMOS transistor 22 The drain of the PMOS transistor, the upper end of resistor R7, and the upper end of resistor R8 are all connected to the power supply voltage VCC; PMOS transistor P 20 The gate and drain are connected together and connected to the PMOS transistor P. 21 Gate of NMOS transistor 16 The drain of the PMOS transistor; PMOS transistor P 21 The gate of the PMOS transistor is connected to P 24 The gate of the PMOS transistor; PMOS transistor P 21 The drain of the PMOS transistor is connected to P 22 The source of the PMOS transistor P 23 The source of the PMOS transistor; PMOS transistor P 22 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 22 The drain of the NMOS transistor is connected to the N. 19 The drain of the PMOS transistor; PMOS transistor P 23 The gate of the NMOS transistor is connected to the N. 22 The source of the NMOS transistor 25 The source of the NMOS transistor 27 The drain of the PMOS transistor; PMOS transistor P 23 The drain of the NMOS transistor is connected to the N. 20 drain of NMOS transistor N 21 The drain of the PMOS transistor, the upper end of capacitor C2; PMOS transistor P 25 The gate of the PMOS transistor; PMOS transistor P 24 The drain of the PMOS transistor is connected to P 25 The source of the NMOS transistor 22 Gate of NMOS transistor 26 The drain of the PMOS transistor; PMOS transistor P 25 The drain of the PMOS transistor is connected to ground voltage; 26 The gate of the PMOS transistor is connected to the second enable drive signal ENP1S; 26 The drain of the NMOS transistor is connected to the N. 28 The source of the NMOS transistor 29 drain of NMOS transistor N 30 The drain of the NMOS transistor; 18 The source of the NMOS transistor 19 The source of the NMOS transistor 20 The source of the NMOS transistor 26 The source of the NMOS transistor 27 The source of the NMOS transistor, the lower end of resistor R9, and the lower end of capacitor C2 are all grounded to GND; NMOS transistor N 16 The gate of the NMOS transistor is connected to the third enable drive signal ENP2S; 16 The source of the NMOS transistor is connected to the N-terminal. 17 The drain of the NMOS transistor; 17 gate connected to V b1 NMOS transistor N 17 The source of the NMOS transistor is connected to the N-terminal. 18 The drain of the NMOS transistor; 18 gate connected to V b2 NMOS transistor N 19 The gate and drain are connected together and connected to the NMOS transistor N. 20 The gate of the NMOS transistor; 19 The gate voltage is V. b4 NMOS transistor N 21 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 23 The gate is connected to the bandgap voltage input terminal V. BG NMOS transistor N 23 The drain of the NMOS transistor is connected to the lower end of resistor R7; NMOS transistor N 23 The source of the NMOS transistor is connected to the N-terminal. 24 The drain of the NMOS transistor; 24 The gate of the NMOS transistor is connected to the first enable signal ENP0; 24 The source of the NMOS transistor is connected to the N-terminal. 25 drain of NMOS transistor N 28 The gate is connected to the output terminal V of the primary error amplifier A1. C1 NMOS transistor N 25 The gate of the NMOS transistor is connected to the third enable signal ENP2; 26 The gate of the NMOS transistor is connected to the third enable inverting signal ENN2; 27 gate connected to V b4 NMOS transistor N 28 The drain of the NMOS transistor is connected to the lower end of resistor R8; NMOS transistor N 28 The source of the NMOS transistor is connected to the N-terminal. 29 drain of NMOS transistor N 30 the drain of the NMOS transistor N 29 the gate of the NMOS transistor N 29 the source of the NMOS transistor N 30 the gate of the NMOS transistor N 30 the source of the NMOS transistor N 10 the upper end of the resistor R 10 the lower end of the resistor R FB the feedback voltage input terminal V 4. The use according to claim 1, applied to V 2 A DC error correction circuit for COT-controlled DC / DC converter, characterized by, The secondary error amplifier A3 comprises: a PMOS tube P 12 a PMOS tube P 13 a PMOS tube P 14 a PMOS tube P 15 a PMOS tube P 16 a PMOS tube P 17 a PMOS tube P 18 a PMOS tube P 19 a NMOS tube N 11 a NMOS tube N 12 a NMOS tube N 13 a NMOS tube N 14 a NMOS tube N 15 a resistance R5, a resistance R6 Among them, ENP0 is the first enable signal input terminal, and ENN0 is the first enable inverted signal after ENP0 is inverted by inverter INV1; PMOS transistor P 12 The source of the PMOS transistor P 15 The source of the PMOS transistor P 16 The source of the PMOS transistor P 18 The sources of both transistors are connected to the power supply voltage VCC; PMOS transistor P 12 gate connected to V b3 PMOS transistor P 12 The drain of the PMOS transistor is connected to the upper end of resistor R5 and resistor R6; 13 The gate is connected to the output terminal V of the primary error amplifier A1. C1 PMOS transistor P 13 The source of the PMOS transistor is connected to the lower end of resistor R5; PMOS transistor P 13 The drain of the NMOS transistor is connected to the N. 11 The source of the NMOS transistor 12 The drain of the PMOS transistor; PMOS transistor P 14 The gate is connected to the bandgap voltage input terminal V. BG PMOS transistor P 14 The source of the PMOS transistor is connected to the lower end of resistor R6; 14 The drain of the NMOS transistor is connected to the N. 13 The source of the NMOS transistor 14 The drain of the PMOS transistor; PMOS transistor P 15 The gate of the PMOS transistor is connected to the first enable inverting signal ENN0; 15 The drain of the PMOS transistor is connected to P 16 The drain of the PMOS transistor P 17 The source of the PMOS transistor; PMOS transistor P 16 The gate and drain are connected together and connected to the PMOS transistor P. 18 The gate of the PMOS transistor; PMOS transistor P 17 The gate and drain are connected together and connected to the PMOS transistor P. 19 Gate of NMOS transistor 11 The drain of the PMOS transistor; PMOS transistor P 18 The drain of the PMOS transistor is connected to P 19 The source of the PMOS transistor; PMOS transistor P 19 The drain of the NMOS transistor is connected to the N. 13 drain of NMOS transistor N 15 The drain of the circuit is connected in parallel to the output terminal V of the secondary error amplifier. C2 NMOS transistor N 12 The source of the NMOS transistor 14 The source of the NMOS transistor 15 The source of the NMOS transistor is grounded to GND; 11 gate of the NMOS transistor N 13 gate of the NMOS transistor N b1 gate of the NMOS transistor N 12 gate of the NMOS transistor N 14 gate of the NMOS transistor N b2 gate of the NMOS transistor N 15 gate of the NMOS transistor N 5. The use according to claim 1, applied to V 2 A DC error correction circuit for COT-controlled DC / DC converter, characterized by, The reference voltage buffer A4 comprises: a PMOS tube P 27 a PMOS tube P 28 a PMOS tube P 29 a PMOS tube P 30 a PMOS tube P 31 a PMOS tube P 32 a PMOS tube P 33 a PMOS tube P 34 a NMOS tube N 31 a NMOS tube N 32 a NMOS tube N 33 a NMOS tube N 34 a NMOS tube N 35 a NMOS tube N 36 a NMOS tube N 37 a resistance R 11 a resistance R 12 a resistance R 13 a capacitor C3, a capacitor C4 Wherein, ENP0 is the first enable signal input end, ENN0 is the first enable inverse signal after the inversion of ENP0 by the inverter INV1; the source of PMOS tube P 27 , the source of PMOS tube P 30 , the source of PMOS tube P 31 , the upper end of resistance R 33 , the gate of PMOS tube P 11 is connected to V 27 ; the drain of PMOS tube P b3 is connected to the source of PMOS tube P 27 , the source of PMOS tube P 28 , the source of PMOS tube P 29 ; the gate of PMOS tube P 28 is connected to the source of NMOS tube N 35 , the drain of NMOS tube N 37 , the upper end of resistance R 12 , the left end of resistance R 13 , the upper end of capacitor C4; the drain of PMOS tube P 28 is connected to the source of NMOS tube N 31 , the drain of NMOS tube N 32 ; the gate of PMOS tube P 29 is connected to the reference voltage input end V ref ; the drain of PMOS tube P 29 is connected to the source of NMOS tube N 33 , the drain of NMOS tube N 34 ; the gate of PMOS tube P 30 is connected to the first enable signal ENP0; the drain of PMOS tube P 30 is connected to the drain of PMOS tube P 31 , the source of PMOS tube P 32 ; the gate and the drain of PMOS tube P 31 are connected together and connected to the gate of PMOS tube P 33 ; the gate and the drain of PMOS tube P 32 are connected together and connected to the gate of PMOS tube P 34 , the drain of NMOS tube N 31 ; the drain of PMOS tube P 33 is connected to the source of PMOS tube P 34 ; the drain of PMOS tube P 34 is connected to the drain of NMOS tube N 33 , the drain of NMOS tube N 36 , the gate of NMOS tube N 35 , the upper end of capacitor C3; the source of NMOS tube N 32 , the source of NMOS tube N 34 source of NMOS transistor N 36 source of NMOS transistor N 37 source of resistor R 12 lower end of NMOS transistor N 31 gate of NMOS transistor N 33 gate of NMOS transistor N b1 ; NMOS transistor N 32 gate of NMOS transistor N 34 gate of NMOS transistor N b2 ; NMOS transistor N 35 drain of NMOS transistor N 11 lower end of NMOS transistor N 36 gate of NMOS transistor N 37 gate of NMOS transistor N 13 right end of resistor R C2 output end V 6. The use according to claim 1, applied to V 2 A DC error correction circuit for COT-controlled DC / DC converter, characterized by, The unit gain drive buffer A5 comprises: PMOS P 35 , PMOS P 36 , PMOS P 37 , PMOS P 38 , PMOS P 39 , PMOS P 40 , PMOS P 41 , PMOS P 42 , PMOS P 43 , PMOS P 44 , PMOS P 45 , NMOS N 38 , NMOS N 39 , NMOS N 40 , NMOS N 41 , NMOS N 42 , NMOS N 43 , NMOS N 44 , NMOS N 45 , NMOS N 46 , NMOS N 47 , NMOS N 48 , resistance R 14 , resistance R 15 , resistance R 16 , resistance R 17 , resistance R 18 , capacitor C5, capacitor C6; Wherein, ENP0 is the first enable signal input end, ENN0 is the first enable inverse signal after the inversion of ENP0 by the inverter INV1; the source of PMOS tube P 36 , the source of PMOS tube P 37 , the source of PMOS tube P 38 , the source of PMOS tube P 41 , the source of PMOS tube P 42 , the source of PMOS tube P 44 , the upper end of resistor R 16 is connected to the power voltage VCC; the gate of PMOS tube P 35 is connected to the first enable inverse signal ENN0; the source of PMOS tube P 35 is connected to the second bias current input end I bias2 ; the drain of PMOS tube P 35 is connected to the gate of NMOS tube N 39 , the gate of NMOS tube N 41 , the upper end of resistor R 14 ; the gate of PMOS tube P 36 is connected to the first enable signal ENP0; the drain of PMOS tube P 36 is connected to the drain of PMOS tube P 37 , the source of NMOS tube N 41 ; the gate and the drain of PMOS tube P 37 are connected together and connected to the gate of PMOS tube P 38 ; the drain of PMOS tube P 38 is connected to the source of PMOS tube P 39 , the source of PMOS tube P 40 ; the gate of PMOS tube P 39 is connected to the source of NMOS tube N 48 , the upper end of resistor R 17 , the left end of resistor R 18 , the upper end of capacitor C6; the drain of PMOS tube P 39 is connected to the source of NMOS tube N 45 , the drain of NMOS tube N 46 ; the gate of PMOS tube P 40 is connected to the output end V C2 of the secondary error amplifier A3; the drain of PMOS tube P 40 is connected to the source of NMOS tube N 43 , the drain of NMOS tube N 44 ; the gate of PMOS tube P 41 is connected to the first enable signal ENP0; the drain of PMOS tube P 41 is connected to the drain of PMOS tube P 42 , PMOS tube P 43 The source of the PMOS transistor; PMOS transistor P 42 The gate and drain are connected together and connected to the PMOS transistor P. 44 The gate of the PMOS transistor; PMOS transistor P 43 The gate and drain are connected together and connected to the PMOS transistor P. 45 Gate of NMOS transistor 43 The drain of the PMOS transistor; PMOS transistor P 44 The drain of the PMOS transistor is connected to P 45 The source of the PMOS transistor; PMOS transistor P 45 The drain of the NMOS transistor is connected to the N. 45 drain of NMOS transistor N 47 drain of NMOS transistor N 48 Gate, resistor R 15 The upper end; NMOS transistor N 38 The source of the NMOS transistor 40 The source of the NMOS transistor 42 The source of the NMOS transistor 44 The source of the NMOS transistor 46 The source of the NMOS transistor 47 The source and resistor R 17 The lower ends of capacitors C5, C6, and C5 are all grounded to GND; NMOS transistor N 38 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 38 The drain of the NMOS transistor is connected to the N. 39 drain of NMOS transistor N 40 Gate of NMOS transistor 42 Gate, resistor R 14 The lower end; NMOS transistor N 39 The source of the NMOS transistor is connected to the N-terminal. 40 The drain of the NMOS transistor; 41 The gate of the NMOS transistor is connected to the N. 43 Gate of NMOS transistor 45 The gate of the NMOS transistor; 41 The source of the NMOS transistor is connected to the N-terminal. 42 The drain of the NMOS transistor; 42 The gate of the NMOS transistor is connected to the N. 44 Gate of NMOS transistor 46 The gate of the NMOS transistor; 47 The gate of the NMOS transistor is connected to the first enable inverting signal ENN0; 48 Drain resistor R 16 The lower end; resistor R 15 The lower end is connected to the upper end of capacitor C5; resistor R 18 The right end is connected to the final modulated voltage output terminal V. C .

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