High-density semiconductor device and preparation method thereof

Abstract

The invention relates to a high-density semiconductor device and a preparation method thereof. The high-density semiconductor device includes a substrate; a plurality of SRAM units, wherein the plurality of SRAM units are vertically stacked above the substrate in a stepped manner through a back-end process; each SRAM unit comprises two transistor combinations with symmetrical structures, and each transistor combination comprises a plurality of GAA transistors of various types which are arranged in parallel. Under the condition that the area of a chip is not increased, a plurality of SRAM units are vertically stacked above a substrate through a back-end process, the area of the substrate is not occupied, and the number of the SRAM units is increased, so that the storage density of the chip is increased, the capacity of the chip is improved, and the overall performance of the semiconductor device is further improved; furthermore, the SRAM unit is composed of multiple types of GAA transistors, higher electrical performance and integration level can be provided, and the stability and reliability of the whole structure are improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, in particular, to a high-density semiconductor device and a preparation method thereof. BACKGROUND

[0002] Static random access memory (SRAM) is a main data cache device in logic chips such as CPUs and MCUs, and the capacity thereof directly affects the data processing bandwidth and computing speed. In the related art, the area ratio of SRAM in a CPU logic chip has reached about 30-50%, and in the face of the increasing computing demand of logic chips, the existing process is difficult to increase the total number of SRAM on the logic chip by reducing the area of a single SRAM, and can only increase the area of the logic chip to achieve the purpose of expansion, but this conflicts with the development trend of reducing the overall area of the logic chip, limiting the further improvement of the performance of the chip. SUMMARY

[0003] The main purpose of the present disclosure is to provide a high-density semiconductor device and a preparation method thereof, aiming at solving the above technical problems.

[0004] According to a first aspect of an embodiment of the present disclosure, a high-density semiconductor device is provided, comprising: a substrate; a plurality of SRAM units vertically stacked in a stepped manner above the substrate through a back-end-of-line (BEOL) process; each of the SRAM units comprises two structurally symmetrical transistor combinations, and each of the transistor combinations comprises a plurality of parallelly arranged GAA transistors of multiple types.

[0005] Optionally, the transistor combination comprises: one P-type transistor and two N-type transistors; or one P-type transistor and three N-type transistors.

[0006] Optionally, at least five SRAM units are included above the substrate.

[0007] Optionally, the semiconductor device further comprises an interconnection metal layer and a peripheral component located below the substrate. The interconnection metal layer is used to connect the peripheral component and the SRAM unit. The peripheral component comprises at least one of a non-SRAM logic device, a logic device, and a logic circuit.

[0008] Optionally, each of the SRAM units further comprises an interlocking metal layer. The interlocking metal layer is used to connect the transistor combination in the SRAM cell.

[0009] Optionally, the gate oxide layer in the transistor is either ISSG oxide or furnace tube oxide; The gate electrode in the transistor is doped polycrystalline silicon.

[0010] According to a second aspect of the present disclosure, a method for fabricating a high-density semiconductor device is provided. The method is used to fabricate the semiconductor device described in the first aspect above, and the method includes: Using a multilayer stacking technique, ISSG oxide or furnace tube oxide and doped polysilicon are repeatedly deposited on a substrate to form a multilayer stacked oxide layer and polysilicon layer; wherein the number of repeated depositions is determined based on the number of vertically stacked SRAM cells in the semiconductor device. Using photolithography and etching techniques, multiple channel holes are generated in the multilayered, repeatedly stacked oxide and polysilicon layers to form multiple parallel-arranged GAA transistors of various types in the SRAM cell; The contact points of the polysilicon gate line in the GAA transistor are formed and cut off by a stepped process. Using back-end processes, an interconnect metal layer and an interlock metal layer are formed on the substrate, and the semiconductor device is packaged therein; wherein the interconnect metal layer is used to connect the SRAM cells and peripheral components; and the interlock metal layer is used to connect the transistor combinations in each SRAM cell.

[0011] Optionally, after generating a plurality of channel holes in the multilayered, repeatedly stacked oxide and polysilicon layers, the method further includes: Phosphorus-doped polycrystalline silicon is used as the initial material for each of the channel holes; wherein, a portion of the channel holes are used as channel holes for N-type transistors to generate the N-type transistors; Another portion of the channel holes in each of the aforementioned channels are reverse-doped with boron to generate P-type transistors.

[0012] Optionally, after generating a plurality of channel holes in the multilayered, repeatedly stacked oxide and polysilicon layers, the method further includes: Undoped polycrystalline silicon was used as the initial material for each of the aforementioned channel holes; A portion of the channel holes in each of the aforementioned channel holes is N-type doped to generate the N-type transistor; Another portion of the channel holes in each of the aforementioned channel holes are P-type doped to generate the P-type transistor.

[0013] Alternatively, the SRAM cell and the peripheral components can be integrated using the following method: The peripheral components are fabricated on the substrate using CMOS technology; or; The fabricated peripheral components are stacked under the substrate, and the peripheral components and the SRAM cells are integrated using TSV and Hybrid bonding processes.

[0014] The technical solutions proposed in this disclosure increase the number of SRAM cells by vertically stacking multiple SRAM cells on the substrate through back-end processes without increasing the chip area, thus increasing the chip's storage density, improving chip capacity, and ultimately enhancing the overall performance of the semiconductor device. Furthermore, the SRAM cells are composed of various types of GAA transistors, which can provide higher electrical performance and integration, and increase the stability and reliability of the overall structure.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a circuit diagram of an SRAM cell.

[0017] Figure 2 This is a planar schematic diagram of an SRAM cell according to an exemplary embodiment.

[0018] Figure 3 This is a cross-sectional layer schematic diagram of the right side of a semiconductor device formed by stacking three layers of SRAM cells, according to an exemplary embodiment.

[0019] Figure 4 This is a flowchart illustrating a method for fabricating a high-density semiconductor device according to an exemplary embodiment. Detailed Implementation

[0020] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0021] Figure 1 This is a circuit diagram of an SRAM cell. (Example) Figure 1As shown, this SRAM cell has a 6T structure, consisting of six transistors: PU1, PU2, PD1, PD2, PG1, and PG2. PU1 and PD1 form an inverter with a storage node of SNL (Storage Node Left), while PU2 and PD2 form an inverter with a storage node of SNR (Storage Node Right). The two inverters form an interlocked structure. Under the control of the word line (WL), PG1 and PG2 respectively control the data transmission between SNL and the bit line (BL), and between SNR and the complementary bit line bar (BLB), to achieve read and write operations.

[0022] Specifically, among the transistors mentioned above, PU1 and PU2 are P-type transistors connected to the power supply voltage Vdd, and are therefore also called pull-up transistors (PU); PD1 and PD2 are N-type transistors connected to the ground line GND, and are therefore also called pull-down transistors (PD); PG1 and PG2 are N-type transistors connected to WL and BL or BLB to control the reading or writing of data, and are therefore also called pass gate transistors (PG).

[0023] It's easy to understand that different SRAM cells composed of the same number of transistors can have the same circuit diagram but different layout designs and different physical structures. Below, we will combine... Figure 2 and Figure 3 The layout structure of the semiconductor devices and SRAM cells in the embodiments of this disclosure is described.

[0024] This disclosure provides a high-density semiconductor device, comprising: a substrate; a plurality of SRAM cells, each SRAM cell including a combination of two symmetrically structured transistors.

[0025] In one embodiment of this disclosure, a 6T SRAM cell structure is used as an example. Figure 2 This is a planar schematic diagram of an SRAM cell according to an exemplary embodiment. Figure 2As shown, a single SRAM comprises transistor combination 1 and transistor combination 2, which are symmetrically structured. Furthermore, each transistor combination includes multiple parallel-arranged GAA transistors of various types. GAA transistors are Gate-All-Around transistors, where the gate material completely surrounds the channel region. This allows GAA transistors to better control the current in the channel, resulting in higher gate control capability, higher performance, and lower power consumption. Simultaneously, this structure makes the GAA transistors relatively small, which is beneficial for improving the overall storage density of the semiconductor device.

[0026] It is readily understood, as can be seen from the fabrication method of the high-density semiconductor device in the following embodiments, that each GAA transistor is perpendicular to the horizontal plane of the substrate, and therefore the GAA transistors are parallel to each other. In three-dimensional space, the GAA transistors can be arranged vertically on the horizontal plane of the substrate in various ways. For example, the GAA transistors can be located on the same vertical plane, or the GAA transistors can be located on multiple different vertical planes, i.e., arranged in a staggered manner. The specific arrangement method can be set according to wiring requirements and other factors, and this disclosure does not limit it.

[0027] Furthermore, given the symmetrical structure of the two transistor combinations in the SRAM cell of the present disclosure embodiment, to avoid repetitive description, the layout structure of the semiconductor device and SRAM cell can be described using the transistor combination on one side as an example. Figure 3 This is a cross-sectional schematic diagram of the right side of a semiconductor device formed by stacking three layers of SRAM cells, according to an exemplary embodiment. Figure 3 As shown, SRAM1, SRAM2, and SRAM3 are vertically stacked in a stepped manner on top of the substrate, which can be achieved through back-end processing (BEOL). This stepped layout design avoids signal interference between the stacked SRAM cells during data transmission, ensuring the overall performance of the semiconductor device. This structure also facilitates the formation of stepped contact landing pads, allowing power or electrical signals for each SRAM to be connected to the metal layer above. Furthermore, the vertical stacking design not only increases the number of memory cells but also allows for more complex circuit designs within a limited space, thereby improving design flexibility and optimization space.

[0028] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: without increasing the chip area, multiple SRAM cells are vertically stacked on top of the substrate through back-end process (BEOL) without occupying the substrate area, thereby increasing the number of SRAM cells, thereby increasing the chip's storage density, improving the chip capacity, and thus improving the overall performance of the semiconductor device; furthermore, the SRAM cells are composed of various types of GAA transistors, which can provide higher electrical performance and integration, and increase the stability and reliability of the overall structure.

[0029] As an alternative implementation, the SRAM cell can be a 6T structure (single port) or an 8T structure (Dual port or two ports), that is, each transistor combination can include one P-type transistor (1PU) and two N-type transistors (1PD and 1PG); or, one P-type transistor (1PU) and three N-type transistors (1PD and 2PG).

[0030] As an optional implementation, at least five SRAM cells are included above the substrate. That is, five or more SRAM cells can be vertically stacked within the same wafer area.

[0031] As an alternative implementation, the semiconductor device further includes: an interconnect metal layer, and peripheral components located beneath the substrate.

[0032] In one embodiment of this disclosure, the peripheral components include at least one of non-SRAM logic devices, logic devices, and logic circuits, all located beneath the substrate. Figure 3 As shown, the semiconductor device also includes an interconnect metal layer for connecting signal lines and power lines between peripheral components and SRAM cells, enabling signal transmission between peripheral components and SRAM cells.

[0033] As an optional implementation, each SRAM cell also includes an interlocking metal layer (not shown in the figure).

[0034] In one embodiment of this disclosure, an interlocking metal layer is used to connect transistor combinations in the SRAM cell. This allows the SNL of the inverter in transistor combination 1 of each SRAM cell to be connected to the gates of PU2 and PD2 in the inverter of transistor combination 2; and the SNR of the inverter in transistor combination 2 to be connected to the gates of PU1 and PD1 in the inverter of transistor combination 1, thus achieving the above-described... Figure 1 Electrical connection of the two inverters.

[0035] As an optional implementation, the gate oxide layer in the transistor is either ISSG oxide or furnace tube oxide; the gate electrode in the transistor is doped polysilicon.

[0036] In one embodiment of this disclosure, ISSG oxide refers to oxides generated by the in-situ-steam-generation (ISSG) method, which have good interface characteristics and electrical properties; furnace tube oxide refers to oxide layers grown on the wafer surface by heating furnace tubes, and the most common furnace tube oxide is silicon dioxide (SiO2).

[0037] Doped polycrystalline silicon refers to a material formed by adding a small amount of dopants (such as phosphorus, boron, etc.) to polycrystalline silicon to adjust its conductivity. It has different conductivity properties and is used to make the gate electrode of P-type transistors or the gate electrode of N-type transistors based on the conductivity properties of doped polycrystalline silicon.

[0038] Figure 4 This is a flowchart illustrating a method for fabricating a high-density semiconductor device according to an exemplary embodiment. Figure 4 As shown, the preparation method is used to prepare the semiconductor device in the above embodiments and may include the following steps S401-S404.

[0039] In S401, ISSG oxide or furnace tube oxide and doped polysilicon are repeatedly deposited on the substrate using a multilayer stacking technique to form a multilayer stacked oxide layer and polysilicon layer.

[0040] In one embodiment of this disclosure, such as Figure 3 As shown, the number of repeated depositions is determined based on the number of SRAM cells vertically stacked in the semiconductor device.

[0041] In some embodiments, in addition to ISSG oxide and furnace tube oxide, the oxide layer may also be formed of TEOS (tetraethoxysilane) oxide; the polycrystalline silicon layer may also be formed of highly doped polycrystalline silicon.

[0042] Specifically, TEOS oxide (thickness can be 200A-600A), highly doped polysilicon (thickness can be 200A-400A), TEOS oxide (thickness can be 200A-600A), highly doped polysilicon (thickness can be 200A-400A), and TEOS oxide (thickness can be 200A-600A) are deposited sequentially on the substrate in the following order to form a vertical structure layer of SRAM 1; wherein, the highly doped polysilicon in the second layer can serve as the drain of the transistors to be formed later, and the highly doped polysilicon in the fourth layer can serve as the gate of the transistors to be formed later.

[0043] In S402, multiple channel holes are generated in the multilayer repeated stacked oxide and polysilicon layers using photolithography and etching techniques to form multiple parallel-arranged GAA transistors of various types in the SRAM cell.

[0044] In one embodiment of this disclosure, lithography is used to define patterns on multiple oxide layers and polysilicon layers using a photosensitive material (photoresist); etching is used to remove the oxide layer and polysilicon layer under the photoresist protective layer to form the desired channel holes.

[0045] Specifically, photoresist can be first coated onto the surface of the stacked layers, and then a pattern can be transferred onto the photoresist using ultraviolet light or other light sources. After the photoresist is exposed, an unexposed area is removed through a development process, thus forming the desired pattern on the photoresist layer. These patterns determine the areas that need to be retained and removed during subsequent etching. Then, based on the photolithographic pattern, the etching process removes excess material, leaving only the desired structure.

[0046] Vertical channel holes can be created in each stacked layer through photolithography and etching. Different types of gate electrode materials can then be injected into the channel holes to form different types of GAA transistors, thereby achieving vertical arrangement and layout of different types of GAA transistors in a multilayer structure.

[0047] Furthermore, the critical dimension (CD) of the channel aperture of a GAA transistor can be individually adjusted according to actual needs to meet its electrical performance requirements. For example... Figure 3 As shown, taking a cross-section of a PU2 as an example, the thickness of the polysilicon in the innermost channel hole can be 100A-300A, the middle layer is a thinner oxide dielectric layer (gate oxide) with a thickness of 25A-60A, and the thickness of the polysilicon in the outermost gate can be 300A-600A.

[0048] In some embodiments, after forming multiple channel holes in the multilayered, repeatedly stacked oxide and polysilicon layers in S402, an oxide dielectric layer (with a thickness of 25-60 Å) can be grown on the outside of the doped polysilicon exposed inside the channel holes using an ISSG process. Excess polysilicon above the channel holes can be removed by polysilicon etching to form a flat surface. Then, polysilicon materials with different conductivity properties are filled into the channel holes to form channels for vertical transistors, thereby forming N-type and P-type transistors (the specific formation methods are described in detail in the embodiments below). Next, a tungsten (W) layer (with a thickness of 300 Å-600 Å) can be deposited on top of the repeatedly stacked oxide and polysilicon layers. Then, a set of metal layer photolithography and dry etching processes are used to process the tungsten layer to form the bit lines, VDD, GND and other signal lines and power lines of the SRAM. Then, the above multilayer thin film deposition steps, photolithography and dry etching steps can be repeated to form the vertical structure layers of SRAM2, SRAM3, and subsequent vertical structure layers of more SRAM cells.

[0049] In S403, the contacts of the polysilicon gate line in the GAA transistor are formed and cut off through a stepped process.

[0050] In one embodiment of this disclosure, a staircase process refers to a process in semiconductor manufacturing where different structural layers are formed layer by layer. This process typically involves progressively adding or removing material to form the desired circuit structure and connections layer by layer.

[0051] Specifically, the specific locations within the transistor used for electrical connections, i.e., contact points, are first identified. These contact points are then cut using etching or other processing methods, ensuring electrical isolation or precise connection between the polysilicon gate line, bit line, VDD, and GND power supply and other components, thereby optimizing the transistor's performance and electrical characteristics. Finally, stepped contact steps are formed for each SRAM cell, connecting to the interconnect metal layer above through their respective contact holes.

[0052] In S404, back-end processes are used to form interconnect metal layers and interlock metal layers on the substrate and to package semiconductor devices.

[0053] In one embodiment of this disclosure, back-end processing (BEOL) refers to the interconnection and packaging steps performed after the front-end processes (such as the formation of transistors and circuit layers) are completed during the manufacturing process of semiconductor devices. This includes metal layer deposition, patterning, etching, and final packaging. Specifically, on the surface of the aforementioned multilayered stacked oxide and polysilicon layers, a metal layer (with a thickness of 300 Å-600 Å) is deposited upwards. Then, using photolithography and dry etching processes, a circuit layout structure (pattern) is formed on the surface of the metal layer to form the word lines, bit lines, and other line connections of each SRAM. In this embodiment, the metal layers generated by the back-end process mainly include interconnect metal layers for connecting SRAM cells and peripheral components, and interlocking metal layers for connecting transistor combinations in each SRAM cell. It may also include... Figure 3 The metal layers shown are used to connect VDD1-VDD3, GND1-GND3, and BLB1-BLB3.

[0054] For example, the material of each of the above metal layers can be tungsten (W).

[0055] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: without increasing the chip area, multiple SRAM cells are vertically stacked on the substrate through back-end processes, without occupying the substrate area, thereby increasing the number of SRAM cells, thereby increasing the chip's storage density, improving the chip capacity, and thus improving the overall performance of the semiconductor device; furthermore, the SRAM cells are composed of various types of GAA transistors, which can provide higher electrical performance and integration, and increase the stability and reliability of the overall structure.

[0056] As an optional implementation, after generating multiple channel holes in the multilayered, repeatedly stacked oxide and polysilicon layers in S402, N-type and P-type transistors can be generated by either method one or method two.

[0057] Method 1: Use phosphorus-doped polycrystalline silicon as the initial material for each channel hole; wherein, a portion of the channel holes are used as channel holes for N-type transistors to generate N-type transistors; and another portion of the channel holes are reverse-doped with boron to generate P-type transistors.

[0058] In one embodiment of this disclosure, phosphorus-doped polysilicon has N-type conductivity, making it suitable for forming N-type transistors. A portion of these channel holes is used as channel holes for N-type transistors. Since the phosphorus-doped polysilicon already possesses N-type conductivity, these holes will be directly used to form N-type transistors. Then, another portion of the channel holes undergoes boron reverse doping implantation. Boron reverse doping refers to the process of implanting P-type impurities (such as boron) into regions already doped with N-type impurities (such as phosphorus) during semiconductor manufacturing to partially offset or neutralize the effect of N-type doping, thereby adjusting the electrical properties of the material. In this way, the polysilicon in this portion of the channel holes can be converted from N-type conductivity to P-type conductivity, and these holes can be used to generate P-type transistors.

[0059] Method 2: Use undoped polysilicon as the initial material for each channel hole; perform N-type doping on a portion of the channel holes to generate N-type transistors; perform P-type doping on the other portion of the channel holes to generate P-type transistors.

[0060] In one embodiment of this disclosure, undoped polysilicon is first used as the initial material in the channel holes. This undoped polysilicon can be doped with the corresponding material as needed to form transistors of the desired type. Then, a portion of the channel holes is N-type doped (e.g., by introducing phosphorus), which makes these holes N-type conductive for generating N-type transistors. And another portion of the channel holes is P-type doped (e.g., by introducing boron), which makes these holes P-type conductive for generating P-type transistors.

[0061] As an optional implementation, the above method further includes: integrating the SRAM cell and peripheral components through method three or method four as follows: Method 3: Use CMOS technology to fabricate peripheral components under a substrate.

[0062] In one embodiment of this disclosure, CMOS (Complementary Metal-Oxide-Semiconductor) technology is widely used in the manufacture of integrated circuits. It can simultaneously fabricate N-type and P-type transistors and utilize these transistors to build complex circuits, including peripheral components.

[0063] Specifically, peripheral components are fabricated under a substrate using CMOS processes. This typically involves steps such as deposition, photolithography, etching, and doping to form various circuits and functional modules, such as amplifiers, data converters, or control circuits.

[0064] In this way, multilayer SRAM cells above the substrate and peripheral components below the substrate can be fabricated simultaneously to achieve integration of the two.

[0065] Method 4: Stack the fabricated peripheral components under the substrate and integrate the peripheral components and SRAM cells using TSV and Hybrid bonding processes.

[0066] In one embodiment of this disclosure, the multilayer SRAM cells and peripheral components described in the above embodiments can be fabricated on two substrates respectively. Then, the peripheral components are stacked under the substrate of the SRAM cells and wafer-level stacking is performed using TSV and Hybridbonding processes to integrate the two into a complete chip.

[0067] TSV refers to Through-Silicon Via technology, which can create vertical interconnects between chips and wafers to achieve chip interconnection; Hybrid bonding refers to hybrid bonding technology, which can interconnect two or more different wafers with metal to achieve three-dimensional integration.

[0068] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0069] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0070] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A high-density semiconductor device, characterized by comprising: Comprising: a substrate; a plurality of SRAM cells vertically stacked in a stepped manner above the substrate by a back end of line (BEOL) process; each of the SRAM cells comprising two structurally symmetric transistor combinations, the transistor combinations comprising a plurality of parallelly arranged GAA transistors of multiple types.

2. The semiconductor device according to claim 1, wherein The transistor combinations comprise: one P-type transistor and two N-type transistors; or, one P-type transistor and three N-type transistors.

3. The semiconductor device of claim 1, wherein The substrate comprises at least five of the SRAM cells above the substrate.

4. The semiconductor device of claim 1, wherein The semiconductor device further comprises: an interconnection metal layer, and, a peripheral component below the substrate; wherein the interconnection metal layer is used to connect the peripheral component and the SRAM cells; The peripheral component comprises at least one of a non-SRAM logic device, a logic device, and a logic circuit.

5. The semiconductor device of claim 1, wherein Each of the SRAM cells further comprises: an interlocking metal layer; The interlocking metal layer is used to connect the transistor combinations in the SRAM cell.

6. The semiconductor device of claim 1, wherein The gate oxide layer in the transistor is any one of an ISSG oxide or a furnace tube oxide; The gate electrode in the transistor is doped polysilicon.

7. A method of fabricating a high-density semiconductor device, comprising: The method is used to prepare the semiconductor device of any one of claims 1-6, the method comprising: repeatedly depositing an ISSG oxide or a furnace tube oxide, and doped polysilicon, above the substrate by a multi-layer stacking technique to form a multi-layer repeatedly stacked oxide layer and polysilicon layer; wherein the number of repeated deposition is determined based on the number of vertically stacked SRAM cells in the semiconductor device; generating a plurality of channel holes in the multi-layer repeatedly stacked oxide layer and polysilicon layer by a photolithography and etching technique to form a plurality of parallelly arranged GAA transistors of multiple types in the SRAM cells; forming and cutting contact points of the polysilicon gate lines in the GAA transistors by a stepped process; forming an interconnection metal layer and an interlocking metal layer above the substrate by a back end of line (BEOL) process, and packaging the semiconductor device; wherein the interconnection metal layer is used to connect the SRAM cells and a peripheral component; and the interlocking metal layer is used to connect the transistor combinations in each SRAM cell.

8. The method of claim 7, wherein, After the generating a plurality of channel holes in the multi-layer repeatedly stacked oxide layer and polysilicon layer, the method further comprises: using phosphorus-doped polysilicon as the initial material for each of the channel holes; wherein a portion of the channel holes are used as channel holes for N-type transistors to generate the N-type transistors; performing boron counter-doping implantation on another portion of the channel holes to generate P-type transistors.

9. The method of claim 7, wherein, After the generating a plurality of channel holes in the multi-layer repeatedly stacked oxide layer and polysilicon layer, the method further comprises: using undoped polysilicon as the initial material for each of the channel holes; performing N-type doping on a portion of the channel holes to generate the N-type transistors; performing P-type doping on another portion of the channel holes to generate the P-type transistors.

10. The method of claim 7, wherein, The method further comprises: integrating the SRAM cells and the peripheral component by the following method: The peripheral component is prepared under the substrate by using a CMOS process; Or; The prepared peripheral component is stacked under the substrate, and the peripheral component and the SRAM unit are integrated by using a TSV process and a Hybrid bonding process.

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