Multi-time programmable memory and manufacturing method, writing method and erasing method thereof

Abstract

The invention provides a multi-time programmable memory and a manufacturing method, a writing method and an erasing method thereof.The multi-time programmable memory comprises an erasing gate oxide layer and an erasing gate, the erasing gate oxide layer covers the side wall, away from a first floating gate, of a second floating gate and extends to cover a floating gate oxide layer of a part of an NMOS device area, the erasing gate is located on the erasing gate oxide layer, and the erasing gate is located on the erasing gate oxide layer; and the erase gate and the second floating gate are isolated from each other through the erase gate oxide layer. Therefore, writing can be performed from the floating gate oxide layer, and erasing can be performed from the erasing gate oxide layer by using the erasing gate during erasing, so that repeated writing and erasing on the same floating gate oxide layer are avoided, the use frequency of the floating gate oxide layer is reduced, the damage rate of the floating gate oxide layer is slowed down, and the effective service life of the memory is prolonged; and the erasing is performed by adopting the erasing gate oxide layer, so that the thickness of the erasing gate oxide layer can be designed according to the voltage applied to the erasing gate subsequently, the voltage resistance of the erasing gate oxide layer is improved, and the erasing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multiple programmable memory and its manufacturing, writing, and erasing methods. Background Technology

[0002] Memory is a crucial component of digital integrated circuits and an indispensable part of building microprocessor-based application systems. In recent years, various types of memory have been embedded within processors to improve their integration and efficiency. Multi-Time Programmable Memory (MTP) retains data even after power loss and, compared to One-Time Programmable Memory (OTP), offers the advantage of allowing multiple write, read, and erase operations, making it a widely adopted memory device in personal computers, electronic devices, and mobile storage. However, traditional MTP devices require the same floating gate oxide layer for programming and erasing. Repeated writes and erases damage this layer, affecting its quality. Furthermore, the shared floating gate oxide layer limits the operating voltage during erasure, impacting the erasure speed. Summary of the Invention

[0003] The purpose of this invention is to provide a multiple programmable memory and its manufacturing, writing, and erasing methods to reduce the frequency of use of the floating gate oxide layer and increase the number of write cycles and erasing efficiency of the device.

[0004] To solve the above-mentioned technical problems, the present invention provides a multiple-programmable memory, comprising:

[0005] Semiconductor substrate, including PMOS device region and NMOS device region;

[0006] A floating gate oxide layer covers the PMOS device region and the NMOS device region;

[0007] A first floating gate and a second floating gate are formed on the floating gate oxide layer. The first floating gate is formed in the PMOS device region, and the second floating gate is formed in the NMOS device region. The first floating gate and the second floating gate are electrically connected.

[0008] The erase gate oxide layer and the erase gate are provided. The erase gate oxide layer covers the sidewall of the second floating gate away from the first floating gate and extends to cover a portion of the NMOS device region. The erase gate is formed on the erase gate oxide layer and is isolated from the second floating gate by the erase gate oxide layer.

[0009] Optionally, in the aforementioned multiple programmable memory, the thickness of the erase gate oxide layer is greater than the thickness of the floating gate oxide layer.

[0010] Optionally, in the aforementioned multiple programmable memory, the multiple programmable memory further includes:

[0011] A well region is formed in the PMOS device region;

[0012] Sidewalls are formed on both sides of the first floating grid, on the sidewall of the second floating grid near the first floating grid, and on the sidewall of the erase grid away from the second floating grid;

[0013] The first source region and the first drain region are respectively formed in the PMOS device regions on both sides of the first floating gate;

[0014] The second source region and the second drain region are respectively formed in the NMOS device regions on both sides of the second floating gate.

[0015] Based on the same inventive concept, the present invention also provides a method for manufacturing a multiple-programmable memory, comprising:

[0016] A semiconductor substrate is provided, the semiconductor substrate including a PMOS device region and an NMOS device region;

[0017] A floating gate oxide layer and a floating gate material layer are sequentially formed on the semiconductor substrate, wherein the floating gate oxide layer covers the PMOS device region and the NMOS device region;

[0018] Etch the floating gate material layer to expose a portion of the floating gate oxide layer in the NMOS device region;

[0019] An erase gate oxide layer and an erase gate material layer are formed sequentially. The erase gate oxide layer covers the exposed floating gate oxide layer and extends to cover the sidewall of the floating gate material layer located in the NMOS device region and the top surface of the floating gate material layer. The erase gate material layer covers the erase gate oxide layer.

[0020] A chemical mechanical polishing process is performed to remove the erase gate oxide material layer and the erase gate material layer on the top surface of the floating gate material layer, and the remaining erase gate oxide material layer constitutes the erase gate oxide layer;

[0021] The erase gate material layer and the floating gate material layer are etched to form an erase gate, a first floating gate and a second floating gate, respectively. The first floating gate is formed in the PMOS device region and the second floating gate is formed in the NMOS device region. The second floating gate is electrically connected to the first floating gate and the erase gate and the second floating gate are isolated from each other by the erase gate oxide layer.

[0022] Optionally, in the manufacturing method of the multiple programmable memory, the method of etching the erase gate material layer and the floating gate material layer includes:

[0023] A patterned photoresist layer is formed on the floating gate material layer and the erase gate material layer, the patterned photoresist layer covering a portion of the floating gate material layer in the PMOS device region, a portion of the floating gate material layer in the NMOS device region, and a portion of the erase gate material layer closest to the floating gate material layer;

[0024] Using the patterned photoresist layer as a mask, the erase gate material layer and the floating gate material layer are etched to form the erase gate, the first floating gate, and the second floating gate, respectively; and,

[0025] Remove the patterned photoresist layer.

[0026] Optionally, in the manufacturing method of the multiple programmable memory, the erase gate oxide material layer is made of silicon oxide and is formed by thermal oxidation or chemical vapor deposition.

[0027] Optionally, in the manufacturing method of the multiple programmable memory, the erase gate material layer is made of polycrystalline silicon and is formed by furnace tube process.

[0028] Optionally, in the method for manufacturing the multiple programmable memory, the method further includes:

[0029] Sidewalls are formed on both sides of the first floating grid, on the sidewall of the second floating grid near the first floating grid, and on the sidewall of the erase grid away from the second floating grid.

[0030] Using the sidewall as a mask, a first ion implantation process is performed to form a first source region and a first drain region, the first source region and the first drain region being formed in the PMOS device regions on both sides of the first floating gate, respectively; and,

[0031] Using the sidewall as a mask, a second ion implantation process is performed to form a second source region and a second drain region, which are respectively formed in the NMOS device regions on both sides of the second floating gate.

[0032] Based on the same inventive concept, the present invention also provides a method for writing a multiple programmable memory as described above, wherein the memory further includes a second source region and a second drain region, the second source region and the second drain region being respectively formed in the NMOS device regions on both sides of the second floating gate, and the method for writing the multiple programmable memory includes:

[0033] A first voltage is applied to the second floating gate, and a second voltage, less than the first voltage, is applied to the second source region and the second drain region to inject negatively charged electrons into the second floating gate and the first floating gate to achieve the write operation, wherein the write operation is performed from the floating gate oxide layer.

[0034] Based on the same inventive concept, the present invention also provides an erasure method for a multiple-programmable memory as described above, comprising:

[0035] A positive voltage is applied to the erase gate, and a negative voltage is applied to the first floating gate and the second floating gate to remove electrons stored in the second floating gate and the first floating gate to achieve the erasure, wherein the erasure operation is performed from the erase gate oxide layer.

[0036] In the multiple programmable memory provided by this invention, the multiple programmable memory includes an erase gate oxide layer and an erase gate. The erase gate oxide layer covers the sidewall of the second floating gate away from the first floating gate and extends to cover a portion of the NMOS device region. The erase gate is formed on the erase gate oxide layer, and the erase gate and the second floating gate are isolated from each other by the erase gate oxide layer. Thus, writing to the multiple programmable memory can be performed from the floating gate oxide layer, and erasing can be performed from the erase gate oxide layer using the erase gate. This avoids repeated writing and erasing of the same floating gate oxide layer, reduces the usage frequency of the floating gate oxide layer, reduces the number of times the floating gate oxide layer is used, and slows down the rate at which the floating gate oxide layer is damaged, thereby increasing the number of write cycles and thus improving the effective lifespan of the memory. Furthermore, since the erasure operation is performed using the erase gate oxide layer, the thickness of the erase gate oxide layer can be designed according to the voltage subsequently applied to the erase gate to improve the voltage withstand capability of the erase gate oxide layer, thereby improving the erasure efficiency. Attached Figure Description

[0037] Figure 1 This is a schematic cross-sectional view of the structure of the multiple programmable memory provided in an embodiment of the present invention;

[0038] Figure 2 This is a flowchart illustrating the manufacturing method of a multiple programmable memory provided in an embodiment of the present invention;

[0039] Figures 3-9 This is a schematic cross-sectional view of the structure formed in the manufacturing method of the multiple programmable memory provided in the embodiment of the present invention;

[0040] Figure 10 This is a top view after the formation of the first floating gate and the second floating gate in the manufacturing method of the multiple programmable memory provided in the embodiment of the present invention;

[0041] Figure 11 It is along Figure 10 A schematic diagram of the cross-sectional structure along the AA' direction;

[0042] The reference numerals in the attached figures are explained as follows:

[0043] 100 - Semiconductor substrate; 100A - PMOS device region; 100B - NMOS device region; 101 - Shallow trench isolation structure; 102 - Well region; 110 - Floating gate oxide layer; 120 - Floating gate material layer; 121 - First floating gate; 122 - Second floating gate; 123 - Floating gate connection; 130 - Patterned mask layer; 140 - Erasing gate oxide material layer; 140a - Erasing gate oxide layer; 150 - Erasing gate material layer; 150a - Erasing gate; 160 - Patterned photoresist layer; 170 - Sidewall; 180a - First source region; 180b - First drain region; 190a - Second source region; 190b - Second drain region. Detailed Implementation

[0044] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed account of the multiple programmable memory and its manufacturing, writing, and erasing methods as proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0045] Figure 1 This is a schematic cross-sectional view of the structure of the multiple programmable memory provided in an embodiment of the present invention. Figure 1 As shown, the multiple programmable memory provided in this embodiment includes: a semiconductor substrate 100, a floating gate oxide layer 110, a first floating gate 121, a second floating gate 122, an erase gate oxide layer 140a, and an erase gate 150a.

[0046] In this embodiment, the semiconductor substrate 100 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 100 is a silicon substrate. The conductivity type of the semiconductor substrate 100 can be P-type.

[0047] The semiconductor substrate 100 includes a PMOS device region 100A and an NMOS device region 100B. The PMOS device region 100A of the semiconductor substrate 100 is used to form a PMOS device, and the NMOS device region 100B is used to form an NMOS device. A shallow trench isolation structure 101 is formed between the PMOS device region 100A and the NMOS device region 100B, and a well region 102 is formed in the PMOS device region 100A. The conductivity type of the well region 102 is N-type.

[0048] like Figure 1 As shown, the floating gate oxide layer 110 covers the PMOS device region 100A and the NMOS device region 100B. The material of the floating gate oxide layer 110 is, for example, silicon dioxide (SiO2).

[0049] Continue to refer to Figure 1 A first floating gate 121 and a second floating gate 122 are formed on the floating gate oxide layer 110. The first floating gate 121 is formed in the PMOS device region 100A. The second floating gate 122 is formed in the NMOS device region 100B, and the first floating gate 121 and the second floating gate 122 are electrically connected. The first floating gate 121 and the second floating gate 122 are made of the same material, namely polysilicon or doped polysilicon. The first floating gate 121 and the second floating gate 122 serve as electron storage layers. During write operations, electrons can be injected into the first floating gate 121 and the second floating gate 122 using the channel hot electron injection (CHEI) effect.

[0050] In this embodiment, the erase gate oxide layer 140a is located on the side of the second floating gate 122 away from the first floating gate 121. The erase gate oxide layer 140a covers the sidewall of the second floating gate 122 away from the first floating gate 121 and extends to cover part of the floating gate oxide layer 110 of the NMOS device region 100B. That is, the shape of the erase gate oxide layer 140a is L-shaped.

[0051] like Figure 1 As shown, the erase gate 150a is formed on the erase gate oxide layer 140a. Specifically, the erase gate 150a is formed in the NMOS device region 100B and is located on the erase gate oxide layer 140a of the NMOS device region 100B. That is, the erase gate 150a is located on the side of the second floating gate 122 away from the first floating gate 121, and the erase gate 150a and the second floating gate 122 are isolated from each other by the erase gate oxide layer 140a. The erase gate 150a is isolated from the NMOS device region by the erase gate oxide layer 140a and the floating gate oxide layer 110.

[0052] During the erase operation, the erase gate 150a can be used to erase electrons in the second floating gate 122. Utilizing the FN (Fowler-Nordheim) tunneling effect, electrons in both the second and first floating gates 122 pass through the erase gate oxide layer 140a and are moved into the erase gate 150a, thus achieving erasure. This avoids repeated writing and erasing of the same floating gate oxide layer 110, reducing its usage frequency and slowing down the rate of damage. This reduces the number of times the floating gate oxide layer is used, improving the effective lifespan of the memory. Furthermore, since erasure is performed using the erase gate oxide layer 140a, its thickness can be designed based on the voltage subsequently applied to the erase gate 150a to improve its withstand voltage and thus increase erasure efficiency.

[0053] like Figure 1 As shown, the multiple programmable memory provided in this embodiment also includes sidewalls 170, which are formed on both sides of the first floating gate 121, the sidewall of the second floating gate 122 near the first floating gate 121, and the sidewall of the erase gate 150a away from the second floating gate 122.

[0054] Continue to refer to Figure 1 The multiple programmable memory provided in this embodiment further includes a first source region 180a, a first drain region 180b, a second source region 190a, and a second drain region 190b. The first source region 180a and the first drain region 180b are respectively formed in the PMOS device region 100A on both sides of the first floating gate 121. Both the first source region 180a and the first drain region 180b have P... + ion.

[0055] The second source region 190a and the second drain region 190b are respectively formed in the NMOS device regions 100B on both sides of the second floating gate 122. Both the second source region 190a and the second drain region 190b have N... + ion.

[0056] Figure 2 This is a schematic flowchart of a method for manufacturing a multiple programmable memory provided in an embodiment of the present invention.

[0057] like Figure 2 As shown, the manufacturing method of the multiple programmable memory provided in this embodiment includes:

[0058] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a PMOS device region and an NMOS device region;

[0059] Step S2: A floating gate oxide layer and a floating gate material layer are sequentially formed on the semiconductor substrate, wherein the floating gate oxide layer covers the PMOS device region and the NMOS device region;

[0060] Step S3: Etch the floating gate material layer to expose a portion of the floating gate oxide layer in the NMOS device region;

[0061] Step S4: Sequentially form an erase gate oxide layer and an erase gate material layer. The erase gate oxide layer covers the exposed floating gate oxide layer and extends to cover the sidewall of the floating gate material layer located in the NMOS device region and the top surface of the floating gate material layer. The erase gate material layer covers the erase gate oxide layer.

[0062] Step S5: Perform a chemical mechanical polishing process to remove the erase gate oxide material layer and the erase gate material layer on the top surface of the floating gate material layer, and the remaining erase gate oxide material layer constitutes the erase gate oxide layer;

[0063] Step S6: Etch the erase gate material layer and the floating gate material layer to form an erase gate, a first floating gate and a second floating gate, respectively. The first floating gate is formed in the PMOS device region and the second floating gate is formed in the NMOS device region. The second floating gate is electrically connected to the first floating gate and the erase gate and the second floating gate are isolated from each other by the erase gate oxide layer.

[0064] Figures 3-9 This is a schematic cross-sectional view of the structure formed in the manufacturing method of the multiple programmable memory provided in the embodiment of the present invention; Figure 10 This is a top view after the formation of the first floating gate and the second floating gate in the manufacturing method of the multiple programmable memory provided in the embodiment of the present invention; Figure 11 It is along Figure 10 A schematic diagram of the cross-sectional structure along the AA' direction is shown below. The following will refer to the attached diagram. Figures 3 to 11 The manufacturing method of the multiple programmable memory provided in the embodiments of the present invention will be described in more detail.

[0065] First, refer to Figure 3 In step S1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a PMOS device region 100A and an NMOS device region 100B; wherein, the conductivity type of the semiconductor substrate 100 can be P-type. The PMOS device region 100A is used to form a PMOS device, the NMOS device region 100B is used to form an NMOS device, and a shallow trench isolation structure 101 is formed between the PMOS device region 100A and the NMOS device region 100B.

[0066] In this embodiment, a well region 102 is formed in the PMOS device region 100A, and the conductivity type of the well region 102 is N-type.

[0067] Next, continue to refer to Figure 3 In step S2, a floating gate oxide layer 110 and a floating gate material layer 120 are sequentially formed on the semiconductor substrate 100. The floating gate oxide layer 110 covers the PMOS device region 100A and the NMOS device region 100B. Specifically, the floating gate oxide layer 110 can be made of silicon dioxide, and it can be formed by a thermal oxidation process.

[0068] In this embodiment, the floating gate material layer 120 covers the floating gate oxide layer 110. The floating gate material layer 120 can be made of polycrystalline silicon and is formed using a furnace tube process. The thickness of the floating gate material layer 120 can be, for example, 1000 angstroms to 2000 angstroms.

[0069] Next, refer to Figure 5 Step S3 is performed to etch the floating gate material layer 120 to expose a portion of the floating gate oxide layer 110 in the NMOS device region 100B. Specifically, the method for etching the floating gate material layer 120 includes: firstly, as... Figure 4 As shown, a patterned mask layer 130 is formed on the floating gate material layer 120. The patterned mask layer 130 exposes a portion of the floating gate material layer 120 of the NMOS device region 100B to define the location of the subsequently formed erase gate 150a. The patterned mask layer 130 can be, for example, a patterned photoresist layer.

[0070] Then, as Figure 5 As shown, the exposed floating gate material layer 120 is etched using the patterned mask layer 130 as a mask to expose a portion of the floating gate oxide layer 110 in the NMOS device region 100B. The floating gate material layer 120 can be etched using a dry etching process, during which a portion of the floating gate oxide layer 110 in the NMOS device region 100B is etched. Afterwards, the patterned mask layer 130 is removed using an ashing process or a stripping method.

[0071] Next, refer to Figure 6 In step S4, erase gate oxide layer 140 and erase gate oxide layer 150 are formed sequentially. Erasure gate oxide layer 140 covers the exposed floating gate oxide layer 110 and extends to cover the sidewall of floating gate oxide layer 120 located in the NMOS device region 100B and the top surface of floating gate oxide layer 120. Erasure gate oxide layer 150 covers erase gate oxide layer 140.

[0072] In this embodiment, the erase gate oxide material layer 140 can be made of silicon oxide, and the erase gate oxide material layer 140 can be formed by a thermal oxidation process.

[0073] In another embodiment, the erased gate oxide material layer 140 may be formed using a chemical vapor deposition (CVD) process.

[0074] Preferably, the thickness of the erase gate oxide layer 140 can be greater than the thickness of the floating gate oxide layer 110 to improve the withstand voltage of the subsequently formed erase gate oxide layer 140a. Furthermore, when forming the erase gate oxide layer 140a, its thickness can be designed based on the voltage subsequently applied to the erase gate. That is, the thickness of the erase gate oxide layer can be preset according to the expected operating voltage to be applied to the erase gate, and the erase gate oxide layer 140a can be formed according to the preset thickness, thereby improving the withstand voltage of the erase gate oxide layer 140a and thus improving the erasure efficiency. The thickness of the erase gate oxide layer 140 can be 30 angstroms to 300 angstroms, for example, 30 angstroms, 50 angstroms, 100 angstroms, 200 angstroms, or 300 angstroms.

[0075] like Figure 6 As shown, the erase gate material layer 150 is formed on the erase gate oxide material layer 140. The erase gate material layer 150 can be made of polycrystalline silicon or doped polycrystalline silicon, and it can be formed using a furnace tube process. The thickness of the erase gate material layer 150 can be the same as the thickness of the floating gate material layer 120, i.e., the thickness of the erase gate material layer 150 can be 1000 angstroms to 2000 angstroms. This improves the flatness of the top surface of the subsequently formed erase gate 150a compared to the top surface of the floating gate.

[0076] In another embodiment, the thickness of the erase gate material layer 150 may be greater than the thickness of the floating gate material layer 120, so as to increase the grinding allowance of the subsequent chemical mechanical polishing process.

[0077] Next, refer to Figure 7 Step S5 is executed, and a chemical mechanical polishing process is performed to remove the erase gate oxide material layer 140 and the erase gate material layer 150 from the top surface of the floating gate material layer 120. That is, the chemical mechanical polishing process stops at the top surface of the floating gate material layer 120 so that the top surface of the floating gate material layer 120 is flush with the top surface of the erase gate material layer 150.

[0078] like Figure 7As shown, the remaining erase gate oxide layer 140 constitutes the erase gate oxide layer 140a, that is, the erase gate oxide layer 140 between the erase gate material layer 150 and the floating gate material layer 120 is retained, and the erase gate oxide layer 140 between the erase gate material layer 150 and the NMOS device region 100B is retained, so as to constitute the erase gate oxide layer 140a. The cross-sectional shape of the erase gate oxide layer 140a can be L-shaped.

[0079] Next, refer to Figure 9 and combined Figure 10 As shown, in step S6, the erase gate material layer 150 and the floating gate material layer 120 are etched to form an erase gate 150a, a first floating gate 121, and a second floating gate 122, respectively. The first floating gate 121 is formed in the PMOS device region 100A, and the second floating gate 122 is formed in the NMOS device region 100B. The second floating gate 122 is electrically connected to the first floating gate 121, and the erase gate 150a and the second floating gate 122 are isolated from each other by the erase gate oxide layer 140a.

[0080] Specifically, the method for etching the erase gate material layer 150 and the floating gate material layer 120 includes: firstly, as... Figure 8 As shown, a patterned photoresist layer 160 is formed on the floating gate material layer 120 and the erase gate material layer 150. The patterned photoresist layer 160 covers a portion of the floating gate material layer 120 in the PMOS device region 100A, a portion of the floating gate material layer 120 in the NMOS device region 100B, and a portion of the erase gate material layer 150 closest to the floating gate material layer 120.

[0081] Then, refer to Figure 9 As shown, using the patterned photoresist layer 160 as a mask, the erase gate material layer 150 and the floating gate material layer 120 are etched to form the erase gate 150a, the first floating gate 121 and the second floating gate 122, respectively. The floating gate material layer 120 and the erase gate material layer 150 can be etched by a dry etching process.

[0082] refer to Figure 10 and combined Figure 11 As shown, after etching the floating gate material layer 120, the remaining floating gate material layer 120 has an n-shaped form, that is, the remaining floating gate material layer 120 includes two vertical portions and one horizontal portion, and the vertical portions are perpendicular to the horizontal portions. Figure 10As shown, the two vertical portions respectively constitute the first floating gate 121 and the second floating gate 122, and the horizontal portion constitutes the floating gate connecting portion 123 for electrically connecting the first floating gate 121 and the second floating gate 122. It should be noted that, in this embodiment, to better illustrate the inventive points of the present invention, therefore... Figure 9 , Figure 11 as well as Figure 1 The illustration of the floating gate connection part 123 is omitted.

[0083] In this embodiment, the first floating gate 121 and the second floating gate 122 serve as electronic storage layers. When writing to the memory, the hot electron injection effect can be used to allow electrons to enter the first floating gate 121 and the second floating gate 122. The erase gate 150a is used to erase the electrons in the first floating gate 121 and the second floating gate 122. During erasure, the FN tunneling effect is used to allow the electrons in the first floating gate 121 and the second floating gate 122 to pass through the erase gate oxide layer 140a and move out into the erase gate 150a, thereby achieving erasure. This avoids repeated writing and erasing of the same floating gate oxide layer 110, reduces the usage frequency of the floating gate oxide layer 110, slows down the rate of damage to the floating gate oxide layer 110, and improves the effective lifespan of the memory.

[0084] like Figure 11 As shown, after etching the floating gate material layer 120 and the erase gate material layer 150, the patterned photoresist layer 160 is removed. The patterned photoresist layer 160 can be removed by an ashing process or by stripping.

[0085] After that, as Figure 1 As shown, sidewalls 170 are formed on both sides of the first floating gate 121, on the sidewall of the second floating gate 122 near the first floating gate 121, and on the sidewall of the erase gate 150a away from the second floating gate 122. The sidewalls 170 can be made of silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride.

[0086] After that, as Figure 1 As shown, using the sidewall 170 as a mask, a first ion implantation process is performed to form a first source region 180a and a first drain region 180b. The first source region 180a and the first drain region 180b are respectively formed in the PMOS device region 100A on both sides of the first floating gate 121. The ions used in the first ion implantation process are P... + ion.

[0087] Furthermore, using the sidewall 170 as a mask, a second ion implantation process is performed to form a second source region 190a and a second drain region 190b. The second source region 190a and the second drain region 190b are respectively formed in the NMOS device regions 100B on both sides of the second floating gate 122. The ions used in the second ion implantation process are N... + .

[0088] This embodiment provides a writing method for a multiple-programmable memory as described in the foregoing embodiments, comprising: applying a first voltage to a second floating gate 122 and applying a second voltage to a second source region 190a and a second drain region 190b, wherein the second voltage is less than the first voltage, so as to inject negatively charged electrons into the second floating gate 122 and the first floating gate 121 to achieve the writing. The writing operation is performed from the floating gate oxide layer 110.

[0089] Specifically, after applying a first voltage to the second floating gate 122 and a second voltage to the second source region 190a and the second drain region 190b, negatively charged electrons enter the second floating gate 122 through the thermionic injection effect. Since the second floating gate 122 is electrically connected to the first floating gate 121, and the first floating gate 121 and the second floating gate 122 share a common potential, the first floating gate 121 also contains negatively charged electrons, i.e., the first floating gate 121 has a negative voltage. Furthermore, since the first floating gate 121 has a negative voltage, the channel between the first floating gate 121 and the PMOS device region 100A can be opened, thereby enabling a read operation.

[0090] This embodiment provides a method for erasing a multiple-programmable memory as described in the foregoing embodiments, comprising: applying a positive voltage to the erase gate 150a and a negative voltage to the first floating gate 121 and the second floating gate 122, so as to remove electrons stored in the second floating gate 122 and the first floating gate 121 to achieve the erasure, wherein the erasure operation is performed from the erase gate oxide layer 140a. That is, the erase gate 150a is used to erase electrons in the first floating gate 121 and the second floating gate 122. During the erasure, the FN tunneling effect is used to allow electrons in the second floating gate 122 to pass through the erase gate oxide layer 140a and move out into the erase gate 150a. Since the second floating gate 122 is electrically connected to the first floating gate 121 and they share a common potential, after the electrons in the second floating gate 122 are erased, the electrons in the first floating gate 121 are also erased, thereby realizing the erasure of the multiple-programmable memory. Since erasing is performed using the erase gate 150a from the erase gate oxide layer 140a, repeated writing and erasing of the same floating gate oxide layer 110 can be avoided, reducing the usage frequency and number of times the floating gate oxide layer 110 is used. This can slow down the rate at which the floating gate oxide layer 110 is damaged and improve the effective lifespan of the memory.

[0091] In summary, the reproducible memory and its manufacturing method, writing method, and erasing method provided in the embodiments of the present invention include an erasable gate oxide layer and an erasable gate. The erasable gate oxide layer covers the sidewall of the second floating gate away from the first floating gate and extends to cover a portion of the NMOS device region. The erasable gate is formed on the erasable gate oxide layer, and the erasable gate and the second floating gate are isolated from each other by the erasable gate oxide layer. Thus, writing can be performed from the floating gate oxide layer, and erasing can be performed from the erasable gate oxide layer using the erasable gate, avoiding repeated writing and erasing of the same floating gate oxide layer, reducing the usage frequency of the floating gate oxide layer, slowing down the rate of damage to the floating gate oxide layer, and improving the effective lifespan of the memory. Furthermore, since erasing is performed using the erasable gate oxide layer, the thickness of the erasable gate oxide layer can be designed according to the voltage subsequently applied to the erasable gate, improving the voltage withstand capability of the erasable gate oxide layer and thus improving the erasing efficiency.

[0092] The above description is merely a description of preferred embodiments of the present invention. Although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A multi-time programmable memory, comprising: The semiconductor substrate comprises a PMOS device region and an NMOS device region; a floating gate oxide layer covering the PMOS device region and the NMOS device region; a first floating gate and a second floating gate formed on the floating gate oxide layer, the first floating gate is formed in the PMOS device region, the second floating gate is formed in the NMOS device region, and the first floating gate is electrically connected with the second floating gate; an erase gate oxide layer covering the sidewall of the second floating gate away from the first floating gate and extending to cover part of the floating gate oxide layer in the NMOS device region, and an erase gate formed on the erase gate oxide layer, and the erase gate and the second floating gate are isolated from each other by the erase gate oxide layer. The thickness of the erase gate oxide layer is greater than the thickness of the floating gate oxide layer.

2. The multi-time programmable memory of claim 1, wherein, The multi-time programmable memory further comprises:

3. The multi-time programmable memory of claim 1, wherein, a well region formed in the PMOS device region; a sidewall formed on both sidewalls of the first floating gate, the sidewall of the second floating gate close to the first floating gate, and the sidewall of the erase gate away from the second floating gate; a first source region and a first drain region formed in the PMOS device region on both sides of the first floating gate, respectively; a second source region and a second drain region formed in the NMOS device region on both sides of the second floating gate, respectively. The semiconductor substrate comprises a PMOS device region and an NMOS device region; 4. A manufacturing method of a multi-time programmable memory, characterized by, a floating gate oxide layer covering the PMOS device region and the NMOS device region; etching the floating gate material layer to expose part of the floating gate oxide layer in the NMOS device region; forming an erase gate oxide material layer and an erase gate material layer in sequence, the erase gate oxide material layer covers the exposed floating gate oxide layer and extends to cover the sidewall of the floating gate material layer in the NMOS device region and the top surface of the floating gate material layer, and the erase gate material layer covers the erase gate oxide material layer; performing a chemical mechanical polishing process to remove the erase gate oxide material layer and the erase gate material layer on the top surface of the floating gate material layer, and the remaining erase gate oxide material layer constitutes an erase gate oxide layer; etching the erase gate material layer and the floating gate material layer to form an erase gate, a first floating gate and a second floating gate, respectively, the first floating gate is formed in the PMOS device region, the second floating gate is formed in the NMOS device region, the second floating gate is electrically connected with the first floating gate, and the erase gate and the second floating gate are isolated from each other by the erase gate oxide layer. The method for etching the erase gate material layer and the floating gate material layer comprises: forming a patterned photoresist layer on the floating gate material layer and the erase gate material layer, the patterned photoresist layer covers part of the floating gate material layer in the PMOS device region, part of the floating gate material layer in the NMOS device region, and part of the erase gate material layer close to the floating gate material layer; 5. The method of manufacturing a multi-time programmable memory according to claim 4, wherein, ​ ​ etching the erase gate material layer and the floating gate material layer to form the erase gate, the first floating gate and the second floating gate respectively; and removing the patterned photoresist layer.

6. The method of manufacturing a multi-time programmable memory according to claim 5, wherein, The material of the erase gate oxide material layer is silicon oxide, and the erase gate oxide material layer is formed by a thermal oxidation process or a chemical vapor deposition process.

7. The method of manufacturing a multi-time programmable memory according to claim 5, wherein, The material of the erase gate material layer is polysilicon, and the erase gate material layer is formed by a furnace tube process.

8. The method of manufacturing a multi-time programmable memory according to claim 4, wherein, The method for manufacturing the multi-time programmable memory further includes: forming a side wall, the side wall being formed on two side walls of the first floating gate, a side wall of the second floating gate close to the first floating gate, and a side wall of the erase gate away from the second floating gate; performing a first ion implantation process to form a first source region and a first drain region in the PMOS device region on both sides of the first floating gate, with the side wall as a mask; and performing a second ion implantation process to form a second source region and a second drain region in the NMOS device region on both sides of the second floating gate, with the side wall as a mask.

9. The method of writing a multi-time programmable memory as claimed in claim 1 or 2, said memory further comprising a second source region and a second drain region formed in said NMOS device region on either side of said second floating gate, characterized by, comprising: applying a first voltage to the second floating gate and a second voltage to the second source region and the second drain region, the second voltage being less than the first voltage, to inject negatively charged electrons into the second floating gate and the first floating gate to implement the writing, wherein the writing is performed from the floating gate oxide layer.

10. An erasing method of a multi-time programmable memory as claimed in any one of claims 1 to 3, characterized by, comprising: applying a positive voltage to the erase gate and a negative voltage to the first floating gate and the second floating gate to remove the electrons stored in the second floating gate and the first floating gate to implement the erasing, wherein the erasing is performed from the erase gate oxide layer.

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