Manufacturing method of memory device

Abstract

The invention relates to a manufacturing method of a memory device. A method of manufacturing a memory device includes forming an opening penetrating a stack structure; forming a channel layer including a first portion and a second portion, the first portion extending on an upper surface of the stacked structure, and the second portion extending on an inner side surface of the opening; forming a protective layer on the first part of the channel layer; and etching a portion of the second portion not covered by the protective layer such that the second portion has a thickness smaller than that of the first portion.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to a method of manufacturing a memory device, and more specifically, to a method of manufacturing a memory device comprising a three-dimensional memory block. Background Technology

[0002] Memory devices can include non-volatile memory devices that retain stored data even without power. Depending on the arrangement of the memory cells in each non-volatile memory device, non-volatile memory devices can be classified as two-dimensional or three-dimensional memory devices. Memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate. Memory cells of a three-dimensional non-volatile memory device can be stacked in a direction perpendicular to the substrate. Because the integration density of three-dimensional non-volatile memory devices is greater than that of two-dimensional non-volatile memory devices, electronic devices incorporating three-dimensional non-volatile memory devices have been continuously increasing recently. Summary of the Invention

[0003] According to one embodiment, a method of manufacturing a memory device may include the steps of: forming an opening through a stacked structure; forming a channel layer comprising a first portion and a second portion, wherein the first portion extends on an upper surface of the stacked structure and has a first thickness, and the second portion extends on an inner surface of the opening and has a second thickness; forming a protective layer on the first portion of the channel layer; and etching a portion of the second portion such that the second portion has a third thickness less than the second thickness, wherein the third thickness of the second portion is less than the first thickness of the first portion.

[0004] According to one embodiment, a method of manufacturing a memory device may include the steps of: forming an opening through a stacked structure; forming a channel layer comprising a first portion and a second portion, wherein the first portion extends on an upper surface of the stacked structure and the second portion extends on an inner surface of the opening; forming a protective layer on the first portion of the channel layer; and etching a portion of the second portion not covered by the protective layer such that the second portion has a thickness less than that of the first portion. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0006] Figure 2 This is a schematic diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figure 3A This is a plan view of the layout of a memory device according to an embodiment of the present disclosure;

[0008] Figure 3B This is a cross-sectional view of a memory device according to an embodiment of the present disclosure;

[0009] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Figure 4I This is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure;

[0010] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F This is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure;

[0011] Figure 6 This is a diagram illustrating a memory card system employing a memory device according to an embodiment of the present disclosure; and

[0012] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0013] The specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0014] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can realize the technical spirit of the invention.

[0015] Various embodiments relate to a method of manufacturing a memory device capable of reducing the thickness of the channel layer included in the cell plug and defects in the memory block.

[0016] Terms such as “first” and “second” are used to distinguish various elements without implying the size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as “top,” “above,” “upper,” “side,” “upper part,” “lower part,” “row,” “column,” “inner,” “outer,” and other terms that imply relative spatial relationships or directions are used only for the purpose of description or reference to the accompanying drawings and are not intended to limit in any other way. Cross-shading throughout the drawings indicates corresponding or similar areas between the drawings and does not indicate material associated with these areas. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “attached to” another element or layer, that element or layer may be directly on, directly connected to, or attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly attached to” another element or layer, there are no intermediate elements or layers.

[0017] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0019] The memory cell array 110 may include first memory blocks BLK1 to the i-th memory block BLKi. Each of the first memory blocks BLK1 to the i-th memory block BLKi may include a memory cell capable of storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL may be connected to each of the first memory blocks BLK1 to the i-th memory block BLKi, and bit line BL may be collectively connected to the first memory blocks BLK1 to the i-th memory block BLKi.

[0020] Each of the first memory block BLK1 to the i-th memory block BLKi may have a three-dimensional structure. Each memory block with a three-dimensional structure may include memory cells stacked vertically on a substrate. The memory cells stacked vertically may correspond to the intersections of cell plugs and word lines included in the memory block. The degree of interference between adjacent memory cells in the vertical direction can be determined based on the thickness of the channel layer included in each cell plug. For example, as the thickness of the channel layer decreases, the interference between adjacent memory cells in the vertical direction (e.g., Z-interference) can be reduced.

[0021] Depending on the programming method, each memory cell can store one, two, or more bits of data. For example, storing one bit of data in a memory cell is called the Single-Level Cell (SLC) method, and storing two bits of data in a memory cell is called the Multi-Level Cell (MLC) method. Storing three bits of data in a memory cell is called the Three-Level Cell (TLC) method, and storing four bits of data in a memory cell is called the Quadruple-Level Cell (QLC) method. Furthermore, five or more bits of data can be stored in a single memory cell.

[0022] The peripheral circuitry 170 can be configured to perform programming operations that store data in the memory cell array 110, reading operations that output data stored in the memory cell array 110, and erasing operations that erase data stored in the memory cell array 110. For example, the peripheral circuitry 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and input / output circuitry 160.

[0023] Voltage generator 120 can generate various operating voltages Vop for programming, reading, or erasing operations in response to operation code OPCD. For example, voltage generator 120 can be configured to generate programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, or erase voltage in response to operation code OPCD. The operating voltage Vop generated by voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the selected memory block via line decoder 130.

[0024] Programming voltage can be applied to the selected word line (WL) during programming operations and can be used to increase the threshold voltage of the memory cell connected to the selected word line. Turn-on voltage can be applied to the drain select line (DSL) or source select line (SSL) and can be used to turn on the drain select transistor (DST) or source select transistor (SST). Turn-off voltage can be applied to the drain select line (DSL) or source select line (SSL) and can be used to turn off the drain select transistor (DST) or source select transistor (SST). For example, the turn-off voltage can be set to 0V. Precharge voltage can be higher than 0V and can be applied to bit line (BL) during read operations. Verification voltage can be used during verification operations to determine whether the threshold voltage of the selected memory cell has increased to the target level. The verification voltage can be set to various levels according to the target level and can be applied to the selected word line.

[0025] A read voltage can be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage can be set to various levels depending on the programming method of the selected memory cell. A voltage can be applied to the unselected word lines (WL) during programming or read operations and can be used to turn on memory cells connected to the unselected word lines. An erase voltage can be used to erase memory cells included in the selected memory block during an erase operation and can be applied to the source line (SL).

[0026] The row decoder 130 can be configured to transmit the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL connected to the memory block selected according to the row address RADD. For example, the row decoder 130 can be connected to the voltage generator 120 via a global line and can be connected to the first memory block BLK1 through the i-th memory block BLKi via the drain select line DSL, word line WL, source select line SSL, and source line SL.

[0027] Page buffer group 140 may include page buffers (not shown) respectively connected to first memory blocks BLK1 through i-th memory blocks BLKi. The page buffers (not shown) may be connected to the first memory blocks BLK1 through i-th memory blocks BLKi respectively via bit lines BL. During a read operation, the page buffers (not shown) may sense the current or voltage of the bit line BL, which varies according to the threshold voltage of the selected memory cell, in response to the page buffer control signal PBSIG, and may store the sensed data.

[0028] The column decoder 150 can be configured to transfer data between the page buffer group 140 and the input / output circuitry 160 in response to a column address CADD. For example, the column decoder 150 can be coupled to the page buffer group 140 via column line CL and can transmit an enable signal via column line CL. The page buffers (not shown) included in the page buffer group 140 can receive or output data via data line DL in response to the enable signal.

[0029] Input / output circuitry 160 can be configured to receive or output commands (CMD), addresses (ADD), or data via input / output line I / O. For example, input / output circuitry 160 can transmit commands (CMD) and addresses (ADD) received from an external controller via input / output line I / O to control circuitry 180, and can transmit data received from an external controller via input / output line I / O to page buffer group 140. Alternatively, input / output circuitry 160 can output data transmitted from page buffer group 140 to an external controller via input / output line I / O.

[0030] Control circuit 180 can output at least one of operation code OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD in response to command CMD and address ADD. For example, when command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 can control peripheral circuit 170 to perform a programming operation on the memory block selected by address ADD. When command CMD input to control circuit 180 corresponds to a read operation, control circuit 180 can control peripheral circuit 170 to perform a read operation on the memory block selected by address ADD and output the read data. When command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 can control peripheral circuit 170 to perform an erase operation on the selected memory block.

[0031] Figure 2 This is a schematic diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The memory device 100 may include a peripheral circuit structure PC disposed above the substrate SUB and first memory blocks BLK1 to BLKi. The first memory blocks BLK1 to BLKi may overlap with the peripheral circuit structure PC.

[0033] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-below-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0034] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and control circuitry 180 constituting circuitry for controlling the operation of the first memory blocks BLK1 to the i-th memory blocks BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the first memory blocks BLK1 to the i-th memory blocks BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the first memory blocks BLK1 to the i-th memory blocks BLKi.

[0035] Each of the first memory block BLK1 to the i-th memory block BLKi may include a source structure, bit lines, a string of cells electrically connected to the source structure and the bit lines, a word line electrically connected to the string of cells, and a select line electrically connected to the string of cells. Each of the string of cells may include a memory cell and a select transistor connected in series via cell plugs. Each select line may serve as the gate electrode of the corresponding select transistor, and each word line may serve as the gate electrode of the corresponding memory cell.

[0036] Each of the first storage blocks BLK1 to the i-th storage blocks BLKi may include a cell region and a contact region. At least a portion of cell plugs and dummy cell plugs may be formed in the cell region of each of the first storage blocks BLK1 to the i-th storage blocks BLKi. The cell plugs included in the first storage blocks BLK1 to the i-th storage blocks BLKi may correspond to cell strings. Dummy cell plugs may have a similar structure to cell plugs and may not correspond to cell strings. References will follow below. Figure 3A and Figure 3B Describe the components in the cell region of each of the first storage block BLK1 to the i-th storage block BLKi.

[0037] Multiple contacts can be formed in the contact area of ​​each of the first memory blocks BLK1 to the i-th memory block BLKi. Each of the contacts can extend in the Z direction. For example, each of the contacts may include a contact plug, each contact plug being electrically connected to a corresponding word line and select line. Furthermore, the contact plug may include a contact plug connected to a peripheral circuit structure PC. Support structures can be provided in the contact area of ​​each of the first memory blocks BLK1 to the i-th memory block BLKi. Each of the support structures can extend in the Z direction.

[0038] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the first memory blocks BLK1 to the i-th memory blocks BLKi can be relative to each other. Figure 2 The order shown is stacked in reverse order. For example, the peripheral circuit structure PC can be positioned above the first memory block BLK1 to the i-th memory block BLKi.

[0039] In another embodiment, besides Figure 2 In addition to those shown, the peripheral circuit structure PC can be disposed in a region of the substrate SUB that does not overlap with the first memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the first memory blocks BLK1 to BLKi can be disposed above different regions of the substrate SUB that do not overlap with each other.

[0040] Figure 3A This is a plan view of the layout of a memory device 100 according to an embodiment of the present disclosure.

[0041] Reference Figure 3AA storage block BLKa (where a is a natural number, 1 < a < i) and its adjacent storage blocks can be separated from each other by slits SI. For example, slits SI can be located in the Y direction relative to the storage block BLKa, or in a direction opposite to the Y direction relative to the storage block BLKa. Each of the slits SI can extend in the X direction. The storage block BLKa can be adjacent to another storage block, with each slit SI interposed between the two storage blocks.

[0042] The a-th memory block BLKa may include multiple cell plugs (CPLs). For example, cell plugs (CPLs) may be formed in the reference... Figure 2 The described cell region. Cell plugs (CPLs) can extend from a substrate (not shown) in a vertical direction (e.g., along the Z direction). Cell plugs (CPLs) can be arranged in multiple rows. Each row can include cell plugs (CPLs) spaced apart from each other in the X direction. The multiple rows can be spaced apart from each other in the Y direction. The center of each cell plug (CPL) included in odd-numbered rows and the center of each cell plug (CPL) included in even-numbered rows can be offset from each other.

[0043] Each of the unit plugs CPL may include a barrier layer BX, a charge trapping layer CT, a tunneling layer TX, a channel layer CH, and a gap-filling layer GF. The barrier layer BX may have a cylindrical shape. The charge trapping layer CT may contact the inner surface of the barrier layer BX. The tunneling layer TX may contact the inner surface of the charge trapping layer CT. The channel layer CH may contact the inner surface of the tunneling layer TX. The gap-filling layer GF may fill the channel layer CH. For example, the gap-filling layer GF may be formed in a cylindrical shape in the region surrounded by the channel layer CH. Although... Figure 3A It is not shown in the figure, but a covering layer can also be formed above the gap filling layer GF.

[0044] Each of the barrier layer BX and tunneling layer TX may comprise an oxide layer (e.g., a silicon oxide layer), an oxide nitride layer (e.g., a silicon oxide nitride layer), or a combination thereof. The charge trapping layer CT may comprise a nitride layer or a variable resistance material. The channel layer CH may comprise an undoped silicon layer or a doped silicon layer. The gap fill layer GF may comprise an insulating layer or a conductive layer. Each of the barrier layer BX, charge trapping layer CT, tunneling layer TX, channel layer CH, and gap fill layer GF included in each of the cell plugs CPL may extend in the vertical direction (e.g., in the Z direction).

[0045] Figure 3B This is a cross-sectional view of a memory device 100 according to an embodiment of the present disclosure. Figure 3B It shows along Figure 3A The cross section intercepted by line A-A'.

[0046] Reference Figure 3B The memory device 100 (e.g., the a-th memory block BLKa) may include a stacked structure STK. The stacked structure STK may include alternately stacked conductive layers CD and interlayer insulating layers IIL. The conductive layers CD and interlayer insulating layers IIL may be alternately stacked in the Z direction. Each of the conductive layers CD may correspond to... Figure 1 The drain select line (DSL), word line (WL), or source select line (SSL) is included. The stacked structure STK may further include an upper insulating layer (UIL). The thickness of the upper insulating layer (UIL) may be greater than the thickness of each of the interlayer insulating layers (IIL). For example, as... Figure 3B As shown, the thickness of the upper insulating layer UIL (i.e., its length in the Z direction) can be greater than the thickness of each of the interlayer insulating layers IIL (i.e., its length in the Z direction).

[0047] The conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si). The interlayer insulating layer IIL may include an oxide layer. For example, the interlayer insulating layer IIL may include a silicon oxide layer. The upper insulating layer UIL may include the same material or the same type of material as the interlayer insulating layer IIL. For example, the upper insulating layer UIL may include a silicon oxide layer.

[0048] Memory device 100 (e.g., the a-th memory block BLKa) may include a cell plug CPL. The cell plug CPL may extend in a vertical direction (e.g., along the Z-direction) within the stacked structure STK. The cell plug CPL may extend through the stacked structure STK. For example, the cell plug CPL may be located in a first opening OP1 extending through the stacked structure STK. (Refer to...) Figure 1 and Figure 2 The memory cell or selection transistor described can be formed at the intersection of the cell plug CPL and the conductive layer CD, respectively.

[0049] The cell plug CPL may include a memory layer ML. The memory layer ML may include a barrier layer BX, a charge trapping layer CT, and a tunneling layer TX. The memory layer ML may extend through the stacked structure STK. The memory layer ML may be formed along the inner wall of the first opening OP1. For example, the barrier layer BX may contact the inner surface of the first opening OP1. That is, the barrier layer BX may contact the inner surface of the stacked structure STK. The memory layer ML may extend on the outer wall of the channel layer CH. For example, the tunneling layer TX may contact the outer surface of the channel layer CH.

[0050] The unit plug CPL may include a channel layer CH. The channel layer CH may extend through the stacked structure STK. The channel layer CH may extend in the Z direction. The channel layer CH may have a cylindrical shape.

[0051] The unit plug CPL may include a gap filler layer GF. The gap filler layer GF may be located within the channel layer CH. The gap filler layer GF may contact the inner surface of the channel layer CH. The gap filler layer GF may be surrounded by the channel layer CH. The gap filler layer GF may fill at least a portion of the region surrounded by the channel layer CH.

[0052] The unit plug CPL may include a cover layer CAP. The cover layer CAP may be disposed on the gap fill layer GF. The cover layer CAP may contact the inner surface of the channel layer CH. The cover layer CAP may be surrounded by the channel layer CH. The cover layer CAP may fill another portion of the unfilled gap fill layer GF in the area surrounded by the channel layer CH.

[0053] The lower surface of the capping layer CAP can be located at a height (level) corresponding to the uppermost conductive layer CD within the conductive layers CD. That is, the height of the interface between the gap filling layer GF and the capping layer CAP can correspond to the height of the uppermost conductive layer CD. Figure 3B The implementation shown differs from the one described above; the cover layer CAP can be formed such that the lower surface of the cover layer CAP is located at a position greater than that of the cover layer CAP. Figure 3B The height shown may be higher or lower. The capping layer CAP may include the same material or the same type of material as the channel layer CH.

[0054] Apart from Figure 3B In addition to the embodiments shown, the stacked structure STK may include a lower stacked structure and an upper stacked structure. The method of dividing the stacked structure STK into an upper stacked structure and a lower stacked structure may be referred to as a double-stack method. When the stacked structure STK includes an upper stacked structure and a lower stacked structure, the interlayer insulating layer IIL located at the interface between the lower and upper stacked structures may have a greater thickness than each of the remaining interlayer insulating layers IIL. Furthermore, when the stacked structure STK includes a lower stacked structure and an upper stacked structure, the cell plug CPL may have curvature at the interface between the lower and upper stacked structures. For example, the width of the cell plug CPL in the Y direction at the bottom of the upper stacked structure may be smaller than the width of the cell plug CPL in the Y direction at the top of the lower stacked structure.

[0055] Figures 4A to 4I This is a diagram illustrating a method for manufacturing a memory device 100 according to an embodiment of the present disclosure. Figures 4A to 4I Each corresponds to Figure 3A The cross section of A-A'.

[0056] Reference Figure 4AA preliminary stacked structure pSTK can be formed. The preliminary stacked structure pSTK may include a first material layer IIL and a second material layer SF alternately stacked in the Z direction. The first material layer IIL may include an insulating material. For example, the first material layer IIL may include an oxide layer (e.g., a silicon oxide layer). The first material layer IIL may be referred to as an interlayer insulating layer IIL. The second material layer SF may include a material that can be selectively removed in subsequent processes. Therefore, the second material layer SF may include a material having an etch selectivity different from that of the first material layer IIL. For example, the second material layer SF may include a nitride layer. The preliminary stacked structure pSTK may further include a hard mask HM. The hard mask HM may be located above the first material layer IIL and the second material layer SF. The hard mask HM may have a thickness greater than the thickness of each of the first material layer IIL and the second material layer SF. For example, the height (e.g., the length in the Z direction) of the hard mask HM may be greater than the height (e.g., the length in the Z direction) of each of the second material layers SF. The hard mask HM may include a nitride material.

[0057] Subsequently, a first opening OP1 can be formed through the initial stacked structure pSTK. The first opening OP1 can penetrate the hard mask HM, the first material layer IIL, and the second material layer SF of the initial stacked structure pSTK. The first opening OP1 can extend in the Z direction. The first opening OP1 can have a hole shape.

[0058] Reference Figure 4B A preliminary barrier layer pBX, a preliminary charge trapping layer pCT, and a preliminary tunneling layer pTX can be formed above the preliminary stacked structure pSTK. For example, the preliminary barrier layer pBX, the preliminary charge trapping layer pCT, and the preliminary tunneling layer pTX can be formed sequentially along the upper surface of the preliminary stacked structure pSTK and the inner surface of the first opening OP1. For example, in one embodiment, the preliminary barrier layer pBX, the preliminary charge trapping layer pCT, and the preliminary tunneling layer pTX can be formed as follows: Figure 4B The structure is formed sequentially along the upper surface of the initial stacked structure pSTK and the inner surface of the first opening OP1.

[0059] The initial barrier layer pBX, the initial charge trapping layer pCT, and the initial tunneling layer pTX can be located sequentially in the first opening OP1. Each of the initial barrier layer pBX, the initial charge trapping layer pCT, and the initial tunneling layer pTX can penetrate the initial stacked structure pSTK.

[0060] Subsequently, a preliminary channel layer pCH can be formed above the preliminary stacked structure pSTK. The preliminary channel layer pCH can be formed along the surface of the preliminary tunneling layer pTX. That is, the preliminary channel layer pCH can be formed along the inner and upper surfaces of the preliminary stacked structure pSTK. The preliminary channel layer pCH can be formed by a deposition process. For example, the preliminary channel layer pCH can be formed by a process of depositing polycrystalline silicon on the preliminary tunneling layer pTX.

[0061] The preliminary channel layer pCH may include a first portion P1 located above the preliminary laminated structure pSTK and a second portion P2 located within the first opening OP1. The first portion P1 of the preliminary channel layer pCH may extend on the upper surface of the preliminary laminated structure pSTK. That is, the first portion P1 may have a plate shape extending in both the X and Y directions. For example, the first portion P1 of the preliminary channel layer pCH may be as follows: Figure 4B As shown, it extends on the upper surface of the initial stacked structure pSTK. The second portion P2 of the initial channel layer pCH can extend on the inner surface of the first opening OP1. For example, the second portion P2 of the initial channel layer pCH can be as follows: Figure 4B The second portion P2 extends on the inner surface of the first opening OP1, as shown. That is, the second portion P2 can have a cylindrical shape extending in the Z direction. The second portion P2 can extend from the first portion P1 in a vertical direction (e.g., in a direction opposite to the Z direction). The first portion P1 can contact the upper surface of the initial tunneling layer pTX, and the second portion P2 can contact the inner surface of the initial tunneling layer pTX. In this disclosure, for ease of description, the initial channel layer pCH is described as being divided into a first portion P1 and a second portion P2; however, in practice, the first portion P1 and the second portion P2 may not be physically separated from each other, or there may be no boundary between them.

[0062] The first portion P1 of the preliminary channel layer pCH can have a first thickness W1. The second portion P2 of the preliminary channel layer pCH can have a second thickness W2. The first thickness W1 can be equal to or greater than the second thickness W2. For example, since the first portion P1 and the second portion P2 are formed by a single process, the first thickness W1 and the second thickness W2 can have substantially equal values. Alternatively, even when the thicknesses of the first portion P1 and the second portion P2 are different, the difference is caused by the characteristics of the deposition process. Therefore, in one embodiment, the difference between the first thickness W1 and the second thickness W2 may not be significant.

[0063] According to one embodiment of this disclosure, the thickness of the first portion P1 may correspond to its length in the vertical direction (e.g., the Z direction), and the thickness of the second portion P2 may correspond to its length in the horizontal direction (e.g., the X or Y direction). That is, the thickness of the initial channel layer pCH may refer to its length in the deposition direction of the initial channel layer pCH.

[0064] Reference Figure 4C A protective layer PL can be formed covering the first portion P1 of the initial channel layer pCH. The protective layer PL can contact the upper surface of the first portion P1. The protective layer PL can selectively cover the first portion P1. The protective layer PL can be formed on the upper surface of the initial channel layer pCH, and may not be formed on the inner surface of the initial channel layer pCH. For example, the protective layer PL may not cover the inner surface of the second portion P2. The coverage area of ​​the protective layer PL may be less than the entire inner surface of the second portion. Therefore, even after the protective layer PL is formed, the second portion P2 can remain exposed to the outside. Furthermore, the protective layer PL may not cover the inner surface of the first portion P1. Therefore, even after the protective layer PL is formed, the inner surface of the first portion P1 can remain exposed to the outside.

[0065] In one embodiment, the protective layer PL can be formed by a process of depositing a nitride material on a first portion P1 of the initial channel layer pCH. For example, the nitride material is selectively deposited on the upper surface of the first portion P1 to form the protective layer PL. When the protective layer PL is deposited on the first portion P1, the first thickness W1' of the first portion P1 can be equal to the first thickness W1.

[0066] In another embodiment, the protective layer PL can be formed by nitriding a first portion P1 of the preliminary channel layer pCH. For example, a portion of the first portion P1 can be nitrided to form the protective layer PL when nitriding gas is supplied on the first portion P1 using plasma. Because a portion of the first portion P1 is changed to the protective layer PL, the first portion P1 can have a reduced first thickness W1' that is less than the first thickness W1.

[0067] Furthermore, the protective layer PL can be formed by various processes for selectively covering the first portion P1 of the first portion P1 and the second portion P2. In one embodiment, the protective layer PL can be formed by various processes and can be located on the first portion P1.

[0068] In one embodiment, an annealing process for the preliminary channel layer pCH can be performed after the formation of the protective layer PL. The annealing process can reduce the grain boundaries of the polysilicon included in the preliminary channel layer pCH. The annealing process can be a process of performing a high-temperature treatment on the preliminary stack structure pSTK having the preliminary channel layer pCH at a specific temperature for a predetermined period of time. In another embodiment, the annealing process can be performed before the formation of the protective layer PL. As used herein with respect to parameters, the term "predetermined" (such as a predetermined period of time, predetermined depth, or predetermined thickness) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0069] Reference Figure 4D A portion of the initial channel layer pCH can be etched. For example, an isotropic wet etching process using a material that selectively etches polysilicon can be performed. Because the protective layer PL comprises a material that is etch-selective to polysilicon (e.g., a nitride material), the etching rate of the protective layer PL can be lower than the etching rate of the initial channel layer pCH.

[0070] The portion of the second part P2 not covered by the protective layer PL can be etched using an etching process. Because the inner surface of the second part P2 is not covered by the protective layer PL and is exposed to the outside, a portion of the second part P2 can be removed. Since the etching process starts from the inner surface of the second part P2, the thickness of the second part P2 can be reduced. The etched second part P2 can have a third thickness W3 that is less than the second thickness W2. The third thickness W3 can be less than... Figure 4B The first thickness W1 and Figure 4C Each of the first thicknesses W1' in the middle.

[0071] Because the upper surface of the first part P1 is covered by the protective layer PL, when a portion of the second part P2 is etched, the first part P1 may not be etched, or may be etched less than the second part P2. Therefore, the first part P1 can have a greater thickness than the second part P2. The first thickness W1” of the first part P1 can be greater than the third thickness W3 of the second part P2.

[0072] In one embodiment, the protective layer PL can be removed when the second portion P2 is etched. Because the etching rate of the protective layer PL is lower than the etching rate of the initial channel layer pCH, the thickness of the etched portion of the first portion P1 can be less than the thickness of the etched portion of the second portion P2. Therefore, the first thickness W1” of the first portion P1 can be less than or equal to Figure 4C The first thickness W1' in the middle.

[0073] In another embodiment, besides Figure 4D In addition to the embodiments shown, when a portion of the second portion P2 is removed, the protective layer PL may not be removed and may instead be retained. For example, when the initial channel layer pCH is etched, the protective layer PL may not be etched, or a portion of the protective layer PL may be etched while the remainder of the protective layer PL may be retained. When the protective layer PL is retained, the first portion P1 may be covered by the protective layer PL. Therefore, when the protective layer PL is not removed, the first portion P1 may not be etched or may only be etched with a negligible amount. In embodiments where the first portion P1 is not etched, the first thickness W1” of the first portion P1 may be equal to Figure 4C The first thickness W1' in the middle. Refer to the following... Figure 5D Describe an implementation method for retaining the protective layer PL.

[0074] In some embodiments, the thickness difference between the first portion P1 and the second portion P2 exists even when the protective layer PL is retained. In other embodiments, the thickness difference between the first portion P1 and the second portion P2 exists even when the protective layer PL is not retained. That is, for all embodiments, the thickness difference between the first portion P1 and the second portion P2 exists regardless of whether the protective layer PL is retained.

[0075] However, since the inner surface of the first part P1 is not covered by the protective layer PL and is exposed to the outside, the inner surface of the first part P1 can be etched together with the inner surface of the second part P2.

[0076] Reference Figure 4E A preliminary gap-filling layer pGF can be formed, filling the first opening OP1 and extending above the preliminary stacked structure pSTK. A portion of the preliminary gap-filling layer pGF may be located within the first opening OP1. This portion of the preliminary gap-filling layer pGF may be surrounded by the preliminary channel layer pCH. The preliminary gap-filling layer pGF may contact the inner surface of the preliminary channel layer pCH. For example, the preliminary gap-filling layer pGF may contact the inner surface of the first portion P1 and the inner surface of the second portion P2. Another portion of the preliminary gap-filling layer pGF may be formed above the preliminary stacked structure pSTK. For example, the preliminary gap-filling layer pGF may contact the upper surface of the first portion P1.

[0077] Reference Figure 4FA portion of the initial gap-filling layer pGF can be etched to form the gap-filling layer GF. Because this portion of the initial gap-filling layer pGF is removed, a portion of the inner surface of the initial channel layer pCH can be exposed. For example, the upper portion of the second portion P2 can be exposed to the outside above the gap-filling layer GF, or the inner surface of the first portion P1 can be exposed to the outside. In one embodiment, the portion of the inner surface of the second portion P2 exposed due to the removal of a portion of the initial gap-filling layer pGF can be referred to as the upper portion of the second portion P2.

[0078] To etch the initial gap-filling layer pGF to a predetermined depth, an anisotropic dry etching process can be performed. When performing the dry etching process, the upper portion of the initial stacked structure pSTK can be protected by a first portion P1. Because the first portion P1 has a first thickness W1” greater than the thickness of the second portion P2, the first portion P1 is sufficient to protect the initial stacked structure pSTK when performing the dry etching process for etching the initial gap-filling layer pGF. For example, in one embodiment, during the etching of the initial gap-filling layer GF, the first portion P1 prevents or mitigates the etching of the initial stacked structure pSTK.

[0079] Reference Figure 4G A preliminary capping layer pCAP can be formed on the gap filling layer GF. The preliminary capping layer pCAP can contact the preliminary channel layer pCH. The preliminary capping layer pCAP can fill the first opening OP1. Besides... Figure 4G In addition to the embodiments shown, the initial cover layer pCAP can also extend above the initial stacked structure pSTK.

[0080] Reference Figure 4H The first portion P1 of the initial channel layer pCH can be removed. Furthermore, a portion of the second portion P2 of the initial channel layer pCH can be removed. Therefore, the channel layer CH can have a cylindrical shape extending along the Z-direction in the initial stacked structure pSTK.

[0081] Furthermore, a portion of the initial tunneling layer pTX located above the initial stacked structure pSTK, a portion of the initial charge trapping layer pCT located above the initial stacked structure pSTK, and a portion of the initial blocking layer pBX located above the initial stacked structure pSTK can be removed. For example, it can be as follows: Figure 4HThe diagram illustrates the removal of a portion of the initial tunneling layer pTX located above (e.g., in the Z direction) the initial stacked structure pSTK, a portion of the initial charge trapping layer pCT located above (e.g., in the Z direction) the initial stacked structure pSTK, and a portion of the initial blocking layer pBX located above (e.g., in the Z direction) the initial stacked structure pSTK. Therefore, the upper surface of the initial stacked structure pSTK can be exposed. For example, the upper surface of the hard mask HM can be exposed. Furthermore, a portion of the initial capping layer pCAP located at a height higher than the upper surface of the initial stacked structure pSTK can also be removed.

[0082] A cell plug CPL can be formed by removing the material layer above the initial stacked structure pSTK, which consists of a barrier layer BX, a charge trapping layer CT, a tunneling layer TX, a channel layer CH, a gap-filling layer GF, and a capping layer CAP. The channel layer CH included in the cell plug CPL can have a third thickness W3.

[0083] Reference Figure 4I The STK stack structure can be formed by replacing the second material layer SF with a third material layer CD and replacing the hard mask HM with an oxide material. The third material layer CD may include a conductive material. Figure 4H The oxide materials of the hard mask HM and the topmost interlayer insulating layer IIL can form Figure 4I The upper insulating layer UIL in the middle.

[0084] According to one embodiment of this disclosure, defects in the memory device 100 can be reduced by supplementing the process of reducing the thickness of the channel layer CH. As the thickness of the channel layer CH included in the cell plug CPL decreases, interference between adjacent memory cells in the Z direction can be reduced. According to one embodiment of this disclosure, the thickness of the channel layer CH can be reduced to a third thickness W3 by etching a portion of the second portion P2 of the preliminary channel layer pCH. When the thicknesses of both the first portion P1 and the second portion P2 of the preliminary channel layer pCH are reduced, defects may appear on the upper part of the preliminary stacked structure pSTK in the subsequent dry etching process. However, according to one embodiment of this disclosure, by using a protective layer PL, the first portion P1 can have a first thickness W1” larger than the third thickness W3 of the second portion P2, thereby preventing or reducing the occurrence of defects in the preliminary stacked structure pSTK when performing a dry etching process to etch the preliminary gap fill layer pGF.

[0085] Figures 5A to 5F This is a diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 5A to 5F Each corresponds to Figure 3A The A-A' cross-section. Combined Figures 5A to 5F The omission or simplification has been referenced. Figures 4A to 4I A detailed description of the configuration.

[0086] Reference Figure 5A A preliminary channel layer pCH can be formed along the upper surface of the preliminary stacked structure pSTK and the inner surface of the first opening OP1. The preliminary channel layer pCH may include a first portion P1 extending above the upper surface of the preliminary stacked structure pSTK and a second portion P2 extending above the inner surface of the first opening OP1. The first portion P1 may have a first thickness W1. The second portion P2 may have a second thickness W2. The first thickness W1 may be equal to or greater than the second thickness W2.

[0087] Reference Figure 5B A portion of the initial channel layer pCH can be etched. To reduce the thickness of the initial channel layer pCH, an isotropic wet etching process can be performed. The first portion P1 of the initial channel layer pCH can have a third thickness W3 that is less than the first thickness W1, and the second portion P2 of the initial channel layer pCH can have a fourth thickness W4 that is less than the second thickness W2. The third thickness W3 can be equal to or greater than the fourth thickness W4.

[0088] Reference Figure 5C A protective layer PL can be formed covering the first portion P1 of the preliminary channel layer pCH. The protective layer PL can contact the upper surface of the first portion P1. The protective layer PL can selectively cover the first portion P1. The protective layer PL can be formed on the upper surface of the preliminary channel layer pCH, and may not be formed on the inner surface of the preliminary channel layer pCH. For example, the protective layer PL may not cover the inner surface of the second portion P2. Therefore, even after the protective layer PL is formed, the second portion P2 can remain exposed to the outside. Furthermore, the protective layer PL may not cover the inner surface of the first portion P1. Therefore, after the protective layer PL is formed, the inner surface of the first portion P1 can be exposed to the outside.

[0089] The protective layer PL can be accessed through references, etc. Figure 4C The protective layer PL can be formed using processes such as those described above. For example, the protective layer PL can be formed by a process of nitriding the first portion P1 of the initial channel layer pCH, a process of depositing nitride material on the first portion P1 of the initial channel layer pCH, or by various other methods. After the protective layer PL is formed, the first portion P1 can have a third thickness W3' that is reduced from or equal to the third thickness W3.

[0090] Reference Figure 5DA portion of the initial channel layer pCH can be etched. For example, an isotropic wet etching process using selective etching of polysilicon material can be performed. The portion of the second part P2 not covered by the protective layer PL can be etched. Because the inner surface of the second part P2 is not covered by the protective layer PL and is exposed to the outside, a portion of the second part P2 can be removed. Because the etching process starts from the inside of the second part P2, the thickness of the second part P2 can be reduced. The etched second part P2 can have a fifth thickness W5 that is less than the fourth thickness W4.

[0091] Because the upper surface of the first part P1 is covered by the protective layer PL, when a portion of the second part P2 is etched, the first part P1 may not be etched, or may be etched less than the second part P2. Therefore, the first part P1 can have a greater thickness than the second part P2. The third thickness W3' of the first part P1 can be greater than the fifth thickness W5 of the second part P2. Figure 5D The third thickness W3' of the first part P1 can be less than or equal to Figure 5C The third thickness W3' in the middle.

[0092] For reference Figure 4D As described above, when a portion of the second portion P2 is etched, the protective layer PL may not be removed but can be retained. For example, if the etching process uses a material that selectively etches the initial channel layer pCH, the protective layer PL may not be etched but can be retained. In another example, because the etching rate of the protective layer PL is lower than the etching rate of the initial channel layer pCH, a portion of the etched protective layer PL can remain on the initial stacked structure pSTK. When a portion of the protective layer PL is etched, Figure 5D The thickness of the protective layer PL in the middle can be less than Figure 5C The thickness of the protective layer PL in the middle.

[0093] In another embodiment, the protective layer PL can be removed when a portion of the second portion P2 is etched. The etching rate of the protective layer PL is lower than the etching rate of the initial channel layer pCH. Therefore, even when the protective layer PL is removed, the thickness of the etched portion of the first portion P1 can be less than the thickness of the etched portion of the second portion P2.

[0094] In some embodiments, the thickness difference between the first portion P1 and the second portion P2 exists even when the protective layer PL is retained. In other embodiments, the thickness difference between the first portion P1 and the second portion P2 exists even when the protective layer PL is not retained. That is, for all embodiments, the thickness difference between the first portion P1 and the second portion P2 exists regardless of whether the protective layer PL is retained.

[0095] Reference Figure 5E This can form a preliminary gap-filling layer pGF that fills the first opening OP1 and extends above the preliminary stacked structure pSTK. The preliminary gap-filling layer pGF can contact the preliminary channel layer pCH and the protective layer PL.

[0096] Reference Figure 5F A portion of the initial gap fill layer pGF can be etched to form a gap fill layer GF that exposes the upper part of the initial channel layer pCH. Since a portion of the initial gap fill layer pGF has been removed, the inner surface of the first portion P1 of the initial channel layer pCH can be exposed, and the upper part of the inner surface of the second portion P2 can be exposed.

[0097] To etch the initial gap-filling layer pGF to a predetermined depth, an anisotropic dry etching process can be performed. When performing the dry etching process, the upper portion of the initial stacked structure pSTK can be protected by at least one of a protective layer PL or a first portion P1. Because the first portion P1 has a third thickness W3' that is greater than the thickness of the second portion P2, the first portion P1 is sufficient to protect the initial stacked structure pSTK when performing the dry etching process for etching the initial gap-filling layer pGF.

[0098] exist Figure 5F After the process shown, it can be performed in accordance with the reference. Figures 4G to 4I The process described corresponds to the process.

[0099] With reference Figures 4A to 4I Compared with the described implementation method, refer to Figures 5A to 5F The described implementation methods may further include Figure 5B The process is illustrated. When the thickness of the initial channel layer pCH is greater than a predetermined thickness, defects (e.g., voids) may occur during the formation of the initial gap fill layer pGF. Therefore, an additional etching process can be performed before forming the protective layer PL to reduce the overall thickness of the initial channel layer pCH to prevent defects (e.g., voids).

[0100] Figure 6 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0101] Reference Figure 6 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0102] Controller 3100 can be coupled to memory device 3200. Controller 3100 can be configured to access memory device 3200. For example, controller 3100 can be configured to control programming, reading, or erasing operations of memory device 3200, or to control background operations. Controller 3100 can be configured to provide an interface between memory device 3200 and a host. Controller 3100 can be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0103] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0104] Memory device 3200 may include a plurality of memory cells and can be coupled with Figure 1 The memory device 100 shown is configured in the same manner. For example, multiple memory cells may be stacked in the vertical direction.

[0105] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card such as a personal computer (PC) card, in the form of a PCMCIA card, a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC or eMMC), a secure digital card (SD) card (SD, mini SD, micro SD or SDHC), and a universal flash memory (UFS).

[0106] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0107] Reference Figure 7 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0108] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined through at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe interface.

[0109] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n can be coupled with... Figure 1 The memory device 100 shown is configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0110] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power voltage from host 4100 and use that power voltage to charge the SSD 4200. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power voltage to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and can provide auxiliary power to SSD 4200.

[0111] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0112] According to various embodiments of this disclosure, defects in memory blocks can be reduced by supplementing the process of reducing the thickness of the channel layer.

[0113] Cross-references to related applications

[0114] This application claims priority to Korean Patent Application No. 10-2024-0123130, filed with the Korean Intellectual Property Office on September 10, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of manufacturing a memory device, the method comprising the steps of: forming an opening through a layer stack; forming a channel layer including a first portion and a second portion, wherein the first portion extends on an upper surface of the layer stack and has a first thickness, and the second portion extends on an inner side surface of the opening and has a second thickness; forming a protective layer on the first portion of the channel layer; and etching a portion of the second portion so that the second portion has a third thickness smaller than the second thickness, wherein the third thickness of the second portion is smaller than the first thickness of the first portion.

2. The method of claim 1, wherein, In the step of forming the protective layer, the protective layer does not cover the inner side surface of the second portion.

3. The method of claim 2, wherein, In the step of etching the portion of the second portion, an inner side surface of the second portion not covered by the protective layer is etched.

4. The method of claim 1, further comprising: After the step of etching the portion of the second portion, a preliminary gap fill layer filling the opening and extending over the layer stack is formed; and a gap fill layer is formed by etching a portion of the preliminary gap fill layer, wherein the gap fill layer exposes an upper portion of the second portion, wherein, when etching the portion of the preliminary gap fill layer, the layer stack is prevented from being etched by the first portion.

5. The method of claim 4, further comprising: After the gap fill layer is formed, a cover layer is formed over the gap fill layer; and the first portion of the channel layer is removed.

6. The method of claim 1, wherein, In the step of forming the protective layer, the protective layer includes a nitride material.

7. The method of claim 1, wherein, In the step of etching the portion of the second portion, the protective layer is removed.

8. The method of claim 1, wherein, In the step of etching the portion of the second portion, the protective layer remains without being removed.

9. The method of claim 1, wherein, In the step of etching the portion of the second portion, the protective layer has an etching speed slower than an etching speed of the second portion.

10. The method of claim 1, further comprising: Before the opening is formed, the layer stack including alternately stacked sacrificial layers and interlayer insulating layers is formed.

11. The method of claim 10, further comprising: Before the channel layer is formed, a barrier layer, a charge trapping layer, and a tunneling layer are sequentially formed on an upper surface of the layer stack and the inner side surface of the opening.

12. The method of claim 11, further comprising: After the portion of the second portion is etched, a gap fill layer and a cover layer are formed in the opening; the protective layer and the first portion of the channel layer are removed; and a portion of the barrier layer, a portion of the charge trapping layer, and a portion of the tunneling layer located over the layer stack are removed.

13. The method of claim 12, further comprising: After the protective layer, the first portion of the channel layer, the portion of the barrier layer, the portion of the charge trapping layer, and the portion of the tunneling layer are removed, the sacrificial layers of the layer stack are replaced with conductive layers.

14. The method of claim 1, wherein, In the step of forming the protective layer, a coverage of the protective layer is smaller than all of the inner side surface of the second portion.

15. A method of manufacturing a memory device, the method comprising the steps of: forming an opening through a layer stack; forming a trench layer including a first portion and a second portion, wherein the first portion extends on an upper surface of the layered structure and the second portion extends on an inner side surface of the opening; forming a protective layer on the first portion of the trench layer; and etching a portion of the second portion that is not covered by the protective layer so that a thickness of the second portion is less than a thickness of the first portion.

16. The method of claim 15, wherein, In the step of forming the trench layer, the first portion has a first thickness; the second portion has a second thickness; and the first thickness is greater than or equal to the second thickness.

17. The method of claim 16, further comprising: After forming the trench layer, a portion of the trench layer is etched so that the first portion has a third thickness that is less than the first thickness and the second portion has a fourth thickness that is less than the second thickness.

18. The method of claim 17, wherein, In the step of etching the portion of the trench layer, the third thickness is greater than or equal to the fourth thickness.

19. The method of claim 17, wherein, In the step of forming the protective layer, the protective layer is formed over the first portion having the third thickness.

20. The method of claim 17, wherein, In the step of etching the portion of the second portion, the portion of the second portion is etched so that the second portion has a fifth thickness that is less than the fourth thickness, and when the portion of the second portion is etched, the first portion remains and has the third thickness due to the protective layer.

21. The method of claim 15, wherein, In the step of forming the protective layer, the protective layer does not cover an inner side surface of the second portion.

22. The method of claim 21, wherein, In the step of etching the portion of the second portion, an inner side surface of the second portion that is not covered by the protective layer is etched.

23. The method of claim 15, further comprising: After etching the portion of the second portion, a preliminary gap fill layer that fills the opening and extends over the layered structure is formed; and a gap fill layer is formed by etching a portion of the preliminary gap fill layer, wherein the gap fill layer exposes an upper portion of the second portion, wherein when the portion of the preliminary gap fill layer is etched, the layered structure is prevented from being etched by the first portion.

24. The method of claim 23, further comprising: After forming the gap fill layer, a cover layer is formed over the gap fill layer; and the protective layer and the first portion of the trench layer are removed.

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