Integrated circuit device

Abstract

An integrated circuit device includes: an active region extending longitudinally in a first direction on a substrate; a gate structure including a gate line extending longitudinally in a second direction perpendicular to the first direction on the active region, a high dielectric layer, and an interface dielectric layer; a nanosheet disposed on the fin upper surface of the active region and contacting the gate structure; a source / drain region disposed on the active region and contacting the nanosheet; and a lower insulating spacer located below the source / drain region in a direction perpendicular to both the first direction and the second direction and arranged in a source / drain recess extending from a fin upper surface of the active region, in which the interface dielectric layer includes: a first portion extending on the nanosheet; and a second portion extending over the source / drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0120320 filed on September 4, 2024, and Korean Patent Application No. 10-2024-0180427 filed on December 6, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to integrated circuit devices, and more specifically, to integrated circuit devices including field-effect transistors. Background Technology

[0004] With the rapid miniaturization of integrated circuit devices, the increased leakage current and high operating speeds necessitate ensuring operational accuracy within these devices. Therefore, various studies have been conducted to provide integrated circuit devices with structures capable of reducing leakage current and improving reliability. Summary of the Invention

[0005] The present invention provides an integrated circuit device having a structure that improves reliability by reducing the leakage current of field-effect transistors including nanosheet channel regions.

[0006] However, the problems to be solved by the present invention are not limited to those described above, and other problems will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: an active region extending longitudinally in a first direction on a substrate; a gate structure including a gate line extending longitudinally in a second direction perpendicular to the first direction on the active region, a high dielectric layer, and an interface dielectric layer; a nanosheet disposed on the upper surface of the active region and contacting the gate structure; a source / drain region disposed on the active region and contacting the nanosheet; and a lower insulating spacer located below the source / drain region in a third direction perpendicular to both the first and second directions, and disposed in a source / drain recess extending from the upper surface of the active region, wherein the interface dielectric layer comprises: a first portion extending on the nanosheet; and a second portion extending on the source / drain region, wherein a first thickness of the first portion is different from a second thickness of the second portion.

[0008] According to another aspect of the inventive concept, there is provided an integrated circuit device, comprising: an active region extending longitudinally on a substrate in a first direction; a gate structure comprising a gate line extending longitudinally on the active region in a second direction perpendicular to the first direction, a high dielectric layer, and an interface dielectric layer; a nanosheet arranged on a front side surface of the active region and at least partially surrounded by the gate structure; a source / drain region arranged on the active region and contacting the nanosheet; a lower insulating spacer between the source / drain region and the substrate; and a backside contact structure extending from a backside surface of the active region facing the front side surface through the active region and the lower insulating spacer and connected to the source / drain region, wherein the interface dielectric layer comprises a first portion extending on the nanosheet and a second portion extending on the source / drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.

[0009] According to another aspect of the inventive concept, there is provided an integrated circuit device, comprising: a plurality of active regions extending longitudinally on a substrate in a first direction and spaced apart from each other in a second direction crossing the first direction; a device separation layer on a sidewall of each of the plurality of active regions; a gate structure comprising a gate line extending longitudinally on the plurality of active regions in the second direction, a high dielectric layer, and an interface dielectric layer; a plurality of nanosheets arranged on a fin top surface of each of the plurality of active regions, each of the plurality of nanosheets comprising at least one nanosheet, and the at least one nanosheet at least partially surrounded by the gate structure; a source / drain region arranged on the plurality of active regions and arranged between a plurality of nanosheet stacks; and a lower insulating spacer below the source / drain region in a third direction perpendicular to both the first direction and the second direction and arranged in a source / drain recess extending from a fin top surface of the active region, wherein the interface dielectric layer comprises a first portion extending on the nanosheet and a second portion extending on the source / drain region, and wherein a first thickness of the first portion is less than a second thickness of the second portion. BRIEF DESCRIPTION OF DRAWINGS

[0010] The embodiments will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0011] FIG. 1 is a layout of an integrated circuit device according to an embodiment;

[0012] FIG. 2 is a cross-sectional view of the integrated circuit device taken along the line X1-X1 in FIG. 1 ;

[0013] FIG. 3A , FIG. 3B andFIG. 3C is an enlarged view of the region EX1 in FIG. 2

[0014] FIG. 4 is an enlarged view of the region EX2 in FIG. 2

[0015] FIG. 5 is a sectional view of the integrated circuit device taken along the line Y1-Y1 in FIG. 1

[0016] FIG. 6 is a view of a region corresponding to the section taken along the line X1-X1 in FIG. 1 and is a sectional view showing the integrated circuit device according to another embodiment;

[0017] FIG. 7A , FIG. 7B and FIG. 7C is an enlarged view of the region EX3 in FIG. 6

[0018] FIG. 8 is a layout of the integrated circuit device according to another embodiment;

[0019] FIG. 9 is a sectional view of the integrated circuit device taken along the line X1-X1 in FIG. 8

[0020] FIG. 10 is a sectional view of the integrated circuit device taken along the line Y1-Y1 in FIG. 8

[0021] FIG. 11 is a sectional view of the integrated circuit device taken along the line Y2-Y2 in FIG. 8

[0022] FIG. 12 to FIG. 24 is a sectional view showing a method of manufacturing the integrated circuit device according to the embodiment;

[0023] FIG. 25A , FIG. 25B , FIG. 25C , FIG. 25D and FIG. 26 are sectional views showing a method of manufacturing the integrated circuit device according to the embodiment; and

[0024] FIG. 27 to FIG. 30 is a sectional view showing a method of manufacturing the integrated circuit device according to the embodiment. DETAILED DESCRIPTION

[0025] ​​​​​​​Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for the same constituent elements and overlapping descriptions thereof are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It is noted that although not specifically described with respect to one embodiment, aspects described with respect to this one embodiment can be incorporated in different embodiments. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0026] In the inventive concept, the horizontal direction can include a first horizontal direction (X direction) or a first direction and a second horizontal direction (Y direction) or a second direction which cross each other. A third direction which vertically intersects the first horizontal direction (X direction) and the second horizontal direction (Y direction) can be referred to as a vertical direction (Z direction). In the inventive concept, the vertical level can be referred to as a height level according to the vertical direction (Z direction) according to any configuration.

[0027] FIG. 1 is a layout of the integrated circuit device 100 according to an embodiment.

[0028] FIG. 2 is a cross-sectional view of the integrated circuit device 100 taken along a line X1-X1 in FIG. 1

[0029] FIG. 3A , FIG. 3B and FIG. 3C are enlarged views of a region EX1 in FIG. 2

[0030] FIG. 4 is an enlarged view of a region EX2 in FIG. 2

[0031] FIG. 5 is a cross-sectional view of the integrated circuit device 100 taken along a line Y1-Y1 in FIG. 1

[0032] Referring to FIG. 2 , FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4 and FIG. 5 ​​​​An integrated circuit device 100 is described that includes a field effect transistor having a gate-all-around structure that includes a nanowire or nanosheet shaped active region and a gate that surrounds the active region. The term "surrounds" (or terms such as "encloses" or "encircles") as can be used herein is intended to broadly refer to an element, structure, or layer that extends around, encloses, encircles, or surrounds another element, structure, or layer on all sides, although there can be interruptions or gaps. Thus, for example, a layer of material that has voids or gaps therein can still "surround" another layer it encircles. For example, the integrated circuit device can include a multi-bridge channel field effect transistor (FET) (MBCFET) device. However, the inventive concepts are not limited to this, and the integrated circuit device 100 can also include planar FETs, finFETs, etc.

[0033] The integrated circuit device 100 can include an active region Fl that protrudes from the substrate 102 to define a trench region Tl (refer to FIG. 1) on the substrate 102. FIG. 5 ) The plurality of active regions Fl can extend longitudinally in parallel to each other in a first horizontal direction (X direction) on the substrate 102, and can be arranged spaced apart from each other in a second horizontal direction (Y direction).

[0034] The substrate 102 can include a semiconductor such as Si and Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, and / or InP. The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and / or "InP" used in embodiments of the inventive concepts can be referred to as including materials of the elements included in each term, but can not be referred to as representing a chemical formula of a stoichiometric relationship. The substrate 102 can include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity.

[0035] The device isolation layer 112 can be arranged in the trench region Tl that defines the active region Fl. The device isolation layer 112 can be located on and at least partially cover portions of the sidewalls of the active region Fl in the trench region Tl, and can be spaced apart from the substrate 102 in a vertical direction (Z direction). The device isolation layer 112 can include silicon oxide. The term "cover" (or terms such as "shroud") as can be used herein is intended to broadly refer to an element, structure, or layer that is directly on or over another element, structure, or layer, or has one or more other intervening elements, structures, or layers therebetween.

[0036] A plurality of gate lines 160 can be disposed on the active area F1. Each of the plurality of gate lines 160 can extend longitudinally in a second horizontal direction (Y direction). A plurality of nanosheet stacks NSS can be disposed on the fin-top surface FT of the active area F1 in an area in which the active area F1 and the plurality of gate lines 160 intersect. Each of the plurality of nanosheet stacks NSS can include at least one nanosheet facing the fin-top surface FT in a vertical direction (Z direction) at a position spaced apart from the fin-top surface FT of the active area F1. The term "nanosheet" used in the present inventive concept can mean an electrically conductive structure having a cross section substantially perpendicular to a direction of current flow. The nanosheet should be understood to include a nanowire.

[0037] Each of the plurality of nanosheet stacks NSS can include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other in a vertical direction (Z direction) on the active area F1. Vertical distances (vertical direction distances) of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 from the fin-top surface FT of the active area F1 can be different from each other. Each of the plurality of gate lines 160 can at least partially surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS and overlapping each other in the vertical direction (Z direction).

[0038] In FIG. 1 , a case in which a planar shape of the nanosheet stack NSS has a substantially rectangular shape is shown, but embodiments are not limited thereto. The nanosheet stack NSS can have various planar shapes according to planar shapes of each of the active areas F1 and each of the plurality of gate lines 160. In an embodiment, the plurality of nanosheet stacks NSS and the plurality of gate lines 160 can be disposed on one active area F1, and a configuration in which the plurality of nanosheet stacks NSS are arranged in a line in a first horizontal direction (X direction) on one active area F1 is shown. However, the number of nanosheet stacks NSS and the number of gate lines 160 disposed on one active area F1 can not be particularly limited.

[0039] Each of the first, second, and third nanosheets N1, N2, and N3 included in the nanosheet stack NSS can have a channel region. In some embodiments, each of the first, second, and third nanosheets N1, N2, and N3 can have a thickness in a range of about 4 nm to about 6 nm, but the thickness thereof is not limited thereto. In this case, the thickness of each of the first, second, and third nanosheets N1, N2, and N3 can represent a dimension in a vertical direction (Z direction). In some embodiments, the first, second, and third nanosheets N1, N2, and N3 can have substantially the same thickness in the vertical direction (Z direction). In other embodiments, at least some of the first, second, and third nanosheets N1, N2, and N3 can have substantially different thicknesses in the vertical direction (Z direction). In some embodiments, each of the first, second, and third nanosheets N1, N2, and N3 included in the nanosheet stack NSS can include a Si layer, a SiGe layer, or a combination thereof.

[0040] The first, second, and third nanosheets N1, N2, and N3 included in one nanosheet stack NSS can have the same size or similar size in the first horizontal direction (X direction). In other embodiments, at least some of the first, second, and third nanosheets N1, N2, and N3 included in one nanosheet stack NSS can have different sizes from each other in the first horizontal direction (X direction), unlike as shown in FIG. 1. FIG. 2 In this example, a case in which each of the plurality of nanosheet stacks NSS includes three nanosheets is shown, but embodiments are not limited thereto. For example, the nanosheet stack NSS can include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0041] Each of the plurality of gate lines 160 can include a main gate portion 160M and a plurality of sub gate portions 160S. The main gate portion 160M can be located on and at least partially cover an upper surface of the nanosheet stack NSS and extend longitudinally in the second horizontal direction (Y direction). The plurality of sub gate portions 160S can be integrally connected to the main gate portion 160M, and each of the plurality of sub gate portions 160S can be disposed between each of the first, second, and third nanosheets N1, N2, and N3 and between the first nanosheet N1 and the active region F1. In the vertical direction (Z direction), a thickness of each of the plurality of sub gate portions 160S can be less than a thickness of the main gate portion 160M.

[0042] Each of the plurality of gate lines 160 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may comprise one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may comprise one of TiN and TaN. The metal carbide may comprise TiAlC. However, the materials constituting the plurality of gate lines 160 are not limited to the examples described above.

[0043] An interface dielectric layer 151 and a high dielectric layer 154 may be disposed between the nanosheet stack NSS and the gate line 160. The interface dielectric layer 151 and the high dielectric layer 154 may surround the gate line 160. Any one of the plurality of gate lines 160, and the interface dielectric layer 151 and the high dielectric layer 154 at least partially surrounding that gate line 160, may constitute a "gate structure GS". The relative thickness of each of the interface dielectric layer 151 and the high dielectric layer 154 is not limited to... FIG. 2 , FIG. 3A , FIG. 3B and FIG. 3C Those shown in the figure. As needed, the integrated circuit device 100 may include a portion in which the thickness of the interface dielectric layer 151 is greater than the thickness of the high dielectric layer 154, a portion in which the thickness of the interface dielectric layer 151 is less than the thickness of the high dielectric layer 154, and a portion in which the thickness of the interface dielectric layer 151 is the same as or similar to the thickness of the high dielectric layer 154.

[0044] In a cross section along the second horizontal direction (Y direction), the interface dielectric layer 151 and the high dielectric layer 154 may at least partially surround each of the first nanosheet N1 to the third nanosheet N3 between the gate line 160 and the periphery of each of the first nanosheet N1 to the third nanosheet N3.

[0045] In some embodiments, the interface dielectric layer 151 may comprise a low dielectric material layer having a dielectric constant of about 9 or less, such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. For example, the interface dielectric layer 151 may comprise a silicon oxide layer. In some embodiments, the high dielectric layer 154 may comprise a material having a dielectric constant higher than that of the silicon oxide layer. For example, the high dielectric layer 154 may have a dielectric constant of about 10 to about 25. The high dielectric layer 154 may comprise hafnium oxide, but the embodiments are not limited thereto.

[0046] The interface dielectric layer 151 can be connected (contacted) to the surface of each of the plurality of active regions F1, and to the surface of each of the first nanosheets N1 to the third nanosheets N3 respectively included in each of the plurality of nanosheet stacks NSS, and can surround each of the plurality of gate lines 160. The high dielectric layer 154 can be disposed between the interface dielectric layer 151 and the gate line 160, and can be connected (contacted) to the bottom surface and sidewalls of the gate line 160.

[0047] Multiple active region recesses R1 can be formed on the active region F1. The vertical level of the lowest surface of each of the multiple active region recesses R1 can be lower than the vertical level of the upper surface FT of the fin of the active region F1.

[0048] Multiple source / drain regions 130 may be arranged between each of multiple gate lines 160. Each of the multiple source / drain regions 130 may be arranged adjacent to at least one of the multiple gate lines 160. Each of the multiple source / drain regions 130 may have a surface facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0049] like FIG. 3A , FIG. 3B and FIG. 3C As shown, each of the plurality of source / drain regions 130 may include a central portion 130M and a protruding portion 130P, the protruding portion 130P extending from the central portion 130M toward the gate structure GS (i.e., a gate structure including a plurality of sub-gate portions 160S and an interface dielectric layer 151 and a high dielectric layer 154 at least partially surrounding the plurality of sub-gate portions 160S). The central portion 130M may be connected (contacted) with the surface of each of the first nanosheets N1 to the third nanosheets N3 included in each of the plurality of nanosheet stacks NSS. The central portion 130M may include a first sidewall 130MS, the first sidewall 130MS being disposed on the same surface as the sidewall of each of the first nanosheets N1 to the third nanosheets N3 included in each of the plurality of nanosheet stacks NSS. The sidewall of each of the first nanosheets N1 to the third nanosheets N3 included in each of the plurality of nanosheet stacks NSS may constitute the first sidewall 130MS of the central portion 130M.

[0050] The protrusion 130P can be connected (contacted) with the surface of the interface dielectric layer 151 included in the plurality of gate structures GS. The protrusion 130P can include a second sidewall 130PS, which is disposed on the same surface as the sidewall of the interface dielectric layer 151 included in each of the plurality of gate structures GS. The sidewall of the interface dielectric layer 151 included in each of the plurality of gate structures GS can form the second sidewall 130PS of the protrusion 130P. The first sidewall 130MS of the central portion 130M and the second sidewall 130PS of the protrusion 130P can be disposed on different flat surfaces. There can be a plurality of protrusions 130P, and the plurality of protrusions 130P can overlap with the plurality of gate structures GS in a first horizontal direction (X direction).

[0051] Each of the plurality of source / drain regions 130 may include an epitaxially grown semiconductor layer. In some embodiments, each of the plurality of source / drain regions 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the source / drain region 130 includes an NMOS transistor, the source / drain region 130 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may include phosphorus (P), arsenic (As), or antimony (Sb). When the source / drain region 130 includes an NMOS transistor, the source / drain region 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may include boron (B) or gallium (Ga).

[0052] Multiple nanosheet stacks (NSS) can be arranged on the fin surface FT of each of the multiple active regions F1 in the regions where the multiple active regions F1 intersect with the multiple gate lines 160, and multiple FETs can be formed in the regions where the multiple active regions F1 intersect with the multiple gate lines 160 on the substrate 102.

[0053] In some embodiments, the source / drain regions 130 constituting the first group of PMOS transistors among the plurality of source / drain regions 130 can be electrically connected to a plurality of power lines to receive a positive voltage, and the source / drain regions 130 constituting the second group of NMOS transistors among the plurality of source / drain regions 130 can be electrically connected to a plurality of ground lines to receive a ground voltage or a negative voltage.

[0054] like FIG. 2As shown, the two sidewalls of each of the plurality of sub-gate portions 160S included in the gate line 160 may be spaced apart from the source / drain region 130, and the interface dielectric layer 151 and the high dielectric layer 154 are located therebetween. Each of the interface dielectric layer 151 and the high dielectric layer 154 may include a portion between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1 to the third nanosheet N3, and a portion between the sub-gate portion 160S included in the gate line 160 and the source / drain region 130.

[0055] like FIG. 4 As shown, the interface dielectric layer 151 may include: a first portion 151_1 extending to each of the first nanosheets N1 to the third nanosheets N3; and a second portion 151_2 extending to the source / drain region (130, specifically, the protruding portion 130P of the source / drain region 130). The high dielectric layer 154 may include: a first portion 154_1 extending to each of the first nanosheets N1 to the third nanosheets N3; and a second portion 154_2 extending to the source / drain region (130, specifically, the protruding portion 130P of the source / drain region 130). The first portion 151_1 of the interface dielectric layer 151 may have a first thickness T11 in the vertical direction (Z direction), and the second portion 151_2 of the interface dielectric layer 151 may have a second thickness T21 in the first horizontal direction (X direction). The first portion 154_1 of the high dielectric layer 154 may have a first thickness T12 in the vertical direction (Z direction), and the second portion 154_2 of the high dielectric layer 154 may have a second thickness T22 in the first horizontal direction (X direction). The first thickness T11 of the first portion 151_1 of the interface dielectric layer 151 may be different from the second thickness T21 of the second portion 151_2. For example, the first thickness T11 of the first portion 151_1 of the interface dielectric layer 151 may be less than the second thickness T21 of the second portion 151_2. The first thickness T12 of the first portion 154_1 of the high dielectric layer 154 may be substantially the same as the second thickness T22 of the second portion 154_2. Because the second thickness T21 of the second portion 151_2 of the interface dielectric layer 151 is greater than the first thickness T11 of the first portion 151_1, the leakage current between the source / drain region 130 and the gate line 160 can be effectively reduced.

[0056] like FIG. 2As shown, in this embodiment, below the source / drain region 130, a lower insulating spacer BS1 may be disposed in an active region recess R1 extending from the upper surface FT of the active region F1. The lower insulating spacer BS1 may be disposed vertically (Z-direction) between the source / drain region 130 and the active region F1. Furthermore, the lower insulating spacer BS1 may be connected (in contact) with the surface of the active region F1 in a first horizontal direction (X-direction) and with the surface of the device separation layer 112 in a second horizontal direction (Y-direction). The lower insulating spacer BS1 may overlap with the active region F1 in the first horizontal direction (X-direction) and may overlap with the device separation layer 112 in the second horizontal direction (Y-direction).

[0057] like FIG. 3A , FIG. 3B and FIG. 3C As shown, the lower insulating spacers BS11, BS12, and BS13 may surround the bottom surface 130B of the source / drain region (130, specifically, the central portion 130M of the source / drain region 130). The bottom surface 130B of the source / drain region 130 may be spaced apart from the active region F1 by the lower insulating spacers BS11, BS12, and BS13. Because the lower insulating spacers BS11, BS12, and BS13 are formed to at least partially fill the interior of the active region recess R1, the lower insulating spacers BS11, BS12, and BS13 may have a concave upper surface relative to the source / drain region 130, and may have an upper surface with a shape in which the vertical horizontal direction (X direction) increases from the central region of the lower insulating spacers BS11, BS12, and BS13 toward the peripheral region. The uppermost portions BS11_T, BS12_T and BS13_T of the lower insulating spacers BS11, BS12 and BS13 may respectively include the outermost portion of the lower insulating spacers BS11, BS12 and BS13.

[0058] like FIG. 3A As shown, the lower insulating spacer BS11 may overlap only with the active region F1 in the first horizontal direction (X direction). The uppermost portion BS11_T of the lower insulating spacer BS11 may have the same vertical level as the upper surface FT of the fin of the active region F1.

[0059] like FIG. 3BAs shown, the lower insulating spacer BS12 may partially overlap with the active region F1 and the gate structure GS in the first horizontal direction (X direction). For example, the lower insulating spacer BS12 may overlap with the active region F1 in the first horizontal direction (X direction), and may overlap with portions of the sub-gate portions 160S surrounding the lowermost ends of the plurality of sub-gate portions 160S and the sub-gate portions 160S surrounding the lowermost ends of the interface dielectric layer 151, as well as portions of the sub-gate portions 160S surrounding the lowermost ends of the high dielectric layer 154. The uppermost portion BS12_T of the lower insulating spacer BS12 may have a vertical level higher than the vertical level of the upper fin surface FT of the active region F1. For example, the uppermost portion BS12_T of the lower insulating spacer BS12 may overlap with portions of the sub-gate portions 160S surrounding the lowermost portions of the plurality of sub-gate portions 160S and the lowermost portions of the sub-gate portions 160S at the interface dielectric layer 151, as well as portions of the sub-gate portions 160S surrounding the lowermost portion of the high dielectric layer 154.

[0060] like FIG. 3C As shown, the lower insulating spacer BS13 may overlap only with the active region F1 in the first horizontal direction (X direction). Although not shown, the lower insulating spacer BS13 may also overlap with portions of the sub-gate portions 160S at least partially surrounding the lowermost ends of the plurality of sub-gate portions 160S and the sub-gate portions 160S at the lowermost ends of the interface dielectric layer 151, and portions of the sub-gate portions 160S at least partially surrounding the lowermost ends of the high dielectric layer 154.

[0061] The uppermost portion BS13_T of the lower insulating spacer BS13 may have the same vertical level as the upper surface FT of the fin of the active region F1. Although not shown, the uppermost portion BS13_T of the lower insulating spacer BS13 may overlap with portions of the sub-gate portions 160S at least partially surrounding the lowermost ends of the plurality of sub-gate portions 160S and the sub-gate portions 160S at the lowermost ends of the interface dielectric layer 151, and portions of the sub-gate portions 160S at least partially surrounding the lowermost ends of the high dielectric layer 154.

[0062] The lower insulating spacer BS13 may have a concave upper surface relative to the source / drain region 130, and may have an upper surface with a shape in which the vertical horizontal increases from the central region of the lower insulating spacer BS13 toward the peripheral region, but may include a portion in which the vertical horizontal remains relatively uniform in the peripheral region. After the lower insulating spacer BS13 is formed in the manufacturing process, the sacrificial semiconductor layer (see reference) is selectively etched. FIG. 16A to FIG. 16DIn a portion of the process of 103), because the thickness of the peripheral region of the lower insulating spacer BS13 is relatively smaller than the thickness of the central region of the lower insulating spacer BS13, the portion of the lower insulating spacer BS13 located in the peripheral region can be removed together with the portion of the lower insulating spacer BS13 located in the central region to form a... FIG. 3C Shapes that are similar in shape to those in the image.

[0063] In some embodiments, the lower insulating spacer BS1 may include an insulating material and may have a single layer or multiple layers. For example, the lower insulating spacer BS1 may include silicon nitride, silicon oxide, or a combination thereof.

[0064] A capping insulating pattern 168 may be disposed on the interface dielectric layer 151 and the gate line 160. The capping insulating pattern 168 may be located on the upper surface of the main gate portion 160M and at least partially cover the upper surface of the main gate portion 160M, and may be located on the upper surface of the portion of the interface dielectric layer 151 that at least partially surrounds the main gate portion 160M and at least partially cover the upper surface of the portion of the interface dielectric layer 151 that at least partially surrounds the main gate portion 160M. The capping insulating pattern 168 may include a silicon nitride layer and a silicon oxide layer.

[0065] Each of the gate line 160 and the capping insulating pattern 168 may have two sidewalls at least partially covered by a first insulating spacer 118. The first insulating spacer 118 may cover the two sidewalls of the main gate portion 160M on the upper surface of the plurality of nanosheet stacks NSS. The first insulating spacer 118 may be spaced apart from the gate line 160, and an interface dielectric layer 151 and a high dielectric layer 154 are located between the first insulating spacer 118 and the gate line 160.

[0066] A plurality of second insulating spacers 119, located on one sidewall of the source / drain region 130 and the other sidewall facing that sidewall and at least partially covering one sidewall of the source / drain region 130 and the other sidewall facing that sidewall, may be arranged on the upper surface of the device separation layer 112. In some embodiments, each of the plurality of second insulating spacers 119 may be integrally connected to an adjacent first insulating spacer 118. In other embodiments, at least some of the plurality of second insulating spacers 119 may be omitted.

[0067] Each of the plurality of first insulating spacers 118 and the plurality of second insulating spacers 119 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. The terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” as used in this invention may refer to materials comprising the elements included in each term, but may not be referred to as chemical formulas representing stoichiometric relationships.

[0068] Interface dielectric layer 151 and high dielectric layer 154 may be located on the surface of active region F1 and on the surface of each of the first nanosheets N1 to the third nanosheets N3 included in the nanosheet stack NSS, within a space defined by a pair of first insulating spacers 118, and at least partially cover the surface of active region F1 and the surface of each of the first nanosheets N1 to the third nanosheets N3 included in the nanosheet stack NSS. Interface dielectric layer 151 and high dielectric layer 154 may be located on the bottom surface and two sidewalls of gate line 160 and at least partially cover the bottom surface and two sidewalls of gate line 160. High dielectric layer 154 may be connected (contacted) to the bottom surface and two sidewalls of gate line 160, and interface dielectric layer 151 may be spaced apart from gate line 160 and high dielectric layer 154 is located between interface dielectric layer 151 and gate line 160.

[0069] The metal silicide layer 172 may be disposed on the upper surface of each of the plurality of source / drain regions 130. The metal silicide layer 172 may include a metal comprising Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er and / or Pd. For example, the metal silicide layer 172 may include titanium silicide, but is not limited thereto.

[0070] An insulating liner 142 and an inter-gate insulating layer 144 may be sequentially disposed on a plurality of source / drain regions 130 and a plurality of metal silicide layers 172. A first insulating spacer 118 and the plurality of source / drain regions 130 may be covered by the insulating liner 142. In some embodiments, the insulating liner 142 may comprise, but is not limited to, silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof. The inter-gate insulating layer 144 may comprise a silicon oxide layer, but is not limited to this embodiment.

[0071] Multiple source / drain contacts CA can be disposed on multiple source / drain regions 130. Each of the multiple source / drain contacts CA can penetrate the insulating liner 142 and the gate insulating layer 144 in the vertical direction (Z direction) and can be configured to be electrically connected to at least one of the multiple source / drain regions 130. Each of the multiple source / drain contacts CA can be connected (contacted) with a metal silicide layer 172 formed on the source / drain region 130. Each of the multiple source / drain contacts CA can be configured to be electrically connected to the source / drain region 130 via the metal silicide layer 172. Each of the multiple source / drain contacts CA can be spaced apart from the main gate portion 160M of the gate line 160 in a first horizontal direction (X direction), and a first insulating spacer 118 is located between each of the multiple source / drain contacts CA and the main gate portion 160M of the gate line 160.

[0072] Each of the plurality of source / drain contacts CA may include a conductive barrier layer 174 and a contact plug 176. The bottom surface and sidewalls of the contact plug 176 may be located on and at least partially covered by the conductive barrier layer 174. The conductive barrier layer 174 may include a metal or a conductive metal nitride. For example, the conductive barrier layer 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but embodiments are not limited thereto. The contact plug 176 may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), or combinations thereof, or alloys thereof, but embodiments are not limited thereto. In other embodiments, the conductive barrier layer 174 may be omitted from each of the plurality of source / drain contacts CA.

[0073] The upper surface of each of the source / drain contacts CA, the capping insulating pattern 168, the insulating liner 142, and the gate insulating layer 144 may be at least partially covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184 sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of capping insulating patterns 168, and the gate insulating layer 144. The etch stop layer 182 may include SiC, SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The interlayer insulating layer 184 may include an oxide layer, a nitride layer, an ultra-low k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, the interlayer insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiOC layer, a SiCOH layer, or a combination thereof, but the embodiments are not limited thereto.

[0074] Multiple source / drain via contacts VA can be disposed on multiple source / drain contacts CA. Each of the multiple source / drain via contacts VA can penetrate or extend through the upper insulating structure 180 and be electrically connected (contacted) to the source / drain contact CA. Each of the multiple source / drain regions 130 can be configured to be electrically connected to the source / drain via contact VA via a metal silicide layer 172 and the source / drain contact CA. The lower surface of each of the multiple source / drain via contacts VA can be electrically connected (contacted) to the upper surface of the source / drain contact CA. Each of the multiple source / drain via contacts VA may include Mo or W, but the embodiments are not limited thereto.

[0075] The upper surface of each of the upper insulating structure 180 and the plurality of source / drain via contacts VA may be at least partially covered by the upper insulating layer 192. The material of the upper insulating layer 192 may be substantially the same as the material of the interlayer insulating layer 184 described above.

[0076] Multiple upper wiring layers M1 may be arranged to penetrate or extend through the upper insulating layer 192. Each of the multiple upper wiring layers M1 may be electrically connected to a source / drain via contact VA located below it, selected from a plurality of source / drain via contacts VA. The multiple upper wiring layers M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but the embodiments are not limited thereto.

[0077] FIG. 6 Is along FIG. 1The diagram shows the region corresponding to the cross section of the integrated circuit device 100A intercepted by line X1-X1, and is a cross-sectional view showing the integrated circuit device 100A according to another embodiment.

[0078] FIG. 7A , FIG. 7B and FIG. 7C yes FIG. 6 A magnified view of region EX3 in the image.

[0079] Because of reference FIG. 6 , FIG. 7A , FIG. 7B and FIG. 7C The described integrated circuit device 100A is constructed to be similar to the integrated circuit device 100 described above. Therefore, in the following text, the description of components similar to those of integrated circuit device 100 may be simplified or omitted, and only the components different from those of integrated circuit device 100 will be described in detail.

[0080] Reference FIG. 6 , FIG. 7A , FIG. 7B and FIG. 7C The integrated circuit device 100A may include a source / drain region 130A and an inner insulating spacer 116 disposed between the source / drain region 130A and the gate structure (GS, specifically, the interface dielectric layer 151).

[0081] Multiple inner insulating spacers 116 can be arranged on the sidewalls of the source / drain region 130A. Each of the multiple inner insulating spacers 116 can be arranged between the upper surface FT of the fin of the active region F1 and the first nanosheet N1, between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3. The multiple inner insulating spacers 116 may include silicon nitride.

[0082] The source / drain region 130A may extend along the sidewalls of the nanosheet stack NSS and the inner insulating spacer 116. The sidewalls of the nanosheet stack NSS and the inner insulating spacer 116 may form part of the sidewalls of the source / drain region 130A. The sidewalls of the nanosheet stack NSS and the inner insulating spacer 116 may be arranged on the same flat surface.

[0083] like FIG. 7A As shown, the lower insulating spacer BS11 may overlap only with the active region F1 in the first horizontal direction (X direction). The uppermost portion BS11_T of the lower insulating spacer BS11 may have the same vertical level as the upper surface FT of the fin of the active region F1. The uppermost portion BS11_T of the lower insulating spacer BS11 may be connected (in contact) with the inner insulating spacer 116.

[0084] like FIG. 7B As shown, the lower insulating spacer BS12 may partially overlap with the active region F1, the gate structure GS, and the inner insulating spacer 116 in the first horizontal direction (X direction). For example, the lower insulating spacer BS12 may overlap with the active region F1 in the first horizontal direction (X direction), may overlap with portions of the sub-gate portions 160S surrounding the lowermost of the plurality of sub-gate portions 160S and the sub-gate portions 160S surrounding the lowermost of the interface dielectric layer 151, and may overlap with the inner insulating spacers 116 on the sub-gate portions 160S at the lowermost of the plurality of inner insulating spacers 116. The uppermost portion BS12_T of the lower insulating spacer BS12 may have a vertical level higher than the vertical level of the upper fin surface FT of the active region F1. For example, the uppermost portion BS12_T of the lower insulating spacer BS12 may overlap in the first horizontal direction (X direction) with portions of the sub-gate portions 160S surrounding the lowermost ends of the plurality of sub-gate portions 160S and the sub-gate portions 160S surrounding the lowermost ends of the interface dielectric layer 151, as well as portions of the sub-gate portions 160S surrounding the lowermost ends of the high dielectric layer 154, and may overlap with the inner insulating spacers 116 on the sub-gate portions 160S at the lowermost ends of the plurality of inner insulating spacers 116. The uppermost portion BS12_T of the lower insulating spacer BS12 may be connected (in contact) with the inner insulating spacers 116.

[0085] like FIG. 7C As shown, the lower insulating spacer BS13 may overlap only with the active region F1 in the first horizontal direction (X direction). The uppermost portion BS13_T of the lower insulating spacer BS13 may have the same vertical level as the upper surface FT of the fin of the active region F1. The lower insulating spacer BS13 may have a concave upper surface relative to the source / drain region 130A, and may have an upper surface with a shape in which the vertical level increases from the central region of the lower insulating spacer BS13 toward the peripheral region, but may include a portion in the peripheral region where the vertical level remains relatively uniform. The uppermost portion BS13_T of the lower insulating spacer BS13 may be connected (in contact) with the inner insulating spacer 116.

[0086] FIG. 8 This is the layout of the integrated circuit device 200 according to the embodiment.

[0087] FIG. 9 It is along FIG. 8 The cross-sectional view of the integrated circuit device 200 taken by line X1-X1 in the figure.

[0088] FIG. 10It is along FIG. 8 The cross-sectional view of the integrated circuit device 200 taken by line Y1-Y1 in the figure.

[0089] FIG. 11 It is along FIG. 8 A cross-sectional view of the integrated circuit device 200 taken by line Y2-Y2 in the diagram.

[0090] Because of reference FIG. 8 , FIG. 9 , FIG. 10 and FIG. 11 The described integrated circuit device 200 is constructed to be similar to the integrated circuit device 100 described above. Therefore, in the following text, the description of components similar to those of integrated circuit device 100 may be simplified or omitted, and only the components different from those of integrated circuit device 100 will be described in detail.

[0091] Reference FIG. 8 , FIG. 9 , FIG. 10 and FIG. 11 The integrated circuit device 200 may include: a back contact structure BKS that penetrates or extends through the active region F2 and is connected to the source / drain region 130; and a lower insulating spacer BS2 disposed on the sidewall of the back contact structure BKS.

[0092] Multiple active regions F2 may extend longitudinally in a first horizontal direction (X direction), extend parallel to each other, and be spaced apart from each other in a second horizontal direction (Y direction). Each of the multiple active regions F2 may include a front surface F2_F and a back surface F2_B facing the front surface F2_F. The multiple active regions F2 may include semiconductors (such as Si and / or Ge) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, InGaAs, and / or InP).

[0093] In some embodiments, the back-side contact structure BKS may extend from the back-side surface F2_B of a plurality of active regions F2 and penetrate the active regions F2 and the lower insulating spacer BS2 to be disposed below the source / drain region 130. The back-side contact structure BKS may include a back-side contact BKC and a back-side insulating spacer BKI. The back-side insulating spacer BKI may be disposed between the back-side contact BKC and the active region F2 closest to the back-side contact BKC, and between the back-side contact BKC and the lower insulating spacer BS2. The back-side contact BKC may be spaced apart from the active regions F2 in a first horizontal direction (X direction), and the back-side insulating spacer BKI is located between the back-side contact BKC and the active regions F2.

[0094] A metal silicide layer 190 may be disposed between the source / drain region 130 and the back contact structure BKS. The metal silicide layer 190 may be electrically connected (contacted) with the source / drain region 130 and the back contact structure BKS. The back contact structure BKS may penetrate or extend in the vertical direction (Z direction) through the space between two adjacent active regions F2 in the first horizontal direction (X direction) to connect (contact) with the metal silicide layer 190.

[0095] The back contact BKC can be configured to be electrically connected to the source / drain region 130 via a metal silicide layer 190. The constituent material of the metal silicide layer 190 can be the same as that of the metal silicide layer 172 described above. In some embodiments, the back contact BKC may comprise only a metal plug containing a single metal. In other embodiments, the back contact BKC may comprise a metal plug and a conductive barrier layer at least partially surrounding the metal plug. The metal plug may comprise Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu or combinations thereof, or alloys thereof, but the embodiments are not limited thereto. The conductive barrier layer may comprise a metal or a conductive metal nitride. For example, the conductive barrier layer may comprise Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN or combinations thereof, but the embodiments are not limited thereto.

[0096] The lower insulating spacer BS2 may be located on a portion of the sidewall of the back contact structure BKS in the first horizontal direction (X direction) and at least partially cover a portion of the sidewall of the back contact structure BKS in the first horizontal direction (X direction), and the active region F2 may be located on the remaining portion of the sidewall of the back contact structure BKS in the first horizontal direction (X direction) and at least partially cover the remaining portion of the sidewall of the back contact structure BKS in the first horizontal direction (X direction). For example, the lower insulating spacer BS2 may be located on the upper part of the sidewall of the back contact structure BKS in the first horizontal direction (X direction) and at least partially cover the upper part of the sidewall of the back contact structure BKS in the first horizontal direction (X direction), and the active region F2 may be located on the lower part of the sidewall of the back contact structure BKS in the first horizontal direction (X direction) and at least partially cover the lower part of the sidewall of the back contact structure BKS in the first horizontal direction (X direction). The lower insulating spacer BS2 and the back-side contact structure BKS may at least partially surround the bottom surface 130B of the source / drain region 130. Although not shown, the lower insulating spacer BS2 may be configured similarly to the lower insulating spacer BS1 described above and may have the features shown in the reference. FIG. 3A to FIG. 3C The various shapes described in the description.

[0097] In some embodiments, the integrated circuit device 200 may include: a lower insulating layer 194 located on and at least partially covering the back surface F2_B of each of the plurality of active regions F2; ​​and a plurality of lower wiring structures MPRs that penetrate or extend through the lower insulating layer 194 in a vertical direction (Z direction). The plurality of lower wiring structures MPRs may include lower wiring structures MPRs connected to back contact BKC. In some embodiments, the material of the lower insulating layer 194 may be substantially the same as the material of the upper insulating layer 192 described above. The material of each of the plurality of lower wiring structures MPRs may be substantially the same as the material of the plurality of upper wiring layers M1 described above.

[0098] However, the inventive concept is not limited to the aforementioned integrated circuit devices 100, 100A, and 200, and various integrated circuit devices with different structures can be provided within the scope of the inventive concept through the application of various transformations and modifications. For example, in integrated circuit device 200, similar to integrated circuit device 100A, an integrated circuit device including a source / drain region 130A instead of a source / drain region 130 and including an inner insulating spacer 116 can also be constructed.

[0099] According to an embodiment, lower insulating spacers BS1 and BS2 may be included below the source / drain region 130, and the lower insulating spacers BS1 and BS2 may reduce the amount of leakage current below the source / drain region 130 to provide integrated circuit devices 100, 100A and 200 with improved reliability.

[0100] Furthermore, according to the embodiments, since the process of increasing the doping concentration (dosage) of the well in the active region F1 to reduce the leakage current below the source / drain region 130 can be omitted, integrated circuit devices 100, 100A and 200 with improved reliability can be provided by reducing the occurrence of through-hole dislocation density (TDD) defects.

[0101] FIG. 12 to FIG. 24 This is a cross-sectional view illustrating a method of manufacturing an integrated circuit device 100 according to an embodiment. (Refer to...) FIG. 12 to FIG. 24 It describes the manufacturing reference. FIG. 1 , FIG. 2 , FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4 and FIG. 5 The example method of the described integrated circuit device 100, and with FIG. 1 , FIG. 2 , FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4and FIG. 5 The same reference numerals in the accompanying drawings may denote the same components, and their detailed descriptions are omitted herein.

[0102] FIG. 12 to FIG. 14 , FIG. 15A , FIG. 16A and FIG. 17 to FIG. 24 It is shown along FIG. 1 A diagram showing the region corresponding to the cross-section of the integrated circuit device 100 intercepted by line X1-X1, and FIG. 15B and FIG. 15C yes FIG. 15A A magnified view of region EX4 in the image, and FIG. 16B to FIG. 16D yes FIG. 16A A magnified view of region EX5 in the image.

[0103] Reference FIG. 12 A stacked structure SS can be formed in which multiple sacrificial semiconductor layers 103 and multiple nanosheet semiconductor layers NS are alternately stacked on a substrate 102. The multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS can comprise semiconductor materials having different etch selectivity to each other. In some embodiments, the multiple nanosheet semiconductor layers NS can comprise Si layers, and the multiple sacrificial semiconductor layers 103 can comprise SiGe layers. In some embodiments, the Ge content ratio in the multiple sacrificial semiconductor layers 103 can be constant. The SiGe layers constituting the multiple sacrificial semiconductor layers 103 can have a constant Ge content ratio selected in the range of about 5 atom% to about 60 atom% (e.g., about 10 atom% to about 40 atom%). The Ge content ratio in the SiGe layers constituting the multiple sacrificial semiconductor layers 103 can be selected in various ways as needed.

[0104] The substrate 102 may include semiconductor elements (such as Si and / or Ge) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, InGaAs and / or InP).

[0105] Each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS constituting the stacked structure SS can be formed using an epitaxial growth process. In some embodiments, the plurality of nanosheet semiconductor layers NS may comprise a single-crystal Si layer, and the plurality of sacrificial semiconductor layers 103 may comprise a SiGe layer.

[0106] Subsequently, the sacrificial semiconductor layer 103, the plurality of nanosheet semiconductor layers NS, and a portion of the substrate 102 can be etched to form a plurality of active regions F1 on the substrate 102 extending along a first horizontal direction (X direction). In this way, a first surface 102_1 of the substrate 102 can be formed, and the plurality of active regions F1 can be arranged on the first surface 102_1. The stacked structure SS of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS can be retained on the fin surface FT of each of the plurality of active regions F1.

[0107] Reference FIG. 13 Multiple pseudo-gate structures (DGS) can be formed on a stacked structure of multiple sacrificial semiconductor layers 103 and multiple nanosheet semiconductor layers NS.

[0108] Each of the plurality of dummy gate structures DGS can be formed to extend longitudinally in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS can have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In some embodiments, the dummy gate layer D124 may comprise polysilicon, and the capping layer D126 may comprise a silicon nitride layer.

[0109] Reference FIG. 14 After forming a plurality of first insulating spacers 118 covering the two sidewalls of each of the plurality of dummy gate structures DGS, portions of the plurality of sacrificial semiconductor layers 103 and portions of the plurality of nanosheet semiconductor layers NS can be etched using the plurality of dummy gate structures DGS and the plurality of first insulating spacers 118 as an etching mask. In this way, the plurality of nanosheet semiconductor layers NS can be divided into a plurality of nanosheet stacks NSS, each of the plurality of nanosheet stacks NSS comprising a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3.

[0110] By using an etching process, a stacked pattern SP comprising multiple sacrificial semiconductor layers 103 and multiple nanosheets N1, N2 and N3 can be formed.

[0111] Multiple active region recesses R1, at least partially exposing the sidewalls of the stacked pattern SP, can be formed using an etching process. To form the multiple active region recesses R1, dry etching operations, wet etching operations, or combinations thereof can be performed. The term "exposed" (or "exposed" etc.) may be used herein to describe the relationship between components and / or to refer to intermediate manufacturing processes, but it may not be necessary to expose all of a particular component in the completed device.

[0112] Reference FIG. 15A , FIG. 15B and FIG. 15CA lower insulating spacer BS1 can be formed in the active region recess R1. Because the lower insulating spacer BS1 is formed to at least partially fill the interior of the active region recess R1, the lower insulating spacer BS1 can have a concave upper surface relative to the source / drain region 130, and can have an upper surface that increases in shape from the central region of the lower insulating spacer BS1 toward the peripheral region in the first horizontal direction (X direction). The uppermost portions BS11_T, BS12_T, and BS13_T of the lower insulating spacers BS11, BS12, and BS13 can each include portions on the outermost periphery of the lower insulating spacer BS1.

[0113] like FIG. 15B As shown, the lower insulating spacer BS11 may overlap only with the active region F1 in the first horizontal direction (X direction). The uppermost portion BS11_T of the lower insulating spacer BS11 may have the same vertical level as the upper surface FT of the fin of the active region F1.

[0114] like FIG. 15C As shown, the lower insulating spacer BS12 may partially overlap with the active region F1 and the sacrificial semiconductor layer 103 in the first horizontal direction (X direction). For example, the lower insulating spacer BS12 may overlap with the active region F1 in the first horizontal direction (X direction) and may also overlap with a portion of the sacrificial semiconductor layer 103 located at the lowermost end of the plurality of sacrificial semiconductor layers 103. The uppermost portion BS12_T of the lower insulating spacer BS12 may have a vertical level higher than the vertical level of the upper surface FT of the fin of the active region F1. For example, the uppermost portion BS12_T of the lower insulating spacer BS12 may overlap with a portion of the sacrificial semiconductor layer 103 located at the lowermost end of the plurality of sacrificial semiconductor layers 103 in the first horizontal direction (X direction).

[0115] Reference FIG. 16A to FIG. 16D Multiple side recesses R2 can be formed by removing a portion of each of the multiple sacrificial semiconductor layers 103 in the stacked pattern SP that is exposed by each of the multiple active region recesses R1. To form the multiple side recesses R2, an etching composition material can be applied to the stacked pattern SP using the multiple active region recesses R1.

[0116] In some embodiments, such as FIG. 16B and FIG. 16C As shown, by applying an etching composition material to a stacked pattern SP, a portion of each of the plurality of nanosheets N1, N2, and N3, and the plurality of sacrificial semiconductor layers 103, can be selectively removed. In some embodiments, such as FIG. 16DAs shown, in a process that selectively removes portions of each of a plurality of nanosheets N1, N2, and N3 and a plurality of sacrificial semiconductor layers 103 among the plurality of nanosheets N1, N2, and N3 by applying an etching composition material to a stacked pattern SP, according to the chemical composition, although the lower insulating spacers (respectively...) FIG. 15A , FIG. 15B and FIG. 15C A portion of BS1, BS11, and BS12 in the original text is removed together, but it can also be done as follows: FIG. 16D The lower insulating spacer BS13 is formed as shown. Because the thickness of the outer region of the lower insulating spacer BS1 is relatively smaller than the thickness of its central region, the portion of the lower insulating spacer BS1 to be removed can correspond to the position on the outer region of the lower insulating spacer BS1.

[0117] Reference FIG. 17 Multiple first drain regions 130 can be formed on multiple lower insulating spacers BS1. In some embodiments, to form multiple source / drain regions 130, semiconductor material can be epitaxially grown from the sidewalls of each of the first nanosheet N1, second nanosheet N2, and third nanosheet N3 included in the nanosheet stack NSS, and from the sidewalls of each of the multiple sacrificial semiconductor layers 103. Because the surface of the active region F1 located below the bottom surface of each of the multiple active region recesses R1 is at least partially surrounded by the lower insulating spacers BS1, the semiconductor material can be epitaxially grown on the surface of the active region F1 located below the bottom surface of the multiple active region recesses R1.

[0118] Reference FIG. 18 In the formation located at FIG. 17 The resulting product having multiple source / drain regions 130 and at least partially covering FIG. 17 The insulating liner 142 of the resulting product having a plurality of source / drain regions 130 is formed therein, and after the inter-gate insulating layer 144 is formed on the insulating liner 142, the insulating liner 142 and the inter-gate insulating layer 144 can be planarized to at least partially expose the upper surface of the capping layer D126.

[0119] Subsequently, the capping layer D126 can be removed to expose the upper surface of the dummy gate layer D124, and the insulating liner 142 and the inter-gate insulating layer 144 can be partially removed so that the upper surface of the inter-gate insulating layer 144 and the upper surface of the dummy gate layer D124 are approximately at the same level.

[0120] Reference FIG. 19The dummy gate layer D124 and the oxide layer D122 below the dummy gate layer D124 can be removed to prepare the main gate space GSM, and multiple nanosheet stacks NSS can be exposed at least partially through the main gate space GSM.

[0121] Next, the multiple sacrificial semiconductor layers 103 retained on the active region F1 can be removed by the main gate space GSM, and the multiple sacrificial semiconductor layers 103 retained on the active region F1 can provide a sub-gate space GSS between each of the first nanosheet N1, the second nanosheet N2 and the third nanosheet N3 and between the first nanosheet N1 and the upper surface FT of the fin.

[0122] In some embodiments, to selectively remove the plurality of sacrificial semiconductor layers 103, the difference in etch selectivity between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the plurality of sacrificial semiconductor layers 103 can be utilized. Liquid or gaseous etchants can be used to selectively remove the plurality of sacrificial semiconductor layers 103. In some embodiments, to selectively remove the plurality of sacrificial semiconductor layers 103, CH3COOH-based etchants (such as etching solutions containing a mixture of CH3COOH, HNO3, and HF, and etching solutions containing a mixture of CH3COOH, H2O2, and HF) can be used, but the embodiments are not limited thereto.

[0123] Reference FIG. 20 An interface dielectric layer 151 can be formed in the main gate space (GSM) and the sub-gate space (GSS). An interface dielectric layer 151 covering the exposed surface of the third nanosheet N3 can be formed in the main gate space (GSM). An interface dielectric layer 151 covering the first nanosheets N1 to the third nanosheets N3 can be formed in the sub-gate space (GSS). An atomic layer deposition (ALD) process can be used to form the interface dielectric layer 151.

[0124] Reference FIG. 21 ,exist FIG. 20 On the resulting product, a high dielectric layer 154 can be formed conformally covering the surface of the interface dielectric layer 151. The ALD process can be used to form the high dielectric layer 154.

[0125] Reference FIG. 22 A main gate space (GSM) and a sub-gate space (GSS) can be formed on the high dielectric layer 154 (see reference). FIG. 21 A conductive layer 160L is formed on the gate of the device. The gate conductive layer 160L may include a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a chemical vapor deposition (CVD) process may be used to form the gate conductive layer 160L.

[0126] Reference FIG. 23Subsequently, the height of each of the gate forming conductive layer 160L, interface dielectric layer 151, and high dielectric layer 154 can be reduced by removing a portion of the upper surface of each of the gate forming conductive layer 160L, interface dielectric layer 151, and high dielectric layer 154, and a plurality of capping insulating patterns 168 can be formed covering the upper surface of each of the gate forming conductive layer 160L, interface dielectric layer 151, and high dielectric layer 154.

[0127] A portion of the gate forming conductive layer 160L can be removed from its upper surface, such that at least partially the upper surface of the inter-gate insulating layer 144 is exposed, and the main gate space (refer to) FIG. 19 A portion of the upper side of the GSM in the gate is cleared again. As a result, multiple gate lines 160 can be formed from the gate forming conductive layer 160L.

[0128] In this case, within the main gate space (GSM), the interface dielectric layer 151, the high dielectric layer 154, and the first insulating spacer 118 can also consume a portion of their respective upper sides, and thus their respective heights can be reduced. Subsequently, a capping insulating pattern 168 filling the main gate space (GSM) can be formed on the gate line 160.

[0129] Reference FIG. 24 Multiple source / drain contact holes (not shown) can be formed that penetrate or extend through the insulating structure including the insulating liner 142 and the gate inter-insulator layer 144 and expose the source / drain regions 130. Through the source / drain contact holes (not shown), specific areas of the multiple source / drain regions 130 can be removed by using an anisotropic etching process, and therefore, the multiple source / drain contact holes (not shown) can extend further toward the substrate 102.

[0130] Subsequently, portions of the source / drain region 130 exposed by a plurality of source / drain contact vias (not shown) may be consumed to form a metal silicide layer 172. In some embodiments, to form the metal silicide layer 172, a metal liner (not shown) may be formed on at least partially exposed surfaces of the source / drain region 130 and at least partially conformally covering at least partially exposed surfaces of the source / drain region 130, and may include a process that induces a reaction between the source / drain region 130 and the metal constituting the metal liner by applying heat treatment. After forming the metal silicide layer 172, the remaining portion of the metal liner may be removed. In some embodiments, when the metal silicide layer 172 comprises titanium silicide, the metal liner may comprise a Ti layer. Source / drain contacts CA comprising a conductive barrier layer 174 and contact plugs 176 may be formed on the metal silicide layer 172.

[0131] Subsequently, an upper insulating structure 180 can be formed by sequentially forming an etch stop layer 182 and an interlayer insulating layer 184 covering the upper surfaces of each of the gate inter-insulating layer 144, the plurality of source / drain contacts CA, and the plurality of capping insulating patterns 168. A plurality of via contacts VA can be formed that penetrate or extend through the upper insulating structure 180 in the vertical direction (Z direction) and are respectively connected to the plurality of source / drain contacts CA.

[0132] Subsequently, an upper insulating layer 192 may be formed on the upper surface of the upper insulating structure 180 and each of the plurality of source / drain via contacts VA, and at least partially covering the upper surface of the upper insulating structure 180 and each of the plurality of source / drain via contacts VA, and a plurality of upper wiring layers M1 may be formed that penetrate or extend through the upper insulating layer 192 in the vertical direction (Z direction) and are electrically connected to the plurality of source / drain via contacts VA respectively.

[0133] FIG. 25A , FIG. 25B , FIG. 25C , FIG. 25D and FIG. 26 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device 100A according to an embodiment. (Refer to...) FIG. 25A , FIG. 25B , FIG. 25C , FIG. 25D and FIG. 26 It describes the manufacturing reference. FIG. 6 and FIG. 7A to FIG. 7C The example method of the described integrated circuit device 100A, and FIG. 6 and FIG. 7A to FIG. 7C The same reference numerals in the accompanying drawings denote the same components, and their descriptions are omitted herein.

[0134] FIG. 25A and FIG. 26 Is along FIG. 1 A diagram showing the region corresponding to the cross section intercepted by line X1-X1, and... FIG. 25B , FIG. 25C and FIG. 25D yes FIG. 25A A magnified view of region EX6 in the image.

[0135] Reference FIG. 25A , FIG. 25B , FIG. 25C and FIG. 25D From respectively FIG. 16A , FIG. 16B , FIG. 16C and FIG. 16D The resulting product can have multiple inner insulating spacers 116 formed on multiple side recesses R2. The multiple inner insulating spacers 116 may include silicon nitride.

[0136] Next, by executing the above reference... FIG. 17 to FIG. 24 Processes similar to those described can form FIG. 26 The integrated circuit device 100A shown in the figure.

[0137] FIG. 27 to FIG. 30 This is a cross-sectional view illustrating a method of manufacturing an integrated circuit apparatus 200 according to an embodiment. (Refer to...) FIG. 27 to FIG. 30 The above reference describes the manufacturing process. FIG. 8 to FIG. 11 The example method of the described integrated circuit device 200, with FIG. 8 to FIG. 11 The same reference numerals in the accompanying drawings may denote the same components, and their descriptions are omitted herein.

[0138] FIG. 27 to FIG. 30 It is along FIG. 8 A diagram showing the region intercepted by line X1-X1.

[0139] Reference FIG. 27 After executing the above reference FIG. 11 to FIG. 24 On a product formed by a process similar to the described process, by using a photolithography process, substrate 102 can be polished from the back surface F2_B of substrate 102, and a portion of a plurality of active regions F2 can be removed to form a plurality of back contact holes BCH. At least a portion of the bottom surface of the lower insulating spacer BS2 can be exposed from the upper surface of the plurality of back contact holes BCH.

[0140] Reference FIG. 28 , through from FIG. 27 The resulting product removes at least a portion of the exposed lower insulating spacer BS2, and the plurality of back-side contact holes BCH can extend to expose the source / drain regions 130. The width of each of the plurality of back-side contact holes BCH in a first horizontal direction (X direction) can be defined by two adjacent active regions F2 among the plurality of active regions F2, and the width of each of the plurality of back-side contact holes BCH in a second horizontal direction (Y direction) can be defined by the device separation layer (see reference). FIG. 10 As defined in 112). In the first horizontal direction (X direction) and the second horizontal direction (Y direction), the width of each of the plurality of back-side contact holes BCH can increase toward the back-side surface F2_B of the active region F2.

[0141] Reference FIG. 29 A back-side insulating spacer BKI can be formed on the surface of the active region F2 exposed on the inner sidewalls of the plurality of back-side contact holes BCH and at least partially covering the surface of the active region F2 exposed on the inner sidewalls of the plurality of back-side contact holes BCH, and is formed by filling the back-side insulating spacer BKI and the device separation layer (see reference) with conductive material at least partially.FIG. 10 Each of the multiple back-side contact holes BCH defined in 112) can form multiple back-side contact structures BKS.

[0142] Reference FIG. 30 A lower insulating layer 194 can be formed covering the lower surface of multiple back-side contact structures BKS and the back-side surface F2_B of each of multiple active regions F2, and multiple lower wiring structures MPRs that penetrate or extend through the lower insulating layer 194 in the vertical direction (Z direction). The multiple lower wiring structures MPRs may include lower wiring structures MPRs connected to the back-side contacts BKC.

[0143] Although embodiments of the inventive concept have been specifically shown and described with reference to examples thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: an active region extending longitudinally in a first direction on a substrate; a gate structure including a gate line, a high dielectric layer, and an interface dielectric layer extending longitudinally in a second direction on the active region, the second direction being perpendicular to the first direction; a nanosheet disposed on a fin-top surface of the active region and contacting the gate structure; a source / drain region disposed on the active region and contacting the nanosheet; and a lower insulating spacer below the source / drain region in a third direction perpendicular to both the first and second directions and disposed in a source / drain recess extending from the fin-top surface of the active region, wherein the interface dielectric layer includes: a first portion extending over the nanosheet; and a second portion extending over the source / drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion. the source / drain region includes a central portion and a protruding portion extending from the central portion toward the gate structure.

2. The integrated circuit device of claim 1, wherein, 3. The integrated circuit device of claim 2, the central portion includes a first sidewall disposed on a same planar surface as a sidewall of the nanosheet, wherein wherein the protruding portion includes a second sidewall disposed on a same planar surface as a sidewall of the gate structure, and wherein the first sidewall of the central portion and the second sidewall of the protruding portion are disposed on different surfaces.

4. The integrated circuit device of claim 1, further comprising an inboard insulating spacer disposed between the source / drain region and the gate structure, the source / drain region is spaced apart from the gate structure with the inboard insulating spacer therebetween. wherein the first thickness of the first portion of the interface dielectric layer is less than the second thickness of the second portion.

5. The integrated circuit device of claim 1, wherein, the lower insulating spacer includes a silicon nitride layer, a silicon oxide layer, or a combination thereof.

6. The integrated circuit device of claim 1, wherein, the lower insulating spacer at least partially surrounds a bottom surface of the source / drain region.

7. The integrated circuit device of claim 1, wherein, the lower insulating spacer overlaps the active region only in the first direction.

8. The integrated circuit device of claim 1, wherein, the lower insulating spacer overlaps the active region and a portion of the gate structure in the first direction.

9. The integrated circuit device of claim 1, wherein, an uppermost end of the lower insulating spacer is at a same level as the fin-top surface or further from the substrate than the fin-top surface in the third direction.

10. The integrated circuit device of claim 1, wherein, 11. An integrated circuit device, comprising: an active region extending longitudinally in a first direction on a substrate; a gate structure including a gate line, a high dielectric layer, and an interface dielectric layer extending longitudinally in a second direction on the active region, the second direction being perpendicular to the first direction; a nanosheet disposed on a front-side surface of the active region and at least partially surrounded by the gate structure; a source / drain region disposed on the active region and contacting the nanosheet; and ​ a lower insulating spacer between the source / drain region and the substrate; and a backside contact structure extending through the active region and the lower insulating spacer from a backside surface of the active region facing the frontside surface and connected to the source / drain region, wherein the interface dielectric layer comprises: a first portion extending over the nanosheet; and a second portion extending over the source / drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.

12. The integrated circuit device of claim 11, wherein the lower insulating spacer is on a portion of a sidewall of the backside contact structure in the first direction, and wherein the active region is on another portion of the sidewall of the backside contact structure in the first direction.

13. The integrated circuit device of claim 11, wherein the backside contact structure comprises: a backside contact; and a backside insulating spacer arranged between the backside contact and the active region and between the backside contact and the lower insulating spacer in the first direction.

14. The integrated circuit device of claim 13, further comprising a metal silicide layer arranged between the backside contact and the source / drain region.

15. The integrated circuit device of claim 11, wherein the source / drain region comprises: a central portion; and a protruding portion extending from the central portion toward the gate structure, wherein sidewalls of the central portion and sidewalls of the protruding portion are arranged on different planar surfaces.

16. The integrated circuit device of claim 11, wherein, the lower insulating spacer comprises a silicon nitride layer.

17. The integrated circuit device of claim 11, wherein, the lower insulating spacer and the backside contact structure at least partially surround a bottom surface of the source / drain region.

18. An integrated circuit device, comprising: a plurality of active regions extending longitudinally in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction; a device separation layer on a sidewall of each of the plurality of active regions; a gate structure comprising a gate line extending longitudinally over the plurality of active regions in the second direction, a high dielectric layer, and an interface dielectric layer; a plurality of nanosheets arranged on a fin-top surface of each of the plurality of active regions, each of the plurality of nanosheets comprising at least one nanosheet, and the at least one nanosheet being at least partially surrounded by the gate structure; a source / drain region arranged on the plurality of active regions and arranged between the plurality of nanosheet stacks; and a lower insulating spacer below the source / drain region in a third direction perpendicular to both the first direction and the second direction and arranged in a source / drain recess extending from a fin-top surface of the active region, wherein the interface dielectric layer comprises: a first portion extending over the nanosheet, and a second portion extending over the source / drain region, and wherein a first thickness of the first portion is less than a second thickness of the second portion.

19. The integrated circuit device of claim 18, wherein, The integrated circuit device also includes a backside contact structure extending through the active region and the lower insulating spacer and connected to the source / drain region, and wherein the lower insulating spacer and the backside contact structure at least partially surround a bottom surface of the source / drain region.

20. The integrated circuit device of claim 18, wherein the lower insulating spacer surrounds a bottom surface of the source / drain region, and the bottom surface of the source / drain region is spaced apart from the active region by the lower insulating spacer.

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