Display panel and electronic device including the same

Abstract

The invention relates to a display panel and an electronic device including the same. The display panel includes: an insulating layer on a substrate; a first pixel electrode on the insulating layer; a partition wall on the insulating layer and surrounding the first pixel electrode in a plan view; a first intermediate layer on the first pixel electrode; and a counter electrode on the first intermediate layer and including: a first conductive layer partitioned by the partition wall; and a second conductive layer on the first conductive layer and extending to cover a side surface and a top surface of the partition wall.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0122578, filed on September 9, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display panel and an electronic device including the display panel. Background Technology

[0004] Recently, display panels have become thinner and lighter, and as a result, their applications are expanding. A display panel may include display elements as well as transistors, capacitors, and wiring for controlling the display elements. The display elements may be organic light-emitting diodes (OLEDs) and may include pixel electrodes, counter electrodes, and an intermediate layer disposed between the pixel electrodes and the counter electrodes.

[0005] The information disclosed above in this background section is intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] Due to leakage current through the intermediate layer, when one display element emits light, adjacent display elements may also emit light along with that display element, which may result in uneven brightness in the image.

[0007] One or more embodiments of this disclosure may be directed to a display panel for displaying high-quality images and an electronic device including the display panel. However, this disclosure is not limited to the above aspects and features.

[0008] The above and other aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing one or more of the embodiments presented in this disclosure.

[0009] According to one or more embodiments of the present disclosure, a display panel includes: an insulating layer on a substrate; a first pixel electrode on the insulating layer; a partition wall on the insulating layer and surrounding the first pixel electrode in a plan view; a first intermediate layer on the first pixel electrode; and a counter electrode on the first intermediate layer, and includes: a first conductive layer separated by the partition wall; and a second conductive layer on the first conductive layer and extending to cover the side surface and top surface of the partition wall.

[0010] In one embodiment, the display panel may further include: a pixel defining layer covering the edge of a first pixel electrode and having a first pixel opening overlapping the first pixel electrode. A partition wall is disposed on the pixel defining layer and surrounds the first pixel opening in a plan view. On the top surface of the partition wall, parallel to the substrate, a second conductive layer has approximately up to approximately The thickness.

[0011] In one embodiment, the cross-section of the partition wall may have an inverted conical shape.

[0012] In one embodiment, the side surface of the partition wall may be inclined at an angle of about 130° to about 140° relative to the top surface of the substrate.

[0013] In one embodiment, the distance from the top surface of the pixel defining layer to the top surface of the separator wall can be from about 1.1 μm to about 3 μm.

[0014] In one embodiment, in a plan view, the distance from the boundary of the first pixel opening to the boundary of the separator wall can be from approximately 4 μm to approximately 7.5 μm.

[0015] In one embodiment, the counter electrode may have a first thickness on the top surface of the partition wall parallel to the substrate, and the counter electrode may have a second thickness on the side surface of the partition wall, the second thickness being approximately 20% to approximately 30% of the first thickness.

[0016] In one embodiment, the first intermediate layer may include multiple transmitting units.

[0017] In one embodiment, the display panel may further include: a second-first pixel electrode and a second-second pixel electrode, on an insulating layer and spaced apart from the first pixel electrode; and a second intermediate layer on the second-first pixel electrode and the second-second pixel electrode. In a plan view, a partition wall may surround the second-first pixel electrode and the second-second pixel electrode.

[0018] In one embodiment, the display panel may further include a pixel defining layer covering the edges of each of the first pixel electrode, the second-1st pixel electrode, and the second-2nd pixel electrode. The pixel defining layer has a first pixel opening overlapping the first pixel electrode, a second-1st pixel opening overlapping the second-1st pixel electrode, and a second-2nd pixel opening overlapping the second-2nd pixel electrode.

[0019] In one embodiment, the display panel may further include: a spacer on the pixel defining layer between the second-1st pixel opening and the second-2nd pixel opening; and an auxiliary partition wall on the spacer.

[0020] In one embodiment, the display panel may further include: an auxiliary electrode on an insulating layer between the second-1st pixel electrode and the second-2nd pixel electrode; and an auxiliary partition wall on the auxiliary electrode. The pixel defining layer may further have an auxiliary opening overlapping the auxiliary electrode, and the second conductive layer may be in direct contact with the auxiliary electrode.

[0021] According to one or more embodiments of the present disclosure, a display panel includes: a first pixel electrode on a substrate; a pixel defining layer on the substrate, having a first pixel opening overlapping the first pixel electrode and a groove surrounding at least a portion of the first pixel electrode exposed by the first pixel opening; a first intermediate layer on the first pixel electrode; and a counter electrode on the first intermediate layer, including: a first conductive layer separated by the groove; and a second conductive layer on the first conductive layer, extending to cover the side surface and bottom surface of the groove.

[0022] In one embodiment, the side surface of the groove may be inclined at an angle of about 40° to about 50° relative to the top surface of the substrate.

[0023] In one embodiment, the first intermediate layer may include multiple transmitting units.

[0024] In one embodiment, the display panel may further include: a second-1 pixel electrode and a second-2 pixel electrode, on a substrate and spaced apart from the first pixel electrode; and a second intermediate layer on the second-1 pixel electrode and the second-2 pixel electrode. The pixel defining layer may further have a second-1 pixel opening overlapping the second-1 pixel electrode and a second-2 pixel opening overlapping the second-2 pixel electrode. In a plan view, a slot may completely surround the second-1 pixel opening and the second-2 pixel opening.

[0025] In one embodiment, the display panel may further include: a spacer having an auxiliary groove on the pixel defining layer between the second-1st pixel opening and the second-2nd pixel opening.

[0026] In one embodiment, the groove extends along the inner surface of the first pixel opening, and the first intermediate layer is separated by the groove into a first portion on the first pixel electrode and a second portion on the pixel defining layer.

[0027] In one embodiment, the display panel may further include a residual sacrificial layer between the pixel defining layer and the edge of the first pixel electrode.

[0028] According to one or more embodiments of this disclosure, an electronic device includes: a display panel; and a lower cover forming the appearance of the electronic device and including a front surface having an opening that exposes a portion of the display panel. The display panel includes: pixel electrodes on a substrate; a pixel defining layer covering the edges of the pixel electrodes and having pixel openings overlapping the pixel electrodes; an intermediate layer on the pixel electrodes; a counter electrode on the intermediate layer; and a spacer surrounding the pixel electrodes in a plan view. The intermediate layer includes a plurality of emitting units. The counter electrode includes: a first conductive layer spaced apart by the spacer; and a second conductive layer on the first conductive layer and extending to cover the spacer.

[0029] In one embodiment, the intermediate layer may include a plurality of emitting units for emitting light.

[0030] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part with reference to the accompanying drawings in the following detailed description, and in part will be apparent from them, or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments, with reference to the accompanying drawings, in which:

[0032] Figure 1A This is a schematic plan view illustrating a display panel according to an embodiment;

[0033] Figure 1B This is a schematic plan view illustrating a display panel according to an embodiment;

[0034] Figure 2 This is a schematic illustration of an equivalent circuit diagram of pixels included in a display panel according to an embodiment;

[0035] Figure 3 This is a schematic cross-sectional view illustrating the structure of a display element according to an embodiment;

[0036] Figure 4 This is a schematic plan view illustrating a display panel according to an embodiment;

[0037] Figure 5 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0038] Figure 6 This is a schematic cross-sectional view illustrating the partition wall according to an embodiment;

[0039] Figure 7 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0040] Figure 8 This is a schematic cross-sectional view illustrating the groove according to an embodiment;

[0041] Figure 9 This is a schematic plan view illustrating a display panel according to an embodiment;

[0042] Figure 10 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0043] Figure 11 This is a schematic plan view illustrating a display panel according to an embodiment;

[0044] Figure 12A This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0045] Figure 12B This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0046] Figure 13 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0047] Figure 14 This is a schematic plan view illustrating a display panel according to an embodiment;

[0048] Figure 15 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0049] Figure 16 This is a schematic cross-sectional view illustrating an organic light-emitting diode according to an embodiment;

[0050] Figure 17 This is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0051] Figure 18 This is a perspective view schematically illustrating an electronic device according to an embodiment; and

[0052] Figure 19 This is a block diagram schematically illustrating an electronic device according to an embodiment. Detailed Implementation

[0053] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the aspects and features of this disclosure to those skilled in the art. Accordingly, unnecessary processes, elements, and techniques for a full understanding of the aspects and features of this disclosure by those of ordinary skill in the art may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions may not be repeated.

[0054] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0055] Furthermore, as those skilled in the art will understand, given that each suitable feature of the various embodiments of this disclosure as a whole may be combined in part or in whole with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0056] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature illustrated in the figures to another element(s). It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “below” or “below” other elements or features would then be oriented “above” other elements or features. Thus, the illustrative terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0057] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Accordingly, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, and should be interpreted in light of possible variations in shape, such as those due to manufacturing processes. Thus, the shapes shown in the figures may not depict the actual shape of areas of the device, and this disclosure is not limited thereto.

[0058] In the diagram, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0059] As used herein, the phrase “in a plan view” may refer to a view of the target portion from above (e.g., when viewed in a direction perpendicular to the top surface of the substrate), and the phrases “in a section” and “in a cross-sectional view” may refer to a vertical section of the target portion as viewed from the side.

[0060] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or section described below may be referred to as the second element, component, area, layer, or section.

[0061] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," or "attached to" another element or layer, the element or layer may be directly on, directly connected to, or attached to the other element or layer, or one or more intermediary elements or layers may exist. Similarly, when a layer, area, or element is referred to as being "electrically connected" to another layer, area, or element, it may be directly electrically connected to the other layer, area, or element, or it may be indirectly electrically connected using one or more intermediary layers, areas, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between those two elements or layers, or one or more intermediary elements or layers may exist.

[0062] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and “having” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the listed items. For example, the expression “A and / or B” means A, B, or A and B. Expressions such as “at least one of…” modify the entire list of elements when following a list of elements, and not individual elements in that list. For example, the expressions “at least one of a, b, and c” and “at least one selected from the group consisting of a, b, and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0063] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms and not as terms of degree, and are intended to describe the inherent variations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the term “use” may be considered synonymous with the term “utilize.”

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0065] Figure 1A This is a schematic plan view illustrating a display panel according to an embodiment. Figure 1B This is a schematic plan view illustrating a display panel according to an embodiment.

[0066] refer to Figure 1A and Figure 1BThe display panel 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display panel 10 can provide an image (e.g., a specific or predetermined image) by using light emitted from a plurality of pixels arranged in the display area DA. As used herein, a pixel represents a sub-pixel that emits light of a desired color (e.g., a specific or predetermined color). For example, each pixel may emit red, green, or blue light. As another example, each pixel may emit red, green, blue, or white light.

[0067] In a plan view, the display area DA can be quadrilateral. In another embodiment, the display area DA can have another suitable polygonal shape, circular shape, elliptical shape, or irregular shape. The corners of the edges of the display area DA can be rounded.

[0068] In one embodiment, such as Figure 1A As shown, the display area DA of the display panel 10 may have a length in a first direction (e.g., the x direction) that is greater than its length in the second direction (e.g., the y direction). In another embodiment, as... Figure 1B As shown, the display area DA of the display panel 10 may have a length in a first direction (e.g., the x direction) that is smaller than the length in the second direction (e.g., the y direction).

[0069] A peripheral region PA is arranged around a display region DA, and the peripheral region PA may surround at least a portion of the display region DA (e.g., around its periphery). In one embodiment, the peripheral region PA may be a non-display region in which no pixels are arranged. Wiring, circuitry, and pads to which a printed circuit board or driver IC chip is attached for transmitting electrical signals to be applied to the display region DA may be arranged in the peripheral region PA.

[0070] Figure 2 This is a schematic illustration of an equivalent circuit diagram of pixels included in a display panel according to an embodiment.

[0071] refer to Figure 2 The pixels included in the display panel 10 may include pixel circuit PC and organic light-emitting diode (OLED) electrically connected to the pixel circuit PC.

[0072] The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. The pixel circuit PC may be electrically connected to a scan line SL and a data line DL. The first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. The second transistor T2 may be electrically connected to the scan line SL and the data line DL, and may transmit the data signal input through the data line DL to the first transistor T1 according to the scan signal input through the scan line SL.

[0073] The capacitor Cst can be connected to the second transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the data signal received from the second transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0074] An organic light-emitting diode (OLED) may include a pixel electrode (e.g., an anode), a counter electrode (e.g., a cathode), and an intermediate layer disposed between the pixel electrode and the counter electrode. A common voltage ELVSS may be applied to the counter electrode.

[0075] The first transistor T1 can be connected to the driving voltage line PL and the capacitor Cst, and the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the value of the voltage stored in the capacitor Cst. The OLED can emit light with a desired brightness (e.g., a certain or predetermined brightness) according to the driving current.

[0076] Figure 2 An example pixel circuit PC includes two transistors and one capacitor, but this disclosure is not limited thereto. In another embodiment, the pixel circuit PC may include at least three transistors and / or at least two capacitors.

[0077] in addition, Figure 2 For example, the first transistor T1 and the second transistor T2 are each provided as P-type transistors, but this disclosure is not limited thereto. In another embodiment, some of the transistors included in the pixel circuit PC may each be provided as N-type transistors, and the other transistors may each be provided as P-type transistors. In another embodiment, the transistors may each be provided as N-type transistors.

[0078] Figure 3 This is a cross-sectional view schematically illustrating the structure of a display element according to an embodiment.

[0079] refer to Figure 3 According to the embodiments, the display element may be an organic light-emitting diode (OLED). Each of the first OLED1 included in a first pixel, the second OLED2 included in a second pixel, and the third OLED3 included in a third pixel may include a pixel electrode 210 (e.g., an anode), a counter electrode 230 (e.g., a cathode), and an intermediate layer 220 disposed between the pixel electrode 210 and the counter electrode 230. The pixel electrode 210 may be provided independently in the first OLED1, the second OLED2, and the third OLED3, respectively.

[0080] Pixel electrode 210 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), gallium zinc oxide (GZO), or aluminum zinc oxide (AZO). Pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or suitable compounds thereof. For example, pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0081] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may comprise a metal, alloy, conductive compound, or suitable combination thereof having a low work function. Counter electrode 230 may comprise a first conductive layer 231 and a second conductive layer 233.

[0082] The first conductive layer 231 may include silver (Ag) or a silver alloy. The silver alloy may be a silver-magnesium alloy (AgMg), a silver-ytterbium alloy (AgYb), a silver-palladium-copper alloy (AgPdCu), or a silver-lithium alloy (AgLi), each having a silver content of 90% or greater. The first conductive layer 231 may be formed by a thermal evaporation process.

[0083] The second conductive layer 233 may include a transparent conductive oxide. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), gallium zinc oxide (GZO), or aluminum zinc oxide (AZO). The second conductive layer 233 may be formed by a sputtering process. The second conductive layer 233 may be continuously and jointly provided in the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3.

[0084] Intermediate layer 220 may comprise a polymer or low molecular weight organic material that emits light of a desired color (e.g., a specific or predetermined color). In addition to various suitable organic materials, intermediate layer 220 may further comprise metal-containing compounds such as organometallic compounds, inorganic materials such as quantum dots, etc. In one embodiment, intermediate layer 220 may comprise at least two emitting units (e.g., at least two emitting layers or stacks) sequentially stacked between pixel electrode 210 and counter electrode 230, and a charge generation layer CGL disposed between the at least two emitting units. When intermediate layer 220 comprises multiple emitting units (e.g., multiple emitting layers or stacks) and a charge generation layer CGL, the organic light-emitting diode may be referred to as a tandem light-emitting device.

[0085] A transmitter unit (e.g., a transmitter layer or stack) may include a transmitter layer, a first functional layer, and a second functional layer. The first and second functional layers may be disposed below and above the transmitter layer, respectively. The first functional layer may include a hole transport layer (HTL), or may include a hole injection layer and a hole transport layer (HIL / HTL). The second functional layer may be an optional component disposed above the transmitter layer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0086] A charge generation layer (CGL) can include a negative charge generation layer (n-CGL) and a positive charge generation layer (p-CGL). The negative charge generation layer (n-CGL) can be an n-type charge generation layer. The negative charge generation layer (n-CGL) can supply electrons. The negative charge generation layer (n-CGL) can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. A positive charge generation layer (p-CGL) can be a p-type charge generation layer. The positive charge generation layer (p-CGL) can supply holes. The positive charge generation layer (p-CGL) can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0087] The intermediate layer 220 of each of the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3 may include a first emission unit EU1 and a second emission unit EU2 (e.g., a first emission layer or stack and a second emission layer or stack) stacked in sequence, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2.

[0088] The first emitting unit EU1 of the first organic light-emitting diode OLED1 may include a hole injection layer and a hole transport layer HIL / HTL, a green auxiliary layer GAXL, a green emitting layer GEML, and an electron transport layer ETL, sequentially stacked on the pixel electrode 210. The first emitting unit EU1 of the second organic light-emitting diode OLED2 may include a hole injection layer and a hole transport layer HIL / HTL, a blue emitting layer BEML, and an electron transport layer ETL, sequentially stacked on the pixel electrode 210. The first emitting unit EU1 of the third organic light-emitting diode OLED3 may include a hole injection layer and a hole transport layer HIL / HTL, a red auxiliary layer RAXL, a red emitting layer REML, and an electron transport layer ETL, sequentially stacked on the pixel electrode 210. The red auxiliary layer RAXL and the green auxiliary layer GAXL are layers that can be included or added to adjust the resonant distance, and may include a resonant auxiliary material. In one embodiment, the red auxiliary layer RAXL and the green auxiliary layer GAXL may include the same material as the hole transport layer HTL. The green auxiliary layer GAXL may be omitted as needed or desired.

[0089] The second emitting unit EU2 of the first organic light-emitting diode OLED1 may include a hole transport layer HTL, a green auxiliary layer GAXL, a green emitting layer GEML, an electron transport layer ETL, and an electron injection layer EIL, sequentially stacked on the charge generation layer CGL. The second emitting unit EU2 of the second organic light-emitting diode OLED2 may include a hole transport layer HTL, a blue emitting layer BEML, an electron transport layer ETL, and an electron injection layer EIL, sequentially stacked on the charge generation layer CGL. The second emitting unit EU2 of the third organic light-emitting diode OLED3 may include a hole transport layer HTL, a red auxiliary layer RAXL, a red emitting layer REML, an electron transport layer ETL, and an electron injection layer EIL, sequentially stacked on the charge generation layer CGL.

[0090] The green emitting layer GEML and the green auxiliary layer GAXL can be patterned to correspond to the first organic light-emitting diode OLED1. The blue emitting layer BEML can be patterned to correspond to the second organic light-emitting diode OLED2. The red emitting layer REML and the red auxiliary layer RAXL can be patterned to correspond to the third organic light-emitting diode OLED3.

[0091] The thickness of each of the green emitting layer GEML, blue emitting layer BEML, and red emitting layer REML can be determined based on the resonant distance. In some embodiments, the hole transport layer HTL, hole injection layer and hole transport layer HIL / HTL, electron transport layer ETL, electron injection layer EIL, and charge generation layer CGL can be deposited on the entire surface or substantially the entire surface of the display area DA. At least one of the hole transport layer HTL, hole injection layer and hole transport layer HIL / HTL, electron transport layer ETL, electron injection layer EIL, and charge generation layer CGL can be separated by a separator and can be independently provided in each of the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3. In some embodiments, the first conductive layer 231 can be separated by a separator and can be independently provided in each of the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3. In some embodiments, the first conductive layer 231 can be continuously and jointly provided in the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3.

[0092] The capping layer 250 can be disposed on the counter electrode 230. The capping layer 250 can be used to improve luminous efficiency based on the principle of constructive interference. The capping layer 250 can include a suitable material having a refractive index of 1.6 (e.g., at a wavelength of 589 nm). The capping layer 250 can be an organic capping layer including organic materials, an inorganic capping layer including inorganic materials, or a composite capping layer including both organic and inorganic materials. In one embodiment, the capping layer 250 can include lithium fluoride (LiF).

[0093] Figure 4 This is a schematic plan view illustrating a display panel according to an embodiment.

[0094] Figure 4 Examples include the first to third pixels PX1, PX2 and PX3, the pixel defining layer PDL and the separator SP arranged in the display area DA of the display panel 10. Figure 4 The pixels PX1, PX2, and PX3 shown represent the emission regions of pixels PX1, PX2, and PX3 defined by the first pixel opening to the third pixel opening OP1, OP2, and OP3 in the pixel definition layer PDL.

[0095] refer to Figure 4 Pixels PX1, PX2, and PX3 can be arranged in the display area DA of the display panel 10. Pixels PX1, PX2, and PX3 may include a first pixel PX1 emitting green light, a second pixel PX2 emitting blue light, and a third pixel PX3 emitting red light. The green light may be light in the wavelength band of approximately 495 nm to approximately 580 nm, the red light may be light in the wavelength band of approximately 580 nm to approximately 780 nm, and the blue light may be light in the wavelength band of approximately 400 nm to approximately 495 nm. In one embodiment, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit white light.

[0096] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged in a pattern such as stripes or a diamond shape (e.g., Arrangement, The arrangement follows a suitable rule (e.g., a fixed or predetermined rule) of the format (which is an officially registered trademark of Samsung Display Co., Ltd.). In one embodiment, third pixel PX3 and first pixel PX1 are arranged alternately along a second direction (e.g., the y-direction) to form a first pixel column, and second pixel PX2 is arranged repeatedly along the second direction (e.g., the y-direction) to form a second pixel column. The first pixel column and the second pixel column may be arranged alternately along a first direction (e.g., the x-direction).

[0097] A pixel limiting layer (PDL) can define pixel apertures OP1, OP2, and OP3. The PDL can also define the emission region of each of pixels PX1, PX2, and PX3 using these apertures. For example, the emission region of the first pixel PX1 can be defined by the first pixel aperture OP1, the emission region of the second pixel PX2 can be defined by the second pixel aperture OP2, and the emission region of the third pixel PX3 can be defined by the third pixel aperture OP3.

[0098] Each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may have a substantially quadrilateral shape in a planar view, but this disclosure is not limited thereto. In another embodiment, each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may have another suitable polygonal shape, a circular shape, or an elliptical shape. The first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 may have a chamfered shape.

[0099] like Figure 4 As shown, the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 can have different sizes (e.g., different areas). For example, the size (e.g., area) of the second pixel opening OP2 can be larger than the size (e.g., area) of the first pixel opening OP1 and the third pixel opening OP3. The size (e.g., area) of the first pixel opening OP1 can be greater than or equal to the size (e.g., area) of the third pixel opening OP3. In another embodiment, the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 can have the same or substantially the same size (e.g., area) as each other.

[0100] The pixel defining layer (PDL) may include an organic insulating material such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The PDL may be black. In one embodiment, the PDL may include a light-shielding material and may be black. The light-shielding material may include a resin or paste comprising carbon black, carbon nanotubes, or a black dye; metal particles such as nickel (Ni), aluminum (Al), molybdenum (Mo), and / or suitable alloys thereof; metal oxide (e.g., chromium oxide) particles; or metal nitride (e.g., chromium nitride) particles. When the PDL includes a light-shielding material, reflections caused by the metal structure disposed beneath the PDL can be reduced.

[0101] Display panel 10 may include separators SP. In one embodiment, separator SP may be a partition wall disposed on pixel defining layer PDL. In another embodiment, separator SP may be a slot defined by pixel defining layer PDL. Separator SP may be arranged to at least partially surround each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 in a plan view (e.g., at least partially around its periphery). In one embodiment, separator SP may be arranged to completely surround each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 in a plan view (e.g., completely around its periphery). For example, separator SP may define a plurality of units having a closed shape in a plan view. Separator SP may have a grid structure. In another embodiment, separator SP may surround each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 in a plan view (e.g., around its periphery) and may have at least one open side. The plurality of units defined by separator SP may have at least one open side and thus may be connected to each other.

[0102] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged in a corresponding one of a plurality of units. For example, the first pixel PX1 can be arranged in a first region CA1 defined by a first unit, the second pixel PX2 can be arranged in a second region CA2 defined by a second unit, and the third pixel PX3 can be arranged in a third region CA3 defined by a third unit. The separator SP can separate the intermediate layer 220 arranged in each of the first region CA1, the second region CA2, and the third region CA3 to reduce leakage current through the intermediate layer 220 between adjacent pixels.

[0103] Figure 5 This is a schematic cross-sectional view illustrating a display panel according to an embodiment. Figure 6 This is a schematic cross-sectional view of the partition wall according to an embodiment.

[0104] Figure 5 Schematic example along Figure 4 The cross-section of the display panel 10 is taken by line I-I', and Figure 6 Example Figure 5 An enlarged view of section II. Figure 5 and Figure 6 An example separator SP includes (for example,) a separator wall PW arranged on a pixel-defining layer PDL.

[0105] refer to Figure 5The display panel 10 may include a substrate 100. The substrate 100 may include glass, metal, or polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or suitable mixtures thereof. In one embodiment, the substrate 100 may have a multilayer structure comprising at least two substrate layers, each comprising a polymer resin, and an inorganic material layer disposed between the at least two substrate layers.

[0106] In another embodiment, substrate 100 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In other words, substrate 100 may be a semiconductor substrate comprising a semiconductor material. More specifically, substrate 100 may be a silicon substrate comprising silicon (Si) (e.g., a silicon semiconductor substrate). In the process of manufacturing display panel 10 using substrate 100 comprising a semiconductor material, processes commonly used in the semiconductor technology field for manufacturing thin-film transistors can be applied to form ultra-small pixels. Therefore, display panel 10 can display ultra-high resolution images.

[0107] A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The buffer layer 101 may increase the smoothness of the top surface of the substrate 100, or may prevent or minimize the penetration of impurities from the substrate 100 into the active layer Act of the thin-film transistor (TFT).

[0108] The first pixel circuit PC1 and the second pixel circuit PC2 can be arranged on the buffer layer 101. The first pixel circuit PC1 and the second pixel circuit PC2 can have the same or similar structures. In the following description, for ease of illustration, the first pixel circuit PC1 will be described in more detail.

[0109] The first pixel circuit PC1 may include a thin-film transistor (TFT) and a capacitor Cst. Figure 5 The thin-film transistor TFT shown can be compared with the reference above. Figure 2 The first transistor T1 described corresponds to this. A thin-film transistor (TFT) may include an active layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0110] The active layer Act may be disposed on the buffer layer 101. In one embodiment, the active layer Act may comprise a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon. In another embodiment, the active layer Act may comprise an oxide-based semiconductor material, such as an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0111] In another embodiment, when the substrate 100 is provided as a semiconductor substrate, the buffer layer 101 may be omitted, and the active layer Act may be formed as part of the substrate 100.

[0112] The gate insulating layer 103 may be disposed on the active layer Act, and the gate electrode GE may be disposed on the gate insulating layer 103 to overlap with the active layer Act in a plan view. The gate electrode GE may comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and may be formed as a multilayer or a single layer comprising at least one of the above materials.

[0113] A first interlayer insulating layer 105 may be disposed on the gate electrode GE, and a second capacitor electrode CE2 may be disposed on the first interlayer insulating layer 105. At least a portion of the gate electrode GE may overlap with the second capacitor electrode CE2 in a plan view and may serve as the first capacitor electrode CE1 of the capacitor Cst. In other words, the gate electrode GE and the first capacitor electrode CE1 may be integrally provided as a single unit. The second capacitor electrode CE2 may comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and may be formed as a multilayer or a single layer, each comprising at least one of the above materials.

[0114] The second interlayer insulating layer 107 can be disposed on the second capacitor electrode CE2, and the source electrode SE and drain electrode DE can be disposed on the second interlayer insulating layer 107. The source electrode SE and drain electrode DE can each comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and can each be formed as a multilayer or a single layer comprising at least one of the above materials. For example, the source electrode SE and drain electrode DE can each have a Ti / Al / Ti multilayer structure.

[0115] The gate insulating layer 103, the first interlayer insulating layer 105, and the second interlayer insulating layer 107 may each comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may each be formed as a multilayer or a single layer comprising at least one of the above materials.

[0116] A planarization layer (also referred to as an insulating layer) 109 may be disposed on the first pixel circuit PC1 and the second pixel circuit PC2. The planarization layer 109 may comprise an organic insulating material. For example, the planarization layer 109 may comprise benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or suitable mixtures thereof.

[0117] The first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2) may be spaced apart from each other on the planarization layer 109. In one embodiment, the first OLED1 and the second OLED2 may emit light of different colors. For example, the first OLED1 may emit green light, and the second OLED2 may emit blue light. In another embodiment, the first OLED1 and the second OLED2 may emit light of the same color. For example, the first OLED1 and the second OLED2 may each emit white light. Hereinafter, for ease of illustration, the case in which the first OLED1 and the second OLED2 emit light of different colors will be described in more detail.

[0118] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The counter electrode 230 of the first OLED 1 may include a first conductive layer 231a and a second conductive layer 233. The second organic light-emitting diode (OLED) 2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a counter electrode 230. The counter electrode 230 of the second OLED 2 may include a first conductive layer 231b and a second conductive layer 233.

[0119] The first pixel electrode 210a can be electrically connected to the first pixel circuit PC1 through a contact hole penetrating the planarization layer 109. In other words, the first organic light-emitting diode OLED1 can be electrically connected to the first pixel circuit PC1. Similarly, the second pixel electrode 210b can be electrically connected to the second pixel circuit PC2 through a contact hole penetrating the planarization layer 109. The second organic light-emitting diode OLED2 can be electrically connected to the second pixel circuit PC2. Each of the first pixel electrode 210a and the second pixel electrode 210b can be connected to the first pixel circuit PC1 as described above. Figure 3 The pixel electrode 210 described corresponds to this.

[0120] The pixel defining layer (PDL) can be arranged to cover the edges of each of the first pixel electrode 210a and the second pixel electrode 210b. The PDL can define a first pixel opening OP1 that exposes a portion of the first pixel electrode 210a and a second pixel opening OP2 that exposes a portion of the second pixel electrode 210b. The PDL can prevent or substantially prevent arcing by increasing the distance between the edge of the first pixel electrode 210a and the counter electrode 230, and the distance between the edge of the second pixel electrode 210b and the counter electrode 230.

[0121] The separator wall PW can be disposed on the pixel defining layer PDL as a separator SP. The separator wall PW can be in direct contact with the top surface of the pixel defining layer PDL. In one embodiment, the separator wall PW may include an organic insulating material. In one embodiment, the separator wall PW may include a negative photoresist material whose solubility relative to a developer is reduced by exposure. In another embodiment, the separator wall PW may have a multilayer structure having an organic insulating material layer and an inorganic insulating material layer. In yet another embodiment, the separator wall PW may include an inorganic insulating material.

[0122] The cross-section of the partition wall PW can have an inverted conical shape, with a width at the lower end smaller than that at the upper end. For example, as... Figure 6 As shown, the first width w1, which is the width of the top surface PWu of the partition wall PW, can be greater than the second width w2, which is the width of the bottom surface of the partition wall PW. In one embodiment, in order to form an inverted conical shape of the partition wall PW, the first width w1 can be approximately 5 μm or greater.

[0123] The separator wall PW may have a first side surface PWs1 and a second side surface PWs2 that are opposite to each other. The first side surface PWs1 of the separator wall PW may be tilted at a first angle θ1 relative to the top surface PDLu of the pixel defining layer PDL (or the top surface of the substrate 100).

[0124] In one embodiment, the first angle θ1 can be approximately 130° to approximately 140°. When the first angle θ1 is less than 130°, the intermediate layer 220 may not be completely isolated by the separator wall PW and may remain connected, and therefore leakage current may flow between adjacent organic light-emitting diodes. When the first angle θ1 is greater than 140°, the counter electrode 230 may become too thin or may be isolated at the first side surface PWs1 and the second side surface PWs2 of the separator wall PW, and therefore the organic light-emitting diode may not emit light.

[0125] A separator wall PW can be disposed between pixel openings OP1, OP2, and OP3, and the edge of the top surface PWu of the separator wall PW (e.g., the boundary of the separator wall PW) can be (e.g., in a plan view) spaced apart from the boundary of the adjacent pixel opening by a first distance d1. The first distance d1 can be from approximately 4 μm to approximately 7.5 μm. When the first distance d1 is less than 4 μm, pixel openings OP1, OP2, and OP3 may be damaged during the process of forming the separator wall PW. When the first distance d1 is greater than 7.5 μm, the resolution of the display panel 10 may be reduced, and the counter electrode 230 may break.

[0126] The top surface PWu of the separator PW can be spaced apart from the top surface PDLu of the pixel defining layer PDL by a second distance d2. The second distance d2 can be approximately 1.1 μm to approximately 3 μm. When the second distance d2 is less than 1.1 μm, the intermediate layer 220 may not be completely separated by the separator PW and may remain connected. When the second distance d2 is greater than 3 μm, the counter electrode 230 may become too thin at the first side surface PWs1 and the second side surface PWs2 of the separator PW, or may be separated.

[0127] Intermediate layer 220 may be disposed on pixel definition layer PDL. Intermediate layer 220 may include a first intermediate layer 220a disposed in first region CA1, a second intermediate layer 220b disposed in second region CA2, and a dummy intermediate layer 220d disposed on the top surface PWu of partition wall PW.

[0128] For reference Figure 3 As described, the intermediate layer 220 may include a plurality of emitting units (e.g., a plurality of emitting layers or stacks) and a charge generation layer CGL disposed between the emitting units. In other words, each of the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may be referred to as a tandem light-emitting device.

[0129] The green emission layer GEML and green auxiliary layer GAXL forming the intermediate layer 220 can be arranged to correspond to the first pixel opening OP1. The blue emission layer BEML can be arranged to correspond to the second pixel opening OP2. The red emission layer REML and red auxiliary layer RAXL can be arranged to correspond to the third pixel opening OP3. Each of the hole injection layer and hole transport layer HIL / HTL, electron transport layer ETL, charge generation layer CGL, hole transport layer HTL, and electron injection layer EIL forming the intermediate layer 220 can be formed on the entire surface or substantially the entire surface of the display area DA by a thermal evaporation process. The intermediate layer 220 can be divided into a first intermediate layer 220a, a second intermediate layer 220b, and a dummy intermediate layer 220d by a partition wall PW having an inverted conical shape. The material used to form the intermediate layer 220 can have a low step coverage and therefore can be separated from the first side surface PWs1 and the second side surface PWs2 of the separator wall PW, or even if it is deposited on a portion of each of the first side surface PWs1 and the second side surface PWs2 of the separator wall PW, it can be separated without being connected. In other words, the first intermediate layer 220a can be separated by the first side surface PWs1 of the separator wall PW, and the second intermediate layer 220b can be separated by the second side surface PWs2 of the separator wall PW. A dummy intermediate layer 220d can be disposed on the top surface PWu of the separator wall PW and can be spaced apart from the first intermediate layer 220a and the second intermediate layer 220b in a third direction (e.g., the z direction). The first intermediate layer 220a and the second intermediate layer 220b can be spaced apart from each other, and the dummy intermediate layer 220d is between them, thereby reducing or preventing leakage current from flowing through the intermediate layer 220 between adjacent first organic light-emitting diodes OLED1 and second organic light-emitting diodes OLED2. Therefore, the display panel 10 can display high-quality images without uneven brightness or color mixing.

[0130] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. The first conductive layer 231 may include a first-1 conductive layer 231a disposed in the first region CA1, a first-2 conductive layer 231b disposed in the second region CA2, and a dummy conductive layer 231d disposed on the top surface PWu of the partition wall PW.

[0131] The first conductive layer 231 may comprise silver (Ag) or a silver alloy and may be formed on the entire or substantially the entire surface of the display area DA by a thermal evaporation process. The first conductive layer 231 may be divided into a first-1 conductive layer 231a, a first-2 conductive layer 231b, and a dummy conductive layer 231d by a partition wall PW having an inverted conical shape. The material used to form the first conductive layer 231 may have a low step coverage and therefore may not be deposited on the side surfaces of the partition wall PW, or even if deposited on a portion of the side surfaces, may be separated without connection. In other words, the first-1 conductive layer 231a may be separated by the first side surface PWs1 of the partition wall PW, and the first-2 conductive layer 231b may be separated by the second side surface PWs2 of the partition wall PW. The dummy conductive layer 231d can be disposed on the top surface PWu of the partition wall PW, and can be spaced apart from the first-1 conductive layer 231a and the first-2 conductive layer 231b in a third direction (e.g., the z direction).

[0132] The second conductive layer 233 may comprise a transparent conductive oxide and may be formed on the entire surface or substantially the entire surface of the display area DA by a sputtering process. The second conductive layer 233 has a relatively high step coverage and can therefore extend to cover the first side surface PWs1, the top surface PWu, and the second side surface PWs2 of the partition wall PW. In other words, the second conductive layer 233 may be provided jointly in the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0133] refer to Figure 6 On a surface parallel or substantially parallel to the substrate 100 (e.g., on the top surface PWu of the partition wall PW), the counter electrode 230 may have a first thickness 230tu. The counter electrode 230 may have a second thickness 230ts at the thinnest portion of the counter electrode 230 at each of the first side surfaces PWs1 and the second side surfaces PWs2 of the partition wall PW. The second thickness 230ts may be approximately 20% to approximately 30% of the first thickness 230tu. In one embodiment, to prevent excessive increase in resistance of the counter electrode 230 or to prevent breakage of the counter electrode 230, the second thickness 230ts may be approximately...

[0134] In one embodiment, the thickness t1 of the second conductive layer 233 on the first pixel electrode 210a and the second pixel electrode 210b can be approximately up to approximately When the thickness t1 of the second conductive layer 233 is less than When the electrode 230 is blocked by the separator PW, the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may not emit light. When the thickness t1 of the second conductive layer 233 is greater than 1, the electrode 230 may be blocked by the separator PW, and therefore the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may not emit light. In this case, the time required for the process of depositing transparent conductive oxides increases, leading to a decrease in the mass production rate of the display panel 10.

[0135] In some embodiments, to prevent the resistance from increasing due to a portion of the second conductive layer 233 becoming too thin at the first side surface PWs1 and the second side surface PWs2 of the separator wall PW, the thickness t1 of the second conductive layer 233 may be greater than or equal to approximately

[0136] The capping layer 250 can be disposed on the counter electrode 230. In one embodiment, on the first pixel electrode 210a and the second pixel electrode 210b, the sum of the thickness t1 of the second conductive layer 233 of the counter electrode 230 and the thickness t2 of the capping layer 250 can be approximately By adjusting the thickness t2 of the capping layer 250, the sum of the thickness t1 of the second conductive layer 233 of the counter electrode 230 and the thickness t2 of the capping layer 250 is approximately... The luminous efficiency of organic light-emitting diodes can be improved based on the principle of constructive interference.

[0137] Figure 7 This is a schematic cross-sectional view illustrating a display panel according to an embodiment. Figure 8 This is a schematic cross-sectional view of the groove according to an embodiment.

[0138] Figure 7 Schematic example along Figure 4 The cross-section of the display panel 10 is taken by line I-I', and Figure 8 yes Figure 7 A magnified view of section III. Figure 7 and Figure 8 An example separator SP includes (for example,) a slot G defined by a pixel-defined layer PDL.

[0139] Let's refer to each other. Figure 7 and Figure 8 A buffer layer 101 can be disposed on the substrate 100, and a first pixel circuit PC1 and a second pixel circuit PC2 can be disposed on the buffer layer 101. A planarization layer 109 can be disposed on the first pixel circuit PC1 and the second pixel circuit PC2, and a first organic light-emitting diode OLED1 and a second organic light-emitting diode OLED2 can be disposed on the planarization layer 109. The first organic light-emitting diode OLED1 can be electrically connected to the first pixel circuit PC1, and the second organic light-emitting diode OLED2 can be electrically connected to the second pixel circuit PC2.

[0140] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The counter electrode 230 of the first OLED 1 may include a first conductive layer 231a and a second conductive layer 233. The second organic light-emitting diode (OLED) 2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a counter electrode 230. The counter electrode 230 of the second OLED 2 may include a first conductive layer 231b and a second conductive layer 233.

[0141] The pixel defining layer (PDL) may be arranged to cover the edges of each of the first pixel electrode 210a and the second pixel electrode 210b. The PDL may define a first pixel opening OP1 that exposes a portion of the first pixel electrode 210a, a second pixel opening OP2 that exposes a portion of the second pixel electrode 210b, and a slot G surrounding each of the first pixel opening OP1 and the second pixel opening OP2 (e.g., around their peripheries). In one embodiment, the slot G may completely surround each of the first pixel opening OP1 and the second pixel opening OP2 (e.g., completely around their peripheries). In another embodiment, the slot G may surround each of the first pixel opening OP1 and the second pixel opening OP2 (e.g., around their peripheries), but may have at least one open side.

[0142] The slot G can be formed by removing a portion of the pixel-defining layer PDL. The slot G can have an undercut shape or an eaves shape, wherein the top surface PDLu of the pixel-defining layer PDL protrudes in a direction toward the center of the slot G. In other words, as... Figure 8 As shown, the width w3 of the slot G in the top surface PDLu of the pixel-defining layer PDL can be smaller than the width w4 of the bottom surface Gb of the slot G.

[0143] The trench G may have a first side surface Gs1 and a second side surface Gs2 facing each other. The first side surface Gs1 of the trench G may be tilted relative to the top surface of the substrate 100 at a second angle θ2. In one embodiment, the second angle θ2 may be approximately 40° to approximately 50°. When the second angle θ2 is less than 40°, the thickness of the counter electrode 230 may be excessively reduced at the first side surface Gs1 and the second side surface Gs2 of the trench G, or the counter electrode 230 may be isolated, and therefore the organic light-emitting diode may not emit light. When the second angle θ2 is greater than 50°, the intermediate layer 220 may not be completely isolated by the trench G and may remain connected, and therefore leakage current may flow between adjacent organic light-emitting diodes.

[0144] The bottom surface Gb of the slot G can be spaced apart from the top surface PDLu of the pixel-defining layer PDL by a third distance d3. The third distance d3 can be greater than or equal to approximately 1.1 μm. When the third distance d3 is less than 1.1 μm, the intermediate layer 220 may not be completely separated by the slot G and may remain connected. Figure 7 and Figure 8 For example, the bottom surface Gb of the groove G is spaced apart from the top surface 109u of the planarization layer 109 in a third direction (e.g., the z-direction or the thickness direction), but this disclosure is not limited thereto. In another embodiment, the groove G may penetrate the pixel defining layer PDL, such that the top surface 109u of the planarization layer 109 can be exposed by the groove G, and the bottom surface Gb of the groove G may be formed.

[0145] Intermediate layer 220 can be disposed on pixel definition layer PDL. Intermediate layer 220 may include a first intermediate layer 220a disposed in the first region CA1, a second intermediate layer 220b disposed in the second region CA2, and a dummy intermediate layer 220d disposed on the bottom surface Gb of the slot G.

[0146] As referenced above Figure 3 As described, the intermediate layer 220 may include a plurality of emitter units (e.g., a plurality of emitter layers or stacks) and a charge generation layer CGL disposed between the emitter units. The intermediate layer 220 may be divided into a first intermediate layer 220a, a second intermediate layer 220b, and a dummy intermediate layer 220d by a groove G having an undercut shape. The material used to form the intermediate layer 220 may have a low step coverage and therefore may not be deposited on the first side surface Gs1 and the second side surface Gs2 of the groove G, or may be separated without being connected even when deposited on a portion of each of the first side surface Gs1 and the second side surface Gs2 of the groove G. In other words, the first intermediate layer 220a may be separated by the first side surface Gs1 of the groove G, and the second intermediate layer 220b may be separated by the second side surface Gs2 of the groove G. The dummy intermediate layer 220d may be disposed on the bottom surface Gb of the groove G and may be spaced apart from the first intermediate layer 220a and the second intermediate layer 220b in a third direction (e.g., the z direction).

[0147] Counter electrode 230 can be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. The first conductive layer 231 may be divided by a groove G having an undercut shape into a first-1 conductive layer 231a disposed in a first region CA1, a first-2 conductive layer 231b disposed in a second region CA2, and a dummy conductive layer 231d disposed on the bottom surface Gb of the groove G. The first-1 conductive layer 231a may be separated by a first side surface Gs1 of the groove G, and the first-2 conductive layer 231b may be separated by a second side surface Gs2 of the groove G. The dummy conductive layer 231d may be disposed on the bottom surface Gb of the groove G and may be spaced apart from the first-1 conductive layer 231a and the first-2 conductive layer 231b in a third direction (e.g., the z direction).

[0148] The second conductive layer 233 has a relatively high step coverage and can therefore extend to cover the first side surface Gs1, the bottom surface Gb, and the second side surface Gs2 of the trench G. In other words, the second conductive layer 233 can be provided together in the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0149] The capping layer 250 can be disposed on the counter electrode 230. In one embodiment, on the first pixel electrode 210a and the second pixel electrode 210b, the sum of the thickness t1 of the second conductive layer 233 of the counter electrode 230 and the thickness t2 of the capping layer 250 can be approximately The thickness t1 of the second conductive layer 233 can be approximately up to approximately The thickness t2 of the capping layer 250 can be approximately up to approximately

[0150] Figure 9 This is a schematic plan view illustrating a display panel according to an embodiment. Figure 10 This is a schematic cross-sectional view illustrating a display panel according to an embodiment.

[0151] Figure 9 Examples include pixels PX1, PX2, and PX3, a pixel limiting layer PDL, and separators SP arranged on a display panel 10. Figure 10 Schematic example along Figure 9 The cross-section of the display panel 10 is shown by line IV-IV'. Figure 10 An illustrative partition SP includes, for example, a partition wall PW with a cross-sectional shape having an inverted conical shape, but this disclosure is not limited thereto. In another embodiment, as referenced above... Figure 8 As described, the separator SP may include (for example, it may be) a slot G defined by a pixel-defined layer PDL.

[0152] refer to Figure 9 Pixels PX1, PX2, and PX3 can be arranged in the display area DA of the display panel 10. Pixels PX1, PX2, and PX3 may include a first pixel PX1 that emits green light, a second pixel PX2 that emits blue light, and a third pixel PX3 that emits red light. In one embodiment, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit white light.

[0153] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged in a pattern such as stripes or a diamond shape (e.g., Arrangement, The arrangement follows a suitable rule (e.g., a fixed or predetermined rule) of color (which is an officially registered trademark of Samsung Display Co., Ltd.). In one embodiment, the third pixel PX3 and the first pixel PX1 may be arranged alternately in a second direction (e.g., the y-direction), and the second pixel PX2 may be spaced apart from the third pixel PX3 and the first pixel PX1 in a first direction (e.g., the x-direction). The second pixel PX2 may include a second-first pixel PX2a and a second-second pixel PX2b that are adjacent to each other in the second direction (e.g., the y-direction).

[0154] like Figure 10 As shown, the second-first pixel PX2a may include a second-first organic light-emitting diode (OLED) 2a, and the second-second pixel PX2b may include a second-second OLED 2b. The second-first OLED 2a may include a second-first pixel electrode 210ba, a second intermediate layer 220b, and a counter electrode 230. The second-second OLED 2b may include a second-second pixel electrode 210bb, a second intermediate layer 220b, and a counter electrode 230. The second-first pixel electrode 210ba and the second-second pixel electrode 210bb may be connected to the second pixel circuit PC2. Therefore, the second-first OLED 2a and the second-second OLED 2b may emit light synchronously with each other (e.g., simultaneously or substantially simultaneously) according to the same scan signal and the same data signal. In one embodiment, the second-first pixel electrode 210ba and the second-second pixel electrode 210bb may be connected to each other via wiring or the like. In another embodiment, the second-1st pixel electrode 210ba and the second-2nd pixel electrode 210bb can be provided as a single unit integrated with each other.

[0155] A pixel-defining layer (PDL) can define a first pixel opening OP1, a second-first pixel opening OP2a, a second-second pixel opening OP2b, and a third pixel opening OP3. The PDL can define the emission region of each of pixels PX1, PX2a, PX2b, and PX3 using the pixel openings OP1, OP2a, OP2b, and OP3. For example, the emission region of the first pixel PX1 can be defined by the first pixel opening OP1, the emission region of the second-first pixel PX2a can be defined by the second-first pixel opening OP2a, the emission region of the second-second pixel PX2b can be defined by the second-second pixel opening OP2b, and the emission region of the third pixel PX3 can be defined by the third pixel opening OP3. The distance between a pair of second-first pixel openings OP2a and second-second pixel openings OP2b can be less than the distance between the second-second pixel opening OP2b in that pair and the second-first pixel opening OP2a in another adjacent pair.

[0156] The display panel 10 may include a separator SP. In one embodiment, such as Figure 10 As shown, the separator SP may include (for example, it may be) a separator wall PW disposed on the pixel defining layer PDL. The cross-section of the separator wall PW may have an inverted conical shape.

[0157] In one embodiment, the separator SP may have a grid structure having a plurality of cells having a closed shape in a planar view. Each of the first pixel PX1, the second pixel PX2 including the second-first pixel PX2a and the second-second pixel PX2b, and the third pixel PX3 may be arranged in a corresponding one of the plurality of cells. For example, the first pixel PX1 may be arranged in a first region CA1 defined by a first cell, the second-first pixel PX2a and the second-second pixel PX2b may be arranged in a second region CA2 defined by a second cell, and the third pixel PX3 may be arranged in a third region CA3 defined by a third cell. The separator SP may be arranged to completely surround each of the first pixel opening OP1 and the third pixel opening OP3 in the planar view (e.g., completely around their periphery). The separator SP may be arranged to completely surround the second-first pixel opening OP2a and the second-second pixel opening OP2b in the planar view (e.g., completely around their periphery).

[0158] In another embodiment, the separator SP may surround each of the first pixel opening OP1, the second-first pixel opening OP2a and the second-second pixel opening OP2b, and the third pixel opening OP3 in a plan view (e.g., around their periphery), and may have at least one open side. For example, a plurality of units defined by the separator SP may have at least one open side and thus may be connected to each other.

[0159] The separator SP can isolate and separate at least a portion of the intermediate layer 220 arranged in each of the first region CA1, the second region CA2, and the third region CA3 to prevent or reduce leakage current flow through the intermediate layer 220 between adjacent pixels. For example, as Figure 10 As shown, the intermediate layer 220 may include a first intermediate layer 220a disposed in the first region CA1, a second intermediate layer 220b disposed in the second region CA2, and a dummy intermediate layer 220d disposed on the top surface PWu of the partition wall PW. The first intermediate layer 220a may be disposed on the first side surface PWs1 of the partition wall PW (see...). Figure 6 The second intermediate layer 220b can be separated by the second side surface PWs2 of the partition wall PW (see...). Figure 6 ) partition. A virtual intermediate layer 220d can be placed on the top surface PWu of the partition wall PW (see... Figure 6 On the third direction (e.g., the z direction), and can be spaced apart from the first intermediate layer 220a and the second intermediate layer 220b.

[0160] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. Separator SP may separate and divide the first conductive layer 231 disposed in each of the first region CA1 and the second region CA2. For example, the first conductive layer 231 may include a first-1 conductive layer 231a disposed in the first region CA1, a first-2 conductive layer 231b disposed in the second region CA2, and a dummy conductive layer 231d disposed on the top surface PWu of the separator wall PW. The first-1 conductive layer 231a may be separated by a first side surface PWs1 of the separator wall PW, and the first-2 conductive layer 231b may be separated by a second side surface PWs2 of the separator wall PW. The dummy conductive layer 231d may be disposed on the top surface PWu of the separator wall PW and may be spaced apart from the first-1 conductive layer 231a and the first-2 conductive layer 231b in a third direction (e.g., the z direction).

[0161] In this embodiment, since the separator SP is not arranged between the second-1 organic light-emitting diode OLED2a and the second-2 organic light-emitting diode OLED2b, the second intermediate layer 220b and the first-2 conductive layer 231b can be jointly provided in the second-1 organic light-emitting diode OLED2a and the second-2 organic light-emitting diode OLED2b.

[0162] The second conductive layer 233 may not be broken by the separator SP and may be integrally provided as a single unit on the entire surface or substantially the entire surface of the display area DA. The second conductive layer 233 may be provided together in the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b. The capping layer 250 may be disposed on the counter electrode 230.

[0163] Figure 11 This is a schematic plan view illustrating a display panel according to an embodiment. Figure 12A This is a schematic cross-sectional view illustrating a display panel according to an embodiment. Figure 12B This is a schematic cross-sectional view illustrating a display panel according to an embodiment.

[0164] Figure 11 For example, the spacer SC is arranged between pixel 2-1 PX2a and pixel 2-2 PX2b. Figure 12A and Figure 12B Each schematically illustrates along Figure 11 The cross-section of the display panel 10 is shown by line V-V'.

[0165] refer to Figure 11 Pixels PX1, PX2, and PX3 can be arranged in the display area DA of the display panel 10. Pixels PX1, PX2, and PX3 may include a first pixel PX1 that emits green light, a second-first pixel PX2a and a second-second pixel PX2b that emit blue light, and a third pixel PX3 that emits red light.

[0166] A pixel limiting layer (PDL) can define pixel apertures OP1, OP2a, OP2b, and OP3. The PDL can also define the emission region of each of pixels PX1, PX2a, PX2b, and PX3 using these apertures. For example, the emission region of the first pixel PX1 can be defined by the first pixel aperture OP1, the emission region of the second-first pixel PX2a can be defined by the second-first pixel aperture OP2a, the emission region of the second-second pixel PX2b can be defined by the second-second pixel aperture OP2b, and the emission region of the third pixel PX3 can be defined by the third pixel aperture OP3.

[0167] The display panel 10 may include a separator SP. In one embodiment, such as Figure 12A As shown, the separator SP may include (for example, it may be) a separator wall PW arranged on the pixel defining layer PDL and having a cross-section with an inverted conical shape. In another embodiment, as Figure 12B As shown, the separator SP may include (for example, it may be) a slot G defined by a pixel-defined layer PDL. The slot G may have an undercut shape.

[0168] The separator SP can be defined in a plurality of units having a closed shape in a planar diagram. Each of the first pixel PX1, the second pixel PX2 including the second-first pixel PX2a and the second-second pixel PX2b, and the third pixel PX3 can be arranged in a corresponding one of the plurality of units. For example, the first pixel PX1 can be arranged in a first region CA1 defined by the first unit, the second-first pixel PX2a and the second-second pixel PX2b can be arranged in a second region CA2 defined by the second unit, and the third pixel PX3 can be arranged in a third region CA3 defined by the third unit. The separator SP can be arranged to completely surround each of the first pixel opening OP1 and the third pixel opening OP3 in the planar diagram (e.g., completely surrounding their periphery). Additionally, the separator SP can be arranged to completely surround the second-first pixel opening OP2a and the second-second pixel opening OP2b in the planar diagram (e.g., completely surrounding their periphery).

[0169] In another embodiment, the separator SP may surround each of the first pixel opening OP1, the second-first pixel opening OP2a and the second-second pixel opening OP2b, and the third pixel opening OP3 in a plan view (e.g., around their periphery), and may have at least one open side. For example, a plurality of units defined by the separator SP may have at least one open side and thus may be connected to each other.

[0170] In one embodiment, the spacer SC may be disposed between the second-1st pixel PX2a and the second-2nd pixel PX2b. The spacer SC may be disposed on the pixel defining layer PDL and may protrude from the upper portion of the pixel defining layer PDL, thereby preventing or substantially preventing damage to pixels PX1, PX2a, PX2b, and PX3 by masks, etc. In one embodiment, the spacer SC may be provided integrally with the pixel defining layer PDL as a single unit. For example, by using a halftone mask, the spacer SC and the pixel defining layer PDL may be formed synchronously with each other (e.g., simultaneously or substantially simultaneously).

[0171] In one embodiment, the auxiliary separator SPa can be arranged between the 2-1 pixel PX2a and the 2-2 pixel PX2b to overlap with the separator SC. The auxiliary separator SPa can extend in a first direction (e.g., the x-direction). In one embodiment, as... Figure 12A As shown, the auxiliary separator SPa may include (for example, it may be) an auxiliary separator wall PWa disposed directly on the separator SC. In another embodiment, as Figure 12B As shown, the auxiliary spacer SPa may include (for example, may be) an auxiliary groove Ga defined by the spacer SC. Figure 11An example is shown where the auxiliary separator SP is partially spaced from the separator SP, but this disclosure is not limited thereto. In another embodiment, the auxiliary separator SP may be connected to the separator SP to completely separate the second-1 pixel PX2a and the second-2 pixel PX2b from each other.

[0172] refer to Figure 12A The buffer layer 101 can be disposed on the substrate 100, and the first pixel circuit PC1, the second-first pixel circuit PC2a, and the second-second pixel circuit PC2b can be disposed on the buffer layer 101. The planarization layer 109 can be disposed on the first pixel circuit PC1, the second-first pixel circuit PC2a, and the second-second pixel circuit PC2b, and the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b can be disposed on the planarization layer 109.

[0173] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The second-first organic light-emitting diode (OLED) 2a may include a second-first pixel electrode 210ba, a second intermediate layer 220b, and a counter electrode 230. The second-second organic light-emitting diode (OLED) 2b may include a second-second pixel electrode 210bb, a second intermediate layer 220b, and a counter electrode 230. In one embodiment, the first pixel electrode 210a may be connected to a first pixel circuit PC1, the second-first pixel electrode 210ba may be connected to a second-first pixel circuit PC2a, and the second-second pixel electrode 210bb may be connected to a second-second pixel circuit PC2b.

[0174] The pixel defining layer (PDL) can define pixel openings OP1, OP2a, and OP2b. The PDL can also define the emission regions of pixels PX1, PX2a, and PX2b via these openings. As a separator (SP), a separator wall (PW) can be disposed on the PDL and can completely surround the first pixel opening OP1 (e.g., completely surround its periphery). Additionally, the separator wall (PW) can completely surround the second-first pixel opening OP2a and the second-second pixel opening OP2b (e.g., completely surround their peripheries).

[0175] Intermediate layer 220 can be disposed on pixel limiting layer PDL, separator wall PW, spacer SC, and auxiliary separator wall PWa. Through separator wall PW and auxiliary separator wall PWa, intermediate layer 220 can be divided into a first intermediate layer 220a disposed in first region CA1, a second intermediate layer 220b disposed in second region CA2, a dummy intermediate layer 220d disposed on the top surface of separator wall PW, and a dummy intermediate layer 220d' disposed on the top surface of auxiliary separator wall PWa.

[0176] The spacer SC can be disposed between the second-first pixel opening OP2a and the second-second pixel opening OP2b. The spacer SC can be disposed on the pixel defining layer PDL. The auxiliary separator wall PWa can be disposed on the spacer SC. The cross-section of the auxiliary separator wall PWa can have an inverted conical shape. The auxiliary separator wall PWa can separate and divide the second intermediate layer 220b between the second-first organic light-emitting diode OLED2a and the second-second organic light-emitting diode OLED2b.

[0177] For ease of illustration, with respect to the auxiliary partition wall PWa, the second region CA2 can be represented as a first sub-region SA1 in which the 2-1 pixel opening OP2a is arranged and a second sub-region SA2 in which the 2-2 pixel opening OP2b is arranged. The portion of the second intermediate layer 220b arranged in the first sub-region SA1 can be separated by the first side surface of the auxiliary partition wall PWa, and the portion of the second intermediate layer 220b arranged in the second sub-region SA2 can be separated by the second side surface of the auxiliary partition wall PWa. The dummy intermediate layer 220d' arranged on the top surface of the auxiliary partition wall PWa can be spaced apart from the second intermediate layer 220b in a third direction (e.g., the z direction).

[0178] Counter electrode 230 can be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. The first conductive layer 231 can be divided into a first-1 conductive layer 231a disposed in the first region CA1, a first-2 conductive layer 231b disposed in the second region CA2, a dummy conductive layer 231d disposed on the top surface of the partition wall PW, and a dummy conductive layer 231d' disposed on the top surface of the auxiliary partition wall PWa by means of the partition wall PW and the auxiliary partition wall PWa.

[0179] The auxiliary partition wall PWa can separate and divide the first-second conductive layer 231b between the second-first organic light-emitting diode OLED2a and the second-second organic light-emitting diode OLED2b. The portion of the first-second conductive layer 231b disposed in the first sub-region SA1 can be separated by the first side surface of the auxiliary partition wall PWa, and the portion of the first-second conductive layer 231b disposed in the second sub-region SA2 can be separated by the second side surface of the auxiliary partition wall PWa. The dummy conductive layer 231d' disposed on the top surface of the auxiliary partition wall PWa can be spaced apart from the adjacent first-second conductive layer 231b in a third direction (e.g., the z-direction).

[0180] The second conductive layer 233 can be provided as a single unit without being broken by the separator wall PW and the auxiliary separator wall PWa, and can be integrally provided throughout the entire display area DA. The second conductive layer 233 can be provided together in the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b. The capping layer 250 can be disposed on the counter electrode 230.

[0181] Figure 12B and Figure 12A Similar, but with Figure 12A The difference lies in that the groove G is provided as a spacer SP, and the auxiliary groove Ga is provided as an auxiliary spacer SPa. The auxiliary groove Ga can be defined by a spacer SC. In other words, the auxiliary groove Ga can be formed by removing a portion of the spacer SC. The auxiliary groove Ga can have an undercut shape or an eaves shape, wherein the top surface of the spacer SC protrudes in a direction toward the center of the auxiliary groove Ga.

[0182] Through the slot G and the auxiliary slot Ga, the intermediate layer 220 can be divided into a first intermediate layer 220a arranged in the first region CA1, a second intermediate layer 220b arranged in the second region CA2, a dummy intermediate layer 220d arranged on the bottom surface of the slot G, and a dummy intermediate layer 220d' arranged on the bottom surface of the auxiliary slot Ga.

[0183] The auxiliary trench Ga can be spaced between the second-1 organic light-emitting diode OLED2a and the second-2 organic light-emitting diode OLED2b, and separate the second intermediate layer 220b. The portion of the second intermediate layer 220b disposed in the first sub-region SA1 can be separated by the first side surface of the auxiliary trench Ga, and the portion of the second intermediate layer 220b disposed in the second sub-region SA2 can be separated by the second side surface of the auxiliary trench Ga. A dummy intermediate layer 220d' disposed on the bottom surface of the auxiliary trench Ga can be spaced apart from the second intermediate layer 220b in a third direction (e.g., the z-direction).

[0184] The counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. Through the trench G and the auxiliary trench Ga, the first conductive layer 231 may be divided into a first-1 conductive layer 231a disposed in the first region CA1, a first-2 conductive layer 231b disposed in the second region CA2, a dummy conductive layer 231d disposed on the bottom surface of the trench G, and a dummy conductive layer 231d' disposed on the bottom surface of the auxiliary trench Ga.

[0185] The auxiliary trench Ga can separate and divide the first-second conductive layer 231b between the second-first organic light-emitting diode OLED2a and the second-second organic light-emitting diode OLED2b. The portion of the first-second conductive layer 231b disposed in the first sub-region SA1 can be separated by the first side surface of the auxiliary trench Ga, and the portion of the first-second conductive layer 231b disposed in the second sub-region SA2 can be separated by the second side surface of the auxiliary trench Ga. The dummy conductive layer 231d' disposed on the bottom surface of the auxiliary trench Ga can be spaced apart from the adjacent first-second conductive layer 231b in a third direction (e.g., the z-direction).

[0186] The second conductive layer 233 can be provided as a single unit without being broken by the trench G and the auxiliary trench Ga, and can be integrally provided throughout the entire display area DA. The second conductive layer 233 can be provided together in the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b. The capping layer 250 can be disposed on the counter electrode 230.

[0187] Figure 13 This is a schematic cross-sectional view illustrating a display panel according to an embodiment.

[0188] Figure 13 and Figure 12A Similarly, but exemplified by an auxiliary electrode AE ​​disposed between the 2-1 pixel opening OP2a and the 2-2 pixel opening OP2b, and an auxiliary opening OPa exposing a portion of the auxiliary electrode AE, instead of a spacer SC. An auxiliary partition wall PWa may be disposed on the auxiliary electrode AE.

[0189] refer to Figure 13 The buffer layer 101 can be disposed on the substrate 100, and the first pixel circuit PC1, the second-first pixel circuit PC2a, and the second-second pixel circuit PC2b can be disposed on the buffer layer 101. The planarization layer 109 can be disposed on the first pixel circuit PC1, the second-first pixel circuit PC2a, and the second-second pixel circuit PC2b, and the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b can be disposed on the planarization layer 109.

[0190] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The second-first organic light-emitting diode (OLED) 2a may include a second-first pixel electrode 210ba, a second intermediate layer 220b, and a counter electrode 230. The second-second organic light-emitting diode (OLED) 2b may include a second-second pixel electrode 210bb, a second intermediate layer 220b, and a counter electrode 230. In one embodiment, the first pixel electrode 210a may be connected to a first pixel circuit PC1, the second-first pixel electrode 210ba may be connected to a second-first pixel circuit PC2a, and the second-second pixel electrode 210bb may be connected to a second-second pixel circuit PC2b.

[0191] In one embodiment, the auxiliary electrode AE ​​may be disposed between the planarization layer 109 and the pixel defining layer PDL. The auxiliary electrode AE ​​may be disposed in the same layer (e.g., in or on the same layer) as the first pixel electrode 210a, the second-first pixel electrode 210ba, and the second-second pixel electrode 210bb, and may comprise the same material as each other. The auxiliary electrode AE ​​may be connected to a voltage line VL through contact holes penetrating the planarization layer 109, the voltage line VL being configured to transmit a common voltage ELVSS (see...). Figure 2 ).

[0192] The pixel defining layer PDL can define pixel openings OP1, OP2a, and OP2b, as well as an auxiliary opening OPa that exposes a portion of the auxiliary electrode AE. As a separator SP, a separator wall PW can be disposed on the pixel defining layer PDL and can completely surround the first pixel opening OP1 (e.g., completely surround its periphery). Additionally, the separator wall PW can completely surround the second-first pixel openings OP2a and OP2b (e.g., completely surround their peripheries). In other words, in a plan view, the second-first pixel openings OP2a and OP2b can be disposed within a second unit defined by the separator wall PW.

[0193] As an auxiliary separator SPa, the auxiliary separator wall PWa can be arranged on the auxiliary electrode AE. The auxiliary separator wall PWa can be arranged in the auxiliary opening OPa. The cross-section of the auxiliary separator wall PWa can have an inverted conical shape.

[0194] Intermediate layer 220 can be disposed on pixel defining layer PDL, separator wall PW, and auxiliary separator wall PWa. Through separator wall PW and auxiliary separator wall PWa, intermediate layer 220 can be divided into a first intermediate layer 220a disposed in first region CA1, a second intermediate layer 220b disposed in second region CA2, a dummy intermediate layer 220d disposed on the top surface of separator wall PW, and a dummy intermediate layer 220d' disposed on the top surface of auxiliary separator wall PWa. Auxiliary separator wall PWa can separate the second intermediate layer 220b between the second-first organic light-emitting diode OLED2a and the second-second organic light-emitting diode OLED2b. In a plan view, the portion of auxiliary electrode AE ​​overlapping the top surface of auxiliary separator wall PWa can be exposed from intermediate layer 220.

[0195] Counter electrode 230 can be disposed on intermediate layer 220. Counter electrode 230 may include first conductive layer 231 and second conductive layer 233. The first conductive layer 231 can be divided into a first-1 conductive layer 231a disposed in first region CA1, a first-2 conductive layer 231b disposed in second region CA2, a dummy conductive layer 231d disposed on the top surface of partition wall PW, and a dummy conductive layer 231d' disposed on the top surface of auxiliary partition wall PWa by partition wall PWa. Auxiliary partition wall PWa can separate the first-2 conductive layer 231b between second-1 organic light-emitting diode OLED2a and second-2 organic light-emitting diode OLED2b.

[0196] The second conductive layer 233 can be provided as a single unit without being broken by the partition wall PW and the auxiliary partition wall PWa, and can be integrally provided throughout the entire display area DA. The capping layer 250 can be disposed on the counter electrode 230. The second conductive layer 233 can overlap with the top surface of the auxiliary partition wall PWa, and therefore can directly contact the portion of the auxiliary electrode AE ​​exposed from the intermediate layer 220. Therefore, the second conductive layer 233 can directly contact the auxiliary electrode AE, and therefore can receive the common voltage ELVSS. The second conductive layer 233 can be provided together in the first organic light-emitting diode OLED1, the second-first organic light-emitting diode OLED2a, and the second-second organic light-emitting diode OLED2b. Because the second conductive layer 233 receives the common voltage ELVSS from the auxiliary electrode AE, the display panel 10 can have reduced brightness deviation caused by the voltage drop of the common voltage ELVSS.

[0197] Figure 14 This is a schematic plan view illustrating a display panel according to an embodiment. Figure 15 This is a schematic cross-sectional view illustrating a display panel according to an embodiment. Figure 16This is a schematic cross-sectional view illustrating an organic light-emitting diode according to an embodiment.

[0198] Figure 14 Examples include pixels PX1, PX2, and PX3, a pixel limiting layer PDL, and separators SP arranged in the display area DA of the display panel 10. Figure 14 The pixels PX1, PX2, and PX3 shown can represent the emission regions of pixels PX1, PX2, and PX3 defined by pixel openings OP1, OP2, and OP3 in the pixel definition layer PDL. Figure 15 Schematic example along Figure 14 The cross-section of the display panel 10 is shown by line VI-VI'. Figure 16 yes Figure 15 An enlarged view of region VII.

[0199] refer to Figure 14 Pixels PX1, PX2, and PX3 can be arranged in the display area DA of the display panel 10. Pixels PX1, PX2, and PX3 may include a first pixel PX1 that emits green light, a second pixel PX2 that emits blue light, and a third pixel PX3 that emits red light.

[0200] A pixel limiting layer (PDL) can define pixel apertures OP1, OP2, and OP3. The PDL can also define the emission region of each of pixels PX1, PX2, and PX3 using these apertures. For example, the emission region of the first pixel PX1 can be defined by the first pixel aperture OP1, the emission region of the second pixel PX2 can be defined by the second pixel aperture OP2, and the emission region of the third pixel PX3 can be defined by the third pixel aperture OP3.

[0201] Display panel 10 may include separators SP. In one embodiment, separators SP may be arranged along the edge of each of pixel openings OP1, OP2, and OP3. For example, separators SP may include recesses (e.g., slots) defined along the inner surface of each of pixel openings OP1, OP2, and OP3. The recesses (e.g., slots) extend along the inner surface of each of pixel openings OP1, OP2, and OP3 to completely surround the central portion of each of pixel openings OP1, OP2, and OP3 (e.g., completely surround their periphery). Separators SP may interrupt and separate intermediate layers 220 arranged inside each of pixel openings OP1, OP2, and OP3 to reduce leakage current through intermediate layers 220 between adjacent pixels.

[0202] refer to Figure 15The display panel 10 may include a substrate 100. A buffer layer 101 may be disposed on the substrate 100, and a first pixel circuit PC1 and a second pixel circuit PC2 may be disposed on the buffer layer 101. A planarization layer 109 may be disposed on the first pixel circuit PC1 and the second pixel circuit PC2, and a first organic light-emitting diode OLED1 and a second organic light-emitting diode OLED2 may be spaced apart from each other on the planarization layer 109.

[0203] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The second organic light-emitting diode (OLED) 2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a counter electrode 230. The first pixel electrode 210a can be electrically connected to the first pixel circuit PC1 through a contact hole penetrating the planarization layer 109. In other words, the first organic light-emitting diode OLED1 can be electrically connected to the first pixel circuit PC1. Similarly, the second pixel electrode 210b can be electrically connected to the second pixel circuit PC2 through a contact hole penetrating the planarization layer 109.

[0204] The pixel definition layer (PDL) can be arranged to cover the edges of each of the first pixel electrode 210a and the second pixel electrode 210b. The PDL can define a first pixel opening OP1 that exposes a portion of the first pixel electrode 210a and a second pixel opening OP2 that exposes a portion of the second pixel electrode 210b.

[0205] Let's refer to each other. Figure 15 and Figure 16 A recessed portion Cp can be defined in the inner surface of the first pixel opening OP1, completely surrounding the central portion of the first pixel opening OP1 (e.g., completely surrounding its periphery). The recessed portion Cp can at least surround the portion of the first pixel electrode 210a exposed by the first pixel opening OP1 and the portion of the second pixel electrode 210b exposed by the second pixel opening OP2. The recessed portion Cp extends along the inner surface of each of the first pixel opening OP1 and the second pixel opening OP2. The recessed portion Cp can be formed along the boundary between the pixel defining layer PDL and the edge of the first pixel electrode 210a, and therefore the pixel defining layer PDL can have an undercut structure or an eaves structure, wherein its upper portion protrudes in a direction toward the center of the first pixel opening OP1.

[0206] In one embodiment, the recessed portion Cp can be formed by removing a portion of a sacrificial layer disposed on the first pixel electrode 210a. The sacrificial layer can include a suitable material that can be removed by a wet etching process without damaging the first pixel electrode 210a. For example, the sacrificial layer can include IGZO. In one embodiment, the portion of the sacrificial layer that is not removed by the wet etching process can remain between the pixel defining layer PDL and the first pixel electrode 210a to form a residual sacrificial layer 215. A fourth distance d4 between the top surface 215u of the residual sacrificial layer 215 and the top surface 210u of the first pixel electrode 210a can define the height of the recessed portion Cp. In one embodiment, the fourth distance d4 can be greater than or equal to approximately 1.1 μm.

[0207] Similarly, a recessed portion Cp can be defined in the inner surface of the second pixel opening OP2, completely surrounding the central portion of the second pixel opening OP2 (e.g., completely surrounding its periphery). The recessed portion Cp can be formed between the pixel defining layer PDL and the second pixel electrode 210b, and therefore the pixel defining layer PDL can have an undercut structure or an eaves structure, wherein its upper portion protrudes in a direction toward the center of the second pixel opening OP2. A residual sacrificial layer 215 can be disposed between the second pixel electrode 210b and the pixel defining layer PDL.

[0208] Intermediate layer 220 can be disposed on pixel defining layer PDL. Intermediate layer 220 may include a first intermediate layer 220a disposed within the first pixel opening OP1 and on the first pixel electrode 210a, a second intermediate layer 220b disposed within the second pixel opening OP2 and on the second pixel electrode 210b, and a dummy intermediate layer 220d disposed on pixel defining layer PDL. Intermediate layer 220 can be divided into first intermediate layer 220a, second intermediate layer 220b, and dummy intermediate layer 220d by the undercut structure of pixel defining layer PDL, thereby reducing leakage current through intermediate layer 220 between adjacent pixels. In one embodiment, with respect to the first organic light-emitting diode OLED1, intermediate layer 220 can be separated by a recessed portion (e.g., a trench) Cp into a first portion disposed on the first pixel electrode 210a and a second portion disposed on pixel defining layer PDL.

[0209] As referenced above Figure 3 As described, the intermediate layer 220 may include a plurality of emitting units (e.g., a plurality of emitting layers or stacks) and a charge generation layer CGL disposed between the emitting units. In other words, each of the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may be referred to as a tandem light-emitting device.

[0210] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. The first conductive layer 231 may include silver (Ag) or a silver alloy and may be formed on the entire surface or substantially the entire surface of display area DA by a thermal evaporation process. In one embodiment, as... Figure 15 As shown, the first conductive layer 231 may not be broken by the undercut structure of the pixel defining layer PDL, and may be integrally formed as a single unit on the entire surface or substantially the entire surface of the display area DA. In another embodiment, the first conductive layer 231 may be divided by the undercut structure of the pixel defining layer PDL into a first conductive layer 1-1 disposed on a first intermediate layer 220a, a first conductive layer 1-2 disposed on a second intermediate layer 220b, and a dummy conductive layer disposed on a dummy intermediate layer 220d.

[0211] The second conductive layer 233 may include a transparent conductive oxide, which may not be broken by the undercut structure of the pixel defining layer PDL, and may be integrally provided as a single unit on the entire surface or substantially the entire surface of the display area DA. The second conductive layer 233 may be provided together in the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0212] A capping layer 250 may be disposed on the counter electrode 230. In one embodiment, on a surface substantially parallel to the top surface of the substrate 100, the sum of the thickness t1 of the second conductive layer 233 of the counter electrode 230 and the thickness t2 of the capping layer 250 may be approximately The thickness t1 of the second conductive layer 233 can be approximately up to approximately The thickness t2 of the capping layer 250 can be approximately up to approximately

[0213] Figure 17 This is a schematic cross-sectional view illustrating a display panel according to an embodiment.

[0214] refer to Figure 17 The display panel 10 may include a substrate 100. The substrate 100 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. In other words, the substrate 100 may be a semiconductor substrate comprising semiconductor materials. However, the type of substrate 100 is not limited to semiconductor substrates.

[0215] The first pixel circuit PC1 and the second pixel circuit PC2 can be arranged on the substrate 100. The first pixel circuit PC1 and the second pixel circuit PC2 can have the same or similar structures. In the following description, for ease of illustration, the first pixel circuit PC1 will be described in more detail.

[0216] The first pixel circuit PC1 may include a thin-film transistor (TFT) and a capacitor Cst. The TFT may include an active layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0217] The active layer Act of a thin-film transistor (TFT) can be disposed in the substrate 100. The active layer Act can be formed as a part of the substrate 100. A part of the substrate 100 can be recessed, and the active layer Act can be disposed in the recessed portion of the substrate 100.

[0218] The gate insulating layer 111 may be disposed on the substrate 100. The gate insulating layer 111 may be disposed between the active layer Act and the gate electrode GE. In one embodiment, the gate insulating layer 111 may be patterned to have a shape corresponding to the gate electrode GE in a plan view.

[0219] The gate electrode GE can be disposed on the gate insulating layer 111 to overlap with the active layer Act. The gate electrode GE can include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and can be formed as a multilayer or a single layer, each including at least one of the above materials.

[0220] A first interlayer insulating layer 113 may be disposed on the gate electrode GE, and a second capacitor electrode CE2 may be disposed on the first interlayer insulating layer 113. At least a portion of the gate electrode GE may overlap with the second capacitor electrode CE2 in a plan view and may serve as the first capacitor electrode CE1 of the capacitor Cst. In other words, the gate electrode GE and the first capacitor electrode CE1 may be integrally provided as a single unit. The second capacitor electrode CE2 may comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and may be formed as a multilayer or a single layer, each comprising at least one of the above materials.

[0221] The second interlayer insulating layer 115 can be disposed on the second capacitor electrode CE2, and the source electrode SE and drain electrode DE can be disposed on the second interlayer insulating layer 115. The source electrode SE and drain electrode DE can each comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO), and can each be formed as a multilayer or a single layer comprising at least one of the above materials. For example, the source electrode SE and drain electrode DE can each have a Ti / Al / Ti multilayer structure.

[0222] The gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 115 may each comprise an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may each be formed as a multilayer or a single layer comprising at least one of the above materials.

[0223] The planarization layer 119 can be disposed on the first pixel circuit PC1 and the second pixel circuit PC2. The planarization layer 119 may include an organic insulating material. For example, the planarization layer 119 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or suitable mixtures thereof.

[0224] The first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2) can be spaced apart from each other on the planarization layer 119. The first OLED1 and the second OLED2 can emit light of the same color as each other. For example, the first OLED1 and the second OLED2 can each emit white light. The peak spectrum of each of the first OLED1 and the second OLED2 can have peaks in a first wavelength region of approximately 435 nm to approximately 490 nm, a second wavelength region of approximately 500 nm to approximately 590 nm, and a third wavelength region of approximately 600 nm to approximately 710 nm.

[0225] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a counter electrode 230. The counter electrode 230 of the first OLED 1 may include a first conductive layer 231a and a second conductive layer 233. The second organic light-emitting diode (OLED) 2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a counter electrode 230. The counter electrode 230 of the second OLED 2 may include a first conductive layer 231b and a second conductive layer 233.

[0226] The first pixel electrode 210a can be electrically connected to the first pixel circuit PC1 through a contact hole penetrating the planarization layer 119. Similarly, the second pixel electrode 210b can be electrically connected to the second pixel circuit PC2 through a contact hole penetrating the planarization layer 119.

[0227] As a separator SP, a separator wall PW can be disposed on the planarization layer 119. The separator wall PW can be in direct contact with the top surface of the planarization layer 119. In one embodiment, the separator wall PW may include an organic insulating material. In one embodiment, the separator wall PW may include a negative photoresist material whose solubility relative to a developer is reduced by exposure. In another embodiment, the separator wall PW may have a multilayer structure with organic insulating material layers and inorganic insulating material layers. In yet another embodiment, the separator wall PW may include an inorganic insulating material.

[0228] The cross-section of the partition wall PW can have an inverted conical shape. For example, as... Figure 17 As shown, the width of the top surface of the partition wall PW can be greater than the width of the bottom surface of the partition wall PW. The side surfaces of the partition wall PW can be inclined at an angle of about 130° to about 140° relative to the top surface of the planarization layer 119. The top surface of the partition wall PW can be spaced from the top surface of the planarization layer 119 by about 1.1 μm to about 3 μm.

[0229] Intermediate layer 220 can be disposed on planarization layer 119. Intermediate layer 220 may include a first intermediate layer 220a disposed in first region CA1, a second intermediate layer 220b disposed in second region CA2, and a dummy intermediate layer 220d disposed on the top surface of partition wall PW. (Refer to the above...) Figure 3 As described, the intermediate layer 220 may include a plurality of emitting units (e.g., a plurality of emitting layers or stacks) and a charge generation layer CGL disposed between the emitting units. In other words, each of the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may be a tandem light-emitting device.

[0230] The intermediate layer 220 can be formed on the entire surface or substantially the entire surface of the display area DA by a thermal evaporation process. The intermediate layer 220 can be divided into a first intermediate layer 220a, a second intermediate layer 220b, and a dummy intermediate layer 220d by partition walls PW having an inverted conical shape. The material used to form the intermediate layer 220 can have a low step coverage and therefore can be separated from the side surfaces of the partition walls PW, or even if it is deposited on a portion of the side surfaces of the partition walls PW, it can be separated without being connected. The first intermediate layer 220a and the second intermediate layer 220b can be spaced apart from each other, with the dummy intermediate layer 220d between them, thereby reducing or preventing leakage current from flowing through the intermediate layer 220 between adjacent first organic light-emitting diodes OLED1 and second organic light-emitting diodes OLED2. Therefore, the display panel 10 can display high-quality images without brightness inhomogeneity or color mixing.

[0231] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may include a first conductive layer 231 and a second conductive layer 233. The first conductive layer 231 may include a first-1 conductive layer 231a disposed in the first region CA1, a first-2 conductive layer 231b disposed in the second region CA2, and a dummy conductive layer 231d disposed on the top surface of the partition wall PW.

[0232] The first conductive layer 231 may include silver (Ag) or a silver alloy and may be formed on the entire surface or substantially the entire surface of the display area DA by a thermal evaporation process. The first conductive layer 231 may be divided into a first-1 conductive layer 231a, a first-2 conductive layer 231b and a dummy conductive layer 231d by a partition wall PW having an inverted conical shape.

[0233] The second conductive layer 233 may comprise a transparent conductive oxide and may be formed on the entire or substantially the entire surface of the display area DA by a sputtering process. The second conductive layer 233 has a relatively high step coverage and can therefore extend to continuously cover the side and top surfaces of the partition wall PW. In other words, the second conductive layer 233 may be provided jointly in both the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0234] A capping layer 250 and an encapsulation layer 300 may be disposed on the second conductive layer 233. The encapsulation layer 300 may be disposed to cover the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320 on the first inorganic encapsulation layer 310, and a second inorganic encapsulation layer 330 on the organic encapsulation layer 320. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include at least one inorganic material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymeric material. The polymeric material may include acrylic resins, epoxy resins, polyimide, and / or polyethylene. In one embodiment, the organic encapsulation layer 320 may include acrylate. The organic encapsulation layer 320 may be formed by curing monomers or coating polymers. The organic encapsulation layer 320 can be transparent.

[0235] A color filter layer 400 may be disposed on the encapsulation layer 300. The color filter layer 400 may include a first color filter 410, a second color filter 420, and a third color filter that transmit light of different colors from each other. The first color filter 410, the second color filter 420, and the third color filter may be arranged to correspond to first pixels to third pixels PX1, PX2, and PX3, respectively. For example, the first color filter 410 may be arranged to correspond to a first organic light-emitting diode (OLED1), and the second color filter 420 may be arranged to correspond to a second organic light-emitting diode (OLED2). For example, the first color filter 410 may be a green color filter that selectively transmits green light from the light emitted from the intermediate layer 220. For example, the second color filter 420 may be a blue color filter that selectively transmits blue light from the light emitted from the intermediate layer 220. For example, the third color filter may be a red color filter that selectively transmits red light from the light emitted from the intermediate layer 220.

[0236] In one embodiment, the color filter layer 400 may further include a light-shielding layer defining an opening corresponding to the organic light-emitting diode (OLED). The light-shielding layer may be disposed between the first color filter 410, the second color filter 420, and the third color filter to reduce color mixing of light passing through the color filter layer 400. In another embodiment, the color filter layer 400 may have a light-transmitting region corresponding to the OLED and a light-shielding region outside the light-transmitting region. Only one of the first color filter 410, the second color filter 420, and the third color filter may be disposed in the light-transmitting region, and at least two of the first color filter 410, the second color filter 420, and the third color filter may overlap each other in the light-shielding region.

[0237] Figure 18 This is a perspective view schematically illustrating an electronic device according to an embodiment. Figure 19 This is a block diagram schematically illustrating an electronic device according to an embodiment.

[0238] refer to Figure 18 and Figure 19The electronic device 1, including the display panel 10 according to the embodiment, is a device for displaying moving or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs). The electronic device 1 according to the embodiment can be used in wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). The electronic device 1 according to the embodiment can be used as a vehicle's instrument panel, a central information display (CID) arranged on the vehicle's central dashboard or instrument panel, a room mirror display replacing the vehicle's side mirrors, or a display arranged behind the front seats as an entertainment display for rear-seat passengers.

[0239] Figure 18 An electronic device 1 according to an embodiment is illustrated as a smartphone. The electronic device 1 may include a display panel 10 and a lower cover 90 disposed below the display panel 10. The electronic device 1 may include a cover window covering the top surface of the display panel 10.

[0240] The lower cover 90 can form the appearance of the electronic device 1 and may have an opening in its front surface that exposes a portion of the display panel 10. The lower cover 90 has a shape in which the surface corresponding to the display panel 10 is open and can be assembled with the display panel 10. The lower cover 90 can form the appearance of the lower surface of the electronic device 1, and display circuit boards, components, main circuit boards, batteries, drivers, etc., can be arranged between the display panel 10 and the lower cover 90. The lower cover 90 may include plastic, metal, or both plastic and metal.

[0241] Electronic device 1 may include a main processor 510, a wireless communication unit 520, an input unit 530, a sensor unit 540, an output unit 550, an interface unit 560, a memory 570, and / or a power supply unit 580.

[0242] The main processor 510 can control all functions of the electronic device 1. For example, the main processor 510 can output digital video data to a data driver via a display circuit board, causing the display panel 10 to display an image. The main processor 510 can receive sensing data from a touch sensor driver unit. Based on the sensing data, the main processor 510 can determine whether a user touch has occurred and can perform operations corresponding to a direct touch or proximity touch by the user. The main processor 510 can be an application processor, a central processing unit, or a system-on-a-chip, each including integrated circuits.

[0243] Camera device 531 processes image frames, such as still images or moving images, acquired by an image sensor in camera mode, and outputs the processed image frames to main processor 510. Camera device 531 may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a light sensor (e.g., an image sensor), and a laser sensor. Camera device 531 may be connected to an image sensor and can process images input to the image sensor.

[0244] The wireless communication unit 520 may include at least one of the following: a broadcast receiving module 521, a mobile communication module 522, a wireless internet module 523, a short-range communication module 524, and a location information module 525.

[0245] The broadcast receiving module 521 receives broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a terrestrial channel.

[0246] The mobile communication module 522 can transmit and receive radio signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network constructed according to technical standards or communication methods used for mobile communication (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), CDMA 2000, Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Advanced LTE (LTE-A), etc.). The radio signals may include various types of data based on the transmission and reception of voice call signals, video call signals, or text / multimedia messages.

[0247] Wireless Internet module 523 refers to a module used for accessing the wireless Internet. Wireless Internet module 523 can be configured to transmit and receive wireless signals in a communication network based on wireless Internet technology. Wireless Internet technologies include, for example, Wireless Local Area Network (WLAN), Wi-Fi, Wi-Fi Direct, and Digital Living Network Alliance (DLNA).

[0248] The short-range communication module 524 is used for short-range communication and can be used by... At least one of the following technologies supports short-range communication: Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), ZigBee, Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and Wireless Universal Serial Bus (Wireless USB). The short-range communication module 524 can support wireless communication between electronic device 1 and a wireless communication system, between electronic device 1 and another electronic device, or between electronic device 1 and the network where another electronic device (e.g., an external server) is located, via a wireless local area network. The wireless local area network can be a wireless personal area network. The other electronic device can be a wearable device capable of exchanging data with electronic device 1 (e.g., interacting with electronic device 1).

[0249] The location information module 525 is a module for obtaining the location (e.g., current location) of the electronic device 1, and may include a Global Positioning System (GPS) module or a Wi-Fi module.

[0250] The input unit 530 may include an image input unit such as a camera device 531 for inputting image signals, an audio input unit such as a microphone 532 for inputting audio signals, and an input device 533 for receiving information from a user.

[0251] The camera device 531 processes image frames, such as still images or moving images, acquired by the image sensor in video call mode or shooting mode. The processed image frames can be displayed on the display panel 10 or stored in the memory 570.

[0252] Microphone 532 processes external audio signals into electronic voice data. Depending on the function being performed in electronic device 1 (e.g., application), the processed voice data can be utilized in various ways.

[0253] The main processor 510 can control the operation of the electronic device 1 to correspond to the information input via the input device 533. The input device 533 may include a touch input device or a mechanical input device such as a button, dome switch, jog wheel, or jog switch located on the rear or side surface of the electronic device 1. The touch input device may include the touch screen layer of the display panel 10.

[0254] Sensor unit 540 may include at least one sensor that senses at least one of the following: information inside electronic device 1, information about the environment surrounding electronic device 1, and user information, and generates a corresponding sensing signal. Based on the sensing signal, main processor 510 may control the driving or operation of electronic device 1, or may perform data processing, functions, or operations related to applications installed on electronic device 1. Sensor unit 540 may include at least one of the following: proximity sensor, illuminance sensor, accelerometer, magnetic sensor, gravity sensor (G-sensor), gyroscope sensor, motion sensor, RGB sensor, infrared (IR) sensor, fingerprint scanner, ultrasonic sensor, optical sensor, battery level meter, environmental sensor (e.g., barometer, hygrometer, thermometer, radiation detection sensor, thermal detection sensor, gas detection sensor, etc.), and chemical sensor (e.g., electronic nose, healthcare sensor, biometric sensor, etc.).

[0255] The output unit 550 is used to generate outputs related to vision, hearing or touch, and may include at least one of the display panel 10, audio output unit 551, haptic module 552 and light output unit 553.

[0256] Display panel 10 can display (output) information processed by electronic device 1. For example, display panel 10 can display execution screen information of an application running on electronic device 1 or user interface (UI) or graphical user interface (GUI) information based on the execution screen information. Display panel 10 may include a display layer for displaying images and a touch screen layer for detecting user touch input. Accordingly, display panel 10 can act as an input device 533 providing an input interface between electronic device 1 and the user, and simultaneously as an output unit 550 providing an output interface between electronic device 1 and the user.

[0257] The audio output unit 551 can output audio data received from the wireless communication unit 520 or stored in the memory 570 in signal reception, call mode, recording mode, voice recognition mode, broadcast reception mode, etc. The audio output unit 551 can also output audio signals related to the functions performed in the electronic device 1 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 551 may include a receiver or a speaker. At least one of the receiver and speaker may be an audio generating device attached to the lower portion of the display panel 10 and outputting audio by vibrating the display panel 10. The audio generating device may be a piezoelectric element or piezoelectric actuator that each contracts and expands according to an electrical signal, or it may be an exciter that generates magnetic force by using a voice coil to vibrate the display panel 10.

[0258] The haptic module 552 generates various haptic effects that can be felt by the user. The haptic module 552 can provide vibrations as haptic effects to the user. The haptic module 552 can not only transmit haptic effects through direct contact, but can also be implemented so that the user can feel the haptic effects through muscle sensations such as those in the fingers or arms.

[0259] The light output unit 553 outputs a signal to notify of an event by using light from a light source. Examples of events occurring in the electronic device 1 may include message reception, call signal reception, missed calls, alarms, calendar notifications, email reception, and information reception via an application. The signal output by the light output unit 553 is generated by the electronic device 1 emitting monochromatic or polychromatic light from its front or rear surface. The signal output may be terminated when the electronic device 1 detects an event confirmation from the user.

[0260] Interface unit 560 serves as a channel for connecting to various types of external devices of electronic device 1. Interface unit 560 may include at least one of the following: a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting to a device equipped with an identification module, an audio input / output (I / O) port, a video I / O port, and a headphone port. In response to an external device being connected to interface unit 560, electronic device 1 can perform appropriate controls associated with the connected external device.

[0261] Memory 570 stores data supporting various functions of electronic device 1. Memory 570 may store multiple applications running on electronic device 1, data for the operation of electronic device 1, and commands. At least some of the multiple applications can be downloaded from an external server via wireless communication. Memory 570 may store applications for the operation of main processor 510, and may also temporarily store input / output data, such as data like phonebooks, messages, still images, moving images, etc. In addition, memory 570 may store tactile data for providing various vibration modes to tactile module 552 and audio data related to various audio provided to audio output unit 551. Memory 570 may include at least one type of storage medium selected from flash memory, hard disk, solid-state drive (SSD), multimedia card micro, card memory (e.g., SD or XD memory), random access memory (RAM), static RAM (SRAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), programmable ROM (PROM), magnetic storage, magnetic disk, and optical disk.

[0262] Under the control of the main processor 510, the power supply unit 580 receives external or internal power and supplies power to each of the components included in the electronic device 1. The power supply unit 580 may include a battery. Additionally, the power supply unit 580 includes a connection port, which can be configured to supply power to an interface unit 560 electrically connected to an external charger for charging the battery, as an example. As another example, the power supply unit 580 can be configured to wirelessly charge the battery without using the connection port.

[0263] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices may be implemented on flexible printed circuit films, tape-on-a-package (TCP), and / or printed circuit boards (PCBs), or formed on a substrate. Additionally, various components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

[0264] According to one embodiment, a display panel capable of displaying high-quality images and an electronic device including the display panel can be realized. However, this disclosure is not limited thereto.

[0265] The foregoing exemplifies some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it should be understood that the foregoing exemplifies various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: an insulating layer on a substrate; a first pixel electrode on the insulating layer; a partition wall on the insulating layer and surrounding the first pixel electrode in a plan view; a first intermediate layer on the first pixel electrode; and an opposite electrode on the first intermediate layer and comprising: a first conductive layer partitioned by the partition wall; and a second conductive layer on the first conductive layer and extending to cover side surfaces and a top surface of the partition wall. 2.The display panel of claim 1, further comprising: a pixel defining layer covering edges of the first pixel electrode and having a first pixel opening overlapping the first pixel electrode, wherein the partition wall is disposed on the pixel defining layer and surrounds the first pixel opening in the plan view, and 3.The display panel of claim 1, wherein a cross section of the partition wall has an inverted taper shape. 4.The display panel of claim 3, wherein the side surfaces of the partition wall are inclined at an angle of 130° to 140° with respect to a top surface of the substrate. wherein on the top surface of the partition wall parallel to the substrate, the second conductive layer has to a thickness of to a thickness of 5.The display panel of claim 3, wherein a distance from a bottom surface of the partition wall to the top surface of the partition wall is 1.1 μm to 3 μm. a distance from a boundary of the first pixel opening to a boundary of the partition wall is 4 μm to 7.5 μm in the plan view. the opposite electrode has a first thickness on the top surface of the partition wall parallel to the substrate, and a second thickness on the side surfaces of the partition wall, the second thickness being 20% to 30% of the first thickness.

6. The display panel of claim 2, wherein, 8.The display panel of any one of claims 1 to 7, wherein the first intermediate layer comprises a plurality of emission units.

7. The display panel of claim 3, wherein, 9.The display panel of claim 1, further comprising: a 2-1 pixel electrode and a 2-2 pixel electrode on the insulating layer and spaced apart from the first pixel electrode; and a second intermediate layer on the 2-1 pixel electrode and the 2-2 pixel electrode, wherein the partition wall surrounds the 2-1 pixel electrode and the 2-2 pixel electrode in the plan view. 10.The display panel of claim 9, further comprising: a pixel defining layer covering edges of each of the first pixel electrode, the 2-1 pixel electrode, and the 2-2 pixel electrode and having a first pixel opening overlapping the first pixel electrode, a 2-1 pixel opening overlapping the 2-1 pixel electrode, and a 2-2 pixel opening overlapping the 2-2 pixel electrode. 11.The display panel of claim 10, further comprising: a spacer on the pixel defining layer between the 2-1 pixel opening and the 2-2 pixel opening; and an auxiliary partition wall on the spacer. 12.The display panel of claim 10, further comprising: ​ ​ ​ ​ an auxiliary electrode on the insulating layer between the 2-1 pixel electrode and the 2-2 pixel electrode; and an auxiliary partition wall on the auxiliary electrode, wherein the pixel-defining layer further has an auxiliary opening overlapping the auxiliary electrode, and the second conductive layer is in direct contact with the auxiliary electrode.

13. A display panel, comprising: a first pixel electrode on a substrate; a pixel-defining layer on the substrate and having a first pixel opening overlapping the first pixel electrode and a trench surrounding at least a portion of the first pixel electrode exposed by the first pixel opening; a first intermediate layer on the first pixel electrode; and a counter electrode on the first intermediate layer and comprising: a first conductive layer partitioned by the trench; and a second conductive layer on the first conductive layer and extending to cover side surfaces and a bottom surface of the trench.

14. The display panel of claim 13, wherein the side surfaces of the trench are inclined at an angle of 40° to 50° with respect to a top surface of the substrate.

15. The display panel of claim 13 or 14, wherein the first intermediate layer comprises a plurality of emission units.

16. The display panel of claim 13, further comprising: a 2-1 pixel electrode and a 2-2 pixel electrode on the substrate and spaced apart from the first pixel electrode; and a second intermediate layer on the 2-1 pixel electrode and the 2-2 pixel electrode, wherein the pixel-defining layer further has a 2-1 pixel opening overlapping the 2-1 pixel electrode and a 2-2 pixel opening overlapping the 2-2 pixel electrode, and wherein, in a plan view, the trench completely surrounds the 2-1 pixel opening and the 2-2 pixel opening.

17. The display panel of claim 16, further comprising: a spacer on the pixel-defining layer between the 2-1 pixel opening and the 2-2 pixel opening, the spacer having an auxiliary trench.

18. The display panel of claim 13, wherein the trench extends along an inner surface of the first pixel opening, and the first intermediate layer is separated by the trench into a first portion disposed on the first pixel electrode and a second portion disposed on the pixel-defining layer.

19. The display panel of claim 18, further comprising: a residual sacrificial layer between the pixel-defining layer and an edge of the first pixel electrode.

20. An electronic device, comprising: a display panel; and a lower cover forming an appearance of the electronic device and including a front surface having an opening exposing a portion of the display panel, wherein the display panel is the display panel according to any one of claims 1 to 19. ​

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