Chip packaging structure and packaging method

Abstract

The invention discloses a chip packaging structure and a packaging method, and the chip packaging structure comprises a substrate which is provided with a first surface; the at least one first chip is arranged on the first surface and is electrically connected with the substrate; the second chip is arranged on the side, away from the substrate, of the first chip, and the second chip is electrically connected with the substrate; and the supporting structure is arranged on the outer side of the at least one first chip, the supporting structure is connected with the first surface and the second chip, and the mechanical supporting reliability when the first chip and the second chip are stacked and packaged is improved.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing and packaging, and in particular to a chip packaging structure and packaging method. Background Technology

[0002] As electronic devices evolve towards miniaturization and higher performance, multi-chip integrated packaging technology has become a key path to improve system integration and functional density. Currently, there are two main technical approaches for achieving interconnection and integration between multiple chips: horizontal layout and vertical stacking. However, both still have significant limitations in terms of structural design, process complexity, and reliability.

[0003] The horizontal layout arranges multiple chips laterally along the substrate surface. Although the process is relatively simple and the interconnection path is clear, the package area expands linearly with the increase of the number of chips, resulting in a significant increase in package size, which makes it difficult to meet the strict space requirements of high-density integration and compact electronic devices.

[0004] In vertical stacking solutions, various three-dimensional integrated structures have been proposed to reduce planar dimensions. One typical method involves creating recesses in the substrate, embedding smaller chips within them, and then bonding larger chips to the substrate surface. While this structure helps reduce the overall package height, the high precision required for recess fabrication significantly increases substrate manufacturing costs and process complexity, while also imposing stringent requirements on chip thickness consistency and mounting accuracy.

[0005] Another common stacking method involves directly bonding one chip to the substrate surface, then stacking another chip on top of it, using metal conductive pillars to achieve electrical connection and mechanical support between the upper chip and the substrate. However, in this structure, the conductive pillars not only provide electrical interconnection but also need to support all or part of the weight of the upper chip and even the subsequent packaging structure. Under conditions such as thermal stress and mechanical vibration, insufficient support and decreased connection reliability can easily occur, affecting the overall stability and electrical connection performance of the packaging structure.

[0006] Therefore, existing technologies have not yet achieved a good balance between size control, cost-effectiveness and structural reliability in multi-chip integrated packaging. There is an urgent need for a new packaging structure that can achieve high-density three-dimensional integration while having better mechanical support strength and process feasibility. Summary of the Invention

[0007] One of the objectives of this invention is to provide a chip packaging structure to at least solve the technical problem of insufficient support force when multiple chips are vertically stacked in the prior art.

[0008] One of the objectives of this invention is to provide a chip packaging method.

[0009] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging structure, comprising: a substrate having a first surface; At least one first chip is disposed on the first surface and electrically connected to the substrate; The second chip is disposed on the side of the first chip away from the substrate, and the second chip is electrically connected to the substrate; A support structure is disposed on the outside of at least one of the first chips, the support structure connecting the first surface and the second chip.

[0010] As a further improvement of one embodiment of the present invention, the support structure includes a first dam, which extends along a first direction and is located on both sides of the first chip along a second direction, wherein the first direction and the second direction are horizontal and perpendicular to each other.

[0011] As a further improvement of one embodiment of the present invention, the support structure includes a second dam, which extends along a second direction and is located on both sides of the first chip along a first direction; the first dam connects the first surface and the second chip, and the two ends of the second dam are connected to the first surface or the first dam, with at least a portion of the second dam and the first surface spaced apart.

[0012] As a further improvement of one embodiment of the present invention, the first dam and the second dam are arranged to form a frame structure, the size of which matches the size of the second chip.

[0013] As a further improvement of one embodiment of the present invention, the first dam and the second dam are made of insulating materials.

[0014] As a further improvement of one embodiment of the present invention, the support structure is not lower than the first chip.

[0015] As a further improvement of one embodiment of the present invention, the substrate has a first welding area and a second welding area, the first welding area and the second welding area being disposed at an interval on the first surface; the first chip is electrically connected to the first welding area, the second chip is electrically connected to the second welding area, and at least a portion of the support structure is located between the first welding area and the second welding area.

[0016] As a further improvement of one embodiment of the present invention, the second chip has a third welding area, a functional surface and a non-functional surface disposed opposite to each other, the third welding area is disposed on the functional surface, the third welding area is electrically connected to the substrate, and the non-functional surface is connected to the support structure.

[0017] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a molding layer that fills the gap between the first chip, the support structure and the second chip and encapsulates the first chip, the support structure and at least a portion of the second chip.

[0018] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging method, comprising the steps of: A substrate, a first chip, a support structure, and a second chip are provided; the substrate has a first surface. The first chip and the substrate are electrically connected; The support structure is disposed on the first surface, and the support structure is located on the outside of the first chip; The second chip is connected to the side of the support structure opposite to the substrate.

[0019] As a further improvement of one embodiment of the present invention, the support structure is disposed on the first surface, which includes the steps of: disposing a first dam on the first surface along a first direction, and disposing at least two first dams on both sides of the first chip along a second direction, wherein the first direction and the second direction are horizontal and perpendicular to each other, and at least a portion of the support structure is composed of the first dams. As a further improvement of one embodiment of the present invention, the support structure is disposed on the first surface, which includes the steps of: connecting two first dams along a second direction with a second dam, the second dam being spaced apart from the first surface, the second dam being located on both sides of the first chip along a first direction, and at least a portion of the support structure being composed of the second dam. As a further improvement of one embodiment of the present invention, connecting the second chip to the side of the support structure away from the substrate includes the following steps: The non-functional surface of the second chip is connected to the frame structure formed by the first and second dams; The third soldering area of ​​the second chip is electrically connected to the substrate. As a further improvement of one embodiment of the present invention, the molding layer is fabricated by the steps of: injecting molding material into the first surface along the first direction, the molding material flowing from one side of the substrate to the other side of the substrate along the first direction, and the molding material curing to form the molding layer. Compared with the prior art, the present invention provides a chip packaging structure in which a first chip is disposed on a first surface and a second chip is disposed on the side of the first chip away from the substrate. The substrate, the first chip and the second chip are stacked vertically. A support structure is located outside the first chip and connects the first surface and the second chip to provide mechanical support for the second chip. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a chip packaging structure according to one embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of a chip packaging structure in another embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of a first chip and a substrate provided in one embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of setting up a first dam in one embodiment of the present invention.

[0024] Figure 5 This is a schematic diagram of setting up a first dam in another embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of setting up a second dam in one embodiment of the present invention.

[0026] Figure 7-8 This is a schematic diagram of a second chip disposed on the side of the first chip away from the substrate in one embodiment of the present invention.

[0027] Figure 9 This is a schematic diagram of the fabrication of a molding layer according to one embodiment of the present invention. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0029] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0031] Please see Figure 1 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present invention.

[0032] The chip packaging structure 100 includes a substrate 10, at least one first chip 20 and a second chip 30, realizing the integrated packaging of the first chip 20 and the second chip 30.

[0033] The substrate 10 has a first surface 101, a first chip 20 is disposed on the first surface 101 and electrically connected to the substrate 10, and a second chip 30 is disposed on the side of the first chip 20 away from the substrate 10. The second chip 30 is electrically connected to the substrate 10. The substrate 10, the first chip 20 and the second chip 30 are vertically interconnected and stacked, which reduces the planar size and is beneficial to the miniaturization of the chip packaging structure 100.

[0034] The chip packaging structure 100 includes a support structure 40 disposed on the outside of at least one first chip 20. The support structure 40 connects a first surface 101 and a second chip 30. It is understood that the support structure 40 connects to the first surface 101, thereby connecting to the substrate 10. By providing the support structure 40 to connect the substrate 10 and the second chip 30, the technical problem of insufficient support force in multi-chip vertical stacking packaging is solved. The support structure 40 provides mechanical support independently of the electrical connection structure. The support structure 40 directly supports the second chip 30, providing stable support force and stable connection performance between the second chip 30 and the substrate 10, ensuring the reliability of the mechanical connection and the electrical connection performance of the chip packaging structure 100.

[0035] In a specific embodiment, the substrate 10 is a printed circuit board or a ceramic substrate. The first chip 20 is a smaller chip, and the first chip 20 is a control chip or a logic chip. The second chip 30 is a larger chip, and the second chip 30 is an image sensing chip. The second chip 30 is vertically stacked above the first chip 20 and the support structure 40. The support structure 40 is located outside the first chip 20. The support structure 40 does not increase the planar size and ensures mechanical support for the second chip 30.

[0036] The support structure 40 includes a first dam 41, which extends along a first direction and is located on both sides of the first chip 20 along a second direction. The first and second directions are horizontal and perpendicular to each other. The first dam 41 is disposed on both sides of the first chip 20, and can at least support both sides of the second chip 30 along the second direction.

[0037] The first dam 41 extends along the first direction, providing directional support to ensure the stability of the second chip 30 in the horizontal direction. The design of the first dam 41 optimizes the distribution of support forces, reduces the risk of displacement of the second chip 30 under vibration or thermal cycling conditions, and improves the mechanical integrity of the chip packaging structure 100.

[0038] Combination Figure 1 , 4 As shown, the chip package structure 100 may include only one first chip 20, with the first dam 41 located on both sides of the first chip 20. Alternatively, the chip package structure 100 may include at least two first chips 20, with the first dam 41 located on both sides of the at least two first chips 20 along a second direction.

[0039] Combination Figure 2 , 5 As shown, in other embodiments, when the chip packaging structure 100 includes at least two first chips 20, the first dam 41 can also be disposed between adjacent first chips 20. In this way, multiple first chips 20 are arranged along the second direction, the distance between the two sides of the multiple first chips 20 is long, and the length of the second chip 30 along the second direction is long. The first dam 41 is further disposed between adjacent first chips 20 to better support the middle part of the second chip 30.

[0040] Combination Figure 4-5 As shown, the substrate 10 has a length direction and a width direction. When the first direction is parallel to the width direction of the substrate 10, the second direction is parallel to the length direction of the substrate 10; when the first direction is parallel to the length direction of the substrate 10, the second direction is parallel to the width direction of the substrate 10. The first dam 41 extends along the first direction, and two first dams 41 are spaced apart along the second direction, so that the second chip 30 can be supported above the first chip 20 across the first chip 20.

[0041] The first dam 41 is made of an insulating material, such as silicone, epoxy resin, or polyimide, and has high hardness and a low coefficient of thermal expansion. The first dam 41 is not used to provide electrical connection between the second chip 30 and the substrate 10; it is only used to provide insulating support for the second chip 30. The first dam 41 may be attached to the first surface 101 using an insulating adhesive.

[0042] The support structure 40 includes a second dam 42, which extends along a second direction and is located on both sides of the first chip 20 along a first direction; the first dam 41 connects the first surface 101 and the second chip 30, and the two ends of the second dam 42 are connected to the first surface 101 or the first dam 41, with at least a portion of the second dam 42 and the first surface 101 spaced apart; the second dam 42 extends along the second direction and is located on both sides of the first chip 20 along the first direction, and is used to support the second chip 30 on both sides along the first direction, optimize the distribution of support force on the second chip 30, and provide multi-directional and balanced support force for the second chip 30.

[0043] The second dam 42 and the first surface 101 are spaced apart at least in order to reserve the inlet and outlet for subsequent injection molding, so as to allow the molding material to enter the space around the first chip 20 and wrap and protect the first chip 20.

[0044] In summary, the second cofferdam 42, combined with the first cofferdam 41, forms a multi-directional support frame, enhancing the integrity and uniformity of the support structure 40, thereby improving the support strength and balance. The suspended design of the second cofferdam 42 provides a pre-installed injection molding channel, facilitating subsequent molding processes and improving process flexibility.

[0045] The second dam 42 is made of an insulating material, such as silicone, epoxy resin, or polyimide, and has high hardness and a low coefficient of thermal expansion. The second dam 42 is not used to provide electrical connection between the second chip 30 and the substrate 10; it is only used to provide insulating support for the second chip 30. The second dam 42 is attached to the first surface 101 or the first dam 41.

[0046] Specifically, the second dam 42 includes support ends located at both ends. The support ends can be connected to the first dam 41, and the second dam 42 is supported by the first dam 41. Alternatively, the support ends can be directly connected to the first surface 101, and the second dam 42 is supported by the base plate 10. The second dam 42 includes a suspended portion 421 located between the support ends, and the suspended portion 421 and the first surface 101 are spaced apart.

[0047] An injection opening 401 is formed between the suspended portion 421 and the first surface 101. Two second dams 42 are disposed on both sides of the first chip 20 along the first direction. It can be understood that the two second dams 42 form two injection openings 401 on both sides of the first chip 20. The two injection openings 401 are used for the inflow and outflow of the molding compound, respectively.

[0048] It is understandable that when the first direction is the width direction of the substrate 10, the two injection openings 401 are connected relative to each other along the first direction, and injection molding is performed along the first direction, that is, along the width direction of the substrate 10. When the first direction is the length direction of the substrate 10, the two injection openings 401 are connected relative to each other along the first direction, and injection molding is performed along the first direction, that is, along the length direction of the substrate 10. In this way, even if the support structure 40 is disposed around the first chip 20, it does not affect the molding compound's ability to encapsulate and protect the first chip 20.

[0049] The first and second dams 41 and 42 form a frame structure, the dimensions of which match the dimensions of the second chip 30, precisely supporting the second chip 30 without excessively occupying planar space. Specifically, combined with Figure 1 , 6 The outer contour of the second chip 30 matches the frame structure, and the outer contour of the second chip 30 is completely supported by the frame structure, which provides uniform and surrounding support for the second chip 30.

[0050] The support structure 40 is not lower than the first chip 20. The height design of the support structure 40 ensures that it effectively contacts the second chip 30, provides sufficient support, and prevents the second chip 30 from tilting or stress concentration due to insufficient height, thereby improving the reliability and yield of the chip packaging structure.

[0051] Specifically, when the chip packaging structure 100 only has a first dam 41, the second dam 41 is higher than the first chip 20, and the two sides of the second chip 30 are supported by the first dam 41. When the chip packaging structure 100 has a first dam 41 and a second dam 42, both the first dam 41 and the second dam 42 are higher than the first chip 20, and the first dam 41 and the second dam 42 are used to support the four sides of the second chip 30.

[0052] The substrate 10 has a first welding area 11 and a second welding area 12, which are spaced apart on the first surface 101; a first chip 20 is electrically connected to the first welding area 11, a second chip 30 is electrically connected to the second welding area 12, and at least a portion of the support structure 40 is located between the first welding area 11 and the second welding area 12.

[0053] The support structure 40 provides insulating support for the second chip 30 without affecting the electrical connection between the second chip 30 and the substrate 10. Located between the first soldering area 11 and the second soldering area 12, the support structure 40 provides physical isolation, reducing electrical crosstalk and short-circuit risks. Simultaneously, this layout optimizes the wiring space of the substrate 10, improving the flexibility of the packaging design and electrical performance.

[0054] Combination Figure 4As shown, the first dam 41 is disposed between the first welding area 11 and the second welding area 12. The inner side of the first dam 41 is used to dispose of the first chip 20, thereby electrically connecting the second chip 30 and the first welding area 11. The outer side of the first dam 41 is used to dispose of the second welding area 12, thereby electrically connecting the second chip 30 and the second welding area 12.

[0055] Combination Figure 5 As shown, when the chip package structure 100 includes a first dam 41 located between adjacent first chips 20, the first dam 41 is located between adjacent first solder areas 12.

[0056] Combination Figure 6 As shown, when the chip packaging structure 100 includes a second dam 42, the second dam 42 is located outside the first welding area 11 and inside the second welding area 12.

[0057] The first chip 20 is flip-chip mounted on the first surface 101. The first chip 20 is electrically connected to the first soldering area 11 via metal pillars or metal balls. The metal pillars or metal balls can be made of gold or tin. The side of the first chip 20 facing away from the first surface 101 is spaced apart from the second chip 30.

[0058] The second chip 30 has a third soldering area 31, a functional surface 301, and a non-functional surface disposed opposite to it. The third soldering area 31 is disposed on the functional surface 301 and is electrically connected to the substrate 10. The non-functional surface is connected to the support structure 40. The connection between the non-functional surface of the second chip 30 and the support structure 40 provides mechanical support for the second chip 30. The electrical connection between the third soldering area 31 of the second chip 30 and the substrate 10 enables the electrical function of the second chip 30. This protects the functional surface 301 from mechanical stress and contamination, ensuring its performance and reliability. Simultaneously, the electrical connection of the second chip 30 is independent of the support structure 40, avoiding the influence of the support structure 40 on the electrical signals.

[0059] Specifically, the non-functional surface of the second chip 30 is connected to the surface of the support structure 40 via insulating bonding adhesive. The support structure 40 is electrically connected to the outer part of the non-functional surface of the second chip 30, the third welding area 31, and the lead wire 80 of the substrate 10.

[0060] The second chip 30 is an image sensor chip. Its functional surface 301 and the third bonding area 31 are opposite to the first chip 20 and the substrate 10. The third bonding area 31 and the second bonding area 12 are connected by wire bonding. The second chip 30 includes a functional area 32, and the third bonding area 31 is located outside the functional area 32.

[0061] The chip packaging structure 100 includes a cover plate 50 and a third dam 60. The third dam 60 is located on the functional surface 301 of the second chip 30, and the third soldering area 31 is located outside the third dam 60. The third dam 60 surrounds the functional area 32. The cover plate 50 is disposed on the side of the second chip 30 away from the support structure 40. The cover plate 50 and the third dam 60 are connected, and the cover plate 50 and the third dam 60 together seal the functional area 32.

[0062] Understandably, the support structure 40 has good support strength and can be used to support the second chip 30, the third dam 60 and the cover plate 50 at the same time, thereby enhancing the reliability of the chip packaging structure 100.

[0063] The chip package structure 100 includes a molding compound 70, which fills the gap between the first chip 20, the support structure 40, and the second chip 30, and encapsulates the first chip 20, the support structure 40, and at least a portion of the second chip 30. The molding compound 70 fills the gap, avoiding increased thermal resistance and weakened mechanical strength caused by voids, ensuring the mechanical strength and electrical connection stability of the chip package structure 100 under harsh environments. The molding compound 70 provides mechanical protection, thermal management, environmental protection, and stress buffering, significantly improving the durability and reliability of the chip package structure 100. The molding compound 70 at least exposes a cover plate 50, allowing light to pass through the cover plate 50 into the functional area 32 in applications where the second chip 30 is an image sensing chip, thus ensuring the optical performance of the chip package structure 100.

[0064] A molding layer 70 is disposed on a first surface 101 of a substrate 10. The substrate 10 also includes a second surface facing away from the first surface 101. The second surface is provided with solder pads 13. It is understood that the first soldering area 11, the second soldering area 12 and the solder pads 13 are electrically connected. The solder pads 13 are used to electrically connect to an external circuit to transmit signals from the first chip 20 and the second chip 30 to the outside.

[0065] This application also discloses a chip packaging method for fabricating the chip packaging structure 100 in any of the above technical solutions. Specific technical features of the structure will not be detailed below. The chip packaging method includes the following steps: S1: A substrate 10, a first chip 20, a support structure 40, and a second chip 30 are provided; the substrate 10 has a first surface 101; it is understood that there is no difference in the order in which the substrate 10, the first chip 20, the support structure 40, and the second chip 30 are provided. The substrate 10 is a printed circuit board or a ceramic substrate, the first chip 20 and the second chip 30 are thinned and surface-treated, and the support structure 40 is pre-formed.

[0066] S2: Electrically connect the first chip 20 and the substrate 10; combine Figure 3As shown, at least one first chip 20 is flip-chip mounted on the first surface 101, and the metal pillars or metal balls of the first chip 20 are electrically connected to the first soldering area 11 by reflow soldering or thermoforming.

[0067] S3: The support structure 40 is disposed on the first surface 101, and the support structure 40 is located outside the first chip 20; combined with Figure 4-6 As shown, the support structure 40 is fixed to the first surface 101 by an insulating adhesive, and the support structure 40 and the first chip 20 are spaced apart.

[0068] S4: Connect the second chip 30 to the side of the support structure 40 away from the substrate 10, so that the support structure 40 supports the second chip 30 and the second chip 30 has good stability.

[0069] Setting the support structure 40 on the first surface 101 includes step S31: setting the first dam 41 along the first direction on the first surface 101, and setting at least two first dams 41 on both sides of the first chip 20 along the second direction. The first direction and the second direction are horizontal and perpendicular to each other, and at least a portion of the support structure 40 is formed by the first dams 41.

[0070] Combination Figure 4-5 As shown, the first dam 41 can be optionally attached to the first surface 101, with the bottom surface of the first dam 41 completely attached to the first surface 101, increasing the contact area and improving support stability. The first direction can be either the length direction or the width direction of the substrate 10. In other words, the first dam 41 can extend along the length direction or the width direction of the substrate, and the two first dams 41 can be spaced apart along the width direction or the length direction of the substrate.

[0071] The support structure 40 is disposed on the first surface 101, including step S32: connecting two first dams 41 with a second dam 42 along a second direction, at least a portion of the second dam 42 is spaced from the first surface 101, the second dam 42 is located on both sides of the first chip 20 along the first direction, and at least a portion of the support structure 40 is formed by the second dam 42.

[0072] Combination Figure 6 As shown, after the first dam 41 is oriented on the first surface 101, the second dam 42 is perpendicular to the first dam 41 and is disposed on the substrate 10. The two ends of the second dam 42 can be directly disposed on the first surface 101 or disposed on the first dam 41, as long as the two ends of the second dam 42 can be supported. The key point is that the second dam 42 includes a suspended part 421, which is located between the two ends of the second dam 42. A gap is formed between the suspended part 421 and the first surface 101, thereby forming an injection opening 401 for the subsequent inflow and outflow of molding compound.

[0073] Figure 6 The middle arrow indicates an injection direction that should be parallel to the first direction. It is understood that even if only the first dam 41 is provided, the injection direction is still preferably parallel to the first direction to facilitate injection molding.

[0074] Connecting the second chip 30 to the side of the support structure 40 away from the substrate 10 includes step S41: The non-functional surface of the second chip 30 is connected to the frame structure formed by the first dam 41 and the second dam 42. The third welding area 31 of the second chip 30 is electrically connected to the substrate 10.

[0075] Combination Figure 7 As shown, when the second chip 30 is an image sensing chip, the second chip 30 is already bonded together as a whole by the third dam 60 and the cover plate 50, which involves the packaging of the image sensing chip, and will not be described in detail here; in other embodiments, the second chip 30 is other functional chips, and the second chip 30 can also be directly connected to the support structure 40.

[0076] The non-functional surface of the second chip 30 is provided with a bonding layer 90. The bonding layer 90 is attached to the support structure 40. The bonding layer 90 does not contact the first chip 20, and is thus spaced apart from the first chip 20.

[0077] Combination Figure 8 As shown, when the second chip 30 is provided, the second chip 30 has been bonded together as a whole by the bonding part 60 and the cover plate 50. The third welding area 31 of the second chip 30 is exposed and used to bond to the lead wire 80 of the second welding area 12 of the substrate 10, which facilitates wire bonding and simplifies the process.

[0078] The chip packaging method includes step S5: fabricating a molding compound 70, which includes the steps of: injecting molding compound material into the first surface 101 along a first direction, the molding compound material flowing from one side of the substrate 10 to the other side of the substrate 10 along the first direction, and the molding compound material curing to form the molding compound 70. The molding compound material can be formed by thermosetting or UV curing to form the molding compound 70.

[0079] Combination Figure 4 , 6 As shown in Figure 9, when the chip packaging structure 100 is provided with only the first dam 41, the molding compound is injected along the first direction. The two sides without the first dam 41 are formed as openings for the molding compound to flow in and out. The molding compound gradually fills the gap between the first dam 41, the first chip 20 and the second chip 30 and wraps the first dam 41, the first chip 20 and at least part of the second chip 30.

[0080] When the chip packaging structure 100 is provided with a first dam 41 and a second dam 42, molding material is injected along the first direction, and an injection opening 401 is formed between the suspended part 421 and the first surface 101 for the molding material to flow in and out.

[0081] The beneficial effects of the present invention are as follows: the support structure 40 provides independent mechanical support, thereby improving the support force on the second chip 30 when multiple chips are stacked; the first dam 41 optimizes the distribution of support force and provides directional support, ensuring the stability of the second chip 30 in the horizontal direction; the combination of the first dam 41 and the second dam 42 provides multi-directional and balanced support force for the second chip 30.

[0082] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0083] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0084] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a substrate having a first surface; at least one first chip disposed on the first surface and electrically connected to the substrate; a second chip disposed on a side of the first chip away from the substrate, the second chip being electrically connected to the substrate; a support structure disposed on an outer side of the at least one first chip, the support structure connecting the first surface and the second chip.

2. The chip package structure of claim 1, wherein, The support structure comprises a first dam extending along a first direction and located on both sides of the first chip along a second direction, the first direction and the second direction being horizontal directions and perpendicular to each other.

3. The chip package structure of claim 2, wherein, The support structure comprises a second dam extending along a second direction and located on both sides of the first chip along a first direction; the first dam connects the first surface and the second chip, and both ends of the second dam are connected to the first surface or the first dam, at least part of the second dam being spaced apart from the first surface.

4. The chip package structure of claim 3, wherein, The first dam and the second dam form a frame-shaped structure, and the size of the frame-shaped structure matches the size of the second chip.

5. The chip package structure of claim 3, wherein, The first dam and the second dam are insulating materials.

6. The chip package structure of claim 1, wherein, The support structure is not lower than the first chip.

7. The chip package structure of claim 1, wherein, The substrate has a first soldering area and a second soldering area, the first soldering area and the second soldering area being spaced apart on the first surface; the first chip is electrically connected to the first soldering area, the second chip is electrically connected to the second soldering area, and at least part of the support structure is located between the first soldering area and the second soldering area.

8. The chip package structure of claim 1, wherein, The second chip has a third soldering area, an oppositely disposed functional surface, and a non-functional surface, the third soldering area being disposed on the functional surface, the third soldering area being electrically connected to the substrate, and the non-functional surface being connected to the support structure.

9. The chip package structure of claim 1, wherein, The chip package structure comprises a plastic encapsulation layer, the plastic encapsulation layer filling the gap between the first chip, the support structure, and the second chip and wrapping the first chip, the support structure, and at least part of the second chip.

10. A chip packaging method, characterized by, The chip package structure comprises: providing a substrate, a first chip, a support structure, and a second chip; the substrate has a first surface; electrically connecting the first chip and the substrate; disposing the support structure on the first surface, the support structure being located on an outer side of the first chip; connecting the second chip to a side of the support structure away from the substrate.

11. The chip packaging method of claim 10, wherein, The step of disposing the support structure on the first surface comprises the steps of: disposing a first dam on the first surface along a first direction, at least two first dams being disposed on both sides of the first chip along a second direction, the first direction and the second direction being horizontal directions and perpendicular to each other, and at least part of the support structure being formed by the first dams.

12. The chip packaging method of claim 11, wherein, The step of disposing the support structure on the first surface comprises the steps of: connecting two first dams with a second dam along a second direction, the second dam being spaced apart from the first surface and located on both sides of the first chip along a first direction, and at least part of the support structure being formed by the second dam.

13. The chip packaging method of claim 12, wherein, The step of connecting the second chip to a side of the support structure away from the substrate comprises the steps of: connecting a non-functional surface of the second chip to a frame-shaped structure formed by the first dam and the second dam; electrically connecting the third bonding area of the second chip and the substrate.

14. The chip packaging method of claim 12, wherein, manufacturing a plastic encapsulation layer, comprising the step of: injecting plastic encapsulation material along the first direction on the first surface, the plastic encapsulation material flowing from one side of the substrate to the other side of the substrate along the first direction, and the plastic encapsulation material being solidified to form the plastic encapsulation layer.

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