Circuit board

Abstract

A circuit substrate is provided with an active region and a bonding region, and comprises a substrate, a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked in the bonding region. The second conductive layer is electrically connected with the first conductive layer through at least one through hole. The vertical projection of the third conductive layer on the substrate overlaps the vertical projection of the at least one through hole on the substrate.

Description

Technical Field

[0001] This invention relates to a circuit board. Background Technology

[0002] COF (Chip-on-Flush) is a technology that uses flip-chip bonding on flexible printed circuit boards (FPCs). A relatively thick planarization layer is placed within the active area of ​​the circuit board. To facilitate bonding, the planarization layer is removed from the bonding area of ​​the circuit board. However, the insulating layer between different conductive layers has a limited thickness. When etching the upper conductive layer, the lower conductive layer is easily damaged by the etchant seeping in, reducing the reliability of the circuit board. Summary of the Invention

[0003] This invention provides a circuit board with excellent structural integrity and high reliability.

[0004] According to an embodiment of the present invention, a circuit board is provided, having an active region and a bonding region, and including a substrate, a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked in the bonding region. The second conductive layer is electrically connected to the first conductive layer through at least one via. The vertical projection of the third conductive layer on the substrate overlaps with the vertical projection of the at least one via on the substrate.

[0005] Based on the above, the circuit board provided by the embodiments of the present invention utilizes an upper conductive layer overlapping a lower conductive layer and conductive vias in the bonding area, which can prevent the lower conductive layer and conductive vias from being damaged in subsequent etching processes, and greatly improve the structural integrity and reliability of the circuit board.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1A A schematic cross-sectional view of a circuit board according to an embodiment of the present invention is shown. Figure 1B Show Figure 1A A schematic diagram of the middle section structure. Figure 1C Show Figure 1A A schematic diagram of the middle part of the structure.

[0008] Figure 2 A schematic cross-sectional view of a circuit board according to a comparative example is shown.

[0009] Explanation of reference numerals in the attached figures: 1: Circuit board 2: Circuit board BP1: Insulation layer BP2: Insulation layer BP3: Insulation layer GI: Gate insulation layer ILD: Interlayer Insulation Layer M1: First conductive layer M2: Second conductive layer M3: Third conductive layer M4: Fourth conductive layer PV1: Insulation layer PV2: Insulation layer PL1: Planarization layer PL2: Planarization layer R1: Active Zone R2: Junction area SB: Substrate S1: Side S2: Side S3: Side S4: Side TH1: Through hole TH2: Through hole TH3: Through hole W2: Width W3: Width W4: Width Detailed Implementation

[0010] Reference Figure 1A , Figure 1B as well as Figure 1C ,in Figure 1A A schematic cross-sectional view of a circuit board according to an embodiment of the present invention is shown. Figure 1B Show Figure 1A A schematic diagram of the middle section structure. Figure 1C Show Figure 1A A schematic diagram of the middle part of the structure.

[0011] The circuit board 1 in this embodiment has an active region R1 and a bonding region R2.

[0012] Within the active region R1, the substrate SB is sequentially stacked with a first conductive layer M1, a gate insulating layer GI, an interlayer insulating layer ILD, a second conductive layer M2, an insulating layer PV1, a planarization layer PL1, an insulating layer BP1, a third conductive layer M3, an insulating layer PV2, a planarization layer PL2, an insulating layer BP2, a fourth conductive layer M4, and an insulating layer BP3.

[0013] Within the bonding region R2, the substrate SB is sequentially stacked with a first conductive layer M1, a gate insulating layer GI, an interlayer insulating layer ILD, a second conductive layer M2, an insulating layer PV1, an insulating layer BP1, a third conductive layer M3, an insulating layer PV2, an insulating layer BP2, a fourth conductive layer M4, and an insulating layer BP3. The first conductive layer M1 is electrically connected to the second conductive layer M2 through multiple vias TH1. The second conductive layer M2 is electrically connected to the third conductive layer M3 through multiple vias TH2. The third conductive layer M3 is electrically connected to the fourth conductive layer M4 through multiple vias TH3.

[0014] It should be noted that within the active region R1, the planarization layer PL1 is positioned between the insulating layers PV1 and BP1, while the insulating layer PV1 directly contacts the insulating layer BP1 within the bonding region R2. In other words, to facilitate bonding, the planarization layers PL1 and PL2 are removed within the bonding region R2. However, the thicknesses of the planarization layers PL1 and PL2 are typically greater than 1 µm, thus providing sufficient protection. In contrast, the combined thickness of the insulating layers PV1 and BP1 is typically less than 8000 Å, offering limited protection. Therefore, some layers within the bonding region R2 are vulnerable to damage in subsequent processes due to the removal of the planarization layers PL1 and PL2, lacking protection.

[0015] Specifically, please refer to Figure 2 This diagram shows a cross-sectional schematic of a circuit board 2 according to a comparative example. In this comparative example, the planarization layer PL1, which provides protection, is removed within the bonding region R2. Because the second conductive layer M2 above the vias TH1 has an uneven upper surface, the insulating layer PV1 on the second conductive layer M2 has poor coverage. Therefore, during the removal of the planarization layer PL1, the developer may penetrate the insulating layer PV1. In particular, during the subsequent etching process of the third conductive layer M3, the etchant may damage the second conductive layer M2 and the vias TH1, resulting in an open circuit structure in the circuit board 2. Similarly, in this comparative example, the planarization layer PL2 of the circuit board 2 is also removed within the bonding region R2. Because the third conductive layer M3 above the vias TH2 has an uneven surface, the insulating layer PV2 on the third conductive layer M3 has poor coverage. Therefore, during the removal of the planarization layer PL2, the developer may penetrate the insulating layer PV2. Furthermore, in the subsequent etching process of the fourth conductive layer M4, the etching solution may damage the third conductive layer M3 and the vias TH2, and may even damage the second conductive layer M2 and the vias TH1 again, resulting in more open circuit structures on the circuit board 2.

[0016] Re-reference Figure 1ATo avoid the situation described in the comparative example above, the third conductive layer M3 of the circuit board 1 according to an embodiment of the present invention is configured to completely overlap or at least partially overlap the vias TH1. In other words, the vertical projection of the vias TH1 on the substrate SB completely falls into the vertical projection of the third conductive layer M3 on the substrate SB, or the vertical projection of the vias TH1 on the substrate SB at least partially overlaps the vertical projection of the third conductive layer M3 on the substrate SB. With this configuration, the third conductive layer M3 can protect the second conductive layer M2 and the vias TH1, preventing subsequent etching processes from damaging the second conductive layer M2 and the vias TH1.

[0017] In some embodiments, to improve the protective effect of the third conductive layer M3 on the second conductive layer M2, the width W3 of the third conductive layer M3 in the Y direction is configured to be greater than the width W2 of the second conductive layer M2 in the Y direction, such as... Figure 1B As shown; in some embodiments, the difference between the width W3 of the third conductive layer M3 and the width W2 of the second conductive layer M2 is greater than or equal to 1 µm; in some embodiments, the vertical projections of the two opposite sides S1, S2 of the second conductive layer M2 in the Y direction onto the substrate SB fall within the vertical projection of the third conductive layer M3 onto the substrate SB.

[0018] Similarly, the vertical projections of the vias TH2 on the substrate SB of the circuit board 1 completely fall within the vertical projection of the fourth conductive layer M4 on the substrate SB, or the vertical projections of the vias TH2 on the substrate SB at least partially overlap the vertical projection of the fourth conductive layer M4 on the substrate SB. In this configuration, the fourth conductive layer M4 can protect the third conductive layer M3 and the vias TH2, preventing subsequent etching processes from damaging the third conductive layer M3 and the vias TH2, thereby improving the structural integrity and reliability of the circuit board 1.

[0019] In some embodiments, to improve the protective effect of the fourth conductive layer M4 on the third conductive layer M3, the width W4 of the fourth conductive layer M4 in the Y direction is configured to be greater than the width W3 of the third conductive layer M3 in the Y direction, such as... Figure 1C As shown; in some embodiments, the difference between the width W4 of the fourth conductive layer M4 and the width W3 of the third conductive layer M3 is greater than or equal to 1 µm; in some embodiments, the vertical projections of the two opposite sides S3, S4 of the third conductive layer M3 in the Y direction onto the substrate SB fall within the vertical projection of the fourth conductive layer M4 onto the substrate SB.

[0020] exist Figure 1A In the structure shown, the fourth conductive layer M4 comprises a metal oxide, such as indium tin oxide and indium zinc oxide. Accordingly, the fourth conductive layer M4 will not be etched by subsequent etching solutions, and therefore can serve as the uppermost conductive layer of the circuit substrate 1 within the bonding region R2.

[0021] In summary, the circuit board provided by the embodiments of the present invention utilizes an upper conductive layer overlapping a lower conductive layer and conductive vias in the bonding area, which can prevent the lower conductive layer and conductive vias from being damaged in subsequent etching processes, and greatly improve the structural integrity and reliability of the circuit board.

Claims

1. A circuit board having an active region and a bonding region, and comprising a substrate, a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked in the bonding region, wherein... The second conductive layer is electrically connected to the first conductive layer through at least one via, and The vertical projection of the third conductive layer on the substrate overlaps with the vertical projection of the at least one via on the substrate.

2. The circuit board of claim 1, wherein the third conductive layer comprises a metal oxide.

3. The circuit board of claim 1, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer is between the second conductive layer and the second insulating layer, the second insulating layer is between the first conductive layer and the third conductive layer, and a planarization layer of the circuit board is disposed in the active region between the first insulating layer and the second insulating layer.

4. The circuit board of claim 3, wherein the thickness of the planarization layer is greater than 1 µm.

5. The circuit board of claim 3, wherein the first insulating layer directly contacts the second insulating layer within the bonding region.

6. The circuit board of claim 5, wherein the first insulating layer has a first thickness, the second insulating layer has a second thickness, and the sum of the first thickness and the second thickness is less than 8000 Å.

7. The circuit board of claim 1, wherein the width of the third conductive layer in one direction is greater than the width of the second conductive layer in that direction.

8. The circuit board of claim 7, wherein the vertical projections of the two opposite sides of the second conductive layer on the board in the direction fall within the vertical projection of the third conductive layer on the board.

9. The circuit board of claim 7, wherein the difference between the width of the third conductive layer and the width of the second conductive layer is greater than or equal to 1 µm.

10. The circuit board of claim 1, wherein the vertical projection of the at least one via on the board falls entirely within the vertical projection of the third conductive layer on the board.

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