Vertical nonvolatile memory device

Abstract

A vertical non-volatile memory device includes a vertical channel structure, first gate lines extending in a horizontal direction while surrounding the vertical channel structure and separated from each other in the vertical direction, second gate lines extending in the horizontal direction on the first gate lines, first semiconductor lines extending in the horizontal direction on the second gate lines, and second semiconductor lines extending in the horizontal direction on the second gate lines. A semiconductor contact plug of a second conductivity type connected to the vertical channel structure by passing through the first semiconductor line and the second gate line, a second semiconductor line of the second conductivity type extending in a horizontal direction on the semiconductor contact plug and connected to the semiconductor contact plug, a first metal contact plug connected to the first semiconductor line and a second metal contact plug connected to the second semiconductor line.

Description

Technical Field

[0001] The present invention relates to a memory device, and more specifically, to a vertical non-volatile memory device. Background Technology

[0002] In electronic systems requiring data storage, there is a need for non-volatile memory devices capable of storing high-capacity data. Therefore, methods to increase the data storage capacity of non-volatile memory devices have been investigated. For example, as one method to increase the data storage capacity of non-volatile memory devices, a vertical non-volatile memory device comprising three-dimensionally arranged vertical memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0003] The present invention provides a vertical non-volatile memory device in which the operational characteristics of a three-dimensionally arranged vertical memory cell are improved.

[0004] According to an exemplary embodiment of the present invention, a vertical non-volatile memory device may include: a plurality of vertical channel structures extending in a vertical direction and separated from each other in a horizontal direction; a plurality of first gate lines extending in a horizontal direction and surrounding the plurality of vertical channel structures, the plurality of first gate lines being separated from each other in a vertical direction and configured as word lines; a second gate line extending in a horizontal direction on the plurality of first gate lines and configured as a ground select line; a first semiconductor line of a first conductivity type extending in a horizontal direction on a second gate line; a plurality of semiconductor contact plugs of a second conductivity type connected to the plurality of vertical channel structures by passing through the first semiconductor line and the second gate line; a second semiconductor line of a second conductivity type extending in a horizontal direction on and connected to the plurality of semiconductor contact plugs; a first metal contact plug connected to the first semiconductor line; and a second metal contact plug connected to the second semiconductor line.

[0005] According to an exemplary embodiment of the present invention, a vertical non-volatile memory device may include: a plurality of vertical channel structures extending in a vertical direction and separated from each other in a horizontal direction; a plurality of first gate lines extending in a horizontal direction and surrounding the plurality of vertical channel structures, the plurality of first gate lines being separated from each other in a vertical direction and configured as word lines; a second gate line extending in a horizontal direction on the plurality of first gate lines and configured as a ground select line; a first semiconductor line of a first conductivity type extending in a horizontal direction on the second gate lines; a plurality of semiconductor contact plugs connected to the plurality of vertical channel structures by passing through the first semiconductor line and the second gate line, and the plurality of semiconductor contact plugs being undoped; a first metal contact plug connected to the first semiconductor line; and a metal line extending in a horizontal direction on the plurality of semiconductor contact plugs and connected to the plurality of semiconductor contact plugs.

[0006] According to an exemplary embodiment of the present invention, a vertical non-volatile memory device may include: a plurality of vertical channel structures extending in a vertical direction and spaced apart from each other in a horizontal direction; a plurality of first gate lines extending in a horizontal direction and surrounding the plurality of vertical channel structures, the plurality of first gate lines being separated from each other in a vertical direction and configured as word lines; a second gate line extending in a horizontal direction on the plurality of first gate lines, the second gate line being spaced apart from the plurality of vertical channel structures in a vertical direction and configured as a ground select line; a first semiconductor line of a first conductivity type extending horizontally on the second gate lines, the first semiconductor line including a first ohmic contact region; and a plurality of semiconductor contact plugs of a second conductivity type. The plurality of semiconductor contact plugs are connected to the plurality of vertical channel structures through a first semiconductor line and a second gate line; a gate dielectric layer of a ground selection transistor is provided in a recessed hole in the sidewalls of the plurality of semiconductor contact plugs, the recessed hole being defined by the space between the sidewalls of the plurality of semiconductor contact plugs and the second gate line; a second semiconductor line of a second conductivity type extends horizontally over the plurality of semiconductor contact plugs and is separated from the first semiconductor line in a vertical direction, the second semiconductor line being connected to the plurality of semiconductor contact plugs, the second semiconductor line including a second ohmic contact region; a first metal contact plug connected to the first semiconductor line through the first ohmic contact region; and a second metal contact plug connected to the second semiconductor line through the second ohmic contact region. Attached Figure Description

[0007] The embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, wherein:

[0008] Figure 1This is a block diagram of a vertical non-volatile memory device according to an embodiment;

[0009] Figure 2A This is a schematic perspective view of a vertical non-volatile memory device according to an embodiment;

[0010] Figure 2B This is an equivalent circuit diagram of a memory cell array of a vertical non-volatile memory device according to an embodiment.

[0011] Figure 3 This is a layout diagram of the main components of a vertical non-volatile memory device according to an embodiment;

[0012] Figure 4 This is a cross-sectional view of a vertical non-volatile memory device according to an embodiment.

[0013] Figure 5 yes Figure 4 Enlarged partial sectional view;

[0014] Figure 6 This is a cross-sectional view of a vertical non-volatile memory device according to an embodiment.

[0015] Figure 7 yes Figure 6 Enlarged partial sectional view;

[0016] Figures 8 to 28 This is a cross-sectional view used to describe a method of manufacturing a vertical non-volatile memory device according to an embodiment; and

[0017] Figures 29 to 32 This is a cross-sectional view used to describe a method for manufacturing a vertical non-volatile memory device according to an embodiment. Detailed Implementation

[0018] The concept of "substantially identical" components can mean that components can be completely identical, and can also mean that components can be determined to be identical considering errors or deviations that occur during the manufacturing process.

[0019] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. The embodiments described below can be implemented as any one of them, and can be implemented as a combination of one or more embodiments. Therefore, the inventive concept should not be construed as being limited to a single embodiment. In this specification, the accompanying drawings are shown in an exaggerated manner to clearly illustrate the inventive concept.

[0020] Figure 1 This is a block diagram of a vertical non-volatile memory device 10 according to an embodiment.

[0021] In detail, the vertical non-volatile memory device 10 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKp (p is a positive integer). Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKp may include multiple vertical memory cells. The multiple memory cell blocks BLK1, BLK2, ..., and BLKp may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL.

[0022] The peripheral circuitry 30 may include a line decoder 32, a page buffer 34, data input and output circuitry 36, control logic 38, and a common source line driver 39. The peripheral circuitry 30 may also include voltage generation circuitry configured to generate various voltages required for the operation of the vertical non-volatile memory device 10, error correction circuitry configured to correct errors in data read from the memory cell array 20, and various circuitry such as input and output interfaces.

[0023] The memory cell array 20 can be connected to the row decoder 32 via word line WL, serial select line SSL, and ground select line GSL, and can be connected to the page buffer 34 via bit line BL. In the memory cell array 20, multiple vertical memory cells included in each of multiple memory cell blocks BLK1, BLK2, ..., and BLKp can include flash memory cells.

[0024] The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include multiple NAND strings, and each NAND string may include multiple vertical memory cells connected to multiple word lines WL stacked vertically.

[0025] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from the outside of the vertical non-volatile memory device 10, and can send data DATA to and receive data DATA from devices outside the vertical non-volatile memory device 10.

[0026] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKp in response to an external address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can transmit the voltage used to perform memory operations to the word line WL of the selected memory cell block.

[0027] Page buffer 34 can be connected to memory cell array 20 via bit line BL. Page buffer 34 can operate as a write driver during programming operations to apply a voltage to bit line BL according to data DATA to be stored in memory cell array 20, and can operate as a sense amplifier during read operations to sense data DATA stored in memory cell array 20. Page buffer 34 can operate in response to control signal PCTL provided from control logic 38.

[0028] Data input / output circuitry 36 can be connected to page buffer 34 via multiple data lines DL. During programming operations, data input / output circuitry 36 can receive data DATA from the memory controller (not shown) and provide programming data DATA to page buffer 34 based on the column address C_ADDR provided from control logic 38. During read operations, data input / output circuitry 36 can provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic 38.

[0029] Data input and output circuitry 36 can transmit input addresses or commands to control logic 38 or line decoder 32. Peripheral circuitry 30 may also include electrostatic discharge (ESD) circuitry and pull-up / pull-down drivers.

[0030] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data input / output circuitry 36. Control logic 38 can generate various internal control signals used in the vertical non-volatile memory device 10 in response to the control signal CTRL. For example, control logic 38 can control the voltage levels supplied to the word line WL and bit line BL during memory operations such as programming or erasing operations.

[0031] The common source line driver 39 can be connected to the memory cell array 20 via the common source line CSL. The common source line driver 39 can apply a common source voltage (e.g., power supply voltage) or ground voltage to the common source line CSL based on the bias control signal CTRL_BIAS of the control logic 38.

[0032] Figure 2A This is a schematic perspective view of the vertical non-volatile memory device 10 according to an embodiment, and Figure 2B This is an equivalent circuit diagram of the memory cell array 20 of the vertical non-volatile memory device 10 according to the embodiment.

[0033] refer to Figure 2AThe vertical non-volatile memory device 10 may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). According to some embodiments, the vertical non-volatile memory device 10 may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that are bonded together in the vertical direction (Z direction). For example, the cell array structure (CAS) may be formed on a first substrate (or a first wafer), and the peripheral circuit structure (PCS) may be formed on a second substrate (or a second wafer). The first and second substrates may then be bonded together to fabricate the vertical non-volatile memory device 10.

[0034] The CAS cell array structure can include a reference. Figure 1 The memory cell array 20 is described. The peripheral circuitry PCS may include reference... Figure 1 The peripheral circuit 30 is described. The cell array structure CAS may include multiple cell tiles 24. Each of the multiple cell tiles 24 may include multiple memory cell blocks BLK1, BLK2, ... and BLKp (p is a positive integer). Each of the multiple memory cell blocks BLK1, BLK2, ... and BLKp may include multiple vertically arranged memory cells in three dimensions.

[0035] According to some implementations, two unit modules 24 can form an integrated block (mat), but the inventive concept is not limited thereto. Reference Figure 1 The described memory cell array 20 may include multiple integrated blocks, for example, four integrated blocks, but the inventive concept is not limited thereto.

[0036] refer to Figure 2B The vertical non-volatile memory device 10 may include a reference. Figure 1 The memory cell array 20 is described. The memory cell array 20 may include multiple vertical memory cells. The vertical memory cells may be arranged in three dimensions.

[0037] Vertical memory cells may include vertical NAND flash memory cells. Memory cell array 20 may include... Figure 1 The multiple memory cell blocks BLK1, BLK2, ... and BLKp shown have each Figure 2B The circuit structure shown is shown in the figure.

[0038] The memory cell array 20 may include multiple memory cell strings MS. The memory cell array 20 may include multiple bit lines BL (e.g., BL1, BL2, ..., BLm), multiple word lines WL (e.g., WL1, WL2, ..., WLn-1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. The multiple memory cell strings MS may be formed between the multiple bit lines BL and the common source line CSL.

[0039] Figure 2B It is shown that each of a plurality of memory cell strings (MS) may include one ground select line (GSL) and two string select lines (SSL). However, the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one ground select line (GSL) and one string select line (SSL).

[0040] Each of the multiple memory cell strings MS may include vertically connected memory cells to each other in the vertical direction. Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to a common source line CSL. The common source line CSL may be a region to which the source regions of the multiple ground select transistors GST are commonly connected.

[0041] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL, namely WL1, WL2, ..., WLn-1 and WLn.

[0042] Figure 3 This is a layout diagram of the main components of the vertical non-volatile memory device 10 according to an embodiment.

[0043] Specifically, the vertical non-volatile memory device 10 may include a memory cell region (MEC). A memory cell array 20 may be formed within the memory cell region (MEC). The memory cell region (MEC) may include multiple word line cut regions (WLCRs). The multiple word line cut regions (WLCRs) may extend longitudinally in a first horizontal direction (X direction). The word line cut regions (WLCRs) may be filled with a cut-buried insulating layer 166. The first horizontal direction (X direction) may correspond to... Figure 2B The direction of the letter line WL.

[0044] The memory cell region (MEC) may include a serial select line cut region (SSLC). The SSLC may extend vertically in a first horizontal direction (X direction). Two adjacent serial select lines (SSLC) in a second horizontal direction (Y direction) (see...) Figure 2B The elements can be spaced apart from each other, with a string selection wire cut area (SSLC) in between. The string selection wire cut area (SSLC) can be filled with an insulating layer (INS).

[0045] The memory cell region (MEC) may include multiple vertical channel structures (CHS) that pass through the stacked structure (STC) in the vertical direction (Z direction) and are separated from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). The stacked structure (STC) may include multiple interlayer insulating layers or gate lines. The stacked structure (STC) may be separated by word line cut regions (WLCRs) in the second horizontal direction (Y direction).

[0046] The area where a vertical channel structure CHS is arranged can be called the channel area CHR (see [link]). Figure 4 The channel region CHR can be defined by the word line cut region WLCR. The vertical channel structure CHS can be located between the word line cut regions WLCR in the second horizontal direction (Y direction).

[0047] Multiple bit lines BL can be connected to the vertical channel structure CHS. The bit lines BL can extend in a second horizontal direction (Y direction) and can be separated from each other in a first horizontal direction (X direction). Multiple bit lines BL can be connected to the vertical channel structure CHS below the vertical channel structure CHS. The second horizontal direction (Y direction) can correspond to... Figure 2B The direction of the bit line BL.

[0048] The vertical nonvolatile memory device 10 may include input and output contact regions 10CR adjacent to the memory cell region MEC. The input and output contact regions 10CR may include a plurality of input and output contact plugs (or input and output contact pads) 190. The input and output contact plugs 190 may be electrically connected to the peripheral circuit structure PCS included in the vertical nonvolatile memory device 10.

[0049] Figure 4 This is a cross-sectional view of the vertical non-volatile memory device 10 according to an embodiment, and Figure 5 yes Figure 4 Enlarged partial sectional view.

[0050] Specifically, the vertical non-volatile memory device 10 may include a channel region CHR, a word line cut-out region WLCR, and input and output contact regions IOCR. The channel region CHR may correspond to the area along the channel line cut-out region WLCR. Figure 4The cross-section cut by the line "A-A'". The word line cutting area WLCR can correspond to the section along... Figure 4 The cross-section cut along line "B-B". The input and output contact areas IOCR can correspond to the section along... Figure 4 The cross section taken by the line "C-C'".

[0051] In the channel region CHR, multiple vertical channel structures CHS, multiple first gate lines 164, second gate lines 162, first semiconductor lines 104 of a first conductivity type, multiple semiconductor contact plugs 172i of a second conductivity type, second semiconductor lines 174i of a second conductivity type, and second metal contact plugs 186 can be arranged. The channel region CHR can be defined by a word line cut region WLCR.

[0052] The vertical channel structure CHS can extend in the vertical direction (Z direction) and can be separated from each other in the horizontal direction (X or Y direction). The first gate lines 164 can extend in the horizontal direction (X or Y direction) while surrounding the vertical channel structure CHS and can be separated from each other in the vertical direction (Z direction). The first gate lines 164 can be used as... Figure 3 The letter line WL.

[0053] The vertical channel structure (CHS) may include a data storage pattern dsp, a vertical channel pattern 158p, and a buried insulating pattern 160p sequentially formed on the inner wall of a channel via 140 that passes vertically through the first gate line 164 and the first interlayer insulating layer 136, as well as a first deformation stop via 124 formed in the third insulating layer 110. The data storage pattern dsp may include a tunnel insulating pattern 152p, a charge storage pattern 154p, and a barrier insulating pattern 156p sequentially formed on the inner wall of the channel via 140 and the first deformation stop via 124.

[0054] The second gate line 162 may extend horizontally over the first gate line 164. The second gate line 162 may be used as... Figure 3 The ground selection line GSL. The first semiconductor line 104 may extend horizontally over the second gate line 162. The first semiconductor line 104 may include a semiconductor layer of a first conductivity type (e.g., N-type). The first semiconductor line 104 may include an N-type polysilicon layer.

[0055] Semiconductor contact plug 172i can be connected to the vertical channel structure CHS by passing through the first semiconductor line 104 and the second gate line 162. Semiconductor contact plug 172i can be buried in a channel exposure via 170, which passes through the third insulating layer 110, the second gate line 162, the second insulating layer 106, the first semiconductor line 104, and the first insulating layer 102 on the vertical channel structure CHS.

[0056] The channel exposure via 170 can expose the upper surface of the vertical channel structure CHS. The channel exposure via 170 can expose the data storage pattern DSP, the vertical channel pattern 158p, and the buried insulation pattern 160p included in the vertical channel structure CHS. The semiconductor contact plug 172i can include a semiconductor layer of a second conductivity type (e.g., P-type). The semiconductor contact plug 172i can include a P-type polysilicon layer.

[0057] A second semiconductor line 174i may extend horizontally over a semiconductor contact plug 172i. The second semiconductor line 174i may be connected to the semiconductor contact plug 172i. The second semiconductor line 174i may include a semiconductor layer of a second conductivity type (e.g., P-type). The second semiconductor line 174i may include a P-type polysilicon layer. A second metal contact plug 186 may be connected to the second semiconductor line 174i.

[0058] A gate dielectric layer can be disposed between the semiconductor contact plug 172i and the second gate line 162 in the channel region CHR. Gate dielectric layers 118p2 and 120p2 can be buried in recessed vias 116 facing the sidewall recesses of the semiconductor contact plug 172i. The gate dielectric layer can correspondingly select the transistor GST (see [link to transistor name]). Figure 2B The gate dielectric layer.

[0059] The gate dielectric layer may include a first gate dielectric pattern 118p2 formed on the inner wall of the recessed via 116 and a second gate dielectric pattern 120p2 formed on the first gate dielectric pattern 118p2 in the recessed via 116. The second gate line 162 and the gate dielectric layer may be separated from the vertical channel structure CHS in the vertical direction.

[0060] The third gate dielectric pattern 118p3 and the fourth gate dielectric pattern 120p3 can be arranged on both sides of the upper portion of the vertical channel structure CHS in the channel region CHR. The third gate dielectric pattern 118p3 and the fourth gate dielectric pattern 120p3 can each comprise the same material as the first gate dielectric pattern 118p2 and the second gate dielectric pattern 120p2.

[0061] The cut-and-buried insulating layer 166, the first ohmic contact region 182, and the first metal contact plug 188 can be arranged in the word line cut region (WLCR). The cut-and-buried insulating layer 166 can be buried in the word line cut hole 146 formed in the first gate line 164, the second gate line 162, and the first interlayer insulating layer 136. The cut-and-buried insulating layer 166 may include a silicon oxide layer.

[0062] The first semiconductor line 104 can extend horizontally from the channel region CHR to the word line cut region WLCR. The first metal contact plug 188 can be connected to the first semiconductor line 104 through the first ohmic contact region 182.

[0063] In the vertical non-volatile memory device 10 conceived according to the present invention, an electronic path EPA can be formed between the first semiconductor line 104 and the first gate line 164 (i.e., the word line) during a read operation, such as... Figure 5 As shown in the diagram. That is, during a read operation, when a read voltage (e.g., 7V) is applied to the first semiconductor line 104 of the first conductivity type (i.e., the N-type polysilicon layer) and 0V is applied to the first gate line 164 (i.e., the word line), an electronic path EPA can be formed to supply electrons from the first gate line 164 (i.e., the word line) through the second conductivity type (i.e., the P-type) semiconductor contact plug 172i to the first metal contact plug 188 and the first semiconductor line 104 to increase the read current.

[0064] A second metal contact plug 186, connected to the second semiconductor line 174i, can be disposed in the channel region CHR. The second metal contact plug 186 can be connected to the second semiconductor line 174i via a second ohmic contact region 178.

[0065] In the vertical non-volatile memory device 10 conceived according to the present invention, a hole path HPA can be formed between the second semiconductor line 174i and the first gate line 164 (i.e., the word line) during an erase operation, such as Figure 5 As shown in the diagram. That is, during the erase operation, when an erase voltage (e.g., 20V) is applied to the second semiconductor line 174i of the second conductivity type (i.e., the P-type polysilicon layer) and 0V is applied to the first gate line 164 (i.e., the word line), a hole path EPA can be formed to supply holes from the second semiconductor line 174i to the first gate line 164 (i.e., the word line) through the semiconductor contact plug 172i of the second conductivity type (i.e., P-type) to increase the erase current.

[0066] Input and output contact structures 168, a fourth buried layer 134, and input and output contact plugs (or input and output pads) 190 may be arranged in the input and output contact region 10CR. The input and output contact structure 168 may be a metal layer buried in an input and output contact hole 148, which is formed in a first interlayer insulating layer 136 and a first interlayer sacrificial layer 138.

[0067] The fourth buried layer 134 can be connected to the input and output contact structure 168. The fourth buried layer 134 may include a metal layer. The fourth buried layer 134 may be formed in the fourth insulating layer 111. Input and output contact plugs 190 can be connected to the fourth buried layer 134. Input and output contact plugs 190 may be formed in the second interlayer insulating layer 175p and the fourth insulating layer 111.

[0068] The vertical non-volatile memory device 10 may include a stacked structure that includes a first stacked region GLS1, a second stacked region GL2 disposed on the first stacked region GLS1, and a wiring region WIRL disposed on the second stacked region GL2 in the vertical direction.

[0069] The first stacked region GSL1 may include a first gate line 164 extending in the horizontal direction and a first portion of the vertical channel structure CHS extending vertically through the first gate line 164. The second stacked region GL2 may include a second portion of the vertical channel structure CHS extending vertically from the first portion of the vertical channel structure CHS in the first stacked region GSL1. In the first stacked region GSL1, input and output contact structures 168 may be formed in the first interlayer insulating layer 136 and the first interlayer sacrificial layer 138 in the input and output contact region IOCR.

[0070] The second stack region GL2 may include a first semiconductor line 104 and a plurality of semiconductor contact plugs 172i. The first semiconductor line 104 is of a first conductivity type and extends in a horizontal direction. The plurality of semiconductor contact plugs 172i are of a second conductivity type and pass through the first semiconductor line 104 and the second gate line 162 and are connected to a second portion of the vertical channel structure CHS. The second stack region GL2 may include a fourth buried layer 134 connected to the input and output contact structures 168 of the input and output contact regions IOCR.

[0071] The first stacked region GSL1 and the second stacked region GL2 may include a cut-and-buried insulating layer 166 buried in a word line cut hole 146 in the word line cut region WLCR, the word line cut hole 146 passing through the first gate line 164 and the second gate line 162.

[0072] The wiring area WIRL may include: a second semiconductor line 174i, which is of a second conductivity type, extending horizontally over and connected to the semiconductor contact plug 172i of the channel region CHR; a second metal contact plug 186 connected to the second semiconductor line 174i of the channel region CHR; and a first metal contact plug 188 connected to the first semiconductor line 104 of the word line cut region WLCR. The wiring area WIRL may include input and output contact plugs 190 connected to the fourth buried layer 134 of the input and output contact regions IOCR.

[0073] The vertical non-volatile memory device 10 having the structure described above may include a semiconductor contact plug 172i and a second semiconductor line 174i. The semiconductor contact plug 172i is of a second conductivity type (i.e., P-type) and is vertically connected to the vertical channel structure CHS. The second semiconductor line 174i extends horizontally over the semiconductor contact plug 172i and includes a polysilicon layer of the second conductivity type (i.e., P-type). Therefore, during an erase operation, the vertical non-volatile memory device 10 may have a hole path HPA between the second semiconductor line 174i and the first gate line 164 (i.e., word line) to increase the erase current.

[0074] Furthermore, the vertical non-volatile memory device 10 according to the present invention may include a first semiconductor line 104 extending horizontally on a vertical channel structure CHS and including a polysilicon layer of a first conductivity type (i.e., N-type). Therefore, during a read operation, the vertical non-volatile memory device 10 may have an electronic path EPA between the first semiconductor line 104 and the first gate line 164 (i.e., word line) to increase the read current. Thus, in the vertical non-volatile memory device 10 according to the present invention, the operating characteristics of the three-dimensionally arranged vertical memory cells as described above can be improved.

[0075] Figure 6 This is a cross-sectional view of the vertical non-volatile memory device 10-1 according to an embodiment, and Figure 7 yes Figure 6 Enlarged partial sectional view.

[0076] In detail, the vertical non-volatile memory device 10-1 may include a channel region CHR, a word line cut-off region WLCR, and input and output contact regions IOCR. The channel region CHR may correspond to the area along the channel line cut-off region WLCR. Figure 4 The cross-section cut by the line "A-A'". The word line cutting area WLCR can correspond to the section along... Figure 4 The cross-section cut along line "B-B". The input and output contact areas IOCR can correspond to the section along... Figure 4 The cross section taken by the line "C-C'".

[0077] Apart from the differences in the configuration of the second stacking region GL2-1 and the wiring region WIRL-1, the vertical non-volatile memory device 10-1 can be compared with... Figure 4 and Figure 5 The vertical non-volatile memory device 10 is the same. Reference for vertical non-volatile memory device 10-1. Figure 4 and Figure 5 The aspects described may be briefly described or not described at all.

[0078] The vertical non-volatile memory device 10-1 may include a stacked structure STC-1, which includes a first stacked region GLS1, a second stacked region GL2-1 disposed on the first stacked region GLS1, and a wiring region WIRL-1 disposed on the second stacked region GL2-1 in the vertical direction.

[0079] The second stack region GL2-1 may include a first semiconductor line 104 and a plurality of semiconductor contact plugs 172. The first semiconductor line 104 is of a first conductivity type and extends in a horizontal direction. The plurality of semiconductor contact plugs 172 pass through the first semiconductor line 104 and the second gate line 162 and are connected to a second portion of the vertical channel structure CHS. The semiconductor contact plugs 172 may include an undoped semiconductor layer.

[0080] The wiring area WIRL-1 may include a metal line 196 and a third metal contact plug 204. The metal line 196 extends horizontally over and connects to the semiconductor contact plug 172 in the channel region CHR. The third metal contact plug 204 connects to the first semiconductor line 104 in the word line cut region WLCR. The third metal contact plug 204 can be connected to the first semiconductor line 104 via a third ohmic contact region 202 of a first conductivity type (i.e., N-type).

[0081] The wiring area WIRL-1 may include a fourth metal contact plug 206 connected to the fourth buried layer 134 of the input and output contact areas IOCR. The wiring area WIRL-1 may include a third interlayer insulation layer 194p that insulates the metal wire 196, the third metal contact plug 204, and the fourth metal contact plug 206 from each other.

[0082] The vertical non-volatile memory device 10-1 having the structure described above may include an undoped semiconductor contact plug 172 connected in the vertical direction to the vertical channel structure CHS, and a metal line 196 extending in the horizontal direction on the semiconductor contact plug 172. Figure 7As shown, during the erase operation, the vertical non-volatile memory device 10-1 may have a hole path HPA between the metal line 196 and the first gate line 164 (i.e., the word line).

[0083] That is, during the erase operation, when the erase voltage (e.g., 20V) is applied to the metal line 196 and 0V is applied to the first gate line 164 (i.e., the word line), a hole path HPA can be formed to supply holes from the metal line 196 to the first gate line 164 (i.e., the word line) through the undoped semiconductor contact plug 172, thereby increasing the erase current.

[0084] Furthermore, in the vertical non-volatile memory device 10-1 conceived according to the present invention, a first semiconductor line 104 may be arranged extending in the horizontal direction on the vertical channel structure CHS and comprising a polysilicon layer of a first conductivity type (i.e., N-type). Therefore, as Figure 7 As shown, the vertical non-volatile memory device 10-1 may have an electronic path EPA between the third metal contact plug 204 and the first gate line 164 (i.e., the word line) during a read operation to increase the read current.

[0085] Therefore, in the vertical non-volatile memory device 10-1 conceived according to the present invention, the operating characteristics of the vertical memory cells arranged in three dimensions as described above can be improved.

[0086] Figures 8 to 28 This is a cross-sectional view used to describe a method for manufacturing a vertical non-volatile memory device according to an embodiment.

[0087] In detail, Figures 8 to 28 It is used to describe manufacturing Figure 4 and Figure 5 A cross-sectional view of a method for constructing a vertical non-volatile memory device 10. Figures 8 to 28 In, with Figure 4 and Figure 5 The same or substantially the same figure references in the figures indicate the same as those in the figures below. Figure 4 and Figure 5 Components that are the same or substantially the same. Figures 8 to 28 In the text, a brief description or no description is provided for reference. Figure 4 and Figure 5 The aspects described.

[0088] refer to Figure 8 and Figure 9 ,like Figure 8As shown, substrate 100 may be defined as a channel region CHR, a word line cut region WLCR, and input and output contact regions IOCR. Substrate 100 may include a semiconductor material. Substrate 100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon-germanium single crystal substrate.

[0089] A first insulating material layer 102r, a first semiconductor line material layer 104r, a second insulating material layer 106r, and a first sacrificial material layer 108r can be formed in the channel region CHR and word line dicing region WLCR of the substrate 100.

[0090] The first insulating material layer 102r, the first semiconductor line material layer 104r, the second insulating material layer 106r, and the first sacrificial material layer 108r can be formed in the horizontal direction ( Figure 4 It extends in the X or Y direction. The first insulating material layer 102r and the second insulating material layer 106r may include silicon oxide layers. The first sacrificial material layer 108r may include a silicon nitride layer having etch selectivity relative to the silicon oxide layer. The first semiconductor line material layer 104r may include a semiconductor layer of a first conductivity type, such as an N-type polysilicon layer.

[0091] A third insulating material layer 110r and a fourth insulating material layer 111r can be formed on the first sacrificial material layer 108r in the channel region CHR and the word line cut region WLCR, and on the substrate 100 in the input and output contact regions IOCR, respectively. The fourth insulating material layer 111r can be formed to be thicker than the third insulating layer 110r. The third insulating layer 110r and the fourth insulating layer 111r may include silicon oxide layers.

[0092] A shielding insulating layer 112r can be formed on the third insulating layer 110r and the fourth insulating layer 111r. The shielding insulating layer 112r can be formed in the channel region CHR, the word line cut region WLCR, and the input and output contact regions IOCR. The shielding insulating layer 112r may include a silicon nitride layer that has etch selectivity relative to the silicon oxide layer.

[0093] like Figure 9 As shown, a plurality of first stop holes 114 can be formed to be spaced apart from each other in the channel region CHR. The first stop holes 114 may be referred to as channel stop holes. The shielding insulating material layer 112r of the channel region CHR can be selectively etched using a photolithography process (see [reference]). Figure 8 ), third insulating material layer 110r (see Figure 8 ), First sacrificial material layer 108r (see Figure 8 ), second insulating material layer 106r (see Figure 8 ), First semiconductor line material layer 104r (see Figure 8 ) and the first insulating material layer 102r (see Figure 8 To form the first stop hole 114.

[0094] Based on the formation of the first stop hole 114, the shielding insulating material layer 112r (see...) Figure 8 ), third insulating material layer 110r (see Figure 8 ), First sacrificial material layer 108r (see Figure 8 ), second insulating material layer 106r (see Figure 8 ), First semiconductor line material layer 104r (see Figure 8 ) and the first insulating material layer 102r (see Figure 8 These can be shielding insulating layer 112, third insulating layer 110, first sacrificial layer 108, second insulating layer 106, first semiconductor line 104, and first insulating layer 102, respectively.

[0095] The surface of the substrate 100 can be exposed by forming the first stop hole 114. By forming the first stop hole 114, the shielding insulating layer 112, the third insulating layer 110, the first sacrificial layer 108, the second insulating layer 106, the first semiconductor line 104, and the sidewall SW1 of the first insulating layer 102 can be exposed.

[0096] refer to Figure 10 and Figure 11 The shielding insulation layer 112 can be as follows Figure 10 The image shown is etched and removed. According to some embodiments, the shielding insulating layer 112 can be removed when the first stop hole 114 is formed. The first sacrificial layer 108 exposed by the first stop hole 114 can be etched in the horizontal direction (X direction) to form a recessed hole 116.

[0097] The recessed hole 116 can be connected to the first stop hole 114. The recessed hole 116 can be connected from the sidewall SW1 of the first sacrificial layer 108 (see...). Figure 10 The indentation is recessed inward. Based on the formation of the recessed hole 116, the first sacrificial layer 108 can be a first sacrificial pattern 108p.

[0098] like Figure 11 As shown, a first gate dielectric material layer 118 and a second gate dielectric material layer 120 can be sequentially formed in the first stop hole 114 and the recessed hole 116. The first gate dielectric material layer 118 can be formed on the inner wall and bottom of the first stop hole 114 and on the inner wall of the recessed hole 116. The second gate dielectric material layer 120 can be formed on the first gate dielectric material layer 118.

[0099] The second gate dielectric material layer 120 may also be formed in the first stop hole 114. The first gate dielectric material layer 118 may include a material different from that of the second gate dielectric material layer 120. The first gate dielectric material layer 118 may include a silicon oxide layer. The second gate dielectric material layer 120 may include a silicon nitride layer.

[0100] refer to Figure 12 and Figure 13 ,like Figure 12 As shown, a first buried layer 122 may be formed on the second gate dielectric material layer 120 and buried in the first stop hole 114. The first buried layer 122 may include a polysilicon layer.

[0101] like Figure 13 As shown, the first buried layer 122 can be etched back (see Figure 122). Figure 12 A first buried pattern 122p1 is formed in the first stop hole 114. The first buried pattern 122p1 can be formed so as not to expose the first gate dielectric material layer 118 and the second gate dielectric material layer 120 formed in the recessed hole 116 (see...). Figure 10 By etching back the first buried layer 122, a first deformation stop hole 124 can be formed in the first buried pattern 122p1.

[0102] refer to Figure 14 and Figure 15 ,like Figure 14 As shown, a second stop hole 126 and a third stop hole 128 can be formed in the word line cut region WLCR and the input and output contact regions IOCR, respectively. The second stop hole 126 can be formed by selectively etching the third insulating layer 110 and the first sacrificial pattern 108p of the word line cut region WLCR using a photolithography process.

[0103] The fourth insulating material layer 111r of the input and output contact areas IOCR can be selectively etched using photolithography (see [reference]). Figure 13 The third stop hole 128 is formed by forming the third stop hole 128. Based on the formation of the third stop hole 128, the fourth insulating material layer 111r (see...) Figure 13 It can be the fourth insulating layer 111.

[0104] like Figure 15 As shown, a first deformation stop hole 124 can be formed by the channel region CHR (see...) Figure 14 A second burial layer 130 is formed on the exposed first burial pattern 122p1. The second burial layer 130 can be formed to bury the first deformation stop hole 124 on the first burial pattern 122p1 (see...). Figure 14 The second burial layer 130 may include a metal layer, such as a tungsten layer.

[0105] A third buried layer 132 and a fourth buried layer 134 may be formed to bury the second stop hole 126 and the third stop hole 128, respectively. The third buried layer 132 and the fourth buried layer 134 may include metal layers, such as tungsten layers.

[0106] refer to Figure 16 and Figure 17 A molded structure MOSC can be formed in the channel region CHR, the word line cutting region WLCR, and the input and output contact regions IOCR, such as Figure 16 As shown in the diagram. A molded structure MOSC can be formed on the third insulating layer 110 and the second buried layer 130 of the channel region CHR. A molded structure MOSC can be formed on the third insulating layer 110 and the third buried layer 132 of the word line cut region WLCR. A molded structure MOSC can be formed on the fourth buried layer 134 and the fourth insulating layer 111 of the input and output contact regions IOCR.

[0107] A molded structure MOC can be formed by repeatedly stacking a first interlayer insulating layer 136 and a first interlayer sacrificial layer 138. The first interlayer insulating layer 136 may include a silicon oxide layer. The first interlayer sacrificial layer 138 may include a silicon nitride layer that has etch selectivity relative to the first interlayer insulating layer 136.

[0108] like Figure 17 As shown, a channel via 140 can be formed in the channel region CHR. The second buried layer 130 can be selectively etched using a photolithography process (see [reference]). Figure 16 The first interlayer insulation layer 136 and the first interlayer sacrificial layer 138 above the second burial layer 130 (see above) Figure 16 The trench hole 140 is formed to expose the first burial pattern 122p1. The first deformation stop hole 124 (see [reference]) is also exposed by the formation of the trench hole 140. Figure 14 ).

[0109] Word line dicing holes 146 can be formed in the word line dicing region WLCR. The first interlayer insulating layer 136, the first interlayer sacrificial layer 138, and the third buried layer 132 can be selectively etched using photolithography (see [link to photolithography]). Figure 16 To form the word line cutting hole 146. When forming the word line cutting hole 146, the third buried layer 132 can be sufficiently etched (see...). Figure 16 Therefore, the lower width of the letter line cutting hole 146 can be increased.

[0110] Input and output contact holes 148 can be formed in the input and output contact area 10CR. The input and output contact holes 148 can be formed by selectively etching the first interlayer insulating layer 136 and the first interlayer sacrificial layer 138 above the fourth buried layer 134 using a photolithography process. The fourth buried layer 134 can be exposed depending on the formation of the input and output contact holes 148.

[0111] In addition, the first horizontal hole 144 and the second horizontal hole 142 can be formed by etching the first interlayer sacrificial layer 138 and the first sacrificial pattern 108p of the channel region CHR and the word line cut region WLCR in the horizontal direction.

[0112] The first horizontal via 144 can be connected via the channel via 140 and the word line cut-through via 146. The first horizontal vias 144 can be vertically spaced apart from each other via the first interlayer insulating layer 136. The first horizontal via 144 may not be formed in the input and output contact regions 10CR. The second horizontal via 142 can expose the side surface of the first gate dielectric material layer 118. The second horizontal via 142 can be connected via the word line cut-through via 146.

[0113] refer to Figure 18 and Figure 19 The channel hole 140 of the CHR in the channel area (see...) Figure 17 ) and the first deformation stop hole 124 ( Figure 14 The vertical channel structure CHS is formed in the ) such as Figure 18 As shown in the diagram. The vertical channel structure CHS may include sequentially formed in the channel aperture 140 (see Figure 140). Figure 17 ) and the first deformation stop hole 124 (see Figure 14 The data storage layer dsl, vertical channel layer 158 and buried insulation layer 160 are located on the inner wall of the )

[0114] Data storage layer DSL can be located in channel hole 140 (see Figure 17 ) and the first deformation stop hole 124 (see Figure 14 The inner wall of the device sequentially includes a tunnel insulating layer 152, a charge storage layer 154, and a barrier insulating layer 156. The tunnel insulating layer 152 may include a silicon oxide layer. The charge storage layer 154 may include a silicon nitride layer. The barrier insulating layer 156 may include a silicon oxide layer.

[0115] The vertical trench layer 158 may include a polycrystalline silicon layer or a monocrystalline silicon layer. The buried insulating layer 160 may bury the trench via 140 on the vertical trench layer 158 (see [link]). Figure 17 ) and the first deformation stop hole 124 (see Figure 14The buried insulating layer 160 may include a silicon oxide layer. The buried insulating layer 166 may be formed in the word line cut hole 146 of the word line cut region WLCR. The buried insulating layer 166 may include a silicon oxide layer.

[0116] The first horizontal hole 144 can be used in the channel region CHR and the word line cutting region WLCR (see...) Figure 17 A metal layer (e.g., a tungsten layer) is buried in the metal to form the first gate line 164. The first gate line 164 can be used as a word line.

[0117] The second horizontal hole 142 can be used in the channel region CHR and the word line cutting region WLCR (see...) Figure 17 The second gate line 162 is formed by burying a metal layer (e.g., a tungsten layer) in the fourth buried layer 134. The second gate line 162 can be used as a ground select line. The input and output contact structure 168 that contacts the fourth buried layer 134 can be formed by burying a metal layer (e.g., a tungsten layer) in the input and output contact holes 148 of the input and output contact region 10CR.

[0118] In addition, it can be executed in Figure 18 The process of forming bit lines, bit line pads, plugs connected to the first gate line 164 (word line), word line pads, etc. on the second gate line 162.

[0119] like Figure 19 As shown, Figure 18 The structure is flipped. By doing so, the substrate 100 can be positioned on top, and the first semiconductor line 104, the second gate line 162, and the first gate line 164 can be positioned below the substrate 100. Furthermore, the vertical channel structure CHS can be arranged below the substrate 100.

[0120] According to some implementation methods, in flipping Figure 18 Prior to the structure, a process can be added to bond the pads (i.e., bit line pads or word line pads) provided below the first gate line 164 to the pads of the peripheral circuit structure.

[0121] refer to Figure 20 and Figure 21 , can be like Figure 20 The substrate 100 shown is removed (see Figure 19 Next, the upper portions of the first gate dielectric material layer 118, the second gate dielectric material layer 120, and the first buried pattern 122p1 can be removed. The first gate dielectric material layer 118, the second gate dielectric material layer 120, and the first buried pattern 122p1 formed above the first stop hole 114 formed in the channel region CHR can be removed.

[0122] In doing so, the first gate dielectric material layer 118 and the second gate dielectric material layer 120 can be respectively a first gate dielectric material layer 118p1 and a second gate dielectric material layer 120p1, with their upper portions exposed. The first buried pattern 122p1 can be a second buried pattern 122p2, with its upper portion exposed.

[0123] like Figure 21 As shown, a second buried pattern 122p2 can be etched into the first stop hole 114 using an etching process. By doing so, a channel exposure hole 170 can be formed, exposing the upper surface of the vertical channel structure CHS within the first deformable stop hole 124. The channel exposure hole 170 can expose the tunnel insulation layer included in the vertical channel structure CHS.

[0124] refer to Figure 22 and Figure 23 ,like Figure 22 As shown, a first gate dielectric material layer 118p1 can be etched into the first stop hole 114 at the upper portion of the vertical channel structure CHS (see Figure 118p1). Figure 21 ) and the second gate dielectric material layer 120p1 (see Figure 21 ).

[0125] By doing so, the first gate dielectric material layer 118p1 (see...) Figure 21 ) and the second gate dielectric material layer 120p1 (see Figure 21 The first gate dielectric pattern 118p2 buried in the recessed via 116 and the second gate dielectric pattern 120p2 formed on the first gate dielectric pattern 118p2 in the recessed via 116 can be referred to as gate dielectric layers 118p2 and 120p2, respectively. Gate dielectric layers 118p2 and 120p2 can be ground-selective transistors (GSTs) (see [link to relevant documentation]). Figure 2B The gate dielectric layer.

[0126] Furthermore, the first gate dielectric material layer 118p1 and the second gate dielectric material layer 120p1 can be the third gate dielectric pattern 118p3 and the fourth gate dielectric pattern 120p3 respectively arranged on both sides of the vertical channel structure CHS in the first deformation stop hole 124.

[0127] like Figure 23As shown, the upper surface of the vertical channel structure CHS exposed by the channel exposure hole 170 in the first deformation stop hole 124 can be etched. Therefore, the vertical channel structure CHS may include a data storage pattern dsp, a vertical channel pattern 158p, and a buried insulation pattern 160p sequentially formed on the inner walls of the channel hole 140 and the first deformation stop hole 124.

[0128] The data storage pattern DSP may sequentially include a tunnel insulating pattern 152p, a charge storage pattern 154p, and a barrier insulating pattern 156p on the inner walls of the channel via 140 and the first deformation stop via 124. The vertical channel pattern 158p included in the vertical channel structure CHS may be exposed through the channel exposure via 170. The channel exposure via 170 may expose the vertical channel pattern 158p by passing through the first semiconductor line 104 and the second gate line 162.

[0129] refer to Figure 24 and Figure 25 ,like Figure 24 As shown, a semiconductor contact plug 172 can be formed on the vertical channel structure CHS and buried in the channel exposure via 170. The semiconductor contact plug 172 can be formed as a burial in the channel exposure via 170 passing through the first semiconductor line 104 and the second gate line 162 (see [reference]). Figure 23 )middle.

[0130] Furthermore, a second semiconductor line 174 extending horizontally on the semiconductor contact plug 172 and the first insulating layer 102 can be formed. The second semiconductor line 174 can be formed in the channel region CHR by forming a semiconductor material layer on the first insulating layer 102, including the channel region CHR, the word line cut region WLCR, and the input and output contact regions IOCR, and then patterning the semiconductor material layer using a photolithography process. The semiconductor contact plug 172 and the second semiconductor line 174 may comprise an undoped polysilicon layer.

[0131] like Figure 25 As shown, the semiconductor contact plug 172 and the second semiconductor line 174 can be annealed by implanting an impurity of a second conductivity type (e.g., boron) (which is a P-type impurity). By doing so, the semiconductor contact plug 172 and the second semiconductor line 174 can be a semiconductor contact plug 172i of the second conductivity type (i.e., P-type) and a second semiconductor line 174i of the second conductivity type (i.e., P-type), respectively.

[0132] refer to Figure 26 and Figure 27 A second interlayer insulating layer 175p can be formed on the first insulating layer 102 and the second semiconductor line 174i of the second conductivity type, such as Figure 26As shown in the diagram, a second contact hole 176 exposing a second semiconductor line 174i of the second conductivity type can be formed in a second interlayer insulating layer 175p. Next, a second ohmic contact region 178 of the second conductivity type (i.e., P-type) can be formed in the second contact hole 176. The second ohmic contact region 178 can be formed by implanting a second conductivity type (i.e., P-type) impurity into the second semiconductor line 174i of the second conductivity type in the second contact hole 176.

[0133] like Figure 27 As shown, a first contact hole 180 exposing the first semiconductor line 104 can be formed in the first insulating layer 102 and the second interlayer insulating layer 175p on the first semiconductor line 104 of the first conductivity type disposed on the word line cut region WLCR.

[0134] Next, a first ohmic contact region 182 of a first conductivity type (i.e., N-type) can be formed in the first contact hole 180. The first ohmic contact region 182 can be formed by implanting an impurity of the first conductivity type (i.e., N-type) into the first semiconductor line 104 of the first conductivity type in the first contact hole 180.

[0135] refer to Figure 28 A third contact hole 184 can be formed in the fourth insulating layer 111 and in the second interlayer insulating layer 175p on the fourth buried layer 134 of the input and output contact areas IOCR. Furthermore, as... Figure 4 As shown, a first metal contact plug 188 connected to the first semiconductor line 104 may be formed in the first contact hole 180. The first metal contact plug 188 can be connected to the first semiconductor line 104 through a first ohmic contact region 182.

[0136] A second metal contact plug 186, which is connected to the second semiconductor line 174i, can be formed in the second contact hole 176. The second metal contact plug 186 can be connected to the second semiconductor line 174i through the second ohmic contact area 178.

[0137] Input and output contact plugs 190 connected to the fourth buried layer 134 can be formed in the third contact hole 184. The first metal contact plug 188, the second metal contact plug 186, and the input and output contact plug 190 can be formed using the same process. The first metal contact plug 188, the second metal contact plug 186, and the input and output contact plug 190 may include a metal layer, such as a tungsten layer. Figure 4 and Figure 5 The vertical non-volatile memory device 10 can be manufactured using the manufacturing process described above.

[0138] Figures 29 to 32This is a cross-sectional view used to describe a method for manufacturing a vertical non-volatile memory device according to an embodiment.

[0139] In detail, Figures 29 to 32 It is used to describe manufacturing Figure 6 and Figure 7 A cross-sectional view of a method for a vertical non-volatile memory device 10-1. Figures 29 to 32 In, with Figure 6 and Figure 7 The same or substantially the same figure references in the figures indicate the same as those in the figures below. Figure 6 and Figure 7 Components that are the same or substantially the same. Figures 29 to 32 In the text, a brief description or no description is provided for reference. Figure 6 and Figure 7 The aspects described.

[0140] First, it can be executed Figures 8 to 23 The manufacturing process allows for the formation of a channel exposure via 170 in the upper surface of the vertical channel structure CHS. The channel exposure via 170 exposes the vertical channel pattern 158p by passing through the first semiconductor line 104 and the second gate line 162.

[0141] refer to Figure 29 and Figure 30 ,like Figure 29 As shown, a semiconductor contact plug 172 can be formed on the vertical channel structure CHS and buried in the channel exposure via 170. The semiconductor contact plug 172 can be formed to be buried in the channel exposure via 170 passing through the first semiconductor line 104 and the second gate line 162. The semiconductor contact plug 172 may include an undoped polysilicon layer.

[0142] According to some embodiments, the semiconductor contact plug 172 can be manufactured by a series of processes described below. That is, after forming a semiconductor material layer (e.g., a polysilicon layer) on the first insulating layer 102 to bury the channel exposure via 170, a semiconductor material pattern can be formed only in the channel region CHR using a photolithography process. Furthermore, the semiconductor material pattern can be chemically and mechanically polished with the first insulating layer 102 as an etch stop layer to form the semiconductor contact plug 172 only in the channel exposure via 170.

[0143] like Figure 30As shown, a third interlayer insulating layer 194 can be formed over the plug exposure hole 192 of the semiconductor contact plug 172 having an exposed channel region CHR. By etching the interlayer insulating material layer using a photolithography process after forming the interlayer insulating material layer on the semiconductor contact plug 172 and the first insulating layer 102, the third interlayer insulating layer 194 can be formed only in the input and output contact regions IOCR and the word line cut region WLCR.

[0144] refer to Figure 31 and Figure 32 , can be like Figure 31 The formation shown is achieved by burying the plug exposure hole 192 (see...) Figure 30 The metal line 196 is connected to the semiconductor contact plug 172. The metal line 196 may be formed to extend in a horizontal direction. The metal line 196 may include a metal layer, such as a tungsten layer. The plug exposure hole 192 can be buried by forming a metal material layer on the third interlayer insulating layer 194 (see [link]). Figure 30 Then, the metal material layer is chemically and mechanically polished to form metal lines 196.

[0145] like Figure 32 As shown, a fourth contact hole 198 exposing the first semiconductor line 104 can be formed in the third interlayer insulating layer 194 and the first insulating layer 102 on the first semiconductor line 104 of the word line cut region WLCR. Then, a third ohmic contact region 202 of the first conductivity type (i.e., N-type) can be formed in the fourth contact hole 198.

[0146] The third ohmic contact region 202 can be formed by implanting a first conductivity type (i.e., N-type) impurity into the first semiconductor line 104 of the first conductivity type in the fourth contact hole 198. The fifth contact hole 200 can be formed on the fourth buried layer 134 of the input and output contact regions 10CR, in the fourth insulating layer 111, and in the third interlayer insulating layer 194p.

[0147] In addition, such as Figure 6 As shown, a third metal contact plug 204 connected to the first semiconductor line 104 can be formed in the fourth contact hole 198. The third metal contact plug 204 can be connected to the first semiconductor line 104 through a third ohmic contact region 202.

[0148] A fourth metal contact plug 206, connected to the fourth buried layer 134, can be formed in the fifth contact hole 200. The third metal contact plug 204 and the fourth metal contact plug 206 can be formed using the same process. The third metal contact plug 204 and the fourth metal contact plug 206 may include a metal layer, such as a tungsten layer. Using the above-described manufacturing process, it is possible to manufacture... Figure 6 and Figure 7Vertical non-volatile memory device 10-1.

[0149] One or more of the elements disclosed above may include processing circuitry (such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof) or implemented in processing circuitry. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0150] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0151] This application is based on and claims priority to Korean Patent Application No. 10-2024-0124243, filed on September 11, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A vertical non-volatile memory device, comprising: Multiple vertical channel structures extend vertically and are separated from each other horizontally; A plurality of first gate lines extend in the horizontal direction and surround the plurality of vertical channel structures, the plurality of first gate lines being separated from each other in the vertical direction, the plurality of first gate lines being configured as word lines; A second gate line extends along the horizontal direction on the plurality of first gate lines, and the second gate line is configured as a ground selection line; A first semiconductor line of a first conductivity type extends along the horizontal direction on the second gate line; A plurality of semiconductor contact plugs of a second conductivity type are connected to the plurality of vertical channel structures via passing through the first semiconductor line and the second gate line; A second semiconductor line of a second conductivity type extends along the horizontal direction and connects to the plurality of semiconductor contact plugs; A first metal contact plug is connected to the first semiconductor line; as well as The second metal contact plug is connected to the second semiconductor line.

2. The vertical non-volatile memory device according to claim 1, wherein... The first semiconductor line includes an N-type polysilicon layer, and The plurality of semiconductor contact plugs and the second semiconductor line include a P-type polycrystalline silicon layer.

3. The vertical non-volatile memory device according to claim 1, wherein... The stacked structure including the plurality of first gate lines and second gate lines defines a word line cut-out region and a channel region defined by the word line cut-out region. The plurality of vertical channel structures, the first gate line, and the second gate line are located in the channel region.

4. The vertical non-volatile memory device of claim 3, wherein the first semiconductor line extends in the horizontal direction to the word line cutting region.

5. The vertical non-volatile memory device of claim 3, wherein the second semiconductor line is in the channel region.

6. The vertical non-volatile memory device according to claim 1, further comprising: The gate dielectric layer of the ground selection transistor between the plurality of semiconductor contact plugs and the second gate line, wherein The gate dielectric layer of the ground selection transistor is located in a recessed aperture defined by the space between the sidewalls of the plurality of semiconductor contact plugs and the second gate line. The recessed hole is recessed toward the sidewall of the plurality of semiconductor contact plugs and between the plurality of semiconductor contact plugs and the second gate line.

7. The vertical non-volatile memory device of claim 6, wherein the gate dielectric layer comprises a first gate dielectric pattern on the inner wall of the recessed via and a second gate dielectric pattern on the first gate dielectric pattern in the recessed via.

8. The vertical non-volatile memory device of claim 7, wherein the second gate line and the gate dielectric layer are separated from the plurality of vertical channel structures in the vertical direction.

9. The vertical non-volatile memory device according to claim 1, wherein... The plurality of vertical channel structures include a data storage pattern, a vertical channel pattern, and a buried insulation pattern, wherein the data storage pattern, the vertical channel pattern, and the buried insulation pattern are sequentially formed on the inner wall of a channel hole that passes through the plurality of first gate lines along the vertical direction.

10. The vertical non-volatile memory device according to claim 1, wherein... The first semiconductor line further includes a first ohmic contact region of a first conductivity type, and The first metal contact plug is located in the first ohmic contact area.

11. The vertical non-volatile memory device according to claim 1, wherein... The second semiconductor line also includes a second ohmic contact region of a second conductivity type, and The second metal contact plug is disposed in the second ohmic contact area.

12. A vertical non-volatile memory device, comprising: Multiple vertical channel structures extend vertically and are separated from each other horizontally; A plurality of first gate lines extend in the horizontal direction while surrounding the plurality of vertical channel structures, the plurality of first gate lines are separated from each other in the vertical direction, and the plurality of first gate lines are configured as word lines; A second gate line extends along the horizontal direction on the plurality of first gate lines, and the second gate line is configured as a ground selection line; A first semiconductor line of a first conductivity type extends along the horizontal direction on the second gate line; Multiple semiconductor contact plugs are connected to the multiple vertical channel structures through the first semiconductor line and the second gate line, and the multiple semiconductor contact plugs are free of impurities; A first metal contact plug is connected to the first semiconductor line; as well as Metal wires extend along the horizontal direction on the plurality of semiconductor contact plugs and are connected to the plurality of semiconductor contact plugs.

13. The vertical non-volatile memory device according to claim 12, wherein... The first semiconductor line includes an N-type polysilicon layer, and The plurality of semiconductor contact plugs include a polycrystalline silicon layer that is not doped with impurities.

14. The vertical non-volatile memory device according to claim 12, wherein... The stacked structure including the plurality of first gate lines and second gate lines defines a word line cut-out region and a channel region defined by the word line cut-out region. The plurality of vertical channel structures, the plurality of first gate lines, and the second gate lines are located in the channel region, and The first semiconductor line extends in the horizontal direction and in the word line cutting region.

15. The vertical non-volatile memory device according to claim 12, further comprising: The gate dielectric layer of the ground selection transistor between the plurality of semiconductor contact plugs and the second gate line. The gate dielectric layer of the ground selection transistor is located in a recessed aperture defined by the space between the sidewalls of the plurality of semiconductor contact plugs and the second gate line. The recessed hole is recessed toward the sidewalls of the plurality of semiconductor contact plugs and between the plurality of semiconductor contact plugs and the second gate line. The gate dielectric layer includes a first gate dielectric pattern on the inner wall of the recessed hole and a second gate dielectric pattern on the first gate dielectric pattern in the recessed hole.

16. The vertical non-volatile memory device of claim 12, wherein the plurality of vertical channel structures include a data storage pattern, a vertical channel pattern, and a buried insulating pattern, the data storage pattern, the vertical channel pattern, and the buried insulating pattern being sequentially formed on the inner wall of a channel via passing through the plurality of first gate lines along the vertical direction.

17. The vertical non-volatile memory device of claim 12, wherein... The first semiconductor line includes a first ohmic contact region of a first conductivity type, and The first metal contact plug is located in the first ohmic contact area.

18. A vertical non-volatile memory device, comprising: Multiple vertical channel structures extend vertically and are spaced apart from each other horizontally; A plurality of first gate lines extend in the horizontal direction while surrounding the plurality of vertical channel structures, the plurality of first gate lines are separated from each other in the vertical direction, and the plurality of first gate lines are configured as word lines; A second gate line extends along the horizontal direction on the plurality of first gate lines, and the second gate line is spaced apart from the plurality of vertical channel structures in the vertical direction and is configured as a ground selection line. A first semiconductor line of a first conductivity type extends along the horizontal direction on the second gate line, and the first semiconductor line includes a first ohmic contact region. A plurality of semiconductor contact plugs of a second conductivity type are connected to the plurality of vertical channel structures via passing through the first semiconductor line and the second gate line; The gate dielectric layer of the ground selection transistor has a recessed hole in which the sidewalls of the plurality of semiconductor contact plugs are recessed, the recessed hole being defined by the space between the sidewalls of the plurality of semiconductor contact plugs and the second gate line. A second semiconductor line of a second conductivity type extends horizontally over the plurality of semiconductor contact plugs and is separated from the first semiconductor line in the vertical direction. The second semiconductor line is connected to the plurality of semiconductor contact plugs and includes a second ohmic contact region. The first metal contact plug is connected to the first semiconductor line through the first ohmic contact area; as well as The second metal contact plug is connected to the second semiconductor line through the second ohmic contact area.

19. The vertical non-volatile memory device of claim 18, wherein... The first semiconductor line includes an N-type polysilicon layer, and The plurality of semiconductor contact plugs and the second semiconductor line include a P-type polycrystalline silicon layer.

20. The vertical non-volatile memory device of claim 18, wherein the gate dielectric layer comprises a first gate dielectric pattern on the inner wall of the recessed via and a second gate dielectric pattern on the first gate dielectric pattern in the recessed via.

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