Vertical double-diffused metal-oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a vertical double-diffused metal-oxide semiconductor field effect transistor and a preparation method, and relates to the technical field of semiconductors. According to the preparation method, a gate oxide layer, a gate electrode and a first dielectric layer are sequentially formed on one side of an epitaxial layer, and oxygen can penetrate through the first dielectric layer to react with silicon in the epitaxial layer to generate silicon dioxide (namely a first compact oxide layer) under the oxygen condition by utilizing the fact that the first dielectric layer has relatively high density (loose structure); the first compact oxide layer is filled in the gap between the gate edge and the gate oxide layer, so that the thickness of the gate oxide layer at the gate edge is increased, and the reliability of the gate oxide layer at the gate edge is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] In the field of power semiconductors, vertically conductive metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using a vertical double-diffused process are called vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS). VDMOS is widely used in power electronics due to its advantages such as fast switching speed, high input impedance, good frequency characteristics, and good thermal stability.

[0003] In related technologies, the gate layer needs to be etched during gate formation. During the etching process, ions incident on the gate sidewalls reflect off the gate oxide layer around the sidewalls, causing excessive erosion of the gate oxide layer below the gate edge, resulting in localized porosity. Various micro-contaminants easily accumulate at this location, leading to a decrease in the reliability of the gate oxide layer. Summary of the Invention

[0004] This application provides a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. By utilizing the porous properties of the first dielectric layer, oxygen atoms pass through the first dielectric layer and react with silicon atoms to form a first dense oxide layer. The first dense oxide layer fills the pores between the gate edge and the gate oxide layer, increasing the thickness of the gate oxide layer at the gate edge, thereby improving the reliability of the gate oxide layer at the gate edge.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, comprising: A gate oxide layer is formed on one side of the epitaxial layer; The gate is formed on the side of the gate oxide layer away from the epitaxial layer; A first dielectric layer is formed on the side of the gate away from the gate oxide layer. The first dielectric layer covers the side surface of the gate away from the gate oxide layer, the side surface of the gate, and the unoccupied surface of the epitaxial layer. The density of the first dielectric layer is less than or equal to a preset density. Under oxygen-containing conditions, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer, and the density of the first dense oxide layer is greater than the density of the first dielectric layer. The first dielectric layer is densified.

[0006] According to any of the foregoing embodiments of the first aspect of this application, a first dielectric layer is formed on the side of the gate away from the gate oxide layer, including: Using tetraethoxysilane as a precursor, a first dielectric layer is formed on the side of the gate away from the gate oxide layer by chemical vapor deposition.

[0007] According to any of the foregoing embodiments of the first aspect of this application, under oxygen-containing conditions, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer, including: Under preset environmental conditions and a preset temperature, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer. The preset environmental conditions include dry oxygen or wet oxygen conditions, and the preset temperature ranges from 750°C to 1200°C.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the preparation method further includes, before densifying the first dielectric layer: Under oxygen-containing conditions, a second dense oxide layer is formed on the side of the first dielectric layer near the gate. The second dense oxide layer encapsulates the gate, and the density of the second dense oxide layer is greater than the density of the first dielectric layer.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the gate includes a composite gate, which includes a polysilicon gate layer and a metal gate layer. Accordingly, the gate is formed on the side of the gate oxide layer away from the epitaxial layer, including: A polysilicon gate layer is formed on the side of the gate oxide layer away from the epitaxial layer; A metal gate layer is formed on the side of the polysilicon gate layer away from the gate oxide layer.

[0010] According to any of the foregoing embodiments of the first aspect of this application, after densifying the first dielectric layer, the preparation method further includes: A second dielectric layer is formed on the side of the first dielectric layer opposite to the gate.

[0011] According to any of the foregoing embodiments of the first aspect of this application, a gate oxide layer is formed on one side of the epitaxial layer, including: A field oxide layer is formed on one side of the epitaxial layer; Remove the field oxide layer located in the active region; A gate oxide layer is formed in the active region.

[0012] According to any of the foregoing embodiments of the first aspect of this application, before forming a gate oxide layer on one side of the epitaxial layer, the preparation method includes: A trap region is formed within the epitaxial layer; The source region is formed within the well region, and the conductivity type of the well region is different from that of the source region.

[0013] Secondly, embodiments of this application also provide a vertically double-diffused metal-oxide-semiconductor field-effect transistor, comprising: Epitaxial layer; The gate oxide layer is located on one side of the epitaxial layer; The gate is located on the side of the gate oxide layer away from the epitaxial layer; The first dielectric layer after densification is located on the side of the gate away from the gate oxide layer. The first dielectric layer covers the side surface of the gate away from the gate oxide layer, the side surface of the gate, and the surface of the epitaxial layer that is not occupied. The density of the first dielectric layer before densification is less than or equal to a preset density. The first dense oxide layer fills the pores between the edge of the gate and the gate oxide layer, and the density of the first dense oxide layer is greater than the density of the first dielectric layer.

[0014] According to any of the foregoing embodiments of the second aspect of this application, the vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes: The second dense oxide layer is located on the side of the first dielectric layer near the gate. The second dense oxide layer encapsulates the gate, and the density of the second dense oxide layer is greater than the density of the first dielectric layer.

[0015] The vertical double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method provided in this application embodiment are fabricated by sequentially forming a gate oxide layer, a gate, and a first dielectric layer on one side of an epitaxial layer. Taking advantage of the low density (loose structure) of the first dielectric layer, under oxygen-containing conditions, oxygen can penetrate the first dielectric layer and react with silicon in the epitaxial layer to generate silicon dioxide (i.e., the first dense oxide layer). The first dense oxide layer fills the pores between the gate edge and the gate oxide layer, increasing the thickness of the gate oxide layer at the gate edge, thereby improving the reliability of the gate oxide layer at the gate edge. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the pore between the gate edge and the gate oxide layer provided in the embodiments of this application; Figure 2 This is a schematic flowchart of a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to an embodiment of this application; Figures 3-14 This is a schematic diagram of the structure corresponding to each step of the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application; Figure 15 This is a schematic diagram illustrating the principle of preparing the first dense oxide layer provided in the embodiments of this application. Detailed Implementation

[0018] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0019] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0020] In related technologies, such as Figure 1 As shown, during the etching of gate 103, the gate oxide layer 102 below the edge of gate 103 is excessively etched, forming localized pores. These pores easily accumulate various micro-contaminants, causing a decrease in the reliability of the gate oxide layer. The reliability of the gate oxide layer plays a crucial role in the key parameters and long-term reliability of the device. Related technologies use ultrapure hydrogen fluoride (HF) to remove contaminants to improve the breakdown performance of the gate oxide layer, but the pore structure still exists, and the etched corners of the gate are prone to stress concentration, making them weak points in reliability.

[0021] Based on this, the present invention aims to improve the reliability of the gate oxide layer at the gate edge.

[0022] This application provides a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. The fabrication method involves sequentially forming a gate oxide layer, a gate, and a first dielectric layer on one side of an epitaxial layer. Taking advantage of the low density (loose structure) of the first dielectric layer, oxygen can penetrate the first dielectric layer and react with silicon in the epitaxial layer under oxygen-containing conditions to generate silicon dioxide (i.e., the first dense oxide layer). The first dense oxide layer fills the pores between the gate edge and the gate oxide layer, increasing the thickness of the gate oxide layer at the gate edge, thereby improving the reliability of the gate oxide layer at the gate edge.

[0023] The fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application will be described first below.

[0024] Figure 2 This is a schematic flowchart illustrating a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to an embodiment of this application. (Refer to...) Figure 2 The preparation method may include the following steps: S110~S150.

[0025] S110, A gate oxide layer is formed on one side of the epitaxial layer.

[0026] Combination Figure 6 A gate oxide layer is formed on one side of the epitaxial layer 101. The gate oxide layer 102 may include a silicon dioxide layer, or a high dielectric constant material layer known to those skilled in the art, such as a zirconium oxide layer or a silicon nitride layer. This application does not limit the fabrication process of the gate oxide layer 102; all fabrication processes known to those skilled in the art can be used, such as thermal growth processes. The thickness of the gate oxide layer 102 ranges from 200 angstroms to 2000 angstroms.

[0027] Epitaxial layer 101 may include a silicon epitaxial layer.

[0028] In one embodiment, S110 may include the following steps: forming a field oxide layer on one side of the epitaxial layer; removing the field oxide layer located in the active region; and forming a gate oxide layer in the active region.

[0029] In this embodiment, the field oxide layer and the gate oxide layer 102 can be fabricated using the same material, such as silicon dioxide layers, but they differ in fabrication process, function, distribution location, and thickness. The field oxide layer is located in the non-active region of the transistor. Since the electric field strength at the chip terminal surface is much higher than that in the bulk, field oxide is typically used at the terminal to avoid problems such as electric field concentration. The gate oxide layer 102 is located in the active region of the transistor, between the gate 103 and the epitaxial layer 101, controlling the formation of the conductive channel. Typically, the thickness of the field oxide layer is much greater than the thickness of the gate oxide layer 102.

[0030] For example, such as Figure 5As shown, a field oxide layer 113 is formed on the side of the epitaxial layer 101 away from the substrate 111 using a deposition process, and the field oxide layer 113 is then densified. Figure 6 As shown, the field oxide layer 113 is selectively and anisotropically etched to remove the field oxide layer 113 in the active region; then, a gate oxide layer 102 is formed in the active region using a thermal growth process. The thickness of the field oxide layer 113 is greater than the thickness of the gate oxide layer 102.

[0031] Compared with the simultaneous fabrication process, the stepwise fabrication of the field oxide layer 113 and the gate oxide layer 102 in this embodiment can simultaneously meet the differentiated performance requirements of the two, which can not only ensure the core performance of the transistor, but also avoid the problem of electric field concentration at the terminal, and at the same time help to reduce costs.

[0032] S120, A gate is formed on the side of the gate oxide layer away from the epitaxial layer.

[0033] The embodiments of this application do not limit the type of gate, and all types of gates known to those skilled in the art can be used, such as polysilicon gates. The gate can also be in the form of a single gate or a composite gate.

[0034] The embodiments of this application do not limit the fabrication process of the gate; all fabrication processes known to those skilled in the art can be used, such as deposition processes. In other embodiments, ion implantation can also be performed on the gate.

[0035] Combination Figure 7 A gate layer is formed on the side of the gate oxide layer 102 away from the epitaxial layer, and the gate layer completely covers the gate oxide layer 102. Figure 8 The gate layer is etched to form a patterned gate 103. The etching process may include wet etching or dry etching.

[0036] S130. A first dielectric layer is formed on the side of the gate away from the gate oxide layer. The first dielectric layer covers the side surface of the gate away from the gate oxide layer, the side surface of the gate, and the surface of the epitaxial layer that is not occupied.

[0037] Combination Figure 9 The density of the first dielectric layer 104 is less than or equal to a preset density. The first dielectric layer 104 has a low density and is a loose structure that allows gas (e.g., oxygen) to pass through, so that in subsequent steps, oxygen can pass through the first dielectric layer 104 and react with the silicon of the epitaxial layer 101 to form a first dense oxide layer.

[0038] In one embodiment, S130 may include the following steps: using tetraethoxysilane (Si(OC2H5)4, TetraethylOrthosilicate, TEOS) as a precursor, a first dielectric layer is formed on the side of the gate away from the gate oxide layer using a chemical vapor deposition process.

[0039] The chemical vapor deposition process employs low-pressure chemical vapor deposition (LPCVD).

[0040] In this step, gaseous TEOS undergoes thermal decomposition under low pressure and high temperature conditions, forming a loose silicon dioxide layer, namely the first dielectric layer 104, on the side of the gate 103 away from the gate oxide layer 102. The first dielectric layer 104, prepared using LPCVD, contains numerous micropores, dangling bonds (Si-H, Si-OH), and a weak silicon-oxygen bond network, with a low density of approximately 2.1 g / cm³. 3~ 2.15g / cm 3 .

[0041] S140. Under oxygen-containing conditions, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer.

[0042] The density of the first dense oxide layer is greater than that of the first dielectric layer 104. The density of the first dense oxide layer is approximately 2.20 g / cm³. 3 ~2.27g / cm 3 .

[0043] In this step, under aerobic conditions, oxygen can penetrate the first dielectric layer 104 and react with silicon at the silicon oxide-silicon (SiO2-Si) interface to generate silicon dioxide, i.e., the first dense oxide layer. Combined with... Figure 15 Oxygen reacts with silicon in the epitaxial layer 101 to generate silicon dioxide (i.e., the first dense oxide layer). The silicon dioxide lattice expands, so that the generated first dense oxide layer can fill the pores between the edge of the gate 103 and the gate oxide layer 102, which is equivalent to increasing the thickness of the gate oxide layer 102 at that point, which is beneficial to improving the reliability of the gate oxide layer 102.

[0044] Compared with the first dielectric layer 104, the gate oxide layer 102 has a larger density and a more compact structure, which is beneficial for reducing leakage current, increasing breakdown voltage, improving transistor reliability and extending service life.

[0045] In one embodiment, S140 may include the following step: forming a first dense oxide layer in the pores between the edge of the gate and the gate oxide layer under preset environmental conditions and a preset temperature.

[0046] The preset environmental conditions may include dry oxygen or wet oxygen conditions, and the preset temperature range is 750℃~1200℃.

[0047] The gas source under dry oxygen conditions is high-purity oxygen, with no water vapor. The first dense oxide layer formed under dry oxygen conditions has a high density, approximately 2.25 g / cm³. 3 ~2.27g / cm 3 .

[0048] The gas source for humid oxygen conditions is a mixture of oxygen and water vapor, which can be formed by passing oxygen into deionized water. Water vapor accelerates the oxidation reaction, at a rate approximately 3 to 5 times that under dry oxygen conditions, but its density is lower, approximately 2.20 g / cm³. 3 ~2.25g / cm 3 .

[0049] S150. The first dielectric layer is densified.

[0050] Because the first dielectric layer 104 prepared by S130 has a low density and poor compactness, its overall structure is loose, containing a large number of pores, dangling bonds (Si-H and Si-OH), and a weak silicon-oxygen bond network. These characteristics result in relatively poor insulation, leakage resistance, and reliability of the first dielectric layer 104.

[0051] This step densifies the first dielectric layer 104, increasing its density and thus improving its insulation, leakage resistance, and reliability.

[0052] This application can employ any densification process known to those skilled in the art, such as annealing or plasma densification, and is not limited thereto. As an example, the transistor fabricated in S140 is placed in a nitrogen atmosphere (or a mixture of nitrogen and hydrogen) at a preset temperature of approximately 500°C for degradation treatment; at high temperature, the Si-O bonds in the first dielectric layer 104 rearrange, the pores are filled, and excess hydroxyl groups (-OH) are desorbed, resulting in an increase in the density and a decrease in the porosity of the first dielectric layer 104, thereby improving the insulation, leakage resistance, and reliability of the first dielectric layer 104.

[0053] The vertical double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method provided in this application embodiment are fabricated by sequentially forming a gate oxide layer 102, a gate 103, and a first dielectric layer 104 on one side of an epitaxial layer 101. Taking advantage of the low density (loose structure) of the first dielectric layer 104, under oxygen-containing conditions, oxygen can penetrate the first dielectric layer 104 and react with silicon in the epitaxial layer to generate silicon dioxide (i.e., a first dense oxide layer). The first dense oxide layer fills the pores between the edge of the gate 103 and the gate oxide layer 102, increasing the thickness of the gate oxide layer 102 at the edge of the gate 103, thereby improving the reliability of the gate oxide layer 102 at the edge of the gate 103.

[0054] In one embodiment, prior to S150, the preparation method may further include the following steps: under oxygen-containing conditions, forming a second dense oxide layer on the side of the first dielectric layer near the gate, the second dense oxide layer encapsulating the gate, the density of the second dense oxide layer being greater than the density of the first dielectric layer.

[0055] In this embodiment, the gate 103 may include a polycrystalline gate, fabricated from polycrystalline silicon material. Combined with... Figure 10 Under oxygen-rich conditions, oxygen can penetrate the first dielectric layer 104 and react with the silicon in the polygate to generate silicon dioxide. The generated silicon dioxide bonds together to form a second dense oxide layer 105, which covers the upper surface and sides of the polygate. Compared with the first dielectric layer 104, the second dense oxide layer 105 has a higher density, which can isolate the polygate from the source / drain regions, prevent short circuits, and protect the polygate from corrosion or contamination by impurities in subsequent processes.

[0056] As an example, the first dense oxide layer and the second dense oxide layer 105 can be prepared simultaneously. Under dry or wet oxygen conditions, the mixture is heated to a preset temperature, and oxygen reacts with the silicon in the epitaxial layer 101 to form the first dense oxide layer. Oxygen reacts with the silicon in the polycrystalline gate to form the second dense oxide layer.

[0057] In one embodiment, the gate includes a composite gate comprising a polysilicon gate layer and a metal gate layer. As an example, the composite gate comprises a polysilicon gate layer and a tungsten silicide (WSi2) gate layer.

[0058] Accordingly, S120 may include the following steps: forming a polysilicon gate layer on the side of the gate oxide layer away from the epitaxial layer; forming a metal gate layer on the side of the polysilicon gate layer away from the gate oxide layer.

[0059] In this embodiment, a polysilicon gate layer is first formed on the surface of the gate oxide layer 102 away from the epitaxial layer 101. Then, a metal gate layer is formed on the surface of the polysilicon gate layer away from the gate oxide layer 102. The polysilicon gate layer and the metal gate layer are patterned using either dry etching or wet etching to form a composite gate. The composite gate combines the complementary advantages of polysilicon and metal, balancing the process compatibility of polysilicon with the low resistivity of metal, while reducing the direct contact area between silicon and silicon dioxide, which is beneficial for improving transistor reliability.

[0060] In one embodiment, after S150, the fabrication method may further include the step of forming a second dielectric layer on the side of the first dielectric layer opposite to the gate.

[0061] Combination Figure 11A second dielectric layer 106 is formed on the side of the first dielectric layer 104 away from the gate 103. By superimposing the second dielectric layer 106 on the outside of the first dielectric layer 104, the insulation protection is strengthened and the reliability of the transistor is further improved.

[0062] As an example, the second dielectric layer 106 is prepared by deposition process using undoped silicate glass (USG) as raw material.

[0063] In one embodiment, prior to S110, the fabrication method may further include the following steps: forming a well region within the epitaxial layer; and forming a source region within the well region, wherein the conductivity type of the well region is different from that of the source region.

[0064] If the conductivity type of the well region is N-type, then the conductivity type of the source region is P-type; if the conductivity type of the well region is P-type, then the conductivity type of the source region is N-type.

[0065] As an example, such as Figure 4 As shown, an ion implantation-high temperature diffusion process can be used to first form a well region 107 in the epitaxial layer 101; then a source region 108 is formed in the well region 107. The two ion implantations are of different types, which makes the conductivity type of the well region different from that of the source region.

[0066] In this embodiment, to ensure the reliability of the gate oxide layer 102, a post-gate oxide process is adopted, that is, the well region 107 and the source region 108 are prepared first, and then the gate oxide layer 102 and the gate 103 are prepared. By adopting the post-gate oxide process, the gate oxide layer 102 does not undergo a high-temperature process, which reduces the silicon-silicon dioxide interface state density and ensures its reliability.

[0067] For example, the fabrication method of this vertically double-diffused metal-oxide-semiconductor field-effect transistor may include the following steps: Step a, an epitaxial layer 101 is formed on one side of the substrate 111, such as... Figure 3 As shown.

[0068] Step b: An oxide pad layer is formed on the side of the epitaxial layer 101 away from the substrate 111.

[0069] Step c, prepare a well region 107 and a source region 108 in the epitaxial layer 101, such as Figure 4 As shown.

[0070] Step d: Remove the oxide layer on the epitaxial layer using a wet etching process; such as Figure 5 As shown, a field oxide layer 113 is deposited on the side of the epitaxial layer 101 away from the substrate 111 using a deposition process, and the field oxide layer 113 is densified.

[0071] Step e involves selectively and anisotropically etching the field oxide layer 113 to remove the field oxide layer 113 in the active region; then, a gate oxide layer is formed on the side of the epitaxial layer 101 in the active region away from the substrate 111 using a thermal growth process, such as... Figure 6 As shown.

[0072] Step f involves forming an undoped polysilicon gate layer on the side of the gate oxide layer 102 away from the epitaxial layer 101 using a deposition process, followed by ion implantation, such as... Figure 7 As shown; then, dry etching is used to etch the polysilicon gate layer to form a patterned gate, as shown. Figure 8 As shown.

[0073] Step g, using LPCVD process, a first dielectric layer 104 is formed on the side of gate 103 away from gate oxide layer 102, such as... Figure 9 As shown.

[0074] Step h involves utilizing the porous nature of the first dielectric layer 104 to perform dry or wet oxidation, forming a first dense oxide layer and a second dense oxide layer 105, as shown below. Figure 10 As shown.

[0075] In this step, the first dense oxide layer fills the pores between the edge of the gate 103 and the gate oxide layer 102, and the second dense oxide layer 105 covers the surface of the gate 103.

[0076] Step i: The first dielectric layer 104 is densified.

[0077] Step j: Deposit a second dielectric layer 106 on the side of the first dielectric layer 104 away from the gate 103, as follows. Figure 11 As shown.

[0078] Step k involves selective wet etching of the first dielectric layer 104 and the second dielectric layer 106, such as... Figure 12 As shown.

[0079] Step 1: Deposit the source metal layer and selectively etch the source metal layer to form the source 109, as shown below. Figure 13 As shown.

[0080] Step m involves forming a passivation layer 110 on the side of the source 109 away from the second dielectric layer 106, and selectively etching the passivation layer 110, such as... Figure 14 As shown.

[0081] Step n: A drain metal layer is fabricated on the side of the substrate 111 away from the epitaxial layer 101 to form a drain 112, as shown below. Figure 14 As shown.

[0082] Based on the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the above embodiments, this application embodiment also provides a vertical double-diffused metal-oxide-semiconductor field-effect transistor, which is obtained based on any of the above-described fabrication methods of the vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0083] The vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application is described below.

[0084] like Figure 14 As shown, the vertical double-diffused metal-oxide-semiconductor field-effect transistor may include: an epitaxial layer 101, a gate oxide layer 102, a gate 103, a first dielectric layer 104, and a first dense oxide layer (not shown in the figure).

[0085] The epitaxial layer 101 includes a silicon epitaxial layer. A gate oxide layer is located on one side of the epitaxial layer, and a gate 103 is located on the side of the gate oxide layer 102 away from the epitaxial layer. A first dielectric layer 104, after densification, is located on the side of the gate away from the gate oxide layer, and the first dielectric layer 104 covers the surface of the gate 103 away from the gate oxide layer 102, the side surface of the gate 103, and the unoccupied surface of the epitaxial layer 101.

[0086] The density of the first dielectric layer 104 before densification is less than or equal to a preset density. The first dielectric layer 104 before densification has a low density and a loose structure, allowing gas (e.g., oxygen) to permeate. Oxygen can pass through the first dielectric layer 104 and react with the silicon of the epitaxial layer 101 to form a first dense oxide layer. The first dense oxide layer fills the pores between the edge of the gate 103 and the gate oxide layer 102, and the density of the first dense oxide layer is greater than the density of the first dielectric layer 104.

[0087] As an example, the density of the first dense oxide layer is approximately 2.20 g / cm³. 3 ~2.27g / cm 3 The density of the first dielectric layer 104 before densification is approximately 2.1 g / cm³. 3~ 2.15g / cm 3 .

[0088] The vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this application includes an epitaxial layer 101, a gate oxide layer 102, a gate 103, and a first dielectric layer 104 stacked sequentially. Before densification, the first dielectric layer 104 has a low density (its structure is loose). Under oxygen-containing conditions, oxygen can penetrate the first dielectric layer 104 and react with silicon in the epitaxial layer to generate silicon dioxide (i.e., the first dense oxide layer). The first dense oxide layer fills the pores between the edge of the gate 103 and the gate oxide layer 102, increasing the thickness of the gate oxide layer 102 at the edge of the gate 103, thereby improving the reliability of the gate oxide layer 102 at the edge of the gate 103.

[0089] In one embodiment, such as Figure 14 As shown, the vertical double-diffused metal-oxide semiconductor field-effect transistor further includes: a second dense oxide layer 105; the second dense oxide layer 105 is located on the side of the first dielectric layer 104 near the gate 103, the second dense oxide layer 105 surrounds the gate 103, and the density of the second dense oxide layer 105 is greater than the density of the first dielectric layer 104.

[0090] In this embodiment, the gate 103 may include a polygate. Under oxygen-containing conditions, oxygen can penetrate the first dielectric layer 104 and react with the silicon in the polygate to generate silicon dioxide. The generated silicon dioxide bonds together to form a second dense oxide layer 105, which covers the upper surface and sides of the polygate. Compared with the first dielectric layer 104, the second dense oxide layer 105 has a higher density, which can isolate the polygate from the source / drain regions, prevent short circuits, and protect the polygate from impurities or contamination in subsequent processes.

[0091] In some embodiments, such as Figure 14 As shown, the vertical double-diffused metal-oxide-semiconductor field-effect transistor further includes: a second dielectric layer 106, a well region 107, a source region 108, a source electrode 109, a passivation layer 110, a substrate 111, and a drain electrode 112.

[0092] The second dielectric layer 106 is located on the side of the first dielectric layer 104 away from the gate 103. The second dielectric layer 106 may include a silicon dioxide layer, and may also include a high dielectric constant material layer known to those skilled in the art, such as a zirconium oxide layer or a silicon nitride layer. As an example, the second dielectric layer 106 may include a USG dielectric layer.

[0093] The well region 107 is located on the side surface of the epitaxial layer 101 near the gate oxide layer 102 and is located within the epitaxial layer 101. The source region 108 is located within the well region 107. The conductivity type of the well region 107 is different from that of the source region 108.

[0094] The source 109 is located on the side of the second dielectric layer 106 away from the first dielectric layer 104, and is also electrically connected to the well region 107 and the source region 108.

[0095] The passivation layer 110 is located on the side of the source 109 away from the second dielectric layer 106.

[0096] Substrate 111 is located on the side of epitaxial layer 101 away from gate oxide layer 102. Substrate 111 is the growth basis for other film structures and may include all types of substrates known to those skilled in the art, such as silicon-based substrates or silicon carbide substrates, without limitation herein.

[0097] The drain 112 is located on the side of the substrate 111 away from the epitaxial layer 101.

[0098] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0099] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, The preparation method includes: A gate oxide layer is formed on one side of the epitaxial layer; A gate is formed on the side of the gate oxide layer away from the epitaxial layer; A first dielectric layer is formed on the side of the gate away from the gate oxide layer. The first dielectric layer covers the side surface of the gate away from the gate oxide layer, the side surface of the gate, and the unoccupied surface of the epitaxial layer. The density of the first dielectric layer is less than or equal to a preset density. Under oxygen-containing conditions, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer, and the density of the first dense oxide layer is greater than the density of the first dielectric layer. The first dielectric layer is densified.

2. The preparation method according to claim 1, characterized in that, The formation of a first dielectric layer on the side of the gate away from the gate oxide layer includes: Using tetraethoxysilane as a precursor, a first dielectric layer is formed on the side of the gate away from the gate oxide layer using a chemical vapor deposition process.

3. The preparation method according to claim 1, characterized in that, The process of forming a first dense oxide layer in the pores between the edge of the gate and the gate oxide layer under oxygen-containing conditions includes: Under preset environmental conditions and a preset temperature, a first dense oxide layer is formed in the pores between the edge of the gate and the gate oxide layer. The preset environmental conditions include dry oxygen or wet oxygen conditions, and the preset temperature ranges from 750°C to 1200°C.

4. The preparation method according to claim 3, characterized in that, Before densifying the first dielectric layer, the preparation method further includes: Under aerobic conditions, a second dense oxide layer is formed on the side of the first dielectric layer near the gate, the second dense oxide layer encapsulates the gate, and the density of the second dense oxide layer is greater than the density of the first dielectric layer.

5. The preparation method according to any one of claims 1-4, characterized in that, The gate includes a composite gate, which comprises a polysilicon gate layer and a metal gate. Accordingly, forming the gate on the side of the gate oxide layer away from the epitaxial layer includes: A polysilicon gate is formed on the side of the gate oxide layer away from the epitaxial layer; The metal gate is formed on the side of the polysilicon gate layer away from the gate oxide layer.

6. The preparation method according to any one of claims 1-4, characterized in that, After densifying the first dielectric layer, the preparation method further includes: A second dielectric layer is formed on the side of the first dielectric layer opposite to the gate.

7. The preparation method according to any one of claims 1-4, characterized in that, The formation of a gate oxide layer on one side of the epitaxial layer includes: A field oxide layer is formed on one side of the epitaxial layer; Remove the field oxide layer located in the active region; The gate oxide layer is formed in the active region.

8. The preparation method according to any one of claims 1-4, characterized in that, Before forming a gate oxide layer on one side of the epitaxial layer, the fabrication method includes: A trap region is formed within the epitaxial layer; A source region is formed within the well region, and the conductivity type of the well region is different from that of the source region.

9. A vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, include: Epitaxial layer; A gate oxide layer is located on one side of the epitaxial layer; The gate is located on the side of the gate oxide layer away from the epitaxial layer; The first dielectric layer after densification is located on the side of the gate away from the gate oxide layer. The first dielectric layer covers the side surface of the gate away from the gate oxide layer, the side surface of the gate, and the unoccupied surface of the epitaxial layer. The density of the first dielectric layer before densification is less than or equal to a preset density. A first dense oxide layer is filled in the pores between the edge of the gate and the gate oxide layer, and the density of the first dense oxide layer is greater than the density of the first dielectric layer.

10. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 9, characterized in that, Also includes: A second dense oxide layer is located on the side of the first dielectric layer near the gate. The second dense oxide layer encapsulates the gate, and the density of the second dense oxide layer is greater than the density of the first dielectric layer.

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