Preparation method of trench gate field effect transistor, electronic equipment and readable storage medium
By incorporating a shielding layer in a silicon carbide trench gate field-effect transistor, the problem of gate oxide collapse is solved, improving the reliability and performance of the device, especially under high voltage and high frequency conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-03-13
AI Technical Summary
In reverse blocking mode, the gate oxide layer at the bottom of the trench of a traditional silicon carbide trench field-effect transistor is prone to collapse, resulting in a breakdown voltage limit and affecting the reliability and performance of the device.
A shielding layer is set in the drift layer below the gate. The shielding layer is formed by ion implantation to protect the isolation layer between the gate and the drift layer, avoid high electric field collapse, and optimize the gate structure to reduce the on-resistance.
It improves the reliability of trench gate field-effect transistors and reduces gate leakage current, enhances device performance under high voltage and high frequency, and avoids an increase in on-resistance.
Smart Images
Figure CN121665626A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a method for fabricating a trench gate field-effect transistor, an electronic device, and a readable storage medium. Background Technology
[0002] Currently, silicon carbide (SiC) devices possess excellent material properties, including wide bandgap, high critical electric field, and good thermal conductivity. Among them, silicon carbide trench-gate MOSFETs (TG-MOSFETs) are being studied in depth because they can potentially achieve very high gate density without being limited by parasitic JFET channels, thus reducing the contribution of channel resistance to the total on-resistance. This makes TG-MOSFETs a major focus of attention in the development of SiC devices for high-voltage, high-power, and high-frequency applications.
[0003] However, for conventional TG-MOSFETs in reverse blocking mode, the high electric field in the gate oxide layer at the bottom of the trench is the main problem of TG-MOSFETs. The high electric field in the gate oxide layer at the bottom of the trench may cause the gate oxide layer to collapse, limiting the breakdown voltage (VBR) of the TG-MOSFET. Summary of the Invention
[0004] The purpose of this application is to provide a method for fabricating a trench gate field-effect transistor, an electronic device, and a readable storage medium, aiming to solve the problem of gate oxide layer collapse in traditional silicon carbide trench gate field-effect transistors.
[0005] A first aspect of this application provides a method for fabricating a trench gate field-effect transistor, comprising: sequentially constructing a substrate, a drift layer, a first ion-doped layer, and a second ion-doped layer stacked together; etching the second ion-doped layer, the first ion-doped layer, and the drift layer to form a first trench penetrating the second ion-doped layer and the first ion-doped layer; forming a first dielectric layer covering the second ion-doped layer and the first ion-doped layer and exposing the surface of the drift layer located at the bottom of the first trench using a multi-pattern photolithography process; implanting ions into the drift layer to form a shielding layer; forming a gate in the first trench; forming a source on the side of the first ion-doped layer and the second ion-doped layer away from the substrate; and forming a drain on the side of the substrate away from the drift layer.
[0006] In one embodiment, forming a first dielectric layer covering the second ion-doped layer and the first ion-doped layer, and exposing the surface of the drift layer at the bottom of the first trench, using a multi-pattern photolithography process, includes: depositing a dielectric material of a first thickness on the surfaces of the second ion-doped layer, the first ion-doped layer, and the drift layer to form a second dielectric layer; the first thickness is greater than half the width of the trench; coating a patterned first photoresist on the side of the second dielectric layer away from the substrate; and etching the second dielectric layer using the first photoresist as a mask to form a second trench on the second dielectric layer; wherein the second trench is located on the substrate. The orthographic projection of the first trench is located within the orthographic projection of the first trench on the substrate; the first photoresist is removed and the second dielectric layer is etched to form a third dielectric layer located on both sides of the bottom of the first trench; a dielectric material of a second thickness is deposited on the surfaces of the second ion-doped layer, the first ion-doped layer, the drift layer and the third dielectric layer, and a fourth dielectric layer is formed in combination with the third dielectric layer; the second thickness is less than 0.1 μm; a patterned second photoresist is coated on the surface of the fourth dielectric layer on the side away from the substrate; the fourth dielectric layer is etched using the second photoresist as a mask to form the first dielectric layer; the second photoresist is removed.
[0007] In one embodiment, the step of implanting ions into the drift layer to form a shielding layer includes: implanting P-type ions into the drift layer located at the bottom of the first trench using an ion implantation process; removing the first dielectric layer; and activating the shielding layer at high temperature.
[0008] In one embodiment, forming a gate in the first trench includes: forming a first sub-part and a second sub-part sequentially spaced apart in the trench along a direction away from the substrate using a multi-pattern photolithography process; wherein the gate includes the first sub-part and the second sub-part.
[0009] In one embodiment, the step of forming a first sub-part and a second sub-part spaced sequentially at intervals along a direction away from the substrate in the trench using a multi-pattern photolithography process includes: re-forming the fourth dielectric layer; forming a first polysilicon material layer by depositing a polysilicon material of the first thickness; etching the first polysilicon material layer to form the first sub-part in the trench; forming a fifth dielectric layer by depositing a dielectric material of the second thickness in combination with the fourth dielectric layer; and etching the fifth dielectric layer to form a first gate oxide layer enclosing the first sub-part.
[0010] In one embodiment, the step of forming a first sub-part and a second sub-part sequentially spaced apart in the trench along a direction away from the substrate using a multi-pattern photolithography process further includes: depositing a high-temperature oxide material of a second thickness to form a second gate oxide layer covering the surfaces of the second ion-doped layer and the first ion-doped layer; depositing a polycrystalline silicon material of a first thickness to form a second polycrystalline silicon material layer; etching the second polycrystalline silicon material layer to form the second sub-part in the trench; and aligning the surface of the second sub-part away from the substrate with the surface of the second gate oxide layer away from the substrate.
[0011] In one embodiment, forming a source on the side of the first ion-doped layer and the second ion-doped layer away from the substrate includes: forming an interlayer dielectric layer on the surface of the second sub-part away from the substrate and on the portion of the second gate oxide layer away from the substrate, the interlayer dielectric layer at least covering the surface of the second sub-part away from the substrate; and forming the source by depositing a metal material on the surface of the second gate oxide layer away from the substrate.
[0012] In one embodiment, the sequentially constructed and stacked substrate, drift layer, first ion-doped layer and second ion-doped layer include: the sequentially constructed and stacked substrate, buffer layer, second gate oxide layer, drift layer, current spreading layer, first ion-doped layer and second ion-doped layer.
[0013] A second aspect of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the preparation method described above.
[0014] A third aspect of this application provides a readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the preparation method described above.
[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting a shielding layer in the drift layer below the gate, high-voltage protection can be achieved for the gate and the isolation layer between the gate and the drift layer. Especially when the trench gate field-effect transistor is operating in the reverse blocking state, the trench gate field-effect transistor needs to withstand a high voltage. The shielding layer can shield the high-voltage electric field located near the bottom of the trench in the drift layer, which can protect the isolation layer from high electric field collapse, reduce gate leakage current, and improve reliability. At the same time, since the orthogonal projection of the shielding layer on the substrate is located within the orthogonal projection of the trench on the substrate, the shielding layer can avoid blocking part of the conduction current path, thereby avoiding increasing the on-resistance of the trench gate field-effect transistor. Attached Figure Description
[0016] Figure 1 A flowchart illustrating a method for fabricating a trench gate field-effect transistor according to an embodiment of this application; Figure 2 This is a device structure diagram obtained after executing step S100, as provided in an embodiment of this application. Figure 3 This application provides a device structure diagram obtained after executing step S200 in one embodiment of the present application. Figure 4 This is a device structure diagram obtained after execution step S300, as provided in an embodiment of this application; Figure 5 This application provides a device structure diagram obtained after executing step S400 in one embodiment of the present application. Figure 6 This application provides a device structure diagram obtained after executing step S700 in one embodiment of the present application. Figure 7 This application provides a device structure diagram obtained after executing step S340 in one embodiment of the present application. Figure 8 This application provides a device structure diagram obtained after executing step S520 in one embodiment of the present application. Figure 9 The graph shows the variation of the reverse transfer capacitance Crss. Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0017] The above figures illustrate the following: 10, Trench gate field-effect transistor; 20, Electronic device; 21, Memory; 22, Processor; 23, Computer program; 100, Substrate; 200, Drift layer; 310, First ion-doped layer; 320, Second ion-doped layer; 410, Gate; 411, First sub-sub ... Detailed Implementation
[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0022] Figure 1 A flowchart illustrating a method for fabricating a trench gate field-effect transistor according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are detailed below: A method for fabricating a trench gate field-effect transistor 10 includes steps S100 to S700.
[0023] Step S100: Construct a substrate, a drift layer, a first ion-doped layer, and a second ion-doped layer sequentially. The device structure obtained after performing step S100 is as follows: Figure 2 As shown.
[0024] The process can employ epitaxial growth technology to construct the drift layer 200 by depositing semiconductor material, and to construct the first ion-doped layer 310 and the second ion-doped layer 320 by implanting ions after depositing the semiconductor material. The semiconductor material includes silicon carbide and gallium nitride.
[0025] Specifically, in step S100, N-type silicon carbide or N-type gallium nitride material can be deposited to construct the drift layer 200. A first ion-doped layer 310 is obtained by implanting P-type ions into the semiconductor material. Then, a portion of the first ion-doped layer 310 is converted into a second ion-doped layer 320 by implanting N+ type ions into a portion of the surface of the first ion-doped layer 310 away from the substrate 100. Alternatively, the first ion-doped layer 310 and the second ion-doped layer 320 can be constructed sequentially through multiple deposition and etching processes; this embodiment does not limit this approach.
[0026] Step S200: Etch the second ion-doped layer, the first ion-doped layer, and the drift layer to form a first trench penetrating the second ion-doped layer and the first ion-doped layer. The device structure obtained after performing step S200 is as follows. Figure 3 As shown.
[0027] The depth of the first trench is greater than the sum of the thicknesses of the first ion-doped layer 310 and the second ion-doped layer 320. This exposes a portion of the surface of the drift layer 200, and the upper surface of the drift layer 200 is etched to a certain extent.
[0028] Step S300: A first dielectric layer is formed by a multi-pattern photolithography process, covering the second ion-doped layer and the first ion-doped layer, and exposing the surface of the drift layer at the bottom of the first trench.
[0029] It should be noted that multi-pattern photolithography involves multiple independent photolithography and etching processes combined with corresponding deposition processes to form the desired structure. The device structure obtained after step S300 is as follows: Figure 4 As shown.
[0030] The first dielectric layer 1100 can be formed by depositing a dielectric material. The first dielectric layer 1100 can achieve isolation between different structures and, during ion implantation, block ions from passing through, acting as a mask. In some embodiments, the dielectric material can specifically be silicon oxide or silicon nitride.
[0031] Step S400: Ions are implanted into the drift layer to form a shielding layer. The device structure obtained after performing step S400 is as follows. Figure 5 As shown.
[0032] It is understandable that, due to the presence of the first dielectric layer 1100, during ion implantation in step S400, the shielding layer 600 will only be formed in the drift layer 200, which is not covered by the first dielectric layer 1100.
[0033] Specifically, the shielding layer 600 can be formed in the drift layer 200 by implanting P+ type ions. In some embodiments, the P+ type ions may specifically be aluminum ions.
[0034] Step S500: Form a gate in the first trench.
[0035] Step S600: Form a source electrode on the side of the first ion-doped layer and the second ion-doped layer away from the substrate.
[0036] Step S700: Form the drain on the side of the substrate away from the drift layer. The device structure obtained after performing steps S100 to S700 is as follows. Figure 6 As shown.
[0037] In steps S500 to S700, the gate 410, source 430 and drain 420 can be constructed according to the requirements through a combination of vapor deposition and etching processes.
[0038] By providing a shielding layer 600 within the drift layer 200 below the gate 410, high-voltage protection can be achieved for the gate 410 and the isolation layer 500 between the gate 410 and the drift layer 200. Especially when the trench gate field-effect transistor 10 operates in reverse blocking mode, it needs to withstand higher voltages. The shielding layer 600 can shield the high-voltage electric field located near the bottom of the trench in the drift layer 200, protecting the isolation layer 500 from high-field collapse, reducing gate 410 leakage current, and improving reliability. Simultaneously, since the orthogonal projection of the shielding layer 600 onto the substrate 100 lies within the orthogonal projection of the trench onto the substrate 100, the shielding layer 600 can avoid blocking part of the conduction current path, thereby preventing an increase in the on-resistance of the trench gate field-effect transistor 10.
[0039] In one embodiment, step S300 specifically includes steps S310 to S380.
[0040] Step S310: A dielectric material of a first thickness is deposited on the surfaces of the second ion-doped layer 320, the first ion-doped layer 310, and the drift layer 200 to form a second dielectric layer 1200. The first thickness is greater than half the trench width.
[0041] Step S320: A patterned first photoresist 2100 is coated on the side of the second dielectric layer 1200 away from the substrate 100.
[0042] Step S330: Using the first photoresist 2100 as a mask, the second dielectric layer 1200 is etched to form a second trench on the second dielectric layer 1200. The orthogonal projection of the second trench onto the substrate 100 lies within the orthogonal projection of the first trench onto the substrate 100.
[0043] Step S340: Remove the first photoresist 2100 and etch the second dielectric layer 1200 to form a third dielectric layer 1300 located on both sides of the bottom of the first trench. The device structure obtained after performing step S340 is as follows. Figure 7 As shown.
[0044] Step S350: A dielectric material of a second thickness is deposited on the surface of the second ion-doped layer 320, the first ion-doped layer 310, the drift layer 200, and the third dielectric layer 1300, and a fourth dielectric layer 1400 is formed by bonding the third dielectric layer 1300. The second thickness is less than 0.1 μm.
[0045] Step S360: A patterned second photoresist is coated on the side of the fourth dielectric layer 1400 away from the substrate 100.
[0046] Step S370: Using the second photoresist as a mask, etch the fourth dielectric layer 1400 to form the first dielectric layer 1100.
[0047] Understandably, the first dielectric layer 1100 can be used to protect the sidewalls on both sides of the first trench, preventing the ion implantation process in step S400 from affecting the first ion-doped layer 310.
[0048] After etching away part of the dielectric material to expose part of the surface of the drift layer 200 in step S370, the required shielding layer 600 can be formed only at the bottom of the first trench during ion implantation in step S400.
[0049] Step S380: Remove the second photoresist. The device structure obtained after performing step S380 is as follows. Figure 4 As shown.
[0050] Understandably, the width of the second trench affects the width of the third dielectric layer 1300; the wider the second trench, the narrower the third dielectric layer 1300. The width of the third dielectric layer 1300, in turn, affects the width of the sidewalls of the fourth dielectric layer 1400 near the bottom of the first trench, ultimately controlling the area of the drift layer 200 exposed by the first dielectric layer 1100. This allows for control over the width of the shielding layer 600.
[0051] In one embodiment, step S400 includes steps S410 to S430.
[0052] Step S410: P-type ions are implanted into the drift layer 200 located at the bottom of the first trench using an ion implantation process.
[0053] Step S420: Remove the first dielectric layer 1100.
[0054] Step S430: Activate the shielding layer 600 at high temperature.
[0055] It should be noted that high-temperature activation of the shielding layer 600 can repair lattice damage, activate the electroactivity of impurities, and eliminate defects and stress. The specific temperature for high-temperature activation can be set according to the actual process and requirements. For example, it can be heated to 700°C to 1100°C for high-temperature activation.
[0056] In one embodiment, step S500 includes: forming a first sub-part 411 and a second sub-part 412 sequentially spaced apart in a direction away from the substrate 100 within a trench using a multi-pattern photolithography process. The gate 410 includes the first sub-part 411 and the second sub-part 412.
[0057] By using the gate 410, which is composed of the first sub-section 411 and the second sub-section 412, the reverse transmission capacitance can be reduced, the switching performance of the trench gate field-effect transistor 10 can be improved, and the switching loss of the trench gate field-effect transistor 10 under high-frequency operating conditions can be reduced.
[0058] In one embodiment, step S500 specifically includes steps S510 to S550.
[0059] Step S510: Form the fourth dielectric layer 1400 again.
[0060] It is understood that the specific steps for forming the fourth dielectric layer 1400 in step S510 can be the same as those in steps S310 to S350. That is, the same photomask pattern can be used to construct the fourth dielectric layer 1400.
[0061] Step S520: A first polycrystalline silicon material layer 2200 is formed by depositing a polycrystalline silicon material of a first thickness. The device structure obtained after performing step S520 is as follows. Figure 8 As shown.
[0062] Step S530: The first polysilicon material layer 2200 is etched to form a first sub-part 411 within the trench. The structure of the formed first sub-part 411 is as follows: Figure 6 As shown, Step S540: By depositing a dielectric material of a second thickness, a fifth dielectric layer is formed by combining the fourth dielectric layer 1400.
[0063] Step S550: Etch the fifth dielectric layer to form the first gate oxide layer 510 that encapsulates the first sub-part 411.
[0064] In some embodiments, the thickness of the first gate oxide layer 510 on the side of the first sub-part 411 away from the substrate 100 is less than 0.1 μm.
[0065] In some embodiments, the first sub-part 411 includes a first surface and a second surface disposed opposite to each other, the first surface being located on the side of the second surface closer to the substrate 100, and the orthogonal projection of the first surface on the substrate 100 being smaller than the orthogonal projection of the second surface on the substrate 100.
[0066] Understandably, when the orthogonal projection of the first surface onto the substrate 100 is smaller than the orthogonal projection of the second surface onto the substrate 100, the cross-section of the first sub-section 411 is an inverted trapezoid. Therefore, the thickness of the isolation layer 500 located on both sides of the first sub-section 411 gradually increases in the direction close to the substrate 100, further reducing gate drain charge (Qgd) and improving the dynamic quality factor of the optimized trench gate field-effect transistor 10.
[0067] In some embodiments, the orthographic projection of the first sub-part 411 onto the substrate 100 is smaller than the orthographic projection of the second sub-part 412 onto the substrate 100.
[0068] Similarly, when the orthographic projection of the first sub-part 411 onto the substrate 100 is smaller than that of the second sub-part 412 onto the substrate 100, the thickness of the isolation layer 500 on both sides of the first sub-part 411 is greater. This can reduce the electric field concentration effect at the trench corners, avoid high electric field collapse, reduce gate leakage current, improve the operational reliability of the trench gate field-effect transistor 10, and improve the dynamic quality factor during high-frequency operation.
[0069] In one embodiment, step S500 further includes: A second gate oxide layer 520 is formed by depositing a high-temperature oxide material of a second thickness, covering the surfaces of the second ion-doped layer 320 and the first ion-doped layer 310. A second polysilicon material layer is formed by depositing a polysilicon material of a first thickness. The second polysilicon material layer is etched to form a second sub-part 412 within a trench. The surface of the second sub-part 412 away from the substrate 100 is aligned with the surface of the second gate oxide layer 520 away from the substrate 100.
[0070] The second gate oxide layer 520 can be constructed by depositing a high-temperature oxide (HTO) material. In addition to providing isolation between the gate 410 and the first ion-doped layer 310 and the second ion-doped layer 320, the second gate oxide layer 520 can also be used to construct the source electrode 430 on the surface of the second gate oxide layer 520.
[0071] The second gate oxide layer 520 can be prepared using an oxide deposition process at 300° or higher. When constructing the source electrode 430, the high-temperature oxide material is relatively unaffected by the construction process of the source electrode 430, and can protect the first gate oxide layer 510, the first ion-doped layer 310, and the second ion-doped layer 320.
[0072] In one embodiment, step S600 includes: An interlayer dielectric layer 700 is formed on the surface of the second sub-part 412 away from the substrate 100 and on the portion of the second gate oxide layer 520 away from the substrate 100, the interlayer dielectric layer 700 at least covering the surface of the second sub-part 412 away from the substrate 100. A source electrode 430 is formed by depositing a metal material on the surface of the second gate oxide layer 520 away from the substrate 100.
[0073] The interlayer dielectric layer 700 can enhance the isolation between the gate 410 and the source 430, and prevent the gate 410 and the source 430 from interfering with each other.
[0074] In one embodiment, step S100 specifically includes: A substrate 100, a buffer layer 900, a second gate oxide layer 520, a drift layer 200, a current spreading layer, a first ion doped layer 310, and a second ion doped layer 320 are sequentially constructed and stacked.
[0075] By adding a current diffusion layer 800 between the drift layer 200 and the first ion-doped layer 310, it is helpful to reduce the parasitic junction field-effect transistor resistance effect and thus reduce the specific conductance value.
[0076] Figure 9 The diagram shows the variation curves of the reverse transfer capacitance Crss for four different technical schemes under varying critical voltage Vds between the source 430 and drain 420. The four technical schemes are: Scheme 1 (conventional); Scheme 2 (a current diffusion layer 800 with a first doping concentration); Scheme 3 (a current diffusion layer 800 with a first doping concentration and a gate 410 divided into a first sub-section 411 and a second sub-section 412); and Scheme 4 (a current diffusion layer 800 with a second doping concentration and a gate 410 divided into a first sub-section 411 and a second sub-section 412). The first doping concentration is greater than the second doping concentration.
[0077] exist Figure 9 The curves showing the variation of the reverse transfer capacitance Crss indicate that the current diffusion layer 800 is depleted when the critical voltage Vds equals 10V. Schemes 2, 3, and 4 show a significant decrease in the reverse transfer capacitance Crss. Schemes 2, 3, and 4 exhibit better high-frequency characteristics than Scheme 1. It is understandable that the presence of the current diffusion layer 800 can improve the high-frequency characteristics of the trench gate MOSFET 10. Furthermore, appropriately reducing the current diffusion layer 800 can cause the reverse transfer capacitance Crss to decrease rapidly when a smaller critical voltage Vds is applied to the trench gate MOSFET 10.
[0078] Figure 10A schematic diagram of an electronic device 20 according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: An electronic device 20 includes a memory 21, a processor 22, and a computer program 23 stored in the memory 21 and executable on the processor 22. When the processor 22 executes the computer program 23, it implements the steps of the preparation method as described in any of the above embodiments.
[0079] The processor 22 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.
[0080] In some embodiments, memory 21 may be an internal storage unit of electronic device 20, such as a hard disk or memory of electronic device 20. In other embodiments, memory 21 may be an external storage device of electronic device 20, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on electronic device 20. Furthermore, memory 21 may include both internal and external storage units of electronic device 20. Memory 21 is used to store operating system, application programs, bootloader, data, and other programs, such as the program code of computer program 23. Memory 21 may also be used to temporarily store data that has been output or will be output.
[0081] This application also provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the preparation method as described in any of the above embodiments.
[0082] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0083] One embodiment of this application provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the preparation method as described in any of the above embodiments.
[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0086] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for fabricating a trench gate field-effect transistor, characterized in that, include: A substrate, a drift layer, a first ion-doped layer, and a second ion-doped layer are sequentially constructed and stacked. The second ion-doped layer, the first ion-doped layer, and the drift layer are etched to form a first trench that penetrates the second ion-doped layer and the first ion-doped layer. A first dielectric layer is formed by a multi-pattern photolithography process, covering the second ion-doped layer and the first ion-doped layer, and exposing the surface of the drift layer located at the bottom of the first trench. Ions are injected into the drift layer to form a shielding layer; A gate is formed within the first trench; A source electrode is formed on the side of the first ion-doped layer and the second ion-doped layer away from the substrate; A drain is formed on the side of the substrate away from the drift layer.
2. The preparation method according to claim 1, characterized in that, The first dielectric layer, formed by a multi-pattern photolithography process, covering the second ion-doped layer and the first ion-doped layer, and exposing the surface of the drift layer at the bottom of the first trench, includes: A dielectric material of a first thickness is deposited on the surfaces of the second ion-doped layer, the first ion-doped layer, and the drift layer to form a second dielectric layer; the first thickness is greater than half the width of the trench. A patterned first photoresist is coated on the side of the second dielectric layer away from the substrate; Using the first photoresist as a mask, the second dielectric layer is etched to form a second trench on the second dielectric layer; wherein the orthographic projection of the second trench on the substrate is located within the orthographic projection of the first trench on the substrate; The first photoresist is removed and the second dielectric layer is etched to form a third dielectric layer located on both sides of the bottom of the first trench. A dielectric material of a second thickness is deposited on the surface of the second ion-doped layer, the first ion-doped layer, the drift layer, and the third dielectric layer, and a fourth dielectric layer is formed by bonding the third dielectric layer; the second thickness is less than 0.1 μm. A patterned second photoresist is coated on the surface of the fourth dielectric layer on the side away from the substrate; Using the second photoresist as a mask, the fourth dielectric layer is etched to form the first dielectric layer; Remove the second photoresist.
3. The preparation method according to claim 1, characterized in that, The step of injecting ions into the drift layer to form a shielding layer includes: P-type ions are implanted into the drift layer located at the bottom of the first trench using an ion implantation process; Remove the first dielectric layer; The shielding layer is activated at high temperature.
4. The preparation method according to claim 2, characterized in that, The step of forming a gate within the first trench includes: A first sub-section and a second sub-section are formed in the trench by a multi-pattern photolithography process, which are arranged sequentially at intervals in a direction away from the substrate; wherein the gate includes the first sub-section and the second sub-section.
5. The preparation method according to claim 4, characterized in that, The process of forming a first sub-part and a second sub-part in the trench, spaced apart sequentially in a direction away from the substrate, using a multi-pattern photolithography process includes: The fourth dielectric layer is formed again; A first polycrystalline silicon material layer is formed by depositing polycrystalline silicon material of the first thickness; The first polycrystalline silicon material layer is etched to form the first sub-part within the trench; A fifth dielectric layer is formed by depositing a dielectric material of a second thickness and combining it with the fourth dielectric layer; The fifth dielectric layer is etched to form a first gate oxide layer that encapsulates the first sub-part.
6. The preparation method according to claim 5, characterized in that, The method of forming a first sub-part and a second sub-part sequentially spaced apart in a direction away from the substrate within the trench using a multi-pattern photolithography process further includes: A second thickness of high-temperature oxide material is deposited to form a second gate oxide layer covering the surfaces of the second ion-doped layer and the first ion-doped layer; A second polycrystalline silicon material layer is formed by depositing a first-thickness polycrystalline silicon material. The second polysilicon material layer is etched to form the second sub-section within the trench; the surface of the second sub-section away from the substrate is aligned with the surface of the second gate oxide layer away from the substrate.
7. The preparation method according to claim 6, characterized in that, The step of forming a source electrode on the side of the first ion-doped layer and the second ion-doped layer away from the substrate includes: An interlayer dielectric layer is formed on the surface of the second sub-part away from the substrate and on the portion of the second gate oxide layer away from the substrate, the interlayer dielectric layer at least covering the surface of the second sub-part away from the substrate; The source electrode is formed by depositing a metallic material on the surface of the second gate oxide layer away from the substrate.
8. The preparation method according to any one of claims 1 to 6, characterized in that, The substrate, drift layer, first ion-doped layer, and second ion-doped layer, which are sequentially constructed and stacked, include: The substrate, buffer layer, second gate oxide layer, drift layer, current spreading layer, first ion doped layer and second ion doped layer are constructed and stacked sequentially.
9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the preparation method as described in any one of claims 1 to 8.
10. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the preparation method as described in any one of claims 1 to 8.