Display panel

Abstract

A display panel is disclosed. The display panel includes: a base member; a plurality of pixels; a plurality of first lines configured to transmit electrical signals to the plurality of pixels; a first insulating layer covering the plurality of first lines; a second line disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering the second line; a plurality of third lines disposed on the second insulating layer, in which at least one of the plurality of third lines overlaps the plurality of first lines; a third insulating layer covering the plurality of third lines; and a connection line overlapping at least one of the plurality of third lines, in which the connection line is configured to electrically connect a portion of the plurality of first lines and the second line to each other.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0125433, filed on September 13, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a display panel having reduced defects caused by residual film and an electronic device including the display panel. Background Technology

[0003] With the approach of the information age, electronic devices with new technologies are being developed to meet various consumer needs. Among these technologies, development is focused on display devices with high resolution and clear images.

[0004] To improve the resolution of a display device, titanium (Ti) and aluminum (Al) can be used to reduce the resistance between the wiring adjacent to a portion of the spider wiring located below the bottom of a conventional display panel, thereby reducing power consumption.

[0005] However, unlike wiring that includes molybdenum (Mo), wiring that includes titanium (Ti) and aluminum (Al) can have a greater thickness. This prevents the angle between the bottom substrate component and the starting point of the electrode pattern from decreasing. Due to this property, this thickness variation can create horizontal differences in areas where wiring that includes titanium (Ti) and aluminum (Al) is used, and can become difficult to etch completely during the process.

[0006] Additionally, there may be a problem where wiring using titanium (Ti) and aluminum (Al) is not completely removed during the etching process, potentially allowing short-circuit current to flow through the display panel and thus causing defects. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display panel with a reduced defect rate due to residual film and an electronic device including the display panel.

[0008] A display panel according to embodiments of the present disclosure may include a substrate member defining a first region and a second region surrounding the first region. A plurality of pixels may be disposed on the first region. A plurality of first lines may be disposed on the second region and configured to transmit electrical signals to the plurality of pixels, the plurality of first lines extending in a predetermined direction. A first insulating layer may cover the plurality of first lines. A second line may be disposed on the first insulating layer. A second insulating layer may be disposed on the first insulating layer and cover the second line. A plurality of third lines may be disposed on the second insulating layer, the plurality of third lines extending in a direction intersecting the predetermined direction. At least one of the plurality of third lines may overlap with the plurality of first lines. A third insulating layer may be disposed on the second insulating layer and cover the plurality of third lines. A connecting line may extend in the predetermined direction, overlap with at least one of the plurality of third lines, and be configured to electrically connect a portion of the plurality of first lines to the second line.

[0009] In embodiments of this disclosure, each of the plurality of first lines may have a first thickness, and the second line may have a second thickness greater than the first thickness.

[0010] In embodiments of this disclosure, each of the plurality of first lines may include a first metal material, and the second line may include a second metal material different from the first metal material.

[0011] In embodiments of this disclosure, the first metallic material may include molybdenum (Mo), and the second metallic material may include at least one of titanium (Ti) and aluminum (Al).

[0012] In embodiments of this disclosure, the connecting wire may be disposed below the first insulating layer.

[0013] In embodiments of this disclosure, the first contact hole, second contact hole, third contact hole, and fourth contact hole may be defined within a second insulating layer. The first contact hole may overlap with any one of the plurality of third wires and a portion of the plurality of first wires. The second contact hole may overlap with one of the plurality of third wires and a connecting wire. The third contact hole may overlap with another of the plurality of third wires and a connecting wire. The fourth contact hole may overlap with the other of the plurality of third wires and a second wire.

[0014] In embodiments of this disclosure, the first contact hole, the second contact hole, and the third contact hole may be defined within a second insulating layer. The connecting wire may contact a portion of a plurality of first wires. The first contact hole may overlap with any one of a plurality of third wires. The first contact hole may overlap with the connecting wire or the aforementioned portion of the plurality of first wires. The second contact hole may overlap with another of the plurality of third wires and the connecting wire. The third contact hole may overlap with the other of the plurality of third wires and the second wire.

[0015] In embodiments of this disclosure, the connecting wire may be disposed on the third insulating layer.

[0016] In embodiments of this disclosure, the first and second contact holes may be defined in a second insulating layer, and the third and fourth contact holes may be defined in a third insulating layer. The first contact hole may overlap with any one of the plurality of third wires and a portion of the plurality of first wires. The second contact hole may overlap with another of the plurality of third wires and a second wire. The third contact hole may overlap with a connecting wire and the aforementioned third wire. The fourth contact hole may overlap with a connecting wire and the aforementioned third wire.

[0017] In embodiments of this disclosure, the data driving circuit may be disposed on the second region. The demultiplexer may be configured to receive data signals from the data driving circuit and provide the data signals to multiple pixels, and the demultiplexer is disposed in a plane between the data driving circuit and the first region. At least one of a plurality of first lines, second lines, a plurality of third lines, and connecting lines may be disposed in a plane between the data driving circuit and the demultiplexer.

[0018] According to embodiments of this disclosure, it becomes possible to provide a display panel with a reduced defect rate due to residual film and an electronic device including the display panel. Attached Figure Description

[0019] The above and other aspects and features of the present invention will become clearer from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which: Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention; Figure 2 This is an exploded view of an electronic device according to an embodiment of the present invention; Figure 3 This is a plan view of a display panel according to an embodiment of the present invention; Figure 4 This is a diagram of the equivalent circuit of a pixel according to an embodiment of the present invention; Figure 5 Is applied to Figure 4 A diagram illustrating the signals of the pixels shown; Figure 6 This is a cross-sectional view of a display panel according to an embodiment of the present invention; Figure 7 Is with Figure 3 The diagram shows the layout corresponding to the portion marked with AA. Figure 8A It is along Figure 7 An illustration of a portion of the cross-section taken by line I-I' shown; Figure 8B It is along Figure 7 An illustration of a portion of the cross-section taken by line II-II' shown in the diagram; Figure 9A yes Figure 7 An illustration of the layout of multiple first lines and connecting lines in the second gate electrode pattern shown; Figure 9B It adds multiple second lines. Figure 9A The illustration; Figure 9C It adds multiple third lines. Figure 9B The illustration; Figure 9D It is along Figure 7 An illustration of a portion of the cross-section taken by line III-III' shown; Figure 10A Is with Figure 3 An illustration of an embodiment of the layout corresponding to the portion marked with AA shown; Figure 10B This is a diagram illustrating the layout of multiple first lines and connecting lines in the second gate electrode pattern; Figure 10C It adds multiple second lines. Figure 10B The illustration; Figure 10D It adds multiple third lines. Figure 10C The illustration; Figure 10E It is along Figure 10A An illustration of a portion of the cross-section taken by line IV-IV' shown; Figure 11A It is according to an embodiment of the present invention and Figure 3 The diagram shows the layout corresponding to the portion marked with AA. Figure 11B This is a diagram illustrating the layout of multiple first lines in the second gate electrode pattern; Figure 11C It adds a layout with multiple second lines. Figure 11B The illustration; Figure 11D It adds a layout with multiple third lines. Figure 11C The illustration; Figure 11E It adds the layout of the connecting lines. Figure 11D The illustration; Figure 11F It is along Figure 11A An illustration of a portion of the cross-section taken by the line V-V' shown; Figure 12 This is a block diagram of an electronic device according to an embodiment of the present invention; and Figure 13 A schematic diagram of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0020] Embodiments of the invention will now be described more fully with reference to the accompanying drawings. It will be understood that the invention may be embodied in different forms and therefore should not be construed as limited to the embodiments set forth herein. It will be understood that throughout the specification, the same reference numerals may refer to the same elements, and therefore redundant descriptions may be omitted.

[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Any term defined in a general dictionary shall be interpreted as having the same meaning in the context of the relevant field and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined otherwise.

[0022] Embodiments of the present invention relate to a display panel designed to improve manufacturing efficiency and display performance, and an electronic device comprising the display panel. Conventional display panels face challenges related to residual metal film remaining after etching processes, leading to potential defects such as short circuits and increased power consumption. To address these issues, the present invention introduces a multilayer wiring structure to increase etching precision and electrical connectivity within the display panel.

[0023] Embodiments of the present invention use different metallic materials for the gate electrode patterns. The second gate electrode pattern may include molybdenum (Mo), while the third gate electrode pattern may include titanium (Ti) and aluminum (Al). This material selection reduces the resistance between adjacent wirings, but also introduces manufacturing challenges due to differences in etching characteristics. To mitigate this, embodiments of the present invention define the layer thickness and sidewall angle to ensure that unwanted residual metallic material is minimized, thereby preventing electrical defects in the display panel.

[0024] Embodiments of the present invention further improve signal transmission within the display panel through wiring and contact hole structures. By including multiple conductive layers comprising a first line, a second line, and a third line, and strategically placing contact holes, the display panel can achieve effective electrical connectivity while maintaining structural integrity.

[0025] Figure 1 This is a perspective view of an electronic device ED according to an embodiment of the present invention.

[0026] Figure 2 This is an exploded view of an electronic device ED according to an embodiment of the present invention.

[0027] The first direction DR1, the second direction DR2, and the third direction DR3 can be defined. The first direction DR1 and the second direction DR2 can be in... Figure 1 The directions defined on the plane of the electronic device ED shown are as follows. Furthermore, the first direction DR1 and the second direction DR2 may intersect each other. The third direction DR3 may be... Figure 1 The thickness direction of the electronic device ED shown. For example, the third direction DR3 can be perpendicular to the first direction DR1 and the second direction DR2.

[0028] According to an embodiment of the present invention, Figure 1 An electronic device ED including a display device is shown. For example, the display device can be incorporated into the electronic device ED. The display device can be a device configured to display images and can be incorporated into electronic devices ED such as monitors, televisions, smartphones, wearable devices, navigators, terminals installed in vehicles, or tablet computers. The shape and function of the display device are not limited thereto. For example, the front of the display device can be various shapes such as circles or polygons. Additionally, the display device can have a curved surface shape that curves in a particular direction instead of being flat.

[0029] Reference Figure 2 The electronic device ED may include a display panel DP, a front housing FS, an intermediate mold MM, and a rear housing BH. Additionally, multiple pixels PX may be included in the display panel DP. Furthermore, the electronic device ED can be manufactured by setting the display panel DP in an opening provided in the front housing FS, attaching the display panel DP to the intermediate mold MM, and subsequently attaching the intermediate mold MM to the rear housing BH.

[0030] A display panel (DP) configured to display images in an electronic device (ED) can be exposed in front of the ED, allowing the user to view the images. Additionally, multiple pixels (PX) can be arranged in the display panel (DP), and an image can be provided on the display panel (DP) through the operation of each of the pixels (PX).

[0031] The opening can be defined at the front of the front housing FS, and the display panel DP can be disposed in the opening. Therefore, the bezel of the electronic device ED can be minimized without any additional components obstructing the front surface of the display panel DP.

[0032] The intermediate mold MM can have a portion that is attached to the rear surface of the display panel DP and another portion that is attached to the front housing FS. Therefore, the display panel DP can be fixedly mounted on the front of the front housing FS.

[0033] The rear housing BH can be integrated into the intermediate mold MM. Additionally, the rear housing BH can be plate-shaped to protect the display panel DP from external impacts. Furthermore, the rear housing BH may include vents to dissipate internal heat from the electronic device ED to the external environment.

[0034] Figure 3 This is a plan view of a display panel DP according to an embodiment of the present invention.

[0035] The display area DA and the non-display area NDA can be defined within the display panel DP. The non-display area NDA can at least partially surround the display area DA. Multiple pixels PX can be arranged to overlap with the display area DA. The multiple pixels PX can be arranged in a specific configuration within the display panel DP. For example, the multiple pixels PX can be repeatedly arranged in a first direction DR1, and the multiple pixels PX repeatedly arranged in the first direction DR1 can be repeatedly arranged in a second direction DR2. Ultimately, the multiple pixels PX can be arranged in a matrix. Furthermore, each of the multiple pixels PX can display a different color within the display panel DP.

[0036] The display panel (DP) may include a demultiplexer (DMX), a data driver circuit (DIC), a flexible printed circuit board (FPCB), and signal pads (PDs). The demultiplexer (DMX), data driver circuit (DIC), flexible printed circuit board (FPCB), and signal pads (PDs) may be located in the non-display area (NDA) of the display panel (DP).

[0037] The data drive circuit (DIC) can have the shape of an integrated circuit (IC) chip and be mounted in the display panel (DP). The data drive circuit (DIC) can be a component configured to transmit data signals to pixels (PX).

[0038] The data signal output from the data drive circuit DIC can be transmitted to the demultiplexer DMX. The demultiplexer DMX can be configured to divide the received data signal and provide the data signal to multiple pixels PX.

[0039] Multiple signal pads (PDs) can be mounted on a flexible printed circuit board (FPCB). According to embodiments of this disclosure, the multiple signal pads (PDs) can be electrically connected to a data drive circuit (DIC) to transmit signals for operating the DIC.

[0040] Additionally, the printed circuit board (PCB) can be mounted on the flexible printed circuit board (FPCB). However, this disclosure is not limited thereto; the flexible printed circuit board (FPCB) can be electrically connected to the PCB via a separate component.

[0041] Figure 3The portion marked with AA shown can be defined as the portion of the wiring between the demultiplexer DMX and the data drive circuit DIC.

[0042] Figure 3 The portion marked BB in the diagram may refer to the bottom portion of the non-display area NDA of the display panel DP.

[0043] According to embodiments of this disclosure, Figure 3 The wiring in the section marked with BB shown can be equivalently applied as Figure 3 The wiring is shown in the section marked with AA. The shape of the wiring is explained below based on the section marked with AA.

[0044] Figure 4 This is a diagram of the equivalent circuit of a pixel PX according to an embodiment of the present disclosure. Figure 5 Showing the application to Figure 4 Examples of the light emission control signal Ei and scan signals Si-1, Si, and Si+1 for pixel PX. Figure 4 An example of a pixel PX connected to the i-th scan line SLi and the i-th emission control line ECLi is shown.

[0045] A pixel (PX) may include a light-emitting diode (LD) and a pixel circuit (CC).

[0046] In this disclosure, organic light-emitting diodes (OLEDs) are shown as light-emitting diodes (LDs), but this disclosure is not limited thereto.

[0047] The pixel circuit CC may include multiple transistors T1 to T7 and a capacitor CP. The pixel circuit CC may be configured to control the current flowing through the light-emitting diode LD in response to a data signal.

[0048] A light-emitting diode (LD) can be configured to emit light at a predetermined brightness level based on the amount of current supplied by the pixel circuit CC. To achieve this, a first power level ELVDD is set higher than a second power level ELVSS.

[0049] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this disclosure, for convenience, one of the input electrode and the output electrode may be referred to as the first electrode, and the other remaining electrode may be referred to as the second electrode.

[0050] The first electrode of the first transistor T1 is connected via the fifth transistor T5 to the power line PL, which is subject to a first power level ELVDD. The second electrode of the first transistor T1 is connected via the sixth transistor T6 to the anode electrode of the light-emitting diode LD. In this specification, the first transistor T1 may be referred to as the driving transistor.

[0051] The first transistor T1 is configured to control the amount of current flowing through the light-emitting diode LD in response to a voltage applied to the control electrode.

[0052] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. Additionally, the control electrode of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the second transistor T2 is turned on to electrically connect the data line DL and the first electrode of the first transistor T1.

[0053] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0054] The fourth transistor T4 is connected between node ND and the initialization power generation unit (not shown). Additionally, the control electrode of the fourth transistor T4 is connected to the (i-1)th scan line SLi-1. When the (i-1)th scan signal Si-1 is provided to the (i-1)th scan line SLi-1, the fourth transistor T4 is turned on to provide the initialization voltage Vint to node ND.

[0055] The fifth transistor T5 is connected between the power line PL and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 is connected to the i-th light-emitting control line ECLi.

[0056] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting diode LD. Additionally, the control electrode of the sixth transistor T6 is connected to the i-th light-emitting control line ECLi.

[0057] The seventh transistor T7 is connected between the initialization power generation unit (not shown) and the anode electrode of the light-emitting diode LD. Additionally, the control electrode of the seventh transistor T7 is connected to the (i+1)th scan line SLi+1. When the (i+1)th scan signal Si+1 is provided to the (i+1)th scan line SLi+1, the seventh transistor T7 is turned on to provide the initialization voltage Vint to the anode electrode of the light-emitting diode LD.

[0058] The seventh transistor T7 improves the black level representation of pixel PX. Specifically, when the seventh transistor T7 is turned on, it discharges the parasitic capacitor of the light-emitting diode LD. As a result, when displaying black levels, the light-emitting diode LD does not emit light, thus preventing unwanted emission caused by leakage current from the first transistor T1. This effectively increases the accuracy of black level representation.

[0059] In addition, Figure 4 In the diagram, the control electrode of the seventh transistor T7 is shown connected to the (i+1)th scan line SLi+1, but this disclosure is not limited to this configuration. In another embodiment of this disclosure, the control electrode of the seventh transistor T7 may be connected to the i-th scan line SLi or the (i-1)th scan line SLi-1.

[0060] Figure 4 The transistors of the pixel PX are shown based on PMOS, but this disclosure is not limited to this construction. In another embodiment of this disclosure, the transistors of the pixel PX may be constructed from NMOS. In yet another embodiment of this disclosure, the transistors of the pixel PX may be constructed from a combination of NMOS and PMOS.

[0061] A capacitor CP is placed between the power line PL and node ND. The capacitor CP is configured to store the voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CP.

[0062] Reference Figure 5 The light emission control signal Ei can be either high (E-HIGH) or low (E-LOW). Each of the scan signals Si-1, Si, and Si+1 can be either high (S-HIGH) or low (S-LOW).

[0063] When the light emission control signal Ei has a high level (E-HIGH), the fifth transistor T5 and the sixth transistor T6 are turned off. When the fifth transistor T5 is turned off, the power line PL and the first electrode of the first transistor T1 are electrically disconnected. When the sixth transistor T6 is turned off, the second electrode of the first transistor T1 and the anode electrode of the light-emitting diode LD are electrically disconnected. Therefore, when the light emission control signal Ei with a high level (E-HIGH) is provided to the i-th light emission control line ECLi, the light-emitting diode LD does not emit light.

[0064] Subsequently, when the (i-1)th scan signal Si-1 supplied to the (i-1)th scan line SLi-1 has a low level S-LOW, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the initialization voltage Vint is supplied to node ND.

[0065] When the i-th scan signal Si provided to the i-th scan line SLi has a low level S-LOW, the second transistor T2 and the third transistor T3 are turned on.

[0066] When the second transistor T2 is turned on, the data signal is supplied to the first electrode of the first transistor T1. Here, since node ND is initialized to the initialization voltage Vint, the first transistor T1 is turned on. When the first transistor T1 is turned on, the voltage corresponding to the data signal is supplied to node ND. Here, capacitor CP stores the voltage corresponding to the data signal.

[0067] When the i+1 scan signal Si+1 provided to the i+1 scan line SLi+1 has a low level S-LOW, the seventh transistor T7 is turned on.

[0068] When the seventh transistor T7 is turned on, the initialization voltage Vint is provided to the anode electrode of the light-emitting diode LD, thereby discharging the parasitic capacitor of the light-emitting diode LD.

[0069] When the light emission control signal Ei supplied to the i-th light emission control line ECLi is low (E-LOW), the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the first power level ELVDD is supplied to the first electrode of the first transistor T1. When the sixth transistor T6 is turned on, the second electrode of the first transistor T1 and the anode electrode of the light-emitting diode LD are electrically connected. Then, the light-emitting diode LD generates light of a predetermined brightness in response to the supplied current.

[0070] Figure 6 This is an illustration of a portion of a cross-section of a display panel DP according to an embodiment of the present invention.

[0071] The display panel (DP) may include a substrate (BL), a circuit layer (CL), a light-emitting layer (ELL), and a packaging layer (TFE).

[0072] The substrate component BL may include at least one of organic materials, inorganic materials, and glass. The substrate component BL may include a first region and a second region at least partially surrounding the first region. Multiple pixels PX may be disposed on the first region of the substrate component BL. The first region of the substrate component BL may correspond to the display area DA of the display panel DP. The second region of the substrate component BL may correspond to the non-display area NDA of the display panel DP.

[0073] The circuit layer CL can be disposed on the substrate component BL. The circuit layer CL may include a barrier layer BR, a buffer layer BF, a semiconductor pattern ACT, gate insulating layers GI1, GI2 and GI3, gate electrode patterns GAT1, GAT2 and GAT3, an interlayer insulating layer ILD, source-drain electrode patterns SD1 and SD2, and via insulating layers VIA1 and VIA2. A portion of the semiconductor pattern ACT may be an active cell of a transistor, a portion of the gate electrode patterns GAT1, GAT2 and GAT3 may be a control electrode of a transistor, and a portion of the source-drain electrode patterns SD1 and SD2 may be the input electrode and output electrode of a transistor.

[0074] The light-emitting layer ELL can be disposed on the circuit layer CL. The light-emitting layer ELL may include a light-emitting diode LD and a pixel-defining film DL.

[0075] The encapsulation layer TFE can be configured to seal and cover the light-emitting layer ELL to protect the light-emitting layer ELL from external oxygen and / or moisture.

[0076] The encapsulation layer TFE may include a first inorganic layer CVD1, an organic layer MN, and a second inorganic layer CVD2. Figure 6 In this example, the encapsulation layer TFE is shown as comprising two inorganic layers and one organic layer, but the invention is not limited to this example. For instance, the encapsulation layer TFE may comprise three inorganic layers and two organic layers, in which case the inorganic and organic layers may be stacked alternately. Functional layers BR and BF may be disposed on one side of the substrate member BL. Functional layers BR and BF may comprise a barrier layer BR and a buffer layer BF.

[0077] The functional layers BR and BF can be configured to prevent impurities present at the bottom of the substrate member BL during the manufacturing process from diffusing into the pixel PX. Specifically, the functional layers BR and BF can be configured to prevent impurities from diffusing into the semiconductor pattern ACT included in the pixel PX.

[0078] The semiconductor pattern ACT constituting the transistor is disposed on the buffer layer BF. The semiconductor pattern ACT may include, for example, polycrystalline silicon or amorphous silicon. In addition to the above, the semiconductor pattern ACT may, for example, include a metal-oxide-semiconductor. In embodiments of the present invention, the thickness of the semiconductor pattern ACT may be about 470 Å, but the present invention is not limited thereto.

[0079] The semiconductor pattern ACT may include a channel region serving as a conduction channel for the movement of electrons or holes, and a first ion-doped region and a second ion-doped region are disposed on opposite sides of the channel region.

[0080] A first gate insulating layer GI1 covering the semiconductor pattern ACT can be disposed on the buffer layer BF. The first gate insulating layer GI1 may include, for example, silicon dioxide or silicon nitride. In embodiments of the present invention, the thickness of the first gate insulating layer GI1 may be about 1600 Å, but the present invention is not limited thereto.

[0081] The first gate electrode pattern GAT1 may be disposed on the first gate insulating layer GI1. The first gate electrode pattern GAT1 may include molybdenum (Mo). In embodiments of the present invention, the thickness of the first gate electrode pattern GAT1 may be about 3000 Å, but the present invention is not limited thereto.

[0082] A second gate insulating layer GI2 covering the first gate electrode pattern GAT1 may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may include, for example, silicon nitride. In embodiments of the present invention, the thickness of the second gate insulating layer GI2 may be about 1400 Å, but the present invention is not limited thereto.

[0083] The second gate electrode pattern GAT2 can be disposed on the second gate insulating layer GI2. The second gate electrode pattern GAT2 may include molybdenum (Mo). In embodiments of the present invention, the thickness of the second gate electrode pattern GAT2 may be about 3000 Å, but the present invention is not limited thereto.

[0084] A third gate insulating layer GI3 covering the second gate electrode pattern GAT2 can be disposed on the second gate insulating layer GI2. The third gate insulating layer GI3 may include, for example, silicon nitride. In embodiments of the present invention, the thickness of the third gate insulating layer GI3 may be about 1400 Å, but the present invention is not limited thereto. In this disclosure, the third gate insulating layer GI3 may be referred to as the first insulating layer.

[0085] The third gate electrode pattern GAT3 can be disposed on the third gate insulating layer GI3. The third gate electrode pattern GAT3 may include at least one of titanium (Ti) and aluminum (Al). In embodiments of the present invention, the thickness of the third gate electrode pattern GAT3 may be about 3800 Å, but the present invention is not limited thereto.

[0086] The third gate electrode pattern GAT3 may comprise a different material than the first gate electrode pattern GAT1 and the second gate electrode pattern GAT2. The fact that the third gate electrode pattern GAT3 can be constructed from a different material than the first gate electrode pattern GAT1 and the second gate electrode pattern GAT2 can reduce the resistance between adjacent wirings. Consequently, the third gate electrode pattern GAT3 and the second gate electrode pattern GAT2 can have different thicknesses. Because the third gate electrode pattern GAT3 is thicker than the second gate electrode pattern GAT2, achieving complete etching during the manufacturing process can be challenging. As a result, some areas may retain metal material that should have been removed during the formation of the third gate electrode pattern GAT3.

[0087] This disclosure aims to address such problems.

[0088] The following will explain Figure 7 , Figure 10A and Figure 11A The invention is applied and illustrated in the figures, including embodiments and another embodiment. According to embodiments and another embodiment of the invention, problems caused by using different materials for the second gate electrode pattern GAT2 and the third gate electrode pattern GAT3 can be reduced.

[0089] The above descriptions of gate electrode patterns GAT1, GAT2, and GAT3 correspond to embodiments of the present invention, and the material and thickness of gate electrode patterns GAT1, GAT2, and GAT3 can be modified.

[0090] Scan lines SLi, SLi-1 and SLi+1 (see Figure 4 ) and the i-th emission control line ECLi (see Figure 4 At least a portion of the gate insulating layer GI1, GI2 and GI3 may be disposed on at least one of the gate insulating layers GI1, GI2 and GI3.

[0091] An interlayer insulating layer (ILD) covering the third gate electrode pattern GAT3 can be disposed on the third gate insulating layer GI3. The interlayer insulating layer (ILD) can include organic films and / or inorganic films. The interlayer insulating layer (ILD) can include multiple inorganic or organic thin films. The multiple inorganic thin films can include a silicon nitride layer and a silicon oxide layer. In this disclosure, the interlayer insulating layer (ILD) can be referred to as a second insulating layer.

[0092] Data cable DL (see) Figure 4 ) and power line PL (see Figure 4At least a portion of the first source-drain electrode pattern SD1 can be disposed on the interlayer insulating layer (ILD). The first source-drain electrode pattern SD1 can be disposed on the interlayer insulating layer (ILD). The first source-drain electrode pattern SD1 may include titanium (Ti), aluminum (Al), and titanium (Ti), and each first source-drain electrode pattern SD1 is configured as three layers. In embodiments of the present invention, the thickness of the first source-drain electrode pattern SD1 may be about 6800 Å or less, but the present invention is not limited thereto.

[0093] A first via insulating layer VIA1 may be disposed on the first source-drain electrode pattern SD1. The first via insulating layer VIA1 may comprise an organic film and / or an inorganic film. The first via insulating layer VIA1 may provide a flat surface. The first via insulating layer VIA1 may be positioned between the anode electrode AE ​​and the first source-drain electrode pattern SD1. In this disclosure, the first via insulating layer VIA1 may be referred to as a third insulating layer.

[0094] The second source-drain electrode pattern SD2 can be disposed on the first via insulating layer VIA1. The second source-drain electrode pattern SD2 may include, for example, titanium (Ti), aluminum (Al), and titanium (Ti), and each second source-drain electrode pattern SD2 is configured as three layers. In embodiments of the present invention, the thickness of the second source-drain electrode pattern SD2 may be about 6800 Å or less, but the present invention is not limited thereto.

[0095] A second via insulating layer VIA2 may be disposed on the second source-drain electrode pattern SD2. The second via insulating layer VIA2 may include an organic film and / or an inorganic film. The second via insulating layer VIA2 may provide a flat surface. The second via insulating layer VIA2 may be positioned between the anode electrode AE ​​and the second source-drain electrode pattern SD2.

[0096] The pixel-limiting film (PDL) and the light-emitting diode (LD) can be disposed on the second via insulating layer (VIA2).

[0097] A light-emitting diode (LD) may include an anode electrode AE, a hole control layer HL, a light-emitting layer EML, an electronic control layer EL, and a cathode electrode CE.

[0098] The anode electrode AE ​​can be connected to the first source-drain electrode pattern SD1 through contact holes in the through-hole insulating layers VIA1 and VIA2.

[0099] An opening OP defined in the pixel-limiting film PDL can expose the anode electrode AE.

[0100] Figure 7 Is with Figure 3 The diagram shows the layout corresponding to the portion marked with AA.

[0101] Figure 8A It is along Figure 7 An illustration of a portion of the cross-section taken by line I-I' shown. Figure 8A This is a cross-sectional view of a portion of the third gate electrode pattern GAT3.

[0102] Figure 8B It is along Figure 7 An illustration of a portion of the cross-section taken by line II-II' shown. Figure 8B This is a cross-sectional view of a portion of the second gate electrode pattern GAT2.

[0103] According to an embodiment of the present invention, a plane parallel to the substrate member BL can be disposed below the second gate electrode pattern GAT2 and the third gate electrode pattern GAT3. For example, the upper surface of the substrate member BL can be disposed below the second gate electrode pattern GAT2. (See also...) Figure 8A The first angle R1 can be the angle formed between the normal extending from the substrate member BL and the segment extending from the sidewall of the third gate electrode pattern GAT3. (Refer to...) Figure 8B The second angle R2 can be the angle formed between the normal extending from the substrate member BL and the segment extending from the sidewall of the second gate electrode pattern GAT2.

[0104] The first angle R1 can be smaller than the second angle R2. As an example, the first angle R1 can be approximately 10.2 degrees, and the second angle R2 can be approximately 34.6 degrees.

[0105] Due to the material properties of the second gate electrode pattern GAT2 and the third gate electrode pattern GAT3, the first angle R1 and the second angle R2 can be the predetermined angles described above. When unnecessary portions of the conductive layer used to form the third gate electrode pattern GAT3 are removed during its formation, the first angle R1 decreases due to the material properties of titanium (Ti) and aluminum (Al). Conversely, when unnecessary portions of the conductive layer used to form the second gate electrode pattern GAT2 are removed during its formation, the second angle R2 becomes larger than the first angle R1 due to the material properties of molybdenum (Mo).

[0106] The values ​​of the first angle R1 and the second angle R2 are described by way of example in this disclosure, but the invention is not limited thereto. The first angle R1 and the second angle R2 may have other values.

[0107] According to embodiments of the present invention, the sides of each of the second gate electrode pattern GAT2 and the third gate electrode pattern GAT3 are linear. However, the present invention is not limited to what is shown, and the shape of the sides of the gate electrode patterns can be modified. For example, the sides of each of the second gate electrode pattern GAT2 and the third gate electrode pattern GAT3 may have a predetermined curvature.

[0108] According to an embodiment of the present invention, a plane parallel to the substrate member BL can be disposed below the second gate electrode pattern GAT2. A first tangent representing the first slope can be defined by drawing a tangent from the intersection of the plane parallel to the substrate member BL and the second gate electrode pattern GAT2.

[0109] According to an embodiment of the present invention, a plane parallel to the substrate member BL can be disposed below the third gate electrode pattern GAT3. A second tangent representing the second slope can be defined by drawing a tangent from the intersection of the plane parallel to the substrate member BL and the third gate electrode pattern GAT3.

[0110] The first slope can be less than the second slope. Therefore, the slope of the first tangent line can be less than the slope of the second tangent line.

[0111] Figure 9A yes Figure 7 The illustration shows a partial layout of the second gate electrode pattern GAT2. The second gate electrode pattern GAT2 may include multiple first lines LN1 and connecting lines CLN.

[0112] According to embodiments of the present invention, each of the plurality of first lines LN1 may extend in a predetermined direction. For example, each of the plurality of first lines LN1 may extend in a second direction DR2. The plurality of first lines LN1 may be configured to transmit data signals to a plurality of pixels PX.

[0113] The multiple pixels PX may include a first green pixel, a first red pixel, a first blue pixel, a second green pixel, a second red pixel, and a second blue pixel.

[0114] Multiple first lines LN1 may include first sub-lines SLN1 to sixth sub-lines SLN6. The first sub-line SLN1 may be located at the leftmost position of the multiple first lines LN1 in the first direction DR1, and the second sub-lines SLN2 to sixth sub-lines SLN6 may be arranged continuously from left to right.

[0115] Additionally, the connecting line CLN can be installed separately from multiple first lines LN1. For example, the connecting line CLN can be placed between the third sub-line SLN3 and the fourth sub-line SLN4.

[0116] In an embodiment of the invention, the first sub-line SLN1 can be configured to transmit a data signal to the first green pixel. The second sub-line SLN2 can be configured to transmit a data signal to the first red pixel. The third sub-line SLN3 can be configured to transmit a data signal to the first blue pixel. The fourth sub-line SLN4 can be configured to transmit a data signal to the second green pixel. The fifth sub-line SLN5 can be configured to transmit a data signal to the second red pixel, and the sixth sub-line SLN6 can be configured to transmit a data signal to the second blue pixel. The connecting line CLN can be configured to transmit data signals to the first green pixel and the second green pixel via the first sub-line SLN1 and the fourth sub-line SLN4, respectively.

[0117] The specific process for transmitting data signals is described below. Each of the multiple first lines LN1 can be configured to transmit the data signal to the demultiplexer DMX, which can be configured to transmit the received data signal to the corresponding pixel PX among the multiple pixels PX.

[0118] Figure 9B This involves adding multiple second lines LN2 from the third gate electrode pattern GAT3. Figure 9A The diagram illustrates this. The third gate electrode pattern GAT3 may include multiple second lines LN2. Figure 9B It also includes Figure 9A Illustration of multiple second lines LN2 not included in the diagram.

[0119] Multiple second lines LN2 can be configured to receive data signals from the data drive circuit DIC and transmit the data signals to multiple first lines LN1.

[0120] Multiple second lines LN2 may include a seventh sub-line SLN7 to a ninth sub-line SLN9. The seventh sub-line SLN7 may be located on the leftmost side of the multiple second lines LN2 in the first direction DR1, and the eighth sub-line SLN8 and the ninth sub-line SLN9 may be located consecutively from left to right.

[0121] In embodiments of the present invention, the seventh sub-line SLN7 can be configured to transmit data signals to the first red pixel and the second red pixel via the second sub-line SLN2 and the fifth sub-line SLN5. The eighth sub-line SLN8 can be configured to transmit data signals to the first green pixel and the second green pixel via the connecting line CLN, the first sub-line SLN1, and the fourth sub-line SLN4. The ninth sub-line SLN9 can be configured to transmit data signals to the first blue pixel and the second blue pixel via the third sub-line SLN3 and the sixth sub-line SLN6.

[0122] Figure 9C This involves adding multiple third lines LN3 to the first source-drain electrode pattern SD1. Figure 9BThe diagram illustrates this. The first source-drain electrode pattern SD1 may include multiple third lines LN3. Figure 9C It also includes Figure 9B Illustration of multiple third lines LN3 not included.

[0123] According to an embodiment of the present invention, each of the plurality of third lines LN3 can be coupled with... Figure 9A The multiple first lines LN1 shown extend in the direction where they intersect. For example, each of the multiple third lines LN3 may extend in the first direction DR1.

[0124] Multiple third lines LN3 may include tenth sub-line SLN10 to thirteenth sub-line SLN13. Tenth sub-line SLN10 may be located at the top of the multiple third lines LN3 in the second direction DR2, and eleventh sub-line SLN11 to thirteenth sub-line SLN13 may be continuously arranged from top to bottom.

[0125] The tenth sub-line SLN10 can be configured to electrically connect the first sub-line SLN1 and the fourth sub-line SLN4 to each other.

[0126] The eleventh sub-line SLN11 can be configured to electrically connect the second sub-line SLN2 and the fifth sub-line SLN5 to each other.

[0127] The twelfth sub-line SLN12 can be configured to electrically connect the third sub-line SLN3 and the sixth sub-line SLN6 to each other.

[0128] The thirteenth sub-line SLN13 can be configured to electrically connect the connecting line CLN to the eighth sub-line SLN8.

[0129] The connecting line CLN can be configured to electrically connect the tenth sub-line SLN10 and the thirteenth sub-line SLN13 to each other.

[0130] Figure 9D It is along Figure 7 An illustration of a portion of the cross-section taken by line III-III' shown.

[0131] Will Figure 9D The components shown are Figure 6 The components shown are compared, and components with the same reference numerals can be components formed by the same process.

[0132] Furthermore, for convenience, the terminology used in this disclosure may differ. Therefore, terms related to [specific terms] can be omitted. Figure 6 The description is the same as the description.

[0133] According to an embodiment of the present invention, a plurality of contact holes CNT1 to CNT4 may be defined in an interlayer insulating layer (ILD). The plurality of contact holes CNT1 to CNT4 may include a first contact hole CNT1, a second contact hole CNT2, a third contact hole CNT3, and a fourth contact hole CNT4.

[0134] The first contact hole CNT1 can be superimposed on any one of the plurality of third wires LN3 and a portion of the plurality of first wires LN1. For example, the first contact hole CNT1 can be superimposed on each of the tenth sub-wire SLN10 and the fourth sub-wire SLN4. For example, the first contact hole CNT1 can be disposed between the tenth sub-wire SLN10 and the fourth sub-wire SLN4. The fourth sub-wire SLN4 and the tenth sub-wire SLN10 can be electrically connected to each other through the first contact hole CNT1.

[0135] The second contact hole CNT2 can be superimposed on any one of the multiple third wires LN3 and the connecting wire CLN. For example, the second contact hole CNT2 can be superimposed on the tenth sub-wire SLN10 and the connecting wire CLN. For example, the second contact hole CNT2 can be disposed between the tenth sub-wire SLN10 and the connecting wire CLN. The tenth sub-wire SLN10 and the connecting wire CLN can be electrically connected to each other through the second contact hole CNT2.

[0136] The third contact hole CNT3 can be stacked with the connecting line CLN and another of the multiple third lines LN3. For example, the third contact hole CNT3 can be stacked with the connecting line CLN and the thirteenth sub-line SLN13. The third contact hole CNT3 can be located between the connecting line CLN and the thirteenth sub-line SLN13. The connecting line CLN and the thirteenth sub-line SLN13 can be electrically connected to each other through the third contact hole CNT3.

[0137] The fourth contact hole CNT4 can be stacked with another of the multiple third wires LN3 and a portion of the multiple second wires LN2. For example, the fourth contact hole CNT4 can be stacked with the thirteenth sub-wire SLN13 and the eighth sub-wire SLN8. For example, the fourth contact hole CNT4 can be located between the thirteenth sub-wire SLN13 and the eighth sub-wire SLN8. The thirteenth sub-wire SLN13 and the eighth sub-wire SLN8 can be electrically connected to each other through the fourth contact hole CNT4.

[0138] Therefore, data signals can be transmitted to the corresponding pixel PX among the multiple pixels PX via lines that are electrically connected to each other through the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3 and the fourth contact hole CNT4.

[0139] Figure 10A Is with Figure 3 The illustration shows an embodiment of another layout AA-1 corresponding to the portion marked with AA shown.

[0140] Figure 10B This is an illustration of multiple first lines LN1 and connecting lines CLN-1 in the second gate electrode pattern GAT2. The second gate electrode pattern GAT2 may include multiple first lines LN1 and connecting lines CLN-1.

[0141] exist Figure 10B In this configuration, the fourth sub-line SLN4 and the connecting line CLN-1 can be in contact with each other. For example, the fourth sub-line SLN4 and the connecting line CLN-1 can be a single integrated unit. The details mentioned above can be omitted. Figure 9A The description is essentially the same as the other descriptions to avoid redundancy.

[0142] Figure 10C This involves adding multiple second lines LN2 from the third gate electrode pattern GAT3. Figure 10B The diagram illustrates this. The third gate electrode pattern GAT3 may include multiple second lines LN2. Figure 10C It also includes Figure 10B The diagram does not include multiple second-line LN2 lines. In the following text, regarding... Figure 10C The detailed description above is related to the above. Figure 9B The descriptions are essentially the same, so they can be omitted.

[0143] Figure 10D This involves adding multiple third lines LN3 to the first source-drain electrode pattern SD1. Figure 10C The diagram illustrates this. The first source-drain electrode pattern SD1 may include multiple third lines LN3. Figure 10D This is an illustration with multiple third lines (LN3) added. In the following text, regarding... Figure 10D The detailed description above is related to the above. Figure 9C The descriptions are essentially the same, so they can be omitted.

[0144] Figure 10E It is along Figure 10A An illustration of a portion of the cross-section taken by line IV-IV' shown.

[0145] In this disclosure, the definitions of stacked structures and terms are consistent with those used for... Figure 6 The descriptions are essentially the same, so they can be omitted.

[0146] According to an embodiment of the present invention, a plurality of contact holes CNT1-1 to CNT3-1 may be defined in an interlayer insulating layer (ILD). The plurality of contact holes CNT1-1 to CNT3-1 may include a first contact hole CNT1-1, a second contact hole CNT2-1, and a third contact hole CNT3-1.

[0147] The first contact hole CNT1-1 can be superimposed on any one of the multiple third wires LN3 and a portion of the multiple first wires LN1 or the connecting wire CLN-1. For example, the first contact hole CNT1-1 can be superimposed on the tenth sub-wire SLN10 and the fourth sub-wire SLN4, or on the tenth sub-wire SLN10 and the connecting wire CLN-1. Additionally, the fourth sub-wire SLN4 and the connecting wire CLN-1 can be in contact with each other. The fourth sub-wire SLN4 or the connecting wire CLN-1 and the tenth sub-wire SLN10 can be electrically connected to each other through the first contact hole CNT1-1.

[0148] The second contact hole CNT2-1 can be stacked with connecting line CLN-1 and another of the multiple third lines LN3. For example, the second contact hole CNT2-1 can be stacked with connecting line CLN-1 and the thirteenth sub-line SLN13. Connecting line CLN-1 and the thirteenth sub-line SLN13 can be electrically connected to each other through the second contact hole CNT2-1.

[0149] The third contact hole CNT3-1 can be stacked with another of the multiple third wires LN3 and a portion of the multiple second wires LN2. For example, the third contact hole CNT3-1 can be stacked with the thirteenth sub-wire SLN13 and the eighth sub-wire SLN8. The thirteenth sub-wire SLN13 and the eighth sub-wire SLN8 can be electrically connected to each other through the third contact hole CNT3-1.

[0150] Therefore, data signals can be transmitted to the corresponding pixel PX among the multiple pixels PX via a line electrically connected through the first contact hole CNT1-1, the second contact hole CNT2-1 and the third contact hole CNT3-1.

[0151] Figure 11A Is with Figure 3 The illustration shows an embodiment of layout AA-2 corresponding to the portion marked AA.

[0152] Figure 11B This is an illustration of multiple first lines LN1 in the second gate electrode pattern GAT2. The second gate electrode pattern GAT2 may include multiple first lines LN1. Figure 10B The difference is that the second gate electrode pattern GAT2 includes multiple first lines LN1 and does not include Figure 10B The connecting wire CLN-1 in the middle. In the following text, regarding... Figure 11B The detailed description above is related to the above. Figure 9A The descriptions are essentially the same, so they can be omitted.

[0153] Figure 11C This involves adding multiple second lines LN2 from the third gate electrode pattern GAT3. Figure 11B The diagram illustrates this. The third gate electrode pattern GAT3 may include multiple second lines LN2. Figure 11C It also includes Figure 11B The illustration shows several second lines of LN2 not included in the diagram. In the following text, regarding... Figure 11C The detailed description above is related to the above. Figure 9B The descriptions are essentially the same, so they can be omitted.

[0154] Figure 11D This involves adding multiple third lines LN3 from the first source-drain electrode pattern SD1. Figure 11C An exemplary illustration is provided. The first source-drain electrode pattern SD1 may include multiple third lines LN3. Figure 11D It also includes Figure 11C The illustration shows several third lines LN3 not included in the diagram. In the following text, regarding... Figure 11D The detailed description above is related to the above. Figure 9C The descriptions are essentially the same, so they can be omitted.

[0155] Figure 11E The connection line CLN-2 of the second source-drain electrode pattern SD2 is added to... Figure 11D The illustration shows that the second source-drain electrode pattern SD2 may include the connecting line CLN-2. Figure 11E It also includes Figure 11D The diagram shows the connection line CLN-2, which is not included in the diagram. Connection line CLN-2 can electrically connect the tenth sub-line SLN10 and the thirteenth sub-line SLN13 to each other.

[0156] Figure 11F It is along Figure 11A A diagram illustrating a portion of a cross-section taken by line V-V'. In this disclosure, the definitions of stacked structures and terms are consistent with those above regarding... Figure 6 The descriptions are essentially the same, so they can be omitted.

[0157] Reference Figure 11F The first contact hole CNT1-2 and the second contact hole CNT2-2 can be defined in the interlayer insulating layer ILD. In addition, the third contact hole CNT3-2 and the fourth contact hole CNT4-2 can be formed in the first via insulating layer VIA1.

[0158] The first contact hole CNT1-2 can be superimposed on any one of the multiple third wires LN3 and any one of the multiple first wires LN1. For example, the first contact hole CNT1-2 can be superimposed on the tenth sub-wire SLN10 and the fourth sub-wire SLN4. For example, the first contact hole CNT1-2 can be disposed between the tenth sub-wire SLN10 and the fourth sub-wire SLN4. The fourth sub-wire SLN4 and the tenth sub-wire SLN10 can be electrically connected to each other through the first contact hole CNT1-2.

[0159] The second contact hole CNT2-2 can be superimposed on another of the plurality of third wires LN3 and any of the plurality of second wires LN2. For example, the second contact hole CNT2-2 can be superimposed on the thirteenth sub-wire SLN13 and the eighth sub-wire SLN8. For example, the second contact hole CNT2-2 can be located between the thirteenth sub-wire SLN13 and the eighth sub-wire SLN8. The thirteenth sub-wire SLN13 and the eighth sub-wire SLN8 can be electrically connected to each other through the second contact hole CNT2-2.

[0160] The third contact hole CNT3-2 can be stacked with any one of the multiple third wires LN3 and the connecting wire CLN-2. For example, the third contact hole CNT3-2 can be stacked with the tenth sub-wire SLN10 and the connecting wire CLN-2. For example, the third contact hole CNT3-2 can be located between the tenth sub-wire SLN10 and the connecting wire CLN-2. The tenth sub-wire SLN10 and the connecting wire CLN-2 can be electrically connected to each other through the third contact hole CNT3-2.

[0161] The fourth contact hole CNT4-2 can be superimposed on the connecting line CLN-2 and another of the multiple third lines LN3. For example, the fourth contact hole CNT4-2 can be superimposed on the connecting line CLN-2 and the thirteenth sub-line SLN13. For example, the fourth contact hole CNT4-2 can be located between the connecting line CLN-2 and the thirteenth sub-line SLN13. The connecting line CLN-2 and the thirteenth sub-line SLN13 can be electrically connected to each other through the fourth contact hole CNT4-2.

[0162] Therefore, data signals can be transmitted to the corresponding pixel PX among the multiple pixels PX via lines that are electrically connected to each other through the first contact hole CNT1-2, the second contact hole CNT2-2, the third contact hole CNT3-2 and the fourth contact hole CNT4-2.

[0163] Figure 12 This is an exemplary block diagram of an electronic device ED according to an embodiment of the present invention.

[0164] Reference Figure 12 An electronic device ED according to an embodiment of the present invention may include a display module DPM, a processor PCS, a memory MMR, and a power module PM.

[0165] The processor PCS may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller.

[0166] The memory (MMR) can be configured to store data information for the operation of the processor (PCS) or the display module (DPM). In applications where the processor (PCS) operates with data stored in the memory (MMR), the display module (DPM) can be configured to receive image data signals and / or input control signals, and process the received signals to output image information through a display screen.

[0167] A power module (PM) may include a power module (such as a power adapter or battery device) and a power conversion module, which converts the power supplied by the power module to generate power for the operation of an electronic device (ED).

[0168] At least one of the components of the above-described electronic device ED may be included in the display device according to the above embodiments of the present invention. Furthermore, some modules that are functionally included in a single module may be included in the display device, and other modules may be disposed separately from the display device. For example, the display module DPM may be included in the display device, and the processor PCS, memory MMR, and power module PM may be disposed within the electronic device ED as other devices besides the display device.

[0169] Figure 13 A schematic diagram of an electronic device according to an embodiment of the present invention is shown.

[0170] Reference Figure 13 Various electronic devices having a display device according to embodiments of the present invention may include not only electronic devices configured to display images (such as smartphones ED-1a, tablet PCs ED-1b, laptops ED-1c, TVs ED-1d, and desktop monitors ED-1e), but also wearable electronic devices (such as smart glasses ED-2a, head-mounted displays ED-2b, and smartwatches ED-2c) and vehicle electronic devices ED-3 (such as CIDs (central information displays) and interior mirror displays installed on the dashboard, central instrument panel, and instrument cluster of a car) that include a display module.

[0171] Although the present invention has been described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display panel, the display panel comprising: The base component includes a first region and a second region that at least partially surrounds the first region; Multiple pixels are set on the first region; Multiple first lines are disposed on the second region and configured to transmit electrical signals to the multiple pixels, wherein each of the multiple first lines extends in a predetermined direction; A first insulating layer covers the plurality of first lines; The second line is disposed on the first insulating layer; A second insulating layer is disposed on the first insulating layer and covers the second wire; A plurality of third lines are disposed on the second insulating layer, wherein each of the plurality of third lines extends in a direction intersecting the predetermined direction, and wherein at least one of the plurality of third lines overlaps with the plurality of first lines; A third insulating layer is disposed on the second insulating layer and covers the plurality of third wires; and A connecting line extends in the predetermined direction and overlaps with at least one of the plurality of third lines, wherein the connecting line is configured to electrically connect a portion of the plurality of first lines and the second line to each other.

2. The display panel according to claim 1, in, Each of the plurality of first lines has a first thickness, and the second line has a second thickness greater than the first thickness.

3. The display panel according to claim 2, in, Each of the plurality of first lines includes a first metallic material, and the second line includes a second metallic material that is different from the first metallic material.

4. The display panel according to claim 3, in, The first metallic material includes molybdenum, and the second metallic material includes at least one of titanium and aluminum.

5. The display panel according to claim 1, in, The connecting wire is positioned below the first insulating layer.

6. The display panel according to claim 5, in, The second insulating layer defines a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole. Wherein, the first contact hole overlaps with one of the plurality of third lines and a portion of the plurality of first lines. The second contact hole overlaps with one of the plurality of third lines and the connecting line. The third contact hole overlaps with another third line among the plurality of third lines and the connecting line, and The fourth contact hole overlaps with another third line and the second line among the plurality of third lines.

7. The display panel according to claim 5, in, The second insulating layer defines a first contact hole, a second contact hole, and a third contact hole, and the connecting wire overlaps with a portion of the plurality of first wires. The first contact hole overlaps with one of the plurality of third lines. Wherein, the first contact hole overlaps with a portion of the connecting line or the plurality of first lines. Wherein, the second contact hole overlaps with another third line among the plurality of third lines and the connecting line, and The third contact hole overlaps with another third line and the second line among the plurality of third lines.

8. The display panel according to claim 4, in, The connecting wire is disposed on the third insulating layer.

9. The display panel according to claim 8, in, The second insulating layer defines a first contact hole and a second contact hole. The third insulating layer defines a third contact hole and a fourth contact hole. Wherein, the first contact hole overlaps with one of the plurality of third lines and a portion of the plurality of first lines. The second contact hole overlaps with another third line and the second line among the plurality of third lines. Wherein, the third contact hole overlaps with the connecting line and one of the plurality of third lines, and The fourth contact hole overlaps with the connecting line and another third line among the plurality of third lines.

10. The display panel according to claim 4, further comprising: The data driving circuit is disposed in the second region; as well as A demultiplexer is configured to receive a data signal from the data driving circuit and provide the received data signal to the plurality of pixels, wherein the demultiplexer is positioned between the data driving circuit and the first region. At least one of the plurality of first lines, second lines, plurality of third lines, and connecting lines is positioned between the data driving circuit and the demultiplexer.

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