Test structure and test method for monitoring metal silicide barrier layer process
By designing a PN junction test structure in semiconductor manufacturing and monitoring the metal silicide barrier layer using current-voltage characteristic curves, the problem of inaccurate anomaly location in existing technologies has been solved. This achieves highly sensitive and accurate fault location, reduces the risk of misjudgment, and simplifies the analysis process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies cannot accurately locate anomalies in the metal silicide barrier layer, resulting in insufficient sensitivity and accuracy in monitoring.
A test structure including a PN junction is designed. A metal silicide barrier layer is set at the interface between the P-type and N-type doped regions. The abnormality of the barrier layer is judged by the current-voltage characteristic curve, and the electrical characteristics of the PN junction are monitored.
It achieves highly sensitive monitoring of anomalies in metal silicide barrier layers, reduces the risk of false positives and false negatives, has accurate fault location capabilities, simplifies the anomaly analysis process, and is low in cost and easy to integrate into existing processes.
Smart Images
Figure CN121666034A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a test structure and test method for monitoring metal silicide barrier layer processes. Background Technology
[0002] Salicide (self-aligned metal silicide) processing is a key technology in semiconductor manufacturing, primarily aimed at reducing the series and contact resistances of the gate, source, and drain regions of MOS transistors, thereby improving device switching speed and performance. However, in certain circuit structures, it is necessary to intentionally maintain higher resistance or prevent silicide formation in specific areas. These areas include: manufacturing high-resistance resistors; and in some digital or analog circuits, utilizing the high sheet resistance of un-silicided monocrystalline or polycrystalline silicon to fabricate high-value resistor devices. Typically, specialized test structures are designed in process monitoring to monitor the quality of metal silicide formation. These test structures directly monitor the metal silicide resistance; the quality of the metal silicide directly affects the resistance of the test structure. When the metal silicide thickness and quality are normal, the test structure resistance is low; when metal silicide formation is abnormal, the test structure resistance is high. While current technologies can detect metal silicide anomalies during process monitoring, they cannot precisely pinpoint the specific steps causing the anomalies.
[0003] Existing WTA test structures include monitoring structures for the resistance of the metal silicide barrier layer (SAB). However, testing this resistance only indicates an anomaly in the SAB resistance itself, without pinpointing a problem with the SAB barrier layer. This monitoring structure is typically designed as follows: Figure 1 The SAB resistor test structure shown has a metal silicide barrier layer 700 covering a region with a single doping type (P-type doped region 600), and contact holes 800 are provided at both ends of the P-type doped region 600. Since this test structure itself is a high-resistance resistor, when a process anomaly occurs, such as when the critical dimension of the metal silicide barrier layer on the test structure is too small during the process, the metal silicide barrier layer cannot completely cover the surface of the SAB resistor, causing metal silicide to form at the edges of the SAB resistor. In this case, the sheet resistance of the SAB resistor will only fluctuate slightly, often not easily detected in the early stages of the process anomaly. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a test structure and test method that can more sensitively and accurately monitor whether the metal silicide barrier layer is abnormal.
[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: providing a test structure for monitoring the metal silicide barrier layer process, including a PN junction, wherein the PN junction includes interconnected P-type doped regions and N-type doped regions, and the boundary between the P-type doped regions and the N-type doped regions forms a boundary region of the PN junction, and a metal silicide barrier layer is disposed above the boundary region of the PN junction; the metal silicide barrier layer is used to prevent the formation of metal silicide in the boundary region; a first contact hole is formed in the P-type doped region, and a first metal contact is formed on the first contact hole; a second contact hole is formed in the N-type doped region, and a second metal contact is formed on the second contact hole.
[0006] Furthermore, when the metal silicide barrier layer process is normal, the test structure exhibits the unidirectional conduction characteristics of a diode; when the metal silicide barrier layer process is abnormal, leading to abnormal metal silicide formation, the test structure exhibits the bidirectional conduction characteristics of a resistor.
[0007] Furthermore, the types of the P-type doped region include: P-type substrate, P-type well, or P-type heavily doped region.
[0008] Furthermore, the types of the N-type doped regions include: N-type substrates, N-type wells, or heavily doped N-type regions.
[0009] Furthermore, the PN junction is formed on monocrystalline silicon or polycrystalline silicon.
[0010] Furthermore, the material of the metal silicide barrier layer is silicon nitride or silicon dioxide.
[0011] Furthermore, the metal silicide barrier layer completely covers the boundary region of the PN junction.
[0012] Furthermore, the junction region of the PN junction includes a depletion layer formed between the P-type doped region and the N-type doped region due to the doping concentration distribution.
[0013] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a test method for monitoring the metal silicide barrier layer process, using the aforementioned test structure for monitoring the metal silicide barrier layer process, including the following steps: A test voltage is applied to the test pads led out through the first metal contact and the second metal contact; Measure the current-voltage data flowing through the test structure; Based on the current-voltage data, the electrical characteristics of the test structure are determined to be either diode characteristics or resistive characteristics, in order to monitor whether the metal silicide barrier layer process is abnormal.
[0014] Furthermore, the step of determining whether the electrical characteristics of the test structure are diode characteristics or resistive characteristics based on the current-voltage data, in order to monitor whether the metal silicide barrier layer process is abnormal, includes the following sub-steps: If the test structure is conducting under forward bias and cut off under reverse bias, it is determined to have diode characteristics, the metal silicide barrier layer process is normal, and the PN junction structure is intact. If the test structure conducts under both forward and reverse bias, and the current is proportional to the voltage, then it is determined to have resistive characteristics, the metal silicide barrier layer process is abnormal, and the structure is damaged due to the formation of metal silicide at the PN junction.
[0015] The test structure and method for monitoring the metal silicide barrier layer process of the present invention have at least the following beneficial effects: The present invention creatively couples the physical integrity of the metal silicide barrier layer with the electrical characteristics of the PN junction diode, realizing the transformation from quantitative change to qualitative change, making the monitoring signal extremely significant and the sensitivity far higher than the traditional scheme that relies on measuring the slight fluctuation of the resistance value, and can accurately capture early process fluctuations; The detection standard is based on whether the current-voltage characteristic curve shows diode characteristics or resistance characteristics. This black-and-white criterion is clear and intuitive, which greatly reduces the risk of misjudgment and missed judgment caused by test noise or environmental fluctuations, and ensures the high reliability of the monitoring results; It has accurate fault location capability. The abnormality of the test results can directly and uniquely pinpoint the root cause of the problem to the metal silicide barrier layer process step, which greatly simplifies the online anomaly analysis process and shortens the problem troubleshooting time; The test structure can be fabricated using the existing doping and thin film deposition steps in the standard CMOS process, without the need for additional masks or special processes, and is easy to integrate into the existing process monitoring system (such as WAT testing), with low implementation cost and high practical value. Attached Figure Description
[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of a prior art structure for monitoring the resistance of a metal silicide barrier layer.
[0017] Figure 2 This is a schematic diagram of one embodiment of the test structure for monitoring the metal silicide barrier layer process of the present invention.
[0018] Figure 3 This is a flowchart of one embodiment of the test method for monitoring the metal silicide barrier layer process of the present invention. The meanings of the labels in the attached diagram are as follows: Figure 1Middle: P-type doped region 600; metal silicide barrier layer 700; contact hole 800; Figure 2 In the middle: P-type doped region 100; N-type doped region 200; metal silicide barrier layer 300; first contact hole 400; second contact hole 500. Detailed Implementation
[0019] The invention will now be further described with reference to the accompanying drawings.
[0020] The test structure of this invention binds the physical integrity of the metal silicide barrier layer to the electrical functionality of a PN junction diode, so that any minor failure of the barrier layer will directly and significantly damage the characteristics of the PN junction, thereby transforming a difficult-to-measure process parameter change into an easily detectable electrical characteristic change.
[0021] Please see Figure 2 One embodiment of the test structure for monitoring the metal silicide barrier layer process of the present invention includes a PN junction, wherein the PN junction includes interconnected P-type doped regions 100 and N-type doped regions 200. The test structure described in this embodiment refers to the structure under test. Specifically, the type of the P-type doped region 100 can be any region formed by P-type implantation during the process, including but not limited to a P-type substrate, a P-type well, or a heavily P-type doped region. The type of the N-type doped region 200 can be any region formed by N-type implantation during the process, including but not limited to an N-type substrate, an N-type well, or a heavily N-type doped region. The PN junction is formed on a single-crystal silicon active region, or it can be formed on polycrystalline silicon.
[0022] The boundary region of the PN junction is formed at the junction of the P-type doped region 100 and the N-type doped region 200. The test structure also includes a metal silicide barrier layer 300 disposed above the boundary region of the PN junction. Specifically, the boundary region of the PN junction includes a depletion layer formed between the P-type doped region 100 and the N-type doped region 200 due to the doping concentration distribution. The metal silicide barrier layer 300 is used to prevent the formation of metal silicides in this boundary region. The material of the metal silicide barrier layer 300 is silicon nitride or silicon dioxide. The width of the metal silicide barrier layer 300 needs to be determined according to the feature dimensions of the process platform to ensure that it can completely cover the boundary region of the PN junction.
[0023] The P-type doped region 100 has a first contact hole 400, on which a first metal contact (not shown in the figure) is formed; the N-type doped region 200 has a second contact hole 500, on which a second metal contact (not shown in the figure) is formed. The first metal contact is used to connect to an external first test pad (not shown in the figure), and the second metal contact is used to connect to an external second test pad (not shown in the figure). When the metal silicide barrier layer 300 is processed normally, the test structure exhibits the unidirectional conduction characteristics of a diode; when the metal silicide barrier layer 300 process is abnormal, resulting in abnormal metal silicide formation, the test structure exhibits the bidirectional conduction characteristics of a resistor.
[0024] The design principle of this invention: The core characteristic of a PN junction is unidirectional conductivity. During normal operation, current can only flow from the P-region to the N-region, i.e., forward bias. Reverse bias cuts off the current. This asymmetric, nonlinear current-voltage relationship is the essence of diode function. This invention precisely positions the metal silicide barrier layer 300 as a protective layer for the functional region of the PN junction. The metal silicide barrier layer 300 is designed to completely cover and protect the junction region (depletion layer) of the PN junction, which is extremely sensitive to interface defects. As long as the metal silicide barrier layer 300 is intact, the depletion layer will not be contaminated by metal, and the rectification characteristics of the PN junction will be maintained. If the metal silicide barrier layer 300 fails due to process abnormalities (such as too small a critical dimension, etching through-holes, etc.), in subsequent metal silicide processes, the metal will directly react with the silicon at the depletion layer to generate low-resistivity metal silicides. The metal silicide formed at the PN junction interface is equivalent to connecting an extremely low resistance in parallel between the P-type doped region 100 and the N-type doped region 200, thus completely short-circuiting the PN junction. This completely destroys the depletion region, causing the PN junction to lose its unidirectional conductivity. This transition from a nonlinear device (diode) to a linear device (resistor) is very evident in electrical tests.
[0025] This invention also discloses a test method for monitoring the metal silicide barrier layer process, which is implemented based on the test structure for monitoring the metal silicide barrier layer process described in the above embodiments. Please refer to [link to relevant documentation]. Figure 3 This is a flowchart of one embodiment of the testing method for monitoring the metal silicide barrier layer process of the present invention. This embodiment specifically includes the following steps: S100. Apply a test voltage. Specifically, apply a test voltage to the test pads led out through the first and second metal contacts. The test pads include a first test pad and a second test pad. Using a precision semiconductor parameter analyzer, apply a linearly scanned DC voltage between the two pads of the test structure. The scan range typically covers the forward bias region (e.g., 0V to +1V) and reverse bias region (e.g., 0V to -1V or -5V) of the diode. S200. Measure the current-voltage data flowing through the test structure. Specifically, the first test pad and the second test pad are electrically connected to the P-type doped region 100 and the N-type doped region 200 of the test structure via a first metal contact and a second metal contact, respectively. While applying the test voltage, the current value flowing through the test structure is measured, and the current-voltage data is automatically recorded and generated. S300. Determine if there is an anomaly. Based on the current-voltage data, determine whether the electrical characteristics of the test structure are diode characteristics or resistive characteristics to monitor whether the metal silicide barrier layer 300 process is abnormal. Specifically, the test software automatically plots the current-voltage data into a current-voltage characteristic curve and performs real-time analysis and judgment based on a preset algorithm model. If the test structure is conducting under forward bias and cut off under reverse bias, it is determined to have diode characteristics, the metal silicide barrier layer 300 process is normal, and the PN junction structure is intact. Forward conduction means that when the voltage of the P-type doped region 100 is higher than the voltage of the N-type doped region 200 (forward bias) and exceeds the diode's turn-on voltage (the PN junction is approximately 0.6V-0.7V), the current increases exponentially with the voltage. Reverse cutoff means that when the voltage of the N-type doped region 200 is higher than the voltage of the P-type doped region 100 (reverse bias), the current value remains at an extremely low level (e.g., less than 1nA), and the curve almost coincides with the voltage axis.
[0026] If the test structure conducts under both forward and reverse bias, and the current is proportional to the voltage, then it is determined to have resistive characteristics. This indicates an abnormality in the metal silicide barrier layer 300 process, and structural damage occurs at the PN junction due to the formation of metal silicide. Specifically, if the current and voltage exhibit a direct proportional relationship passing through the origin across the entire scanning voltage range (including positive and negative voltages), and the current-voltage curve is a straight line, this indicates that the test structure has degenerated into a pure resistor.
[0027] This invention creatively couples the physical integrity of the metal silicide barrier layer with the electrical characteristics of the PN junction diode, achieving a qualitative leap from quantitative change. This results in a highly significant monitoring signal with sensitivity far exceeding traditional methods that rely on measuring minute fluctuations in resistance values, enabling precise capture of early process fluctuations. The detection standard is based on whether the current-voltage characteristic curve exhibits diode or resistive characteristics. This clear and intuitive criterion greatly reduces the risk of misjudgment and missed detection due to test noise or environmental fluctuations, ensuring high reliability of the monitoring results. It possesses precise fault location capabilities; anomalies in the test results can directly and uniquely pinpoint the root cause to the metal silicide barrier layer process steps, greatly simplifying the online anomaly analysis process and shortening troubleshooting time. This test structure can be fabricated using existing doping and thin film deposition steps in standard CMOS processes, requiring no additional masks or special processes. It is easily integrated into existing process monitoring systems (such as WAT testing), has low implementation costs, and possesses high practical value.
[0028] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.
Claims
1. A test structure for monitoring the process of a metal silicide barrier layer, characterized in that: The system includes a PN junction, comprising interconnected P-type doped regions and N-type doped regions. The boundary between the P-type and N-type doped regions forms a boundary region of the PN junction. A metal silicide barrier layer is disposed above the boundary region of the PN junction. The metal silicide barrier layer is used to prevent the formation of metal silicide in the boundary region. A first contact hole is formed in the P-type doped region, and a first metal contact is formed on the first contact hole. A second contact hole is formed in the N-type doped region, and a second metal contact is formed on the second contact hole.
2. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that, When the metal silicide barrier layer process is normal, the test structure exhibits the unidirectional conduction characteristics of a diode. When the abnormal metal silicide barrier layer process leads to abnormal metal silicide formation, the test structure exhibits bidirectional conduction characteristics of resistance.
3. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that, The types of P-type doped regions include: P-type substrate, P-type well, or P-type heavily doped region.
4. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that, The types of N-type doped regions include: N-type substrate, N-type well, or N-type heavily doped region.
5. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that: The PN junction is formed on monocrystalline silicon or polycrystalline silicon.
6. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that: The material of the metal silicide barrier layer is silicon nitride or silicon dioxide.
7. The test structure for monitoring the metal silicide barrier layer process as described in claim 1, characterized in that: The metal silicide barrier layer completely covers the junction region of the PN junction.
8. The test structure for monitoring the metal silicide barrier layer process as described in claim 7, characterized in that: The junction region of the PN junction includes the depletion layer formed between the P-type doped region and the N-type doped region due to the doping concentration distribution.
9. A test method for monitoring the process of metal silicide barrier layers, characterized in that, The test structure employing the monitoring metal silicide barrier layer process as described in any one of claims 1 to 8 includes the following steps: A test voltage is applied to the test pads led out through the first metal contact and the second metal contact; Measure the current-voltage data flowing through the test structure; Based on the current-voltage data, the electrical characteristics of the test structure are determined to be either diode characteristics or resistive characteristics, in order to monitor whether the metal silicide barrier layer process is abnormal.
10. The test method for monitoring the metal silicide barrier layer process as described in claim 9, characterized in that, The step of determining whether the electrical characteristics of the test structure are diode characteristics or resistive characteristics based on the current-voltage data, in order to monitor whether the metal silicide barrier layer process is abnormal, includes the following sub-steps: If the test structure is conducting under forward bias and cut off under reverse bias, it is determined to have diode characteristics, the metal silicide barrier layer process is normal, and the PN junction structure is intact. If the test structure conducts under both forward and reverse bias, and the current is proportional to the voltage, then it is determined to have resistive characteristics, the metal silicide barrier layer process is abnormal, and the structure is damaged due to the formation of metal silicide at the PN junction.