Method for improving thermal stability and film cracking margin of low-temperature high-tension silicon nitride film

Abstract

Mitigating wafer warpage of a semiconductor wafer includes depositing one or more backside layers that compensate for wafer warpage caused by one or more front side layers. Deposition of the backside layer stack may mitigate wafer warpage before and after annealing without changing the magnitude of wafer warpage compensated for by the backside layer stack. Each backside layer may be deposited by a backside deposition device.

Description

[0001] By incorporating via reference The PCT application form is filed together with this specification as part of this application. Each application listed in the concurrently filed PCT application form that claims a benefit or priority from this application is incorporated herein by reference in its entirety for all purposes.

[0002] Existing technology In semiconductor processing, it is often necessary to keep wafers substantially flat. However, during normal operation, wafers can experience wafer warpage. Wafer warpage can cause problems such as improper clamping by electrostatic chucks, failure of wafer transporters to hold the wafer, and pattern transfer issues during photolithography. Processes have been developed to control wafer warpage by keeping the wafer flat within process tolerances. One process involves depositing a film on the back side of the wafer to counteract any stresses that could cause wafer warpage.

[0003] The background description provided herein is for the purpose of presenting the general context of this disclosure. The work of the currently designated inventors, within the scope described in this background section and in the various aspects of the specification that could not be identified as prior art at the time of filing, neither expressly nor impliedly acknowledges that it is prior art to this disclosure. Summary of the Invention

[0004] Methods and systems for depositing films are disclosed herein. In one aspect of the embodiments herein, a method for reducing warpage in a substrate is proposed, comprising: receiving a substrate having one or more front-side layers on a front side of the substrate, wherein the one or more front-side layers cause warpage in the substrate; depositing a first back-side layer, wherein the first back-side layer has a first internal stress offset after annealing; and depositing a second back-side layer, wherein the second back-side layer has a second internal stress offset after annealing, the second internal stress offset being opposite to the first.

[0005] In some embodiments, the first back-side layer includes more silicon-hydrogen bonds than the second back-side layer. In some embodiments, the method further includes annealing the substrate, wherein the combined internal stress of the first and second back-side layers changes by less than 10% after annealing. In some embodiments, annealing is performed at a temperature greater than about 700°C. In some embodiments, deposition of the first and second back-side layers is performed at a temperature less than about 500°C. In some embodiments, the deposition rate of the first or second back-side layer is at least about 300 Å per minute. In some embodiments, the first internal stress shift is a tensile stress shift. In some embodiments, the second internal stress shift is a compressive stress shift. In some embodiments, the first and second back-side layers comprise silicon nitrides. In some embodiments, each of the first and second back-side layers has an inherent internal stress magnitude of about 100 MPa to 1000 MPa. In some embodiments, both the first and second back-side layers have tensile internal stress. In some embodiments, the warpage of the substrate is about 300 μm or greater. In some embodiments, the warpage of the substrate is less than about 100 μm after deposition of the first back-side layer and the second back-side layer. In some embodiments, at least one of the one or more front-side layers includes a hard mask. In some embodiments, the one or more front-side layers include a stack of about 100 or more alternating layers. In some embodiments, the stack includes alternating oxide layers and nitride or polysilicon layers. In some embodiments, the first back-side layer and the second back-side layer have a thickness of about 0.1 μm to about 5 μm.

[0006] In another aspect of the embodiments described herein, a substrate is provided comprising: one or more front-side layers located on the front side of the substrate; a first back-side layer having a first internal stress offset after annealing; and a second back-side layer having a second internal stress offset after annealing, the second internal stress offset being opposite to the first. In some embodiments, if the one or more front-side layers are not compensated by the first back-side layer, the substrate has a warpage of about 300 μm or more. In some embodiments, the first internal stress offset is tensile, and the second stress offset is compressive. In some embodiments, if the one or more front-side layers are not compensated by the first back-side layer, the substrate has a warpage of about 300 μm or more. In some embodiments, the first back-side layer and the second back-side layer comprise silicon nitride. In some embodiments, the first back-side layer and the second back-side layer have a thickness of about 0.1 μm to about 5 μm. In some embodiments, the first back-side layer includes more silicon-hydrogen bonds than the second back-side layer. In some embodiments, if annealing is performed, the combined internal stress of the first and second back-side layers changes by less than 10% after annealing.

[0007] In another aspect of the embodiments herein, an apparatus for semiconductor processing is provided, the apparatus comprising: a processing chamber; and a controller including a memory and a processor, configured to: receive a substrate having one or more front-side layers on a front side of the substrate, wherein the one or more front-side layers cause warping in the substrate; deposit a first back-side layer, wherein the first back-side layer has a first type of internal stress offset after annealing; and deposit a second back-side layer, wherein the second back-side layer has a second type of internal stress offset after annealing, the second type of internal stress offset being the opposite of the first.

[0008] These and other features of the disclosed embodiments will be described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figures 1A and 1B show examples of unwarped and warped semiconductor wafers on an electrostatic chuck.

[0010] Figures 2A-C show examples of stress offset after heat treatment.

[0011] Figure 3 shows the FTIR spectra of two different films with tensile stress shift and compressive stress shift after annealing.

[0012] Figure 4 is a table of membrane stress properties corresponding to the membrane shown in Figure 3.

[0013] Figure 5 is a flowchart depicting some operations in semiconductor wafer processing.

[0014] Figures 6A and 6B show block diagrams of an exemplary substrate processing system.

[0015] Figure 7A shows an exemplary cross-section of the edge of the nozzle-base.

[0016] Figure 7B shows a top view of an example carrier ring.

[0017] Figure 8 shows a schematic diagram of an example processing system that can be used to perform the methods described herein. Detailed Implementation

[0018] the term The following terms are used throughout this specification: The terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). Besides semiconductor wafers, other artifacts that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. Artifacts can have a wide variety of shapes, sizes, and materials.

[0019] As used herein, “semiconductor device manufacturing operations” refers to operations performed during the manufacture of semiconductor devices. Typically, the entire manufacturing process comprises multiple semiconductor device manufacturing operations, each performed in its own specific semiconductor manufacturing tooling, such as plasma reactors, electroplating baths, chemical mechanical planarization tools, wet etching tools, and the like. Categories of semiconductor device manufacturing operations include subtractive processes, such as etching and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, substrate etching processes include processes that etch mask layers, or more generally, processes that etch any layers of material previously deposited on and / or otherwise left on the substrate surface. Such etching processes can etch stacks of layers within a substrate.

[0020] "Manufacturing equipment" refers to equipment in which manufacturing processes are performed. Manufacturing equipment typically has a processing chamber where workpieces reside during processing. Typically, when in use, manufacturing equipment performs one or more semiconductor device manufacturing operations. Examples of manufacturing equipment used for semiconductor device manufacturing include deposition reactors, such as electroplating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, as well as subtractive process reactors, such as dry etching reactors (e.g., chemical and / or physical etching reactors, wet etching reactors, and ashing tanks).

[0021] As used herein, “wafer warpage” can refer to the deformation of a wafer. This deformation may have radial and / or azimuth components. Examples of wafer warpage types include dome shapes, bowl shapes, and saddle shapes. Wafer warpage can occur during manufacturing, for example, due to stress on the wafer during material deposition on the active surface of the wafer substrate. Wafer warpage can occur during various manufacturing processes, such as when depositing large amounts of stacked material. Wafer warpage can complicate subsequent processing steps. For example, if the warpage is too large, the wafer may not be properly clamped. Furthermore, performing processing steps (such as photolithography) on an excessively warped wafer may produce poor results.

[0022] Wafer warpage can be measured as the deviation of the average or median distance from the wafer surface to a reference plane. In some embodiments, the median point of the wafer can be the center point (e.g., in the case of concave or dome-shaped warpage), or an edge point of the wafer and / or the average edge point of the wafer (e.g., in the case of flexural or convex warpage). In some embodiments, wafer warpage can be measured from the reference plane such that when the edge point of the wafer is below the reference plane, the edge point is considered to have negative warpage, and when the edge point of the wafer is above the reference plane, the edge point is considered to have positive warpage. In some embodiments, positive or negative warpage can be measured along a z-axis perpendicular to the reference plane.

[0023] Warped wafers Semiconductor device manufacturing typically involves stacking layers deposited on a wafer substrate. Generally, most of the deposition and other processes for forming the device occur on one side of the substrate, often referred to as the front side or front edge of the wafer. As the deposited layers accumulate, they introduce stress into the wafer. Large net tensile or compressive stresses can cause wafer warping, which is undesirable.

[0024] Warpage is particularly likely to occur when depositing large amounts of stacked material (e.g., in the context of 3D-NAND devices) or when depositing thick front-side layers. When warpage is significant, it can adversely affect subsequent processing steps. For example, if the warpage is too large, the wafer may not be properly clamped. Figures 1A and 1B illustrate wafers on electrostatic chucks. Figure 1A shows a wafer 102 on an electrostatic chuck 110. When wafer 102 is substantially flat for a specific process operation purpose, for example, with a warpage of about 100 μm or less, the wafer can be properly clamped, thus securing the wafer for subsequent processing steps. Figure 1B shows a warped wafer 104 on an electrostatic chuck 110. When the warpage is significant, the wafer may not be properly secured to the electrostatic chuck. Wafer warpage can cause other problems. For example, some processing steps (e.g., photolithography) are very precise, and if the wafer is not substantially flat, poor results are produced. This problem may manifest as photolithographic defocusing.

[0025] An exemplary stack that could cause these problems is one with alternating oxide and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example of a stack type that could cause warping includes alternating oxide and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of potentially problematic stack materials include, but are not limited to, tungsten and titanium nitride.

[0026] Material in the stack can be deposited using chemical vapor deposition (CVD) techniques, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or direct metal deposition (DMD). These examples are not intended to be limiting. Some of the disclosed embodiments may be useful whenever wafer stress and / or warping is caused by the presence of material on the front side of the wafer.

[0027] The front-side stack can be deposited as any number of layers and thickness. In examples, the stack comprises about 20 or more layers and has a total thickness of about 2 μm to about 4 μm. However, in some cases, the multilayer stack has about one hundred or more layers. In some embodiments, the multilayer stack may have about five hundred or more layers. In some embodiments, the multilayer stack may have about one thousand or more layers. For example, such a stack may have a thickness of about 4 μm to 12 μm.

[0028] The stress induced in the wafer by stacked components or other front-side deposits can be from about -500 MPa to about +500 MPa. In some embodiments, the resulting warpage is about 150 μm or greater, for example, more than about 300 μm, more than about 400 μm, or about 200 μm to about 400 μm (for a 300 mm wafer).

[0029] Another cause of wafer warpage may be the use of a front-side process with a thick, hard mask that has limited etch selectivity. In these embodiments, at least one of one or more front-side layers is a hard mask. The thick, hard mask may have internal stresses similar to those described above, for example, ranging from 0 MPa to approximately 500 MPa. The stresses induced by the hard mask can be tensile or compressive. A thick, hard mask can cause significant wafer warpage, for example, approximately 150 μm or greater.

[0030] Several techniques have been designed to combat warpage. When warpage becomes more severe, the deposition process can be adjusted to reduce or counteract the internal stress in the deposited layer. However, any such adjustments should not interfere with the process requirements of the manufacturing equipment. A commonly used technique for counteracting warpage is to deposit a film on the back side of the wafer.

[0031] Backside deposition can form high-stress films. If the backside layer has the same type of internal stress (tensile or compressive) and comparable in magnitude as the internal stress generated on the front side, the backside film effectively counteracts and reduces warpage.

[0032] Examples of back-side films used to counteract warpage include amorphous silicon, silicon oxide, silicon nitride, and silicon nitride. Currently, back-side films have high internal stress and are able to alleviate the stress exerted on the wafer by the front-side layer, thereby reducing or eliminating wafer warpage. Generally, the back-side layer is made of a film with high stress.

[0033] Until relatively recently, back-side film thickness remained relatively thin (e.g., <1µm) because the warpage caused by material deposition on the front side was relatively moderate. Therefore, downstream processes at existing technology nodes typically did not encounter the problems that the embodiments described herein aim to address. However, modern IC manufacturing techniques may produce substrates with front-side layers that exhibit more severe warpage than existing nodes. For example, some modern processes have limited etch selectivity between hard masks and etch materials but still use thick hard mask layers in operations that etch deep trenches or vias. In another example, the number of layers in the front-side stack has increased. For example, in existing nodes, stacks could be from about 32 to about 72 layers. Today, stacks can have hundreds or even thousands of layers, increasing the thickness and internal stress of the front-side layer. Typically, wafer warpage compensation is achieved by depositing a single back-side layer. As the degree of wafer warpage continues to increase, thicker back-side films must be deposited to compensate for wafer warpage. This leads to certain problems. Due to the larger internal stress present within the thick back-side layers, these layers may spontaneously form film cracks. For many membrane materials (e.g., stretchable silicon nitride membranes), cracks are observed in membranes of thickness required to compensate for warpage exceeding a critical warpage limit. These warpage limits are often referred to as "warpage cracking limits" or "crack margins".

[0034] In some implementations, the back-side film can be deposited at high temperatures with large internal tensile stresses to compensate for the tensile internal stresses of the front layers. However, in some implementations, the back-side layer may need to be deposited at lower temperatures to avoid annealing of one or more front layers (e.g., hard mask layers for etching). In some implementations, the back-side film used to counteract wafer warpage is deposited at low temperatures (e.g., below 400°C). During subsequent processing, the hard mask layer can be removed and a higher-temperature process can be performed, which allows the back-side film to be annealed. During annealing operations or heat treatments at high temperatures (e.g., above 800°C), the back-side film may experience changes in internal stress. This stress shift may increase the internal tensile stress above the cracking limit, leading to back-side film failure, or decrease the internal tensile stress, reducing the amount of wafer warpage that the back-side film can compensate for. Changes in internal stress are generally undesirable because additional deposition processes may be required to properly compensate for wafer warpage after changes in the internal stress of the previous back-side film during the annealing operation. This increases the complexity of equipment manufacturing and reduces overall production capacity.

[0035] Backside membrane stress offset compensation This paper discloses methods, systems, and techniques for maintaining the internal stress of a back-side layer deposited under low-temperature deposition conditions and subsequently annealed at high temperatures. This reduces the need for additional back-side film deposition, lowers the risk of wafer handling problems during subsequent wafer processing, and maintains wafer warpage compensation without back-side film cracking after annealing.

[0036] Figures 2A and 2B depict layers with tensile stress offset and compressive stress offset, respectively. In Figure 2A, substrate 200 has a tensile stress offset layer 211a, which has internal tensile stress (and is therefore “bowl-shaped”). Wafer warpage 203 is shown as a deflection from the center to the edge of the substrate and can be measured along an axis perpendicular to a plane tangent to the lowest point of the wafer curve (i.e., the solid line shown). After thermal cycling, the annealed tensile stress offset layer 211a has cracked, as shown in the cracked layer 211b with crack 213. Therefore, substrate 200a may have lower wafer warpage 204a when the cracked layer 211b has reduced its internal stress due to the cracking failure. In some embodiments, cracking may not necessarily affect wafer warpage; for example, wafer warpage 204a may be closer to or the same as wafer warpage 203, but cracking can create defects and compromise film integrity. For example, in downstream wet chemical processing, substances may diffuse into cracks and cause undesirable reactions.

[0037] In Figure 2B, substrate 200 has a compressive stress offset layer 215a and wafer warpage 203. The compressive stress offset layer 215a has internal tensile stress, similar to Figure 2A. After thermal cycling, the annealed compressive stress offset layer 215b has lower internal tensile stress, and therefore substrate 200b has reduced wafer warpage 204. In both Figures 2A and 2B, the internal stress offset after annealing reduces the ability of the back-side film to counteract wafer warpage. It should be understood that for Figures 2A and 2B (and 2C), greater wafer warpage indicates a greater ability of the back-side film to counteract wafer warpage from the front layer. The back-side film can be deposited on a flat wafer, and the resulting wafer warpage indicates how much wafer warpage the back-side film can counteract when deposited on a substrate with a front layer (which causes warpage and the substrate is therefore warped).

[0038] To address this issue, in some implementations, a combination of compressive stress offset layers and tensile stress offset layers can be deposited. By depositing both types of layers, wafer warpage can be appropriately compensated before and after the annealing operation, as the internal stress offsets of each type of layer cancel each other out. Figure 2C depicts such a case, where substrate 200 has a tensile stress offset layer 217a and a compressive stress offset layer 219a, as well as wafer warpage 203. After thermal cycling, substrate 200c has substantially the same wafer warpage 204c. The tensile stress offset layer 217b does not crack, and the larger internal tensile stress of the annealed tensile stress offset layer 217b has been offset by the reduced internal tensile stress of the annealed compressive stress offset layer 219b. In some implementations, the compressive stress offset layer 219a can be deposited on top of the tensile stress offset layer 217a, such that the annealed compressive stress offset layer 219b can offset and suppress cracking of the annealed tensile stress offset layer 217b. In some implementations, if the tensile stress offset layer 217a is the last back-side film deposited, it may still crack at the surface due to increased local internal stress.

[0039] The mechanism of internal stress shift under annealing conditions may be related to the proportions of NH, Si-H, and Si-N bonds in the film. Figure 3 depicts the FTIR spectra of two exemplary films (film A and film B) according to various embodiments described herein. Film A is a tensile stress-shifted film, and film B is a compressive stress-shifted film. Figure 4 presents a table of internal stresses for each film before and after annealing. As shown in Figure 3, compared to film B, film A has a smaller proportion of NH bonds 302 and a larger proportion of Si-H bonds 304 and Si-N bonds 306. During annealing, three different reactions may occur: Si-H+NH→Si-N+H2 (Equation 1) Si-H + Si-H → Si-Si + H2 (Equation 2) N-H+NH→N2+H2 (Equation 3) The kinetics of each reaction can depend on the proportions of different bond types in the membrane. Therefore, if there is a large proportion of Si-H and NH bonds, Equation 1 may have a larger reaction rate and thus an increase in Si-N formation, which may increase the internal tensile stress of the membrane. Conversely, if the proportions of Si-H or NH are low, the reaction rate of Equation 1 will be lower, and Equations 2 and 3 may have proportionally larger reaction rates, leading to a shift in compressive internal stress.

[0040] During annealing, the H2 and N2 formed by the above reactions can leave the membrane as gases, thus these reactions are essentially irreversible. During initial membrane deposition, hydrogen may be trapped in the membrane as part of the bonds shown, and during annealing or high-temperature treatment, the higher temperatures may drive these reactions to remove additional hydrogen from the membrane, leading to a shift in internal stress, depending on the relative proportions of each type of bond and therefore the reaction rate for each. After sufficient time under annealing conditions, the proportion of hydrogen in the membrane can be sufficiently reduced to significantly decrease the reaction rate, so that additional annealing does not further alter the internal stress.

[0041] The presence of hydrogen in the film may be caused by low deposition temperatures. Typically, the SiN films disclosed herein are deposited at high temperatures (e.g., above about 700°C or about 800°C) to drive the aforementioned reactions and remove hydrogen from the film. However, in some implementations, the back-side film can be deposited under processing condition limitations (which restrict the maximum temperature of the back-side film deposition process, e.g., less than about 450°C, less than about 500°C, less than about 550°C, less than about 600°C) to compensate for wafer warpage. For example, the front-side layer may undergo undesirable annealing at high temperatures, thus limiting the back-side film deposition conditions to a maximum temperature. Lower-temperature back-side layer deposition may introduce hydrogen into the film, which will then react during subsequent operations where the maximum temperature limit no longer exists and higher-temperature processing is required.

[0042] The ratios of Si-N, Si-H, and NH bonds can be controlled by the deposition conditions of the silicon nitride film (especially the relative flow rates of the silicon-containing precursor and the nitrogen-containing precursor). Although it is difficult to remove hydrogen from the film without annealing, the ratios of each type of bond can be controlled. Increasing the relative ratio of the silicon-containing precursor to the nitrogen-containing reactant increases the proportion of Si-H bonds in the resulting film, thus increasing the reaction rate of Formula 1 during subsequent annealing, resulting in a tensile stress-shifted film. Conversely, decreasing the relative ratio of the silicon-containing precursor to the nitrogen-containing reactant decreases the proportion of Si-H bonds in the resulting film and reduces the reaction rate of Formula 1, favoring Formula 2 and / or Formula 3, thus resulting in a compressive stress-shifted film. In some embodiments, the ratio of the silicon-containing precursor to the nitrogen-containing reactant (e.g., NH3) can be varied between 2:1 and 1:100, where a 2:1 ratio will produce a tensile stress-shifted film, while a 1:100 ratio will produce a compressive stress-shifted film. It should be understood that other gases may also be allowed to flow, including inert gases such as N2 or Ar, which help stabilize the plasma, which is ignited as part of the film deposition process disclosed herein, but does not otherwise react with the deposited film.

[0043] Figure 4 presents the film properties of exemplary films A, B, and A+B as shown in the FTIR spectra of Figure 3. Film A is a tensile stress-shifted film, which is shown as an increase in film stress after annealing. The last column indicates the maximum wafer warpage that this film can compensate for (without cracking after annealing). Because the tensile stress shift of film A increases after annealing, film A can only compensate for 170 µm of wafer warpage; otherwise, it would crack after tensile stress shifting. Conversely, film B has compressive stress shifting (negative stress is compressible), which similarly limits the wafer warpage it can compensate for, as it loses its internal stress after annealing. Depositing a compressive stress-shifted film with high initial warpage will cause it to crack before annealing, similar to the cracking of a tensile stress-shifted film after annealing.

[0044] By combining films A and B, the stress offsets of the two films can be adjusted to cancel each other out. As shown in film A+B, the combined film stress is essentially the same before and after annealing, allowing the back-side film to compensate for wafer warpage under both conditions. Because the stress of the bilayer film does not change significantly after annealing, it can compensate for a much higher maximum wafer warpage, as it does not crack like film A or have reduced tensile stress like film B. It should be understood that the thicknesses of the two films do not need to be the same; in the table of Figure 4, film A will account for a smaller proportion of the total thickness of film A+B than film B because film A has a larger internal stress offset after annealing than film B. Adjusting the proportion of the thicknesses of the two films and the stress offsets of the two films can result in a stress offset of the bilayer of less than approximately 10%, less than approximately 5%, less than approximately 2%, or less than approximately 1%. The film thicknesses shown in Figure 4 are: film A is 3000 Å, film B is 11000 Å, and film A+B is 9000 Å. In some embodiments, the film thickness and its compensable warpage are directly related; the internal stress can be fixed, and the film thickness can be varied to compensate for more or less wafer warpage. In the various embodiments described herein, the thickness of the back-side film can be between about 0.1 and about 5 μm.

[0045] Figure 5 illustrates an exemplary process for depositing a back-side layer structure comprising two or more films with different stress offsets. The process in Figure 5 begins with the deposition of one or more front-side layers (502) having a first type of internal stress (e.g., tensile internal stress). The wafer may have one or more front-side layers deposited thereon that cause wafer warping.

[0046] Once one or more front-side layers are deposited onto the wafer, one or more first back-side layers with a first type of internal stress are deposited onto the wafer (504). The internal stress of the first back-side layer counteracts the internal stress from the front-side layers and helps reduce wafer warpage. The first back-side layer may have tensile stress offset, i.e., under annealing conditions, the internal stress of this layer may increase (become more tensile).

[0047] One or more second backside layers are deposited on a first backside layer having a first type of internal stress (506). The internal stress of the second backside layer is the same as that of the front and first backside layers, but has the opposite stress offset under annealing conditions; for example, the internal stress of the layer may decrease (become more compressible).

[0048] Both the first and second back-side layers can be deposited at low temperatures, such as below about 400°C, below about 450°C, below about 500°C, below about 550°C, or below about 600°C. At such deposition temperatures, a large amount of hydrogen is incorporated into these layers, which can then react during subsequent high-temperature conditions (e.g., above about 700°C, above about 800°C, or above about 900°C) and cause tensile or compressive stress shifts.

[0049] In some embodiments, the deposition rate of the backside layer disclosed herein can be in the range of approximately 300 Å to approximately 800 Å per minute. Low-temperature deposited films typically have an additional hydrogen content to maintain such a deposition rate. While the hydrogen content of the backside film can be reduced, and therefore the magnitude of any internal stress offset can be similarly reduced, the deposition rate of such a film is likely to be a fraction of the aforementioned deposition rate. This is likely due to the extremely low silane precursor partial pressure required to reduce the hydrogen content when deposition is performed at low temperatures. Therefore, the techniques disclosed herein allow for greater deposition rates while maintaining neutral stress offsets under subsequent annealing conditions.

[0050] After the deposition of the first and second back-side layers, the substrate can be processed at temperatures that cause stress shifts in the first and second back-side layers. Although the first and second back-side layers may each experience internal stress shifts individually, the combined internal stress from the two films remains substantially the same; for example, the change in internal stress of the combined first and second back-side layers is less than about 10%, less than about 5%, less than about 2%, or less than about 1%.

[0051] In some embodiments, the internal stress of the deposited first and second back-side layers may be less than the internal stress of the deposited front-side layers; that is, the first and second back-side layers do not fully compensate for the warpage caused by one or more front-side layers. In some embodiments, the first and second back-side layers reduce wafer warpage to about 200 μm or less.

[0052] CVD, PECVD, ALD, epitaxy, PVD, or other deposition processes can be used to deposit the backside layer. A dedicated backside deposition apparatus can be used to deposit the backside layer. The backside deposition apparatus can be a different deposition apparatus than that used to deposit one or more frontside layers.

[0053] The warpage caused by the first back-side layer and the second back-side layer can be the sum of the warpages caused by each. In some embodiments, the combined warpage size of the back-side layer can be approximately the same as the warpage size of one or more front-side layers. In some embodiments, the warpage contributions of all front-side and back-side layers can be combined such that the total warpage of the wafer is minimized (i.e., less than about 100 μm). In some embodiments, after implementing the method of FIG. 5, the wafer can be substantially flat, for example, the wafer has a warpage of about 200 μm or less, about 150 μm or less, or about 100 μm or less.

[0054] Note that mentioning the warpage caused or resulting from each back-side layer assumes that other layers do not compensate for the warpage. For example, when mentioning the magnitude of warpage caused by the first back-side layer, we assume that this is warpage generated on the substrate in the absence of other layers (e.g., no front-side layer). The magnitude of warpage caused by a layer depends on the internal stress of the material in the layer and the thickness of the layer.

[0055] Compensation of the back-side layer refers to the warpage contribution of the back-side layer, which can be combined with the warpage contribution of the front-side layer to reduce or equalize wafer warpage. As described above, the warpage contributions of all front-side and back-side layers can be combined. Positive warpage (forming a bowl shape) caused by the front-side layer can be caused by the front-side layer having tensile internal stress. This warpage can be reduced by the back-side layer, which also has tensile internal stress (causing the opposite negative warpage). The negative warpage caused by the back-side layer compensates for the positive warpage caused by the front-side layer, thus resulting in a minimum total wafer warpage. In some embodiments, compensation may include partially mitigating wafer warpage. As described above, the first and second back-side layers can partially compensate for wafer warpage. In other embodiments, the first and second back-side layers can completely compensate for wafer warpage, for example, reducing wafer warpage to less than about 100 μm.

[0056] In some embodiments, the back-side layers disclosed herein comprise a material with inherent internal stresses of at least about 100 MPa, or from about 100 MPa to about 2000 MPa. These values ​​may relate to tensile or compressive internal stresses, depending on the type of back-side material required to counteract warping caused by the front-side layers. The aforementioned internal stress values ​​may be applicable to any one or more back-side layers in a multilayer back-side stack. Any two back-side layers may have the same or different internal stress values.

[0057] Exemplary materials for fabricating a back-side layer with tensile internal stress include silicon nitride (SiN), silicon oxide nitride, and polymer layers. As an example, CVD or PECVD techniques can be used to deposit the tensile film. To combat wafer warping caused by a front-side layer with compressive internal stress, a compression film can be used for the host back-side layer. Specific materials and / or processing conditions can be used to form the compression film. Exemplary materials for fabricating the compression film include silicon oxide (SiO2). x Materials include silicon nitride, alumina, aluminum nitride, and polycrystalline silicon. CVD or PECVD techniques can be used to deposit compressed films. The above materials and deposition techniques can be applied to any one or more back-side layers in a multilayer back-side stack. Any two back-side layers can be formed using the same or different techniques.

[0058] The back-side films disclosed herein can be deposited using PECVD technology, employing silicon-containing precursors and nitrogen-containing reactants. The internal stress offset of the film can be adjusted to be tensile or compressive, and the magnitude of such change can be adjusted by controlling various processing parameters. These processing parameters may include temperature, pressure, mass flow rate, plasma power, etc. Adjusting a single back-side film to have compressive or tensile internal stress offset is generally easier than adjusting such back-side films to have a neutral stress offset, because hydrogen content and hydrogen bonding can significantly affect the type and magnitude of the stress offset. Furthermore, the relative thickness of each back-side layer can be adjusted so that the magnitude of the stress offset for each film is substantially equal and opposite in sign. In some implementations, the ratio of silicon precursor to nitrogen-containing reactant can be between approximately 2:1 and approximately 1:100, with a larger proportion of silicon precursor potentially resulting in a greater tensile stress offset. Other gaseous substances, including inert gases, can also be co-flowed.

[0059] To deposit silicon-containing films, one or more silicon-containing precursors can be used. In some examples, silicon-containing precursors may include silanes (e.g., SiH4), polysilanes (H3Si-(SiH2)), etc. n -SiH3, where n≥1), organosilanes, halosilanes, aminosilanes, alkoxysilanes, etc. Examples of organosilanes include methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc.

[0060] Halosilanes comprise at least one halogen group, which may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Specific chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, allylchlorosilane, chloromethylsilane, dichloromethylsilane, dichlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, and so on.

[0061] Aminosilanes include at least one nitrogen atom bonded to a silicon atom, but may also include hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), and substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilaneamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2, BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, diisopropylaminosilane (DIPAS), disec-butylaminosilane (DSBAS), SiH2[N(CH2CH3)2]2 (BDEAS), etc. A further example of an aminosilane is trisilylamine (N(SiH3)). In some implementations, aminosilanes with two or more amino groups attached to the central Si atom can be used. This can result in less damage (compared to aminosilanes with only a single amino group attached).

[0062] Further examples of silicon-containing precursors include: trimethylsilane (3MS), ethylsilane, butylsilane, pentalosilane, octylsilane, heptylsilane, hexylsilane, cyclobutylsilane, cycloheptylsilane, cyclohexylsilane, cyclooctylsilane, cyclopentylsilane, 1,4-dioxa-2,3,5,6-tetrasilazane, diethoxymethylsilane (DEMS), diethoxysilane (DES), dimethoxymethylsilane, dimethoxysilane (DMOS), methyldiethoxysilane (MDES), methyldimethoxysilane (MDMS), octamethoxydodecylsiloxane (OMODDS), tert-butoxydisilane, tetramethylcyclotetrasiloxane (TMCTS), tetraoxomethylcyclotetrasiloxane (TOMCTS), triethoxysilane (TES), triethoxysilane (TRIES), and trimethoxysilane (TMS or TriMOS).

[0063] In some implementations, the silicon-containing precursor may include a siloxane or an amino-containing siloxane. In some embodiments, the siloxane used herein may have the formula X(R)1 ) a Si-O-Si(R 2 ) b Y, where a and b are integers from 0 to 2, and X and Y can independently be H or NR. 3 R 4 , where R 1 R 2 R 3 and R 4 Each of them is hydrogen, non-branched alkyl, branched alkyl, saturated heterocyclic, unsaturated heterocyclic group, or a combination thereof. In some embodiments, when at least one X or Y is NR 3 R 4 At that time, R 3 and R 4(Together with the atoms attached to each) a saturated heterocyclic compound is formed. In some embodiments, the silicon-containing precursor is a siloxane containing pentamethylamino or dimethylamino. Examples of amino-containing siloxanes include: 1-diethylamino-1,1,3,3,3-pentamethyldisiloxane, 1-diisopropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-dipropylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-n-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-di-sec-butylamino-1,1,3,3,3-pentamethyldisiloxane, 1-N-methylethylamino-1,1,3,3,3-pentamethyldisiloxane Disiloxane, 1-N-methylpropylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-N-methylbutylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-tert-butylamino-1,1,3,3,3,-pentamethyldisiloxane, 1-piperidinyl-1,1,3,3,3,-pentamethyldisiloxane, 1-dimethylamino-1,1-dimethyldisiloxane, 1-diethylamino-1,1-dimethyldisiloxane, 1-diisopropylamino-1,1-dimethyldisiloxane Alkane, 1-dipropylamino-1,1-dimethyldisiloxane, 1-di-n-butylamino-1,1-dimethyldisiloxane, 1-di-sec-butylamino-1,1-dimethyldisiloxane, 1-N-methylethylamino-1,1-dimethyldisiloxane, 1-N-methylpropylamino-1,1-dimethyldisiloxane, 1-N-methylbutylamino-1,1-dimethyldisiloxane, 1-piperidinyl-1,1-dimethyldisiloxane, 1-tert-butylamino-1,1-dimethyldisiloxane, 1-dimethyl... 1-Dimethylamino-disiloxane, 1-diethylamino-disiloxane, 1-diisopropylamino-disiloxane, 1-dipropylamino-disiloxane, 1-di-n-butylamino-disiloxane, 1-di-sec-butylamino-disiloxane, 1-N-methylethylamino-disiloxane, 1-N-methylpropylamino-disiloxane, 1-N-methylbutylamino-disiloxane, 1-piperidinyl-disiloxane, 1-tert-butylamino-disiloxane, and 1-dimethylamino-1,1,5,5,5,5-pentamethyldisiloxane.

[0064] When the deposited film contains nitrogen, nitrogen-containing reactants can be used. Nitrogen-containing reactants contain at least one nitrogen atom, such as nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or an amine (e.g., an amine with carbon atom), such as methylamine (CH5N), dimethylamine ((CH3)2NH), ethylamine (C2H5NH2), isopropylamine (C3H9N), tert-butylamine (C4H4N), etc. 11 N), di-tert-butylamine (C8H) 19 N), cyclopropylamine (C3H5NH2), sec-butylamine (C4H 11N), cyclobutylamine (C4H7NH2), isopentylamine (C5H 13 N), 2-methylbutyl-2-amine (C5H) 13 N), trimethylamine (C3H9N), diisopropylamine (C6H) 15 N), diethylisopropylamine (C7H) 17 N), di-tert-butylhydrazine (C8H) 20 Nitrogen-containing reactants can contain nitrogen (N2) and aromatic amines such as aniline, pyridine, and benzylamine. Amines can be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). Nitrogen-containing reactants may contain heteroatoms other than nitrogen; for example, hydroxylamine, tert-butoxycarbonylamine, and N-tert-butylhydroxylamine are nitrogen-containing reactants. Other examples include N... x O y Compounds, such as nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2), dinitrogen trioxide (N2O3), dinitrogen tetroxide (N2O4), and / or dinitrogen pentoxide (N2O5).

[0065] Device In some embodiments, FIG6A is a block diagram illustrating a substrate processing system 600 for performing processing on a wafer 602 (also referred to as a wafer) according to some embodiments. As shown, the substrate processing system may include a chamber 634. A central pillar may be configured to support a base when the top surface of wafer 602 is being processed (e.g., a film is being formed on the top surface of wafer 602 or on the back side of wafer 602). According to some embodiments disclosed herein, the base may refer to a nozzle base (“ShoPed”) 606. A nozzle 636 may be disposed above the ShoPed 606.

[0066] In some embodiments, nozzle 636 may be electrically coupled to power supply source 638 via mating network 640. Power supply source 638 may be controlled by control module 642, such as a controller. In some embodiments, power may be provided to nozzle 606 instead of nozzle 636. Control module 642 may be configured to operate substrate processing system 632 by executing process inputs and controls for a specific process recipe. Depending on whether the top surface of wafer 602 is receiving a deposited layer or layer stack, or whether the bottom surface of wafer 602 is receiving a deposited layer or layer stack, controller module 642 may set various operational inputs for the process recipe, such as power level, timing parameters, process gases, mechanical movement of wafer 602, and / or height of wafer 602 relative to nozzle 606.

[0067] In some embodiments, the center post may also include lifting pins controlled by a lifting pin controller. These lifting pins can be used to lift the wafer 602 from the nozzle 606 to allow an end effector (not shown) to pick up the wafer and lower it after the end effector has placed it. The end effector can also position the wafer 602 above the spacer 644. As will be described below, the spacer 644 may be sized to provide controlled separation of the wafer 602 between the top surface of the nozzle 636 (facing the wafer) and the top surface of the nozzle 606 (facing the wafer).

[0068] In some embodiments, the substrate processing system 632 may further include a first gas manifold 646 connected to a first gas source 648 (e.g., a gaseous chemical and / or inert gas supplied from a facility). Depending on the processing being performed on the top surface of the wafer 602, the control module 642 can control the delivery of the first gas source 648 via the first gas manifold 646. The selected gas can then flow into nozzles 636 and be distributed within a space defined between the surfaces of the nozzles 636 facing the wafer 602 when the wafer is positioned above the substrate.

[0069] In some embodiments, the substrate processing system 632 may further include a second gas manifold 650 connected to a second gas source 652 (e.g., gaseous chemicals and / or inert gases supplied from the facility). Depending on the processing being performed on the bottom surface of wafer 602, the control module 642 can control the delivery of the second gas source 652 via the second gas manifold 650. The selected gas can then flow into the nozzle 636 and be distributed within a space defined between the surfaces of the nozzle 606 facing the lower or lower (back) side of wafer 602 when the wafer is positioned above the spacer 644. The spacer 644 provides separation optimized for deposition on the lower surface of wafer 602 and reduces deposition above the top surface of wafer 602. In some embodiments, when the deposition target is the lower surface of wafer 602, inert gas can flow through the nozzle 636 across the top surface of wafer 602, which can push reactant gases away from the top surface and allow reactant gases supplied from the nozzle 606 to be directed to the lower surface of wafer 602.

[0070] Furthermore, the gas may or may not be premixed. Appropriate valves and mass flow control mechanisms can be employed to ensure the correct gas delivery during the deposition and plasma treatment phases of the process. The process gas can exit chamber 634 via an outlet. A vacuum pump (e.g., a first- or second-stage mechanical dry pump and / or a turbomolecular pump) can extract the process gas and maintain an appropriate low pressure within the reactor via a dead-loop flow limiting device (e.g., a throttle valve or a pendulum valve).

[0071] In some embodiments, the carrier ring 654 may surround an outer region of the spray holder 606. When processing the top surface of the wafer 602, for example, when material is being deposited thereon, the carrier ring 654 may be configured to be positioned above a carrier ring support region that forms a step downward from the wafer support region at the center of the spray holder 606. The top surface of the carrier ring 654 is substantially coplanar with the top surface of the wafer 602. The carrier ring 654 may include an outer edge side (e.g., outer radius) of its disk structure and a wafer edge side (e.g., inner radius) of its disk structure, which is closest to the location of the wafer 602. The carrier ring 654 may be associated with an inner diameter (ID). The inner diameter may extend to the inner periphery of the carrier ring and generally surround the substrate (e.g., the wafer 602) in the processing chamber. The wafer edge side of the carrier ring 654 may also include a plurality of contact support structures or "tabs" that are configured to raise the wafer 602 when the carrier ring 654 is held by spacers 644. The carrier ring 654 may include a plurality of tabs, the number of which is selected from the range that supports the wafer 602 during processing. Additional details regarding the tab implementation will be provided below.

[0072] Figure 6B is a block diagram illustrating another substrate processing system 632 for performing processing on wafer 602 according to some embodiments. In some embodiments, the spoke fork 656 can be used to elevate and hold the carrier ring 654 at its process height, for example, to allow deposition on the lower surface (back side) of wafer 602. Thus, the carrier ring 654 can be lifted together with wafer 602. In some embodiments, the carrier ring 654 can be rotated to another station, such as in a multi-station system.

[0073] Broadly speaking, the embodiments disclosed herein are systems for depositing PECVD films on selected sides (front and / or back sides) of a wafer through dynamic control. Some embodiments may include dual-flow electrodes for defining a capacitively coupled PECVD system. This system may include a flow nozzle (e.g., nozzle 636) and a nozzle holder 66. In some embodiments, the flow holder (i.e., the nozzle holder) is a combination of the nozzle and the holder, which is actually used for deposition on the back side of the wafer. The electrode geometry combines features of the nozzle (e.g., gas mixing chamber, orifices, orifice patterns, anti-gas spray baffles) with features of the holder. Examples of holder features include an embedded controlled heater, a wafer lifting mechanism, the ability to maintain a plasma suppression ring, and mobility. This allows wafer transfer and gas handling to be performed with or without RF power from the holder.

[0074] In some implementations, the system may have a wafer lifting mechanism that tightly controls the parallelism of the substrate relative to the electrodes. In one example, this can be achieved by setting a lifting mechanism (e.g., a mandrel or lifting pin mechanism) parallel to the two electrodes and controlling manufacturing tolerances. In another example, lifting can be achieved by raising the wafer lifting component. This option may not allow for dynamic control of the side where deposition takes place.

[0075] In some configurations, the lifting mechanism allows for dynamic control of the substrate position during processing (before, during, and after plasma) to control the side on which deposition occurs, the deposition profile, and the properties of the deposited film. The system can further allow for selective activation / deactivation of the reactant flow on that side. Reactants can flow on one side, while an inert gas can flow on the other to suppress deposition and plasma flow.

[0076] In some implementations, the gap between the sides of the wafer where plasma / deposition is not required can be tightly controlled. This distance can be controlled to suppress plasma. If the distance is not controlled, the wafer may be susceptible to plasma damage. For example, the system may allow a minimum gap of about 2 mm to about 0.5 mm, while in another implementation it may allow about 1 mm to about 0.05 mm (limited by wafer warpage), and such gaps can be controlled. This gap can be controlled according to process conditions.

[0077] In some implementations, the airflow base (i.e., the nozzle) may achieve, but is not limited to: (a) thermally stabilizing the wafer to the processing temperature prior to processing; (b) selectively designing the aperture pattern on the nozzle to selectively deposit films in different regions on the back side of the wafer; (c) attaching replaceable rings to achieve appropriate plasma confinement and aperture patterning; (d) an in-chamber stable wafer transfer mechanism for transferring the wafer outward to another chamber or boat – e.g., lift pins, RF coupling features, minimum contact arrays; (e) implementing gas mixing features, e.g., internal gas chambers, baffles, and manifold line openings; and (f) providing compartments in the airflow base (i.e., the nozzle) to allow selective airflow to flow to different regions on the back side of the wafer, and controlling the flow rate via a flow controller and / or multiple gas chambers.

[0078] In another embodiment, dynamic gap control of the wafer lifting mechanism is used to achieve: (a) controlling the distance from the deposition or reactant flow electrode to the side or middle of the wafer to be deposited, allowing deposition on both sides; and (b) the lifting mechanism dynamically controlling the distance during the process (before plasma, during plasma, after plasma) to control the side to be deposited, the deposition profile, and the characteristics of the deposited film. In another embodiment, for deposition modes used for deposition on the back side of the wafer, edge exclusion control is highly desirable to avoid lithography-related overlay issues. The lifting mechanism used in this system is accomplished via a carrier ring 654, which has design features for shielding deposition on the edges. This edge exclusion control is specified through the design and shape of the carrier ring.

[0079] Figure 7A shows a cross-sectional view of the edge region of the spray nozzle 606. This view provides a cross-sectional representation of the support ring 654, which has an inner radius 654a and an outer radius 654b. In some embodiments, the support ring 654 includes a support extension 654c that extends below a substantially flat surface of the support ring 654.

[0080] The support extension 654c is configured to mate and reside within a support surface defined in the top surface of the spacer 644. The support surface provides a complementary mating surface to the support extension 654c, thereby preventing the carrier ring 654 from sliding or moving when supported by the spacers 644. Although three spacers 644 are shown in FIG. 7B, it is conceivable that any number of spacers can be provided, as long as the carrier ring can be supported substantially parallel to the surface of the nozzle 606 and the spacing is defined to support the wafer 602 at a distance from the top surface of the base 606.

[0081] Further illustration shows that the top surface of the spray holder 606 will include a perforation pattern 606a distributed across the entire surface to provide uniform gas distribution and output during operation. In one embodiment, the perforation pattern 606a is distributed in a plurality of concentric rings, which begin at the center of the top surface of the spray holder 606 and extend to the outer periphery of the spray holder 606. At least one perforation pattern 606a is disposed at an edge perforation region 607 of the perforation pattern, and the orifice defined in the edge perforation region 607 is preferably angled to provide gas without being perpendicular to the surface of the spray holder 606.

[0082] In one example, the angle or tilt of the orifice in the edge hole region 607 is defined as tilted or angled away from the center of the nozzle 106. In one embodiment, this angle is approximately 45° to the horizontal. In other embodiments, this angle may vary between 20° and approximately 80° to the horizontal. In one embodiment, by providing angled orifices in the edge hole region 607, additional distribution of process gases can be provided during backside deposition of the wafer 602. In one embodiment, the remaining orifices 606d of the hole pattern 606a are oriented substantially perpendicular to the surface of the nozzle 106 and pointing towards the underside of the wafer 602.

[0083] Figure 7B shows that when wafer 602 is held by carrier ring 654, the edge of wafer 602 will be located on the edge region of the carrier ring inner radius 654a, which is closer to carrier ring 654. When positioning with spacer 644, the surface of nozzle 636 facing the top surface of wafer 602 can be substantially close enough to prevent deposition from occurring during the deposition mode on the back side of wafer 602.

[0084] For example, the distance between the top of wafer 602 and the surface of nozzle 636 is preferably between about 2 mm and about 0.5 mm, and in some embodiments about 1 mm to about 0.5 mm, depending on wafer warpage. That is, if the wafer is significantly warped, the gap will be about 0.5 mm or more. If the wafer is not significantly warped, the gap may be less than about 0.5 mm. In one embodiment, it is preferable to minimize the gap to prevent deposition on the top side of the substrate when a material layer is being deposited on the back side of the substrate. In some embodiments, nozzle 636 is configured to supply an inert gas flow over the top side of wafer 602 during deposition on the back side of the substrate and supply of deposition gas through nozzle 606.

[0085] Any suitable chamber may be used to implement the disclosed embodiments. Exemplary deposition apparatuses include a variety of systems, such as ALTUS® and ALTUS®Max available from Lam Research Corp. (Fremont, California), or any other commercially available processing systems.

[0086] Figure 8 is a schematic diagram of a processing system suitable for a deposition process (e.g., a front-side deposition process) according to an embodiment. System 800 includes a transfer module 803. Transfer module 803 provides a clean, pressurized environment to minimize the risk of contamination of the substrate being processed as it moves between the various reactor modules. Mounted on transfer module 803 is a multi-station reactor 809 capable of performing ALD, processing, and CVD according to various embodiments. Multi-station reactor 809 may include multiple stations 811, 813, 815, and 817, which may operate sequentially according to the disclosed embodiments. A station may include a heating base or substrate support, one or more gas inlets or nozzles or distribution plates.

[0087] One or more single-station or multi-station modules 807 capable of performing plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations may also be mounted on transfer module 803. This module can also be used for various processes, such as preparing substrates for deposition processes. System 800 also includes one or more wafer source modules 801, where wafers are stored before and after processing. An atmospheric robot (not shown) in atmospheric transfer chamber 819 can first move wafers from source modules 801 to loading locks 821. Wafer transfer devices (typically robotic arm units) in transfer module 803 move wafers from loading locks 821 to modules mounted on transfer module 803 and move wafers between these modules.

[0088] In various implementations, a system controller 842 is used to control the process conditions during the deposition process. The controller 842 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0089] The controller 842 controls all activities of the deposition apparatus. The system controller 842 runs system control software, which includes a set of instructions for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters specific to the process. In some embodiments, additional computer programs stored on memory devices associated with the controller 842 may be used.

[0090] The described implementation includes a user interface associated with controller 842. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and user input devices such as pointing devices, keyboards, touchscreens, microphones, etc.

[0091] The system control logic can be configured in any suitable manner. Generally, this logic can be designed or configured in hardware and / or software. Instructions for controlling the drive circuitry can be hard-coded or provided as software. These instructions can be provided through "programming." Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application-specific integrated circuits (ASICs), and other devices with specific algorithms implemented in hardware. Programming is also understood to include software or firmware instructions executable on a general-purpose processor. The system control software can be encoded in any suitable computer-readable programming language.

[0092] Computer program code used to control processes in a process sequence can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by a processor to perform the tasks identified in the program. Also, as indicated, the program code can be hard-coded.

[0093] The controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be entered using a user interface.

[0094] Signals used for process monitoring can be provided via analog and / or digital input connections to system controller 842. Signals used for process control are output via analog and digital output connections to device 800.

[0095] The system software can be designed or configured in different ways. For example, multiple chamber assembly subroutines or control targets can be written to control the operation of the chamber assembly required to perform the deposition process according to the disclosed embodiments. Examples of programs or program segments used for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0096] In some embodiments, system controller 842 is part of a system that may be part of the embodiments described above. Such systems include semiconductor processing apparatuses that include one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics to control their operation before, during, or after the processing of semiconductor wafers or substrates. The electronics may be referred to as a “controller” that controls various components or sub-sections of one or more systems. Depending on the processing requirements and / or the type of system, system controller 842 may be programmed to control any of the processes disclosed in this invention, including controlling the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, plasma pulse frequency settings, fluid delivery settings, position and operation settings, wafer loading / unloading tools and other transfer tools, and / or the transfer of loading locks connected to or interfaced with a particular system.

[0097] System Controller In a broad sense, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, performs cleaning operations, performs endpoint measurements, etc. Such a controller can be used in or with any of the devices described herein. The integrated circuit may include a chip storing program instructions in firmware form, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions delivered to the controller or system in various settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer. In some embodiments, these operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare dies on the wafer.

[0098] A system controller may be part of or coupled to a computer integrated with, coupled to, or connected to the system or a combination thereof via a network. For example, a system controller may be located in the “cloud” or be a whole or part of a fab mainframe computer system, allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change parameters for the current process, set processing steps to follow the current process, or initiate a new process. In some embodiments, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local network or the Internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed and the type of tool, to which the controller is configured to connect to or control. Therefore, as described above, the controller can be distributed, for example, by comprising one or more discrete controllers connected together via a network and working toward a common goal (e.g., the process and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits located indoors that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which together control the process within the indoor environment.

[0099] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary rinsing chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfering edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0100] As described above, depending on one or more process steps the tool is to perform, the controller may communicate with one or more other tool circuits or modules, other tool components, combined tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a host, another controller, or tools used in material handling that move wafer containers to and from tool locations and / or loading ports within the semiconductor manufacturing plant.

[0101] The system controller may include various programs. A substrate positioning program may include program code for controlling a chamber assembly used to load the substrate onto a pedestal or chuck and controlling the spacing between the substrate and other chamber components, such as gas inlets and / or targets. A process gas control program may include code for controlling gas composition, flow rate, pulse duration, and optionally, for allowing gas to flow into the chamber prior to deposition to stabilize the pressure within the chamber. A pressure control program may include code for controlling the pressure within the chamber by adjusting, for example, a throttle valve in the chamber's exhaust system. A heater control program may include code for controlling the current of a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to the wafer chuck.

[0102] Examples of chamber sensors that can be monitored during the deposition process include mass flow controllers, pressure sensors such as pressure gauges, and thermocouples located in a base or chuck. Appropriately programmed feedback and control algorithms, along with data from these sensors, can be used to maintain the desired process conditions.

[0103] The foregoing describes implementations of the present invention in single-chamber or multi-chamber semiconductor processing tools. The apparatus and processes described herein can be used in conjunction with photolithography patterning tools or processes, for example, for fabricating or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily required, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of a film typically involves some or all of the following steps, each step employing multiple feasible tools: (1) applying a photoresist to the workpiece, i.e., the substrate, using a spin coater or spray coater; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV or X-rays using a tool such as a wafer stepper; (4) developing the photoresist to selectively remove it and thus pattern it using a tool such as a wet cleaning station; (5) transferring the photoresist pattern onto the underlying film or workpiece using a dry or plasma-assisted etching tool; and (6) removing the photoresist using a tool such as an RF or microwave plasma stripper.

[0104] in conclusion Although the above embodiments have been described in detail for clarity of understanding, it is apparent that certain changes and modifications may be made within the scope of the appended claims. The embodiments disclosed herein may be implemented in instances where some or all of these specific details are lacking. In other instances, conventional process operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Furthermore, while specific embodiments will be used to illustrate the disclosed embodiments, it should be understood that this is not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways to implement the processes, systems, and apparatus of the embodiments of this application. Therefore, the embodiments of this application should be considered illustrative rather than restrictive, and should not be limited to the details set forth herein.

Claims

1. A method for reducing warpage in a substrate, comprising: A receiving substrate having one or more front-side layers on its front side, wherein the one or more front-side layers cause warping in the substrate; A first backside layer is deposited, wherein the first backside layer has a first type of internal stress offset after annealing; A second backside layer is deposited, wherein the second backside layer has a second type of internal stress offset after annealing, the second type of internal stress offset being the opposite of the first type.

2. The method of claim 1, wherein the first back-side layer comprises more silicon-hydrogen bonds than the second back-side layer.

3. The method according to claim 1, further comprising: The substrate is annealed, wherein the combined internal stress of the first back-side layer and the second back-side layer changes by less than 10% after annealing.

4. The method of claim 3, wherein the annealing is performed at a temperature greater than about 700°C.

5. The method of claim 1, wherein the deposition of the first backside layer and the deposition of the second backside layer are performed at a temperature of less than about 500°C.

6. The method of claim 1, wherein the deposition rate of the first backside layer or the second backside layer is at least about 300 Å per minute.

7. The method according to claim 1, wherein the first internal stress offset is a tensile stress offset.

8. The method of claim 7, wherein the second internal stress offset is a compressive stress offset.

9. The method of claim 1, wherein the first back-side layer and the second back-side layer comprise silicon nitride.

10. The method of claim 1, wherein each of the first back-side layer and the second back-side layer has an inherent internal stress of about 100 MPa to 1000 MPa.

11. The method of claim 1, wherein both the first back-side layer and the second back-side layer have tensile internal stress.

12. The method of claim 1, wherein the warpage of the substrate is about 300 μm or more.

13. The method of claim 1, wherein the warpage of the substrate is less than about 100 μm after depositing the first backside layer and the second backside layer.

14. The method of claim 1, wherein at least one of the one or more front layers comprises a hard mask.

15. The method of claim 1, wherein the one or more front layers comprise a stack of about 100 or more alternating layers.

16. The method of claim 15, wherein the stack comprises alternating oxide layers and nitride or polysilicon layers.

17. The method of claim 15, wherein the first back-side layer and the second back-side layer have a thickness of about 0.1 μm to about 5 μm.

18. A substrate comprising: One or more front-side layers are located on the front side of the substrate; A first back side layer, wherein the first back side layer has a first type of internal stress offset after annealing; The second back-side layer, wherein the second back-side layer has a second type of internal stress offset after annealing, the second type of internal stress offset being the opposite of the first type.

19. The substrate of claim 18, wherein if the one or more front-side layers are not compensated by the first back-side layer, the substrate has a warpage of about 300 μm or greater.

20. The substrate of claim 18, wherein the first internal stress offset is tensile and the second internal stress offset is compressive.

21. The substrate of claim 18, wherein if the one or more front layers are not compensated by the first back layer, the substrate has a warpage of about 300 μm or greater.

22. The substrate of claim 18, wherein the first back-side layer and the second back-side layer comprise silicon nitride.

23. The substrate of claim 18, wherein the first back-side layer and the second back-side layer have a thickness of about 0.1 μm to about 5 μm.

24. The substrate of claim 18, wherein the first back-side layer comprises more silicon-hydrogen bonds than the second back-side layer.

25. The substrate of claim 18, wherein if annealing is performed, the combined internal stress of the first back-side layer and the second back-side layer changes by less than 10% after annealing.

26. An apparatus for semiconductor processing, comprising: Processing room; as well as The controller, which includes memory and a processor, is configured to: A receiving substrate having one or more front-side layers on its front side, wherein the one or more front-side layers cause warping in the substrate; A first backside layer is deposited, wherein the first backside layer has a first type of internal stress offset after annealing; A second backside layer is deposited, wherein the second backside layer has a second type of internal stress offset after annealing, the second type of internal stress offset being the opposite of the first type.

Images