An apparatus and method for accelerating high-precision ADC data operation

Abstract

The application relates to the technical field of integrated circuit design, and particularly discloses an apparatus and method for accelerating high-precision ADC data operation, which comprises a bus including an address bus and a data bus; a hardware algorithm accelerator including an address mapping logic module, an input-output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from the address bus into two parts of a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module; and the register module comprises a configuration register, a plurality of operand registers and the configuration register. According to the application, the address access request from the address bus is split into two parts, the calculation input and output are selected through address mapping, the calculation result can be directly introduced into a newly initiated calculation input end, the read-write of the operand register by the processor can be reduced, and the operation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to an apparatus and method for accelerating high-precision ADC data processing. Background Technology

[0002] Accelerating high-precision ADC data processing is an important topic in the field of data processing technology. It involves the overall coordinated operation of high-precision ADCs, small-size MCUs, highly integrated sensors, and analog front-ends. The following technical problems typically arise during data processing:

[0003] a) Low-power, small-size MCUs integrating high-precision ADCs, along with highly integrated sensors and analog front-ends, typically do not use processors with hardware dividers and multiply-accumulate instructions. In applications such as pressure sensors, calculations involving nonlinear calibration and compensation algorithms for pressure and temperature, FFT, and filtering generally lack hardware acceleration capabilities. However, the core itself has limited capacity to handle complex calculations. To improve the data processing efficiency of high-precision ADCs without significantly increasing power consumption and chip area, integrating algorithm accelerator peripherals has become an important technological approach.

[0004] (b) The aforementioned low-power, small-size MCU processors are typically 8-bit, 16-bit, and 32-bit machines, supporting multiplication and addition / subtraction operations on a maximum of 32-bit output results. When processing 24-bit or 32-bit ADC output data, overflow issues can easily occur, leading to data errors. Although the overflow problem can be resolved by shifting the data bit width, this will result in a loss of ADC accuracy. While this problem can be solved by redeclaring larger bit-width variables in software or converting the data to floating-point (such as int64, double) for calculation, this comes at the cost of significant performance, power consumption, and real-time performance.

[0005] c) Due to limitations in storage resources, instruction set capabilities, and energy budgets, low-power, small-size MCUs face challenges in balancing code size, execution speed, and power consumption in data processing software algorithms. This restricts the application of low-power, small-size MCUs in high-precision ADC scenarios. Therefore, efficiently solving computational problems with minimal hardware resource overhead is of great significance.

[0006] d) The greater the complexity of the program that calls the hardware algorithm accelerator, the higher the performance of the hardware algorithm accelerator, and the higher the communication frequency between the processor and the hardware algorithm accelerator. In this case, the performance loss caused by register reads and writes to the algorithm becomes more obvious. For example, this applies to scenarios where the multiply-accumulate module accelerates filters, and the butterfly operation module accelerates the fast Fourier transform. Therefore, efficient use of hardware algorithm accelerators is of great significance.

[0007] e) In MCU chip design, the integration difficulty and scalability of peripheral modules directly affect product cost and design cycle. For hardware algorithm accelerators, when adding or expanding functions, such as adding algorithms, it is undesirable to increase the complexity of system integration, thereby affecting the system's scalability and compatibility.

[0008] The hardware algorithm accelerator with the interface design of the invention patent CN105988773A uses low-order address mapping to operand registers and high-order address mapping to configuration selection. This method makes it impossible to optimize the program's space usage using offset addresses.

[0009] The hardware algorithm accelerator with the interface design of the invention patent CN105988773A requires frequent adjustment of the input and output operand registers when the formula calculation is complex. The processor needs to perform frequent register reads and writes, which affects the operating efficiency of peripherals.

[0010] When the hardware algorithm accelerator program with the interface design of the invention patent CN105988773A performs calculations on 64-bit operand inputs, the input data is composed of two 32-bit operand registers. The operand registers need to be written separately to ensure that the sign bit is input correctly.

[0011] The hardware algorithm accelerator with the interface design of the invention patent CN105988773A needs to initialize multiple operand registers when performing complex calculations, which requires multiple operand register write operations.

[0012] The hardware algorithm accelerator program with the interface design of the invention patent CN105988773A needs to store multiple bits of computational configuration information address in the program, which is not conducive to low-power, small-size MCU applications.

[0013] Therefore, existing technologies for accelerating high-precision ADC data processing typically have the following shortcomings:

[0014] a) Low-power, small-size MCUs integrating high-precision ADCs, as well as highly integrated sensors and analog front-ends, typically do not use processors with hardware dividers and multiply-add instructions. In applications such as pressure sensors, these devices generally lack hardware acceleration capabilities for calculations like pressure-temperature nonlinear calibration and compensation algorithms, FFT, and filtering. Furthermore, since ADC data precision is typically 24-bit or 32-bit, it usually exceeds the processing range of processor multiplication and addition instructions. When performing high-precision data processing, overflow issues can occur, leading to data errors. While data processing greater than 32 bits can be achieved in software, this approach incurs significant performance, power consumption, and real-time cost. On the other hand, processors often handle other processes or transactions; if the computation process is lengthy, it often interrupts the real-time response of other processes, resulting in data processing delays.

[0015] b) Low-power, small-size MCUs typically do not have large SRAM and FLASH spaces for program storage and execution. Therefore, high instruction density programs are required to alleviate storage pressure.

[0016] c) To achieve higher efficiency, computations involving complex data processing often involve frequent switching between input / output operations and computational formulas. While the problem described in a) can be solved by integrating hardware algorithm accelerator peripherals, this requires the processor to frequently read and write to the registers of the hardware algorithm accelerator peripherals during program execution, resulting in a significant reduction in computational efficiency.

[0017] d) The addition of new computing functions to the hardware algorithm accelerator relies on the expansion of registers to support new operands and configuration information, which is not conducive to the integration of peripherals.

[0018] Based on this technical background, the present invention studies a device and method for accelerating high-precision ADC data processing. Summary of the Invention

[0019] To address the shortcomings of existing technologies, this invention proposes a device and method for accelerating high-precision ADC data computation. This device splits an address access request from the address bus into two parts: a read / write access command for the register module and parameters and operation commands for the algorithm acceleration core function module. Simultaneously, by selecting the computation input and output through address mapping, the computation result can be directly imported into the newly initiated computation input terminal. This reduces the processor's read / write operations on the operand register, thereby improving computational efficiency and reducing program storage space.

[0020] To achieve the above objectives, a first aspect of the present invention provides an apparatus for accelerating high-precision ADC data processing, comprising:

[0021] Buses include address buses and data buses;

[0022] The hardware algorithm accelerator includes an address mapping logic module, an input / output mapping module, a register module, and a core function module for algorithm acceleration.

[0023] The address mapping logic module is used to split an address access request from the address bus into two parts: the read / write access command of the register module and the parameters and operation commands of the algorithm acceleration core function module.

[0024] The register module includes configuration registers related to this hardware algorithm accelerator, multiple operand registers for storing data, and a configuration register for clearing the data in the operand registers.

[0025] The input / output mapping module is used to select the input and output of the algorithm called by the algorithm acceleration core function module each time according to the information in the parameters and operation commands, send the value in the corresponding operand register module to the input terminal of the algorithm acceleration core function module, and send the value at the output terminal of the algorithm acceleration core function module to the corresponding operand register when the algorithm acceleration core function module completes the calculation.

[0026] A second aspect of the present invention provides a method for accelerating high-precision ADC data processing performed in the above-described apparatus, comprising:

[0027] Hardware algorithm accelerator operation process: First, the parameters and operation address in the access request are judged. Then, the configuration method of the algorithm acceleration core function module is selected. Then, the input and output mapping module is configured. Finally, the algorithm acceleration core function module initiates the operation. After the operation is completed, the status register is updated.

[0028] The software process for calling the hardware algorithm accelerator is as follows: First, the accelerator is called, and it is determined whether the algorithm has resident configuration parameters. Then, it is determined whether the operand register has been prewritten. Next, the final configuration parameters and operation address are written to the operand register. Finally, the calculation is completed, and the call is finished.

[0029] The beneficial effects of this invention include:

[0030] (1) The device for accelerating high-precision ADC data operation proposed in this invention splits an address access request from the address bus into two parts: a read / write access command of the register module and a parameter and operation command of the algorithm acceleration core function module. At the same time, by selecting the calculation input and output through address mapping, the calculation result can be directly imported into the newly initiated calculation input terminal, which can reduce the processor's read and write operations on the operand register, thereby improving the operation efficiency and reducing the program storage space.

[0031] (2) The device proposed in this invention for accelerating high-precision ADC data operation uses the high-order address of the operand register for mapping selection and the low-order address of the parameter operation command for mapping selection. The offset address can be used to optimize the program, reduce the program storage space and improve the program execution efficiency. At the same time, the program can be compressed into one instruction by using the offset address addressing method based on the register address, which increases the instruction density, improves the program execution efficiency and saves storage resources, thereby improving the operation efficiency and reducing the program storage space. Since it does not need to address by byte, the bus address utilization is higher, more parameters and operations can be configured, and the algorithm function expansion space is larger.

[0032] (3) The device proposed in this invention for accelerating high-precision ADC data operation automatically fills the sign bit of the high-order operand register when writing to the low-order operand register of the concatenation, thereby improving the operation efficiency and reducing the program storage space, reducing redundant operations of the program, and thus improving the program execution efficiency; the initialization operation of each operand register is mapped to an independent bit of the configuration register, and the data of the specified operand register can be reset through a single write access operation, thereby improving the operation efficiency and reducing the program storage space.

[0033] (4) The device proposed in this invention for accelerating high-precision ADC data operation can store part of the address mapping function in the configuration register of the peripheral device, thereby reducing the frequent updates of the address and the occupation of the address, which is conducive to the expansion of the hardware algorithm accelerator function and the integration; at the same time, the operand register initialization is mapped to the bit in the independent configuration register, and the one-time writing of the register can perform batch and accurate initialization of all operand registers, improve the program execution efficiency, and reduce the program storage space.

[0034] (5) The device proposed in this invention for accelerating high-precision ADC data operation can perform fixed-point decimal alignment of ADC data according to the parameter operation configuration in the address or the configuration in the configuration register when performing multiplication and division operations on ADC data, thereby ensuring that the high-precision ADC data still has high precision after processing and will not overflow; compared with using a processor to simulate the same operation, it greatly improves the execution efficiency and reduces the program storage space; in applications such as pressure sensors, it significantly improves the calculation accuracy and calculation efficiency of pressure and temperature nonlinear calibration and compensation algorithms.

[0035] (6) The device proposed in this invention for accelerating high-precision ADC data processing allows multiple register data to be read and written simultaneously in a single register read / write operation via register address mapping. In this case, the multiple register data are obtained by splitting the data from a 32-bit or 64-bit data bus. Taking a read / write mapping of two registers as an example, during a write operation, the data is split and written to the two operand registers selected by the address mapping; during a read operation, the data is concatenated and read from the two operand registers selected by the address mapping. This method can effectively improve the efficiency of parallel data stream computation.

[0036] (7) The device proposed in this invention for accelerating high-precision ADC data operation can achieve simultaneous read and write operations of multiple register data through register address mapping when integrating multiple algorithm acceleration core function modules. By utilizing the register splitting and splicing function, the parameters and operations of multiple algorithm acceleration core function modules can be configured simultaneously. Thus, a single read and write operation can simultaneously call multiple algorithm acceleration core function modules, thereby multiplying the computational efficiency.

[0037] (8) The device proposed in this invention for accelerating high-precision ADC data operation has an input port that can be obtained by mapping any operand register and an output port that can be mapped to any operand register, reducing redundant register read and write operations in complex programs and improving computational efficiency. At the same time, some parameters applied to the hardware algorithm accelerator are stored in the configuration register for a long time. At this time, the peripheral function expansion can be directly obtained by mapping the free bits in the address part, improving address utilization and facilitating flexible calling of peripherals and system integration.

[0038] (9) The device proposed in this invention for accelerating high-precision ADC data operation integrates algorithm operation and register read / write access at high density, which improves the execution efficiency of hardware algorithm accelerator peripherals while saving storage space; the calculation can flexibly specify the input data and output target register required for the calculation, reducing the processor's frequent read / write access to peripheral operand registers during complex calculations and improving the calculation efficiency.

[0039] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0040] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0041] Figure 1 This is a schematic diagram of a specific embodiment of the device for accelerating high-precision ADC data processing proposed in this invention.

[0042] Figure 2 This is a schematic diagram of the address mapping logic structure in a specific embodiment of the device for accelerating high-precision ADC data processing proposed in this invention.

[0043] Figure 3 This is a schematic diagram of the address mapping logic structure for multiply-accumulate calculation in a specific embodiment of the device for accelerating high-precision ADC data processing proposed in this invention.

[0044] Figure 4 This is a schematic diagram of the hardware algorithm accelerator operation process in a specific embodiment of the device for accelerating high-precision ADC data processing proposed in this invention.

[0045] Figure 5 This is a schematic diagram illustrating the software flow of calling the hardware algorithm accelerator in a specific embodiment of the device for accelerating high-precision ADC data processing proposed in this invention. Detailed Implementation

[0046] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0047] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its normal operating state, while "inner" and "outer" refer to their position relative to the device's outline. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] This invention provides a device for accelerating high-precision ADC data processing, such as... Figure 1 As shown, it includes:

[0049] Buses include address buses and data buses;

[0050] The hardware algorithm accelerator includes an address mapping logic module, an input / output mapping module, a register module, and a core function module for algorithm acceleration.

[0051] The address mapping logic module is used to split an address access request from the address bus into two parts: read and write access commands from the register module and parameters and operation commands from the algorithm acceleration core function module.

[0052] The register module includes configuration registers related to this hardware algorithm accelerator, multiple operand registers for storing data, and configuration registers for clearing operand register data;

[0053] The input / output mapping module is used to select the input and output of the algorithm called by the algorithm acceleration core function module based on the information in the parameters and operation commands each time. It sends the value in the corresponding operand register module to the input terminal of the algorithm acceleration core function module, and sends the value at the output terminal of the algorithm acceleration core function module to the corresponding operand register when the algorithm acceleration core function module completes the calculation.

[0054] In this invention, by splitting an address access request from the address bus into two parts—a read / write access command for the register module and a parameter and operation command for the algorithm acceleration core function module—and by selecting the computation input and output through address mapping, the computation result can be directly imported into the newly initiated computation input terminal. This reduces the processor's read and write operations on the operand register, thereby improving computational efficiency and reducing program storage space.

[0055] According to the present invention, the algorithm acceleration core function module integrates multiple algorithm core acceleration function units, which are used to update the configuration of calculation-related parameters of each algorithm core acceleration function unit according to parameters and operation commands.

[0056] According to the present invention, the multiple core algorithm acceleration functional units include a multiply-accumulate unit, a division unit, and a cordic unit;

[0057] When concatenating at least two operand registers, the sign bit is automatically padded to the concatenated high operand register when writing to the lower operand register.

[0058] In this invention, when multiple algorithm acceleration core functional modules are integrated, a single register read / write operation can achieve simultaneous read / write operations of multiple register data through register address mapping. By utilizing register splitting and splicing functions, the parameters and operations of multiple algorithm acceleration core functional modules can be configured simultaneously. This allows for the simultaneous invocation of multiple algorithm acceleration core functional modules in a single read / write operation, thereby significantly improving computational efficiency.

[0059] In this invention, when concatenating at least two operand registers, the sign bit of the concatenated high operand register is automatically padded when writing to the lower operand register, thereby improving computational efficiency and reducing program storage space. This reduces redundant operations and improves program execution efficiency. Furthermore, the initialization operation of each operand register is mapped to an independent bit in the configuration register, allowing the reset of the specified operand register data through a single write access operation, thus improving computational efficiency and reducing program storage space.

[0060] According to the present invention, the various modules inside the hardware algorithm accelerator work together to perform the following functions for a single read operation from the address bus: algorithm selection and configuration update, arbitrary arrangement and combination of input / output of the algorithm acceleration core functional module and operand registers, and update of operand register data, in order to reduce redundant register read / write operations from the bus.

[0061] According to the present invention, the address mapping logic module segments the address information of a single address access, uses the high-order address bits for operand register selection, and uses the low-order address bits for parameter generation and operation. This enables a single address access operation to both read and write the register module and update the configuration of the algorithm acceleration core function module. The algorithm selection is carried out simultaneously with the initiation of the calculation operation, thereby saving program space and improving the peripheral execution efficiency.

[0062] In the address mapping logic module, the base address value of the peripheral is stored in memory as data, and the various registers under the peripheral are accessed using offset address addressing, thereby optimizing program execution efficiency and storage space.

[0063] The address mapping logic module maps multiple registers during a single bus write operation. At this time, the high and low bits of the bus data are split and written into the mapped registers respectively. During a single bus read operation, multiple registers are mapped, and the bus data is the result of concatenating the registers.

[0064] In this invention, a single register read / write operation can achieve simultaneous read / write operations on multiple registers through register address mapping. In this case, the data from multiple registers is split from a 32-bit or 64-bit data bus. Taking a read / write mapping of two registers as an example, during a write operation, the two operand registers selected by the address mapping are split and written; during a read operation, the two operand registers selected by the address mapping are concatenated and read. This method can effectively improve the efficiency of parallel data stream computation.

[0065] According to the present invention, the hardware algorithm accelerator maps the operand register by the high-order bits, so that after the program is compiled, it only stores the address corresponding to the operand register as the base address, and the parameters and operations as the offset address, thereby reducing the program's storage space and optimizing execution efficiency.

[0066] When the parameters and operations of the hardware algorithm accelerator need to be updated frequently, the offset address is updated only by the program, without storing the complete address information in the storage space;

[0067] The hardware algorithm accelerator peripheral configuration includes fixed-point decimal related configurations. When the decimal function is selected in this operation, all input and output data will be mapped to fixed points according to the configured decimal places. The calculation always maintains the precision of the decimal places, thereby solving the problem of processing 24-bit or 32-bit data of high-precision ADCs in an efficient and low-power way, and avoiding the overflow problem in high-precision ADC data processing.

[0068] In this invention, when performing multiplication and division operations on ADC data, the ADC data can be aligned to a fixed decimal place according to the parameter operation configuration in the address or the configuration in the configuration register, thereby ensuring that the high-precision ADC data still has high precision after processing and will not overflow. Compared with using a processor to simulate the same operation, it greatly improves the execution efficiency and reduces the program storage space. In applications such as pressure sensors, it significantly improves the calculation accuracy and efficiency of pressure and temperature nonlinear calibration and compensation algorithms.

[0069] In this invention, the operand register is selected by mapping the high-order bits of the address, and the parameter operation command is selected by mapping the low-order bits of the address. The offset address can be used to optimize the program, reducing program storage space and improving program execution efficiency. At the same time, the program can be compressed into a single instruction by using offset addressing based on the register address, increasing instruction density, improving program execution efficiency and saving storage resources, thereby improving computational efficiency and reducing program storage space. Since byte-by-byte addressing is not required, the bus address utilization is higher, more parameters and operations can be configured, and the algorithm function expansion space is larger.

[0070] According to the present invention, some configuration information in parameters and operation commands is stored in the configuration register for a long time. When certain configurations in an algorithm do not need to be changed every time the hardware algorithm accelerator peripheral is called, it is not necessary to update the parameter configuration every time, thereby freeing up more address space for more parameter and operation mapping or algorithm function expansion.

[0071] When using the configuration information in the configuration register as parameters of the algorithm module, only special bits in the parameters and operation address are configured, thereby flexibly utilizing the address space for more configuration mapping or operation mapping;

[0072] After the hardware algorithm accelerator completes the calculation, if it is desired to clear some operand registers to avoid interfering with subsequent calculations, the corresponding registers can be quickly reset by writing 1 to the operand register clear bit in the configuration register, thereby improving the algorithm's running efficiency.

[0073] The configuration register also includes basic configuration information for the algorithm, and whether to use the configuration information in the configuration register is selected by using special bits in the address operation and parameter bits.

[0074] In this invention, some address mapping functions can be stored in the configuration register of the peripheral device, thereby reducing the frequency of address updates and address occupation, which is beneficial for the functional expansion of the hardware algorithm accelerator and for integration; at the same time, the operand register initialization is mapped to the bit in an independent configuration register, and a one-time write to this register can perform batch and precise initialization of all operand registers, improving program execution efficiency and reducing program storage space.

[0075] In this invention, the input port of the algorithm acceleration core functional module can be obtained by mapping any operand register, and the output port can be mapped to any operand register, reducing redundant register read and write operations in complex programs and improving computational efficiency. At the same time, some parameters applied to the hardware algorithm accelerator are stored in the configuration register for long-term storage. At this time, the peripheral function expansion can be directly obtained by mapping the free bits in the address part, improving address utilization and facilitating flexible calling of peripherals and system integration.

[0076] In this invention, the high-density integration of algorithm operation and register read / write access improves the peripheral execution efficiency of the hardware algorithm accelerator while saving storage space; the computation can be initiated by flexibly specifying the input data and output target register required for the computation, reducing the processor's frequent read / write access to peripheral operand registers during complex operations and improving computational efficiency.

[0077] The present invention also provides a method for accelerating high-precision ADC data processing performed in the described apparatus, comprising:

[0078] Hardware algorithm accelerator operation flow: First, the parameters and operation address in the access request are judged. Then, the configuration method of the algorithm acceleration core function module is selected. Next, the input and output mapping module is configured. Finally, the algorithm acceleration core function module initiates the operation. After the operation is completed, the status register is updated.

[0079] The software process for calling the hardware algorithm accelerator is as follows: First, the accelerator is called, and it is determined whether the algorithm has resident configuration parameters. Then, it is determined whether the operand register has been prewritten. Next, the final configuration parameters and operation address are written to the operand register. Finally, the calculation is completed, and the call is finished.

[0080] According to this invention, the parameters and operation address in the access request are first determined, then the configuration method of the algorithm acceleration core function module is selected, then the input / output mapping module is configured, and finally the algorithm acceleration core function module initiates the operation. After the operation is completed, the status register is updated, including:

[0081] The hardware algorithm accelerator judges the parameters and operation address in the received access request;

[0082] If the parameters and the operation address are empty, the data is written to the register based on the high-order bits;

[0083] If the parameters and operation address are not empty, select the configuration register or the parameters and operation address to configure the core functional module for algorithm acceleration;

[0084] Configure the input / output mapping module using parameters and operation addresses;

[0085] The algorithm acceleration core function module initiates the calculation based on the configuration and calculation formula, updates the status flag, enters the busy state, suspends bus access to operand registers, and waits for the calculation to complete.

[0086] Update the status register after the operation is complete.

[0087] According to this invention, the accelerator is first invoked to determine whether the algorithm has resident configuration parameters. Then, it is determined whether the operand register has been pre-written. Next, the final configuration parameters and operation address are written to the operand register. Finally, the calculation is completed. The invocation process includes:

[0088] Call the accelerator to determine if the algorithm is resident in the configuration parameters;

[0089] If the algorithm is to be resident in the configuration parameters, then write to the configuration register and configure the algorithm to be resident in the parameters.

[0090] If the algorithm does not have resident configuration parameters, the algorithm operand register is prewritten. During the prewriting process, the parameters and operation address are kept at 0 until the algorithm operand register is prewritten.

[0091] Write the final configuration parameters and the operation address to the operand register;

[0092] Wait for the calculation to complete, or read the flag bit to determine if the calculation is complete, or read the output result and suspend the bus;

[0093] Once the calculations are complete, the accelerator call will be finished.

[0094] The present invention will now be described in more detail through specific embodiments.

[0095] Example 1

[0096] like Figure 1 As shown, this embodiment provides a device for accelerating high-precision ADC data processing, including an address mapping logic module, an input / output mapping module, a register module, and an algorithm acceleration core function module.

[0097] The address mapping logic module can process an address access request from the bus, splitting it into two parts: register data read / write access commands and parameters and operation commands for the algorithm acceleration core function module. Therefore, an address access can simultaneously complete register read / write and send parameter and operation commands to the algorithm acceleration core function module. The parameter and operation commands include two parts of information, which are sent to the algorithm acceleration core function module and the input / output mapping module, respectively. The algorithm acceleration core function module updates the relevant parameter configurations based on the parameter and operation commands, such as algorithm selection, and initiates the corresponding operation.

[0098] The input / output module selects the input and output of the algorithm called by the algorithm acceleration core function module based on the information in the parameter operation command split from the address mapping logic module each time it comes from the bus. It sends the value in the corresponding operand register to the input terminal of the algorithm acceleration core function module, and sends the value at the output terminal of the algorithm acceleration core function module to the corresponding operand register when the calculation is completed.

[0099] The register module includes configuration registers related to this hardware algorithm accelerator, multiple operand registers for storing data, and configuration registers for clearing operand register data. When writing to the lower operand register of a multi-operand register concatenation (e.g., concatenating two 32-bit operand registers into one 64-bit data for operation), the sign bit of the higher operand register can be automatically padded.

[0100] The core functional modules for algorithm acceleration include hardware algorithm acceleration functions of peripherals, such as multiply-accumulate units, division units, and Cordic units; the hardware algorithm acceleration functions are not limited to the above units; in addition, the number of core algorithm acceleration functional modules integrated in this hardware algorithm accelerator is not limited to one in different practical application scenarios.

[0101] The hardware algorithm accelerator, composed of the above modules, can perform the following functions with a single read operation from the bus: algorithm selection and configuration update, arbitrary combination of input / output and operand registers of the core function module of algorithm acceleration, and update of operand register data; making the hardware algorithm accelerator flexibly invoked and reducing redundant register read / write operations from the bus.

[0102] The address mapping logical structure is as follows: Figure 2 As shown, the address mapping logic segments the address information of a single address access. The higher-order address bits are used for operand register selection, while the lower-order address bits are used for parameter generation and operations. Through this address mapping, a single address access operation can simultaneously read and write registers, update the configuration of the algorithm acceleration core function, select the algorithm, and initiate the calculation operation, thereby saving program space and improving peripheral execution efficiency. In programs, the base address value of peripherals is usually stored in memory as data, and offset address addressing is used to access the various registers under the peripherals to optimize program execution efficiency and storage space.

[0103] In addition, a special mapping method can be used to map multiple registers during a single bus write operation. In this case, the high and low bits of the bus data are split and written to the mapped registers respectively. Similarly, during a bus read operation, multiple registers can be mapped, and the bus data is the result of concatenating the registers. For example, a single write operation can map two 16-bit operand registers simultaneously. In this case, during the write operation, the high 16 bits of the 32-bit data are input to the mapping 1 operand register, and the low 16 bits are input to the mapping 2 operand register. Similarly, during a single read operation, two 16-bit operand registers can be mapped, and the high 16 bits read by the data bus are the value of the mapping 1 operand register, and the low 16 bits are the value of the mapping 2 operand register.

[0104] Because the number of operand registers in this hardware algorithm accelerator is limited, typically four (but not limited to four), which is much smaller than the number of parameters and operations; by mapping the operand registers with the high bits, the program can store only the address corresponding to the operand register as the base address and the parameters and operations as offset addresses after compilation, reducing the program's storage space and optimizing execution efficiency; when the parameters and operations of the hardware algorithm accelerator need to be updated frequently, the program only needs to update the offset address, without having to store the complete address information in the storage space;

[0105] Considering the overflow problem in high-precision ADC data processing, the peripheral configuration of this hardware algorithm accelerator includes fixed-point decimal related configuration. When the decimal function is selected in this configuration, all input and output data will be mapped to fixed points according to the configured decimal places. The calculation always maintains the precision of the decimal places. This can solve the problem of processing 24-bit or 32-bit data of high-precision ADC in an efficient and low-power way.

[0106] Furthermore, some configuration information for parameters and operations can be stored permanently in the configuration register. When certain configurations in an algorithm do not need to be changed each time the hardware algorithm accelerator peripheral is called, it is not necessary to update these parameter configurations every time (such as the number of fixed-point decimal places). This frees up more address space for more parameter and operation mappings or algorithm function expansion. When using the configuration information in the configuration register as parameters of the algorithm module, only special bits in the parameter and operation addresses need to be configured. This method can flexibly utilize address space for more configuration mappings or operation mappings.

[0107] If you wish to clear some operand registers after completing the calculation to avoid interfering with subsequent calculations, you can quickly reset the corresponding registers by writing 1 to the operand register clear bit in the configuration register, thereby improving the algorithm's running efficiency. The configuration register also includes basic configuration information for the algorithm, which can be selected by using special bits in the address operation and parameter bits to determine whether to use the configuration information in the configuration register.

[0108] In this embodiment, taking the multiply-accumulate operation commonly used in high-precision ADC data processing as an example, the address mapping logic structure for this multiply-accumulate operation is as follows: Figure 3 As shown in the diagram, A0, A1, B0, and B1 are all 32-bit operand registers. To complete a multiply-add operation, the operand registers need to be configured with the required values. During the last operand register write, the required multiply-add calculation parameters and the offset address of the operation are added to the base address of the operand register. This offset address contains the input / output mapping and the algorithm mapping. First, the algorithm mapping selects and configures the algorithm for the core functional module of the algorithm acceleration, such as the multiply-add function. Then, the input / output mapping selects the input data required for this calculation from all operand registers through the INPUT MUX and completes the algorithm calculation according to the algorithm mapping. For example, operands A0 and A1 are selected as multipliers MUL0 and MUL1, and {B1, B0} is concatenated into a 64-bit value as the addend. Finally, the output result is selected and output to the corresponding operand register through the OUTPUT MUX, thus completing one calculation operation. For example, the multiply-add result is split into high and low 32 bits and output to registers B1 and B0. In this example, the addition in the multiply-add calculation is selected as a 64-bit input, and the INPUT... When the addend selection in MUX is {B1, B0}, writing to B0 will determine whether the currently configured calculation parameter is a signed number. It will either pad B1 with the sign bit according to the signed two's complement or pad B1 with 0 according to the binary two's complement. This method does not require declaring the variable data as 64 bits in the program, which allows the algorithm to optimize the program's power consumption and program storage space without overflowing errors.

[0109] This embodiment also provides a method for accelerating high-precision ADC data processing, including:

[0110] The operation process of hardware algorithm accelerator, such as Figure 4 As shown, it includes:

[0111] The hardware algorithm accelerator judges the parameters and operation address in the received access request;

[0112] If the parameters and the operation address are empty, the data is written to the register based on the high-order bits;

[0113] If the parameters and operation address are not empty, select the configuration register or the parameters and operation address to configure the core functional module for algorithm acceleration;

[0114] Configure the input / output mapping module using parameters and operation addresses;

[0115] The algorithm acceleration core function module initiates the calculation based on the configuration and calculation formula, updates the status flag, enters the busy state, suspends bus access to operand registers, and waits for the calculation to complete.

[0116] Update the status register after the operation is complete;

[0117] Calling the hardware algorithm accelerator software process, such as Figure 5 As shown, it includes:

[0118] Call the accelerator to determine if the algorithm is resident in the configuration parameters;

[0119] If the algorithm is to be resident in the configuration parameters, then write to the configuration register and configure the algorithm to be resident in the parameters.

[0120] If the algorithm does not have resident configuration parameters, the algorithm operand register is prewritten. During the prewriting process, the parameters and operation address are kept at 0 until the algorithm operand register is prewritten.

[0121] Write the final configuration parameters and the operation address to the operand register;

[0122] Wait for the calculation to complete, or read the flag bit to determine if the calculation is complete, or read the output result and suspend the bus;

[0123] Once the calculations are complete, the accelerator call will be finished.

[0124] The apparatus for accelerating high-precision ADC data computation proposed in the embodiments of the present invention splits an address access request from the address bus into two parts: a read / write access command for the register module and a parameter and operation command for the algorithm acceleration core function module. At the same time, by selecting the computation input and output through address mapping, the computation result can be directly imported into the newly initiated computation input terminal. This reduces the processor's read and write operations on the operand register, thereby improving computational efficiency and reducing program storage space.

[0125] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An apparatus for accelerating high-precision ADC data operation, characterized in that, The application relates to a hardware algorithm accelerator. The application relates to a hardware algorithm accelerator. The address mapping logic module is used for splitting an address access request from the address bus into a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module. The register module comprises configuration registers related to the hardware algorithm accelerator, a plurality of operand registers for storing data, and a configuration register for clearing the data of the operand registers. The input-output mapping module is used for selecting the input and output of an algorithm called by the algorithm acceleration core function module according to information in the parameters and operation commands each time, sending the value in the corresponding operand register module to the input end of the algorithm acceleration core function module, and sending the value at the output end of the algorithm acceleration core function module to the corresponding operand register when the algorithm acceleration core function module completes calculation. The algorithm acceleration core function module is integrated with a plurality of algorithm core acceleration function units and is used for updating the calculation-related parameter configuration of each algorithm core acceleration function unit according to the parameters and operation commands. The plurality of algorithm core acceleration function units comprise multiplication-addition units, division units and cordic units. When at least two operand registers are spliced, the high-bit operand register is automatically completed with a sign bit when the low-bit operand register is written. The modules in the hardware algorithm accelerator work cooperatively, and the functions realized by the read operation from the address bus once include algorithm selection and configuration updating, arbitrary arrangement and combination of the input and output of the algorithm acceleration core function module and the operand registers, and updating of the data of the operand registers, so that the register read-write operation from the bus is reduced.

2. The apparatus of claim 1, wherein, The address mapping logic module processes the address information of one address access in segments, uses the high-bit address bits for operand register selection, uses the low-bit address bits for generating parameters and operations, and realizes that one address access operation is used for reading and writing the register module and updating the configuration of the algorithm acceleration core function module, concurrently initiates the calculation operation while selecting the algorithm, so that program space is saved and peripheral device execution efficiency is improved.

3. The apparatus of claim 1, wherein, The base address value of the peripheral device is stored as data in the memory in the program of the address mapping logic module, and offset addresses are used for addressing and accessing the registers under the peripheral device, so that program execution efficiency and storage space are optimized. The address mapping logic module maps a plurality of registers in one bus write operation, at this time, the high and low bits of the bus data are split and written into the mapped plurality of registers; and the address mapping logic module maps a plurality of registers in one bus read operation, at this time, the bus data is the result after the registers are spliced. ​ 4. The apparatus of claim 1, wherein, The hardware algorithm accelerator maps the operand register by high bits, so that the program only stores the address corresponding to the operand register as a base address after completing the compilation, and the parameter and operation as an offset address, thereby reducing the storage space of the program and optimizing the execution efficiency; When the parameter and operation of the hardware algorithm accelerator need to be frequently updated, only the offset address is updated by the program, and the complete address information is not stored in the storage space; The fixed-point decimal related configuration is included in the peripheral configuration of the hardware algorithm accelerator. When the decimal function of this operation is configured and selected, all input and output data are mapped by fixed-point according to the configured decimal places. The calculation always maintains the precision of the decimal places unchanged, thereby solving the problem of processing 24-bit or 32-bit data of high-precision ADC in an efficient and low-power consumption manner, and avoiding the overflow problem in high-precision ADC data processing.

5. The apparatus of claim 1, wherein, When the parameter and operation command includes part of the configuration information, the configuration information is stored in the configuration register for a long time. When some configurations in an algorithm do not need to be changed every time the hardware algorithm accelerator peripheral is called, the parameter configuration update writing is not needed every time, thereby releasing more address space for more parameter and operation mapping or algorithm function expansion; When the configuration information in the configuration register is used as the parameter of the algorithm module, only the special bits in the parameter and operation address are configured, and the address space is flexibly used for more configuration mapping or operation mapping; After the hardware algorithm accelerator completes the calculation, if it is expected to clear part of the operand register to avoid interfering with subsequent calculation, the corresponding register is quickly reset by writing 1 to the operand register clear bit in the configuration register, thereby improving the algorithm running efficiency; The configuration register also includes basic configuration information of the algorithm. Whether to use the configuration information in the configuration register is selected by the special bits in the operation and parameter bits in the address.

6. A method for accelerating high-precision ADC data operation in the apparatus of any one of claims 1-5, characterized by, The hardware algorithm accelerator running flow includes: First, the parameter and operation address in the access request are judged, then the configuration mode of the algorithm acceleration core function module is selected, then the input and output mapping module is configured, finally the operation is initiated by the algorithm acceleration core function module, and the state register is updated after the operation is completed; The software flow of calling the hardware algorithm accelerator includes:

7. The method of claim 6, wherein, First, the accelerator is called, whether the algorithm is configured as a resident parameter is judged, then whether the operand register is pre-written is judged, then the final configuration parameter and operation address are written to the operand register, and finally the calculation is completed and the calling is completed. The hardware algorithm accelerator running flow includes: The hardware algorithm accelerator judges the parameter and operation address in the received access request; If the parameter and operation address is empty, the data is written according to the mapping to the register by high bits; If the parameter and operation address is not empty, the algorithm acceleration core function module is configured by selecting the configuration register or the parameter and operation address. The input-output mapping module is configured by using the parameters and the operation address; The algorithm acceleration core function module initiates operation according to the configuration and a calculation formula, updates a state flag bit, enters a busy state, suspends a bus access operation to the operand register, and waits for completion of the calculation; The state register is updated after the operation is completed.

8. The method of claim 6, wherein, First, the accelerator is called to determine whether the algorithm is resident in the configuration parameters, then it is determined whether the operand register is pre-written, then the final configuration parameters and the operation address are written into the operand register, and finally the calculation is completed, including: The accelerator is called to determine whether the algorithm is resident in the configuration parameters; If the algorithm is resident in the configuration parameters, the configuration register is written to configure the algorithm resident parameters; If the algorithm is not resident in the configuration parameters, the algorithm operand register is pre-written, and the parameters and the operation address remain 0 during the pre-writing until the algorithm operand register is pre-written; The final configuration parameters and the operation address are written into the operand register; Waiting for the calculation to be completed, or reading the flag bit to determine whether the calculation is completed, or reading the output result bus to be suspended; The accelerator call is completed after the calculation is completed.

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