A register component
By designing register components and utilizing mux selection control areas and signal combinations, the address space of the chip's internal registers was expanded, solving the problem of insufficient register address space and enabling flexible address access.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANJING VPS SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-06-04
- Publication Date
- 2026-05-26
AI Technical Summary
In digital circuits of chips, due to the limitations of communication interfaces, the register address space is insufficient, making it impossible to effectively access a large number of registers.
Design a register assembly including register zero, register one, and register two. Expand the address space through a new address bus and data bus. Access to the new address space is achieved by using a combination of signals from the mux selection control area, read/write enable area, address or write data area, read data area, clock area, and reset area.
Without increasing the width of the register address bus, the address space of the internal registers is expanded, improving access flexibility.
Smart Images
Figure CN224287786U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip architecture technology, and in particular to a register component. Background Technology
[0002] In digital chip circuits, the host computer needs to interact with the chip through a communication interface. The host computer accesses the register spaces of different internal modules through the communication interface to control the overall behavior of the chip and read its internal state. Modern chip circuits are becoming increasingly complex, and the number of registers that need to be accessed is increasing. However, due to the limitations of the communication interface, the number of available register addresses is finite, which can lead to insufficient register address space.
[0003] To address the shortcomings of existing technologies, a register component needs to be designed. Utility Model Content
[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a register component.
[0005] A register assembly, disposed in any partition of the internal register address space of a chip, includes a register zero, a register one, and a register two. The data bits in register zero, register one, and register two generate a new address bus and a new data bus. Register zero includes a mux selection control area divided into m bits, each bit corresponding to a subspace of the new address space, used to generate a selection signal for the subspace. Register one includes a read / write enable area, an address or write data area, and a read data area. Register two includes a clock area and a reset area. Furthermore, the signals generated by register one and register two are decoded by a decoding module and transmitted to the subspace of the new address space selected by register zero through the new address bus and the new data bus.
[0006] Furthermore, the read / write enable area is set to a bit 15 for read / write enable signal, the address or write data area is set to bits [6:0] for generating address signal or write data signal, and the read data area is set to bits [14:8] for generating read data signal.
[0007] Furthermore, the read / write enable area is raised to enable writing and lowered to enable reading.
[0008] Furthermore, the reset area is set to bit 0 to generate a reset signal, and the clock area is set to bit 1 to generate a clock signal.
[0009] Furthermore, when the clock region of register two is pulled high, a rising edge of the clock is generated as a write data signal; when the clock region of register two is pulled low, a falling edge of the clock is generated as an address signal.
[0010] Beneficial effects: The register component provided by this utility model expands the address space of the internal registers by accessing the new address space through indirect read and write without increasing the width of the register address bus, thus providing greater flexibility. Attached Figure Description
[0011] Figure 1 This is a schematic diagram illustrating the access between the host computer and the internal register space of the chip according to this utility model;
[0012] Figure 2 This is a schematic diagram of the partitioning of the register component of this utility model;
[0013] Figure 3 A schematic diagram of the extended register address space for the register component of this utility model; Detailed Implementation
[0014] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0015] Please refer to Figures 1-3 ,like Figure 1 As shown, the host computer and the chip communicate through a communication interface to control the chip's behavior and read its status. The chip's internal register address space is divided into n partitions. The chip's internal decoding module decodes the behavior control and status reading signals and transmits the decoded instructions through the address bus and data bus to read the data in the address space. This embodiment proposes a register component, which is set in any partition of the chip's internal register address space, including a register zero, a register one, and a register two. The data bits in register zero, register one, and register two generate a new address bus and data bus.
[0016] like Figure 2 and Figure 3 As shown, register zero includes a mux selection control area divided into m bits, with each bit corresponding to a subspace of the new address space, used to generate the selection signal for the subspace;
[0017] Register 1 includes a read / write enable area, an address or write data area, and a read data area. The read / write enable area is set to bit 15 for the read / write enable signal. The address or write data area is set to bits [6:0] for generating the address signal or write data signal. The read data area is set to bits [14:8] for generating the read data signal. The read / write enable area is pulled high for writing and pulled low for reading.
[0018] Register 2 includes a clock area and a reset area. The reset area is set to bit 0 to generate a reset signal, and the clock area is set to bit 1 to generate a clock signal. When the clock area of register 2 is pulled high, the rising edge of the clock is used as the write data signal; when the clock area of register 2 is pulled low, the falling edge of the clock is used as the address signal.
[0019] The signals generated by register one and register two are decoded by the decoding module and transmitted to the new address space subspace selected by register zero through the new address bus and data bus. The register component provided by this utility model expands the address space of the internal registers by accessing the new address space through indirect read and write without increasing the width of the register address bus, thus providing greater flexibility.
[0020] When writing data to a new address space: Register 0 selects the address subspace to be written in the new address space, supporting simultaneous or single writing; Bit 1 of Register 2 is pulled high, the selected address signal is written to bits [6:0] of Register 1, Bit 15 of Register 1 is pulled high, Bit 1 of Register 2 is pulled low to generate a falling edge of the clock, at which time the address signal in the new address space is output, the write data signal is written to bits [6:0] of Register 1, Bit 1 of Register 2 is pulled high to generate a rising edge of the clock, at which time the write data signal is output, thus completing one data writing to the new address space of the register.
[0021] When data needs to be read from a new address space: select the address subspace to be read in the new address space through register zero, supporting single reads; pull up bit 1 of register two, write the selected address signal to bits [6:0] of register one, pull down bit 15 of register one, pull down bit 1 of register two to generate a falling edge of the clock, at which time the address signal in the new address space is generated; pull up bit 1 of register two to generate a rising edge of the clock, at which time the read data signal is obtained, thus completing a data read of a new register address space.
[0022] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. A register component, which is arranged in any partition in a chip internal register address space, characterized in that: It includes a register zero, a register one, and a register two. The data bits in register zero, register one, and register two generate a new address bus and a new data bus. Register zero includes a mux selection control area divided into m bits, with each bit corresponding to a subspace of the new address space, used to generate a selection signal for the subspace. Register one includes a read / write enable area, an address or write data area, and a read data area. Register two includes a clock area and a reset area. Furthermore, the signals generated by register one and register two are decoded by a decoding module and transmitted to the subspace of the new address space selected by register zero through the new address bus and data bus.
2. The register assembly of claim 1, wherein: The read / write enable area is set to a bit 15 for read / write enable signal, the address or write data area is set to bits [6:0] for generating address signal or write data signal, and the read data area is set to bits [14:8] for generating read data signal.
3. The register assembly of claim 1 or 2, wherein: The read / write enable area is raised to enable writing and lowered to enable reading.
4. The register assembly of claim 1, wherein: The reset area is set to bit 0 to generate a reset signal, and the clock area is set to bit 1 to generate a clock signal.
5. The register assembly of claim 1 or 4, wherein: When the clock region of register two is pulled high, a rising edge of the clock is generated as a write data signal; when the clock region of register two is pulled low, a falling edge of the clock is generated as an address signal.
6. The register assembly of claim 3, wherein: When the clock region of register two is pulled high, a rising edge of the clock is generated as a write data signal; when the clock region of register two is pulled low, a falling edge of the clock is generated as an address signal.