Semiconductor circuit and power supply circuit

Abstract

The embodiment of the invention relates to a semiconductor circuit and a power supply circuit, which can automatically correct a current sensing circuit in a chip and can improve the accuracy of the current sensing circuit. A semiconductor circuit according to an embodiment includes first to fifth transistors, and an operational amplifier. One end of the first transistor is connected to the first node. One end of the second transistor is connected to a second node different from the first node, and the gate is connected to the gate and the other end of the first transistor. One end of the third transistor is connected to the other end of the first transistor, and the first reference voltage is input to the gate. One end of the fourth transistor is connected to the other end of the second transistor, and the other end is connected to the other end of the third transistor. One end of the fifth transistor is connected to the first node, and the gate is connected to the other end of the second transistor. A first input terminal of the operational amplifier unit is connected to the first node, a second input terminal is connected to the second node, and a voltage corresponding to a voltage difference between the voltage at the first input terminal and the voltage at the second input terminal is input to a gate of the fourth transistor.

Description

[0001] This application takes priority from Japanese Patent Application No. 2024-165357 (Filing Date: September 24, 2024). The entire contents of the base application are hereby incorporated by reference into this application. TECHNICAL FIELD

[0002] The present embodiment relates to a semiconductor circuit and a power supply circuit. BACKGROUND

[0003] A power supply circuit having a current protection circuit is known. The current protection circuit has, for example, a current sensing circuit that detects a current flowing between an input terminal and an output terminal of the power supply circuit using an operational amplifier. Then, the current protection circuit is configured to limit an output current of the power supply circuit based on a detection result of the current sensing circuit to be not more than a prescribed value. SUMMARY

[0004] The present embodiment provides a semiconductor circuit and a power supply circuit that can automatically correct a current sensing circuit on-chip and improve the accuracy of the current sensing circuit.

[0005] The semiconductor circuit according to the present embodiment includes a first transistor to a fifth transistor, and an operational amplifier unit. One end of the first transistor is connected to a first node. One end of a second transistor is connected to a second node different from the first node, and a gate and the other end of the first transistor are connected to a gate of the second transistor. One end of a third transistor is connected to the other end of the first transistor, and a gate is input with a first reference voltage. One end of a fourth transistor is connected to the other end of the second transistor, and the other end is connected to the other end of the third transistor. One end of a fifth transistor is connected to the first node, and a gate is connected to the other end of the second transistor. A first input terminal of the operational amplifier unit is connected to the first node, and a second input terminal is connected to the second node. A voltage corresponding to a voltage difference between the voltage of the first input terminal and the voltage of the second input terminal is input to a gate of the fourth transistor. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a circuit diagram showing an example of a circuit configuration of a power supply circuit having the power supply protection circuit according to the first embodiment.

[0007] Figure 2 FIG. 2 is a circuit diagram showing an example of a more detailed circuit configuration of a power supply circuit having the power supply protection circuit according to the first embodiment.

[0008] Figure 3 FIG. 3 is a schematic diagram showing a first example of an operation of the power supply protection circuit according to the first embodiment.

[0009] Figure 4This is a schematic diagram illustrating a second example of the operation of the power protection circuit according to the first embodiment.

[0010] Figure 5 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit that includes the power protection circuit according to the second embodiment.

[0011] Figure 6 This is a circuit diagram illustrating an example of a power supply circuit having the power protection circuit according to the second embodiment, in more detail.

[0012] Figure 7 This is a timing diagram illustrating an example of the operation of the power protection circuit according to the second embodiment.

[0013] Figure 8 This is a schematic diagram illustrating the operation of the power protection circuit according to the second embodiment, representing a first example.

[0014] Figure 9 This is a schematic diagram illustrating a second example of the operation of the power protection circuit according to the second embodiment.

[0015] Figure 10 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit that includes the power protection circuit according to the third embodiment.

[0016] Figure 11 This is a schematic diagram illustrating the operation of the power protection circuit according to the third embodiment, representing the first example.

[0017] Figure 12 This is a schematic diagram illustrating a second example of the operation of the power protection circuit according to the third embodiment.

[0018] Figure 13 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit that includes the power protection circuit according to the fourth embodiment.

[0019] Figure 14 This is a schematic diagram illustrating the operation of the first example of the power protection circuit according to the fourth embodiment.

[0020] Figure 15 This is a schematic diagram illustrating the operation of the power protection circuit according to the fourth embodiment, representing a second example.

[0021] Figure 16 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit that includes the power protection circuit according to the fifth embodiment.

[0022] Explanation of symbols

[0023] 1, 1A, 1B, 1C, 1D: Power supply circuit; 11: Input terminal; 12: Output terminal; 13: Operational amplifier section; 14: Operational amplifier; 15: Charge pump; PC, PCa, PCb, PCc, PCd: Power protection circuit; AMP, AMPa, AMPb, AMPc1, AMPc2, AMPd1, AMPd2: Correction operational amplifier section; C1~C3: Capacitors; CS1~CS8: Constant current source; IM1, IM2: Current; IV1, IV2: Inverter Devices; LS1, LS2: Level converters; M1~M5, M11~M19, M21~M31, M41~M46, M51~M56, M61~M68: Transistors; N1~N5, N11~N13, N21~N25, N31, N32, N41~N44, N51~N54, N61, N62: Nodes; P1, P1b, P1bh, P2, P2b, P2bh: Control signals; R1~R5: Resistors; S11~S14, S21~S24: Switches. Detailed Implementation

[0024] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the inventive concept. The drawings are schematic or conceptual diagrams. Components having substantially the same function and structure are labeled with the same symbols.

[0025] <1> Implementation Method 1

[0026] The power protection circuit according to the first embodiment is configured to automatically correct the current sensing circuit on-chip. Hereinafter, the details of the power protection circuit according to the first embodiment will be described.

[0027] <1-1> Composition

[0028] Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit 1 equipped with the power protection circuit PC according to the first embodiment. For example... Figure 1 As shown, the power supply circuit 1 includes, for example, an input terminal 11, an output terminal 12, an operational amplifier section 13, an operational amplifier 14, a charge pump 15, transistors M1 to M5, resistors R1 to R3, nodes N1 to N5, and a ground node GND. Transistors M1, M2, and M5 are N-type high-voltage MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Transistors M3 and M4 are P-type high-voltage MOSFETs. A ground voltage is applied to the ground node GND.

[0029] Input terminal 11 is connected to an external power supply (not shown). An input voltage VIN is supplied to input terminal 11 as an external power source. Input terminal 11 is connected to node N1. Output terminal 12 can output the output voltage VOUT of power supply circuit 1. Output terminal 12 is connected to the core circuit (not shown). The core circuit is configured to operate based on the output voltage VOUT supplied from power supply circuit 1.

[0030] Transistor M1 is connected between input terminal 11 and output terminal 12. Specifically, the drain of transistor M1 is connected to input terminal 11, and the source of transistor M1 is connected to output terminal 12. One end of resistor R1 is connected to input terminal 11 via node N1, and the other end of resistor R1 is connected to the drain of transistor M2 via node N2. The source of transistor M2 is connected to output terminal 12.

[0031] Thus, transistor M1, along with resistor R1 (connected in series) and transistor M2, are connected in parallel between input terminal 11 and output terminal 12. Furthermore, the gates of transistors M1 and M2 are each connected to node N4. In this specification, the gate voltages of transistors M1 and M2 are referred to as "VGATE". In power supply circuit 1, the size ratio of transistors M1 and M2 is 1:N. The gate-source voltage Vgs applied between the source and gate of transistor M1 is approximately equal to the gate-source voltage Vgs applied between the source and gate of transistor M2. Thus, transistors M1 and M2 constitute a current mirror circuit.

[0032] One end of resistor R2 is connected to input terminal 11 via node N1. The other end of resistor R2 is connected to the source of transistor M3 via node N3. The drain of transistor M3 is connected to one end of resistor R3 via node N5. The other end of resistor R3 is connected to ground node GND. In this specification, the current flowing through transistor M3 is referred to as "IMON".

[0033] The operational amplifier section 13 is configured to control the gate voltage of transistor M3 so that the voltage at node N2 is equal to the voltage at node N3. Specifically, the non-inverting input terminal (first input terminal) of the operational amplifier section 13 is connected to node N2. The inverting input terminal (second input terminal) of the operational amplifier section 13 is connected to node N3. The output terminal of the operational amplifier section 13 is connected to the gate of transistor M3. Furthermore, the operational amplifier section 13 outputs a signal corresponding to the difference between the voltage at the first input terminal and the voltage at the second input terminal.

[0034] Thus, transistor M3 outputs a signal corresponding to the signal output from operational amplifier section 13. In power supply circuit 1, the resistance values ​​of resistor R1 and resistor R2 are designed to be approximately equal. Therefore, the current IMON flowing through transistor M3 is approximately equal to the current flowing through resistor R1. Current IMON also flows through resistor R3. Therefore, resistor R3 generates a voltage corresponding to the current flowing through resistor R1.

[0035] Operational amplifier 14 is configured to control the gate voltage VGATE based on the voltage at node N5. Specifically, a predetermined reference voltage VREF is input to the non-inverting input (first input terminal) of operational amplifier 14. The inverting input (second input terminal) of operational amplifier 14 is connected to node N5. The output terminal of operational amplifier 14 is connected to node N4. Thus, operational amplifier 14 can output a signal corresponding to the voltage difference between the first and second input terminals to the gates of transistors M1 and M2.

[0036] Charge pump 15 generates a specified voltage based on the input voltage VIN and outputs the generated voltage. The input terminal of charge pump 15 is connected to input terminal 11. The output terminal of charge pump 15 is connected to the source of transistor M4. The drain of transistor M4 is connected to the drain of transistor M5 via node N4. The source of transistor M5 is connected to ground node GND. On / off input signals are input to the gates of transistors M4 and M5 respectively. Figure 1 In the diagram, the group of transistors M4 and M5 is represented as the on / off control circuit SW. The on / off control circuit SW has transistors M4 and M5 connected in series.

[0037] The voltage of node N4, corresponding to the connection nodes of transistors M4 and M5, varies according to the on / off input signal. Specifically, when the on / off input signal is high, node N4 is connected to ground node GND via transistor M5, and the voltage of node N4 (gate voltage VGATE) becomes low. Therefore, transistors M1 and M2 are off, and power supply circuit 1 does not output output voltage VOUT from output terminal 12. On the other hand, when the on / off input signal is low, charge pump 15 is connected to node N4 via transistor M4, and the voltage of node N4 (gate voltage VGATE) becomes high. Therefore, transistors M1 and M2 are on, and power supply circuit 1 outputs output voltage VOUT from output terminal 12.

[0038] When power circuit 1 is turned on, the current flowing through transistor M2 also flows through resistor R1. A pair of transistors M1 and M2 constitute a current mirror circuit. Therefore, the current IM1 flowing through transistor M1 is proportional to the current IM2 flowing through transistor M2. Specifically, the current IM2 is 1 / N of the current IM1 based on the size ratio. Furthermore, operational amplifier section 13 controls transistor M3 to make the voltage at node N2 equal to the voltage at node N3. That is, the current flowing through resistor R1 is controlled to be equal to the current flowing through resistor R2. When the voltage at node N2 is equal to the voltage at node N3, IMON is equal to the current IM2. The current flowing through transistor M3 also flows through resistor R3. Therefore, a voltage corresponding to the current flowing through transistor M2 is generated at node N5. Operational amplifier 14 controls the gate voltage (VGATE) of each of transistors M1 and M2 to make the voltage at node N4 equal to the reference voltage VREF.

[0039] In the power supply circuit 1 described above, the group consisting of transistors M2 and M3, resistors R1 to R3, operational amplifier section 13, and operational amplifier 14 corresponds to the semiconductor circuit that functions as the power protection circuit PC according to the first embodiment. The power protection circuit PC detects the input current input from the input terminal 11. Then, transistor M3 outputs a current IMON corresponding to the input current. The power protection circuit PC can adjust the gate voltages of transistors M1 and M2 based on a comparison between the voltage corresponding to the detected current (IMON) and the reference voltage VREF. A more detailed circuit configuration of the power protection circuit PC will be described below.

[0040] Figure 2 This is a circuit diagram illustrating a more detailed circuit configuration of the power supply circuit 1, which includes the power protection circuit PC according to the first embodiment. Furthermore, in the accompanying drawings referred to below, a portion of the configuration of the power supply circuit 1 has been appropriately omitted. Figure 2 As shown, the power protection circuit PC according to the first embodiment also includes a calibration operational amplifier section AMP. Furthermore, the operational amplifier section 13 includes, for example, transistors M11 to M16, a constant current source CS1, and nodes N11 and N12. Transistors M11 and M12 are P-type high-voltage MOSFETs. Transistors M13 and M14 are N-type high-voltage MOSFETs. Transistors M15 and M16 are, for example, N-type low-voltage MOSFETs.

[0041] The source of transistor M11 is connected to node N3. The drain of transistor M11 is connected to the drain of transistor M13 via node N11. The source of transistor M12 is connected to node N2. The drain of transistor M12 is connected to the drain of transistor M14 via node N12. The gates of transistors M11 and M12 are each connected to node N11. The dimensions of transistor M11 and transistor M12 are approximately the same. Transistors M11 and M12 form a current mirror circuit. Node N12 corresponds to the output terminal of operational amplifier section 13. That is, node N12 is connected to the gate of transistor M3.

[0042] The source of transistor M13 is connected to the drain of transistor M15. The source of transistor M14 is connected to the drain of transistor M16. A clamping voltage VCL is applied to the gates of transistors M13 and M14, respectively. The clamping voltage VCL is a voltage higher than ground. Transistor M13 reduces the source-side voltage based on the clamping voltage VCL. Transistor M14 reduces the source-side voltage based on the clamping voltage VCL. The dimensions of transistors M13 and M14 are approximately the same. By clamping the voltage using transistors M13 and M14, low-voltage MOSFETs can be used as node-connected transistors on the source side.

[0043] The sources of transistors M15 and M16 are connected to node N13. A reference voltage VREF is applied to the gate of transistor M15. The dimensions of transistor M15 are approximately the same as those of transistor M16.

[0044] A constant current source CS1 is connected between node N13 and ground node GND. As a result, the constant current source CS1 operates such that the total current flowing from node N3 to node N13 through transistors M11, M13, and M15, and the total current flowing from node N2 to node N13 through transistors M12, M14, and M16, are constant.

[0045] The operational amplifier section AMP for correction is configured to control the gate voltage of transistor M16 based on the error between the voltages at node N2 and node N3, thereby correcting the operational amplifier section 13. Specifically, the non-inverting input (first input terminal) of the operational amplifier section AMP for correction is connected to node N3. The inverting input (second input terminal) of the operational amplifier section AMP for correction is connected to node N2. The output terminal of the operational amplifier section AMP for correction is connected to the gate of transistor M16. Thus, the operational amplifier section AMP for correction can output a signal corresponding to the voltage difference between the first input terminal and the second input terminal to the gate of transistor M16. When the voltage at the first input terminal is equal to the voltage at the second input terminal, the operational amplifier section AMP for correction outputs a reference voltage VREF.

[0046] In the power protection circuit PC according to the first embodiment described above, transistors M3 and M11 to M14 function as current sensing circuits. Transistors M15 and M16, constant current source CS1, and calibration operational amplifier section AMP function as calibration amplifiers.

[0047] <1-2> Actions

[0048] Next, the operation of the power protection circuit PC according to the first embodiment will be explained.

[0049] Figure 3 This is a schematic diagram illustrating the operation of the power protection circuit PC according to the first embodiment, representing a first example. Figure 3 This example illustrates the operation of the power supply protection circuit PC when the voltage at node N3 is higher than the voltage at node N2. In this example, as... Figure 3 As shown in (1), the voltage (larger) at node N3 is higher than the voltage (smaller) at node N2. In this case, as Figure 3 As shown in (2), the operational amplifier section AMP used for correction controls the output voltage to be higher (larger) than the reference voltage VREF. Therefore, as... Figure 3 As shown in (3), the gate voltage of transistor M16 increases, and the current flowing through transistor M16 increases (becomes larger). The result is as follows: Figure 3 As shown in (4), the gate voltage of transistor M3 decreases, the current flowing through transistor M3 increases, and the voltage of node N3 decreases accordingly.

[0050] Figure 4 This is a schematic diagram illustrating a second example of the operation of the power protection circuit PC according to the first embodiment. Figure 4 This example illustrates the operation of the power supply protection circuit PC when the voltage at node N2 is higher than the voltage at node N3. In this example, as... Figure 4 As shown in (1), the voltage (larger) at node N2 is higher than the voltage (smaller) at node N3. In this case, as Figure 4 As shown in (2), the operational amplifier section AMP used for correction controls the output voltage to be lower (smaller) than the reference voltage VREF. Therefore, as... Figure 4 As shown in (3), the gate voltage of transistor M16 decreases, and the current flowing through transistor M16 decreases (becomes smaller). The result is as follows: Figure 4 As shown in (4), the gate voltage of transistor M3 increases, the current flowing through transistor M3 decreases, and the voltage of node N3 increases accordingly.

[0051] As explained above, the power protection circuit PC according to the first embodiment can adjust the gate voltage of transistor M16 and adjust the current flowing through transistor M3 based on the error between the voltage of node N2 and the voltage of node N3.

[0052] <1-3> Effects of the first embodiment

[0053] In the power protection circuit PC according to the first embodiment, the operational amplifier section 13 is configured to be self-calibrating, which can suppress (reduce) the deviation of the current IMON flowing through the transistor M3. Therefore, the power protection circuit PC according to the first embodiment can automatically calibrate the current sensing circuit on-chip, improving the accuracy of current sensing. Consequently, the power supply circuit 1 equipped with the power protection circuit PC according to the first embodiment can limit the output current with high precision. Furthermore, the power protection circuit PC according to the first embodiment is configured to be self-calibrating, thus simplifying the testing process. As a result, the power protection circuit PC according to the first embodiment can reduce the manufacturing cost of the power supply circuit 1.

[0054] <2> Implementation Method 2

[0055] The second embodiment relates to a more specific circuit configuration of the correction operational amplifier section AMP used as a correction amplifier. Hereinafter, details regarding the power protection circuit PCa according to the second embodiment will be described, focusing on the differences from the first embodiment.

[0056] <2-1> Composition

[0057] Figure 5 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit 1A that includes the power protection circuit PCa according to the second embodiment. For example... Figure 5 As shown, the power protection circuit PCa according to the second embodiment has the following configuration: compared with the power protection circuit PC according to the first embodiment, the calibration operational amplifier section AMP is replaced with the calibration operational amplifier section AMPa. The calibration operational amplifier section AMPa includes, for example, transistors M21 to M26, capacitors C1 and C2, switches S11, S12, S21 and S22, a constant current source CS2, and nodes N21 to N25. Transistors M21 and M22 are both P-type high-voltage MOSFETs. Transistors M23 and M24 are both N-type high-voltage MOSFETs. Transistors M25 and M26 are, for example, N-type low-voltage MOSFETs.

[0058] The groups of switches S11 and S12, and the groups of switches S21 and S22, are controlled complementaryly, for example. When switches S11 and S12 are controlled to the on state, switches S21 and S22 are controlled to the off state. When switches S21 and S22 are controlled to the on state, switches S11 and S12 are controlled to the off state.

[0059] The source of transistor M21 is connected to node N3 via switch S11 and to node N2 via switch S21. The drain of transistor M21 is connected to the drain of transistor M23 via node N21. The source of transistor M22 is connected to node N3. The drain of transistor M22 is connected to the drain of transistor M24. The gates of transistors M21 and M22 are each connected to node N21. The dimensions of transistor M21 and transistor M22 are approximately the same. Transistors M21 and M22 form a current mirror circuit.

[0060] The source of transistor M23 is connected to the drain of transistor M25. The source of transistor M24 is connected to the drain of transistor M26 via node N22. A clamping voltage VCL is applied to the gates of transistors M23 and M24, respectively. Transistor M23 reduces the source-side voltage based on the clamping voltage VCL. Transistor M24 reduces the source-side voltage based on the clamping voltage VCL. The dimensions of transistor M23 and M24 are approximately the same. By clamping the voltage using transistors M23 and M24, low-voltage MOSFETs can be used as transistors connected to the source-side node.

[0061] The sources of transistors M25 and M26 are connected to node N23. A reference voltage VREF is applied to the gate of transistor M25. The dimensions of transistor M25 are approximately the same as those of transistor M26.

[0062] A constant current source CS2 is connected between node N23 and ground node GND. As a result, the constant current source CS2 operates to ensure that the total current flowing from node N2 or N3 to node N23 via transistors M21, M23, and M25, and the total current flowing from node N3 to node N23 via transistors M22, M24, and M26, is constant.

[0063] Furthermore, node N22 is connected to node N24 via switch S12, and to node N25 via switch S22. Node N24 is connected to the gate of transistor M26. Node N25 is connected to the gate of transistor M16. That is, node N25 corresponds to the output terminal of the correction operational amplifier section AMPa.

[0064] One end of capacitor C1 is connected to node N24. The other end of capacitor C1 is connected to ground node GND. Thus, capacitor C1 is configured to store charge based on the voltage at node N24. One end of capacitor C2 is connected to node N25. The other end of capacitor C2 is connected to ground node GND. Thus, capacitor C2 is configured to store charge based on the voltage at node N24.

[0065] Figure 6This is a circuit diagram illustrating an example of a more detailed circuit configuration of a power supply circuit 1A equipped with the power protection circuit PCa according to the second embodiment. For example... Figure 6 As shown, the power protection circuit PCa according to the second embodiment also includes transistors M17-M19 and M27-M30, inverters IV1 and IV2, and level shifters LS1 and LS2. Transistors M17, M27, and M30 are, for example, N-type low-voltage MOSFETs. Transistors M18, M19, M28, and M29 are, for example, P-type low-voltage MOSFETs.

[0066] The drain of transistor M17 is connected to node N13. The drain of transistor M27 is connected to node N23. The sources of transistors M17, M27, and M30 are each connected to ground node GND. A voltage IBIAS is applied to the gate of transistor M17, the gate of transistor M27, and the drain and gate of transistor M30. A constant current based on voltage IBIAS flows between the source and drain of transistor M30. Transistors M17 and M27 reflect the constant current flowing through transistor M30 by applying voltage IBIAS to their gates. Thus, transistors M17 and M27 function as constant current sources CS1 and CS2, respectively.

[0067] The source of transistor M28 is connected to node N3. The source of transistor M18 is connected to node N2. The drains of transistors M28 and M18 are connected to the sources of transistor M21, respectively. Control signals P1 and P2 are input to level shifters LS1 and LS2, respectively. Level shifter LS1 inverts the input control signal P1, and the resulting control signal P1bh is input to the gate of transistor M28. Level shifter LS2 inverts the input control signal P2, and the resulting control signal P2bh is input to the gate of transistor M18. Thus, transistors M28 and M18 function as switches S11 and S21, respectively.

[0068] The sources of transistors M29 and M19 are connected to node N22, respectively. The drain of transistor M29 is connected to node N24. The drain of transistor M19 is connected to node N25. Control signals P1 and P2 are input to inverters IV1 and IV2, respectively. Inverter IV1 inputs the inverted control signal P1b to the gate of transistor M29. Inverter IV2 inputs the inverted control signal P2b to the gate of transistor M19. Thus, transistors M29 and M19 function as switches S12 and S22, respectively.

[0069] <2-2> Actions

[0070] Next, the operation of the power protection circuit PCa according to the second embodiment will be described. In this specification, a high-level voltage is a voltage such that an N-type MOSFET with its gate applied to it is in the ON state, and a P-type MOSFET with its gate applied to it is in the OFF state. For example, a high-level voltage is 3V. A low-level voltage is a voltage where the N-type MOSFET with its gate applied to it is in the OFF state, and the P-type MOSFET with its gate applied to it is in the ON state. For example, a low-level voltage is 0V. Vin is a voltage higher than the ground voltage. The ground voltage is, for example, 0V.

[0071] Figure 7 This is a timing diagram illustrating an example of the operation of the power protection circuit PCa according to the second embodiment. Figure 7 The illustration shows the actions of control signals P1, P1b, P1bh, P2, P2b, and P2bh when power supply circuit 1 is in the ON state. Figure 7 As shown, control signals P1 and P2 are mutually inverted and non-overlapping clock signals. Specifically, for control signals P1, P1b, and P1bh, control during period T_P1on and period T_P1off are performed alternately and repeatedly. For control signals P2, P2b, and P2bh, control during period T_P1on and period T_P1off are performed alternately and repeatedly.

[0072] During period T_P1on, control signal P1 is controlled to, for example, 3V (high level). During period T_P1on, control signal P1b is controlled to, for example, 0V (low level). During period T_P1on, control signal P1bh is controlled to, for example, Vin-3V (low level). Therefore, during period T_P1on, transistors M28 and M29 are turned on. That is, during period T_P1on, switches S11 and S12 are turned on.

[0073] During the period T_P1off, control signal P1 is controlled to, for example, 0V (low level). During the period T_P1off, control signal P1b is controlled to, for example, 3V (high level). During the period T_P1off, control signal P1bh is controlled to, for example, Vin (high level). Therefore, during the period T_P1off, transistors M28 and M29 are in the off state. That is, during the period T_P1off, switches S11 and S12 are controlled to the off state.

[0074] During the period T_P2on, control signal P2 is controlled to, for example, 3V (high level). During the period T_P2on, control signal P2b is controlled to, for example, 0V (low level). During the period T_P2on, control signal P2bh is controlled to, for example, Vin-3V (low level). Therefore, during the period T_P2on, transistors M18 and M19 are turned on. That is, during the period T_P2on, switches S21 and S22 are controlled to be turned on.

[0075] During the period T_P2off, control signal P2 is controlled to, for example, 0V (low level). During the period T_P2off, control signal P2b is controlled to, for example, 3V (high level). During the period T_P1off, control signal P2bh is controlled to, for example, Vin (high level). Therefore, during the period T_P2off, transistors M18 and M19 are in the off state. That is, during the period T_P2on, switches S21 and S22 are controlled to the off state.

[0076] The period T_P1on is included in the period T_P2off. The period T_P2on is included in the period T_P1off. In this way, the groups of switches S11 and S12 and the groups of switches S21 and S22 are controlled to not be turned on simultaneously. The period T_P1on can also be set shorter than the period T_P2off. The period T_P2on can also be set shorter than the period T_P1off. Figure 7 The example illustrates a case where a portion of period T_P1off overlaps with a portion of period T_P2off.

[0077] Figure 8 This is a schematic diagram illustrating the operation of the power protection circuit PCa according to the second embodiment, representing a first example. Figure 8 This example illustrates the operation of the power protection circuit PCa during the period when the periods T_P1on and T_P2off overlap. For example... Figure 8 As shown, in this example, switches S11 and S21 are in the ON and OFF states, respectively. Therefore, current flows from node N3 through transistors M21, M23 and M25, and through transistors M22, M24 and M26 into node N23.

[0078] Furthermore, in this example, since switches S12 and S22 are in the ON and OFF states respectively, current flows from node N22 to node N24 via switch S12, allowing node N24 to be charged. Then, capacitor C1 can store the charge flowing into node N24. Subsequently, the operational amplifier section AMPa adjusts the voltage at node N24, i.e., the gate voltage of transistor M26, so that the difference between the drain voltage of transistor M21 and the drain voltage of transistor M22 is close to zero.

[0079] Specifically, in the operational amplifier section AMPa for correction, when the drain voltage of transistor M21 is lower than the drain voltage of transistor M22, the voltage at node N24 (the gate voltage of transistor M26) increases, and the current flowing through transistor M26 increases. As a result, the drain voltage of transistor M22 decreases. On the other hand, in the operational amplifier section AMPa for correction, when the drain voltage of transistor M21 is higher than the drain voltage of transistor M22, the voltage at node N24 (the gate voltage of transistor M26) decreases, and the current flowing through transistor M26 decreases. As a result, the drain voltage of transistor M22 increases.

[0080] As explained above, during the period when T_P1on and T_P2off overlap, the operational amplifier section AMPa, which functions as a correction amplifier, can be corrected itself. Furthermore, during the period when T_P1on and T_P2off overlap, the voltage at node N25 becomes a voltage based on the charge stored in capacitor C2.

[0081] Figure 9 This is a schematic diagram illustrating a second example of the operation of the power protection circuit PCa according to the second embodiment. Figure 9 This example illustrates the operation of the power protection circuit PCa during the period when the periods T_P2on and T_P1off overlap. For example... Figure 9 As shown, in this example, since switches S11 and S21 are in the off state (OFF) and the on state (ON) respectively, the current from node N3 through transistors M22, M24 and M26 and the current from node N2 through transistors M21, M23 and M25 flow into node N23.

[0082] Furthermore, in this example, since switches S12 and S22 are in the off state (OFF) and on state (ON) respectively, current flows from node N22 into node N25 via switch S22, and node N25 can be charged. Then, capacitor C2 can store the charge flowing into node N25. Subsequently, the operational amplifier section AMPa adjusts the voltage of node N25, i.e., the gate voltage of transistor M16, so that the voltage difference between node N3 and node N2 is close to zero.

[0083] Specifically, when the voltage at node N3 is higher than the voltage at node N2, the correction operational amplifier section AMPa causes the voltage at node N25 to rise. As a result, the current flowing through transistor M16 increases, and the gate voltage of transistor M3 decreases. Consequently, the current flowing through transistor M3 increases, and the voltage at node N3 decreases. Conversely, when the voltage at node N3 is lower than the voltage at node N2, the correction operational amplifier section AMPa causes the voltage at node N25 to decrease. As a result, the current flowing through transistor M16 decreases, and the gate voltage of transistor M3 rises. Consequently, the current flowing through transistor M3 decreases, and the voltage at node N3 rises.

[0084] As explained above, during the period when T_P2on and T_P1off overlap, the current sensing circuit (transistors M11 to M14) can be corrected. Furthermore, during the period when T_P1on and T_P2off overlap, the voltage at node N24 becomes a voltage based on the charge stored in capacitor C1.

[0085] <2-3> Effects of the second implementation method

[0086] In the power protection circuit PCa according to the second embodiment, the calibration operational amplifier section AMPa and the current sensing circuit can be calibrated alternately, thereby improving the accuracy of the calibration operational amplifier section AMPa compared to the first embodiment. As a result, the power protection circuit PCa according to the second embodiment can suppress (reduce) the deviation of the current IMON flowing through the transistor M3 compared to the first embodiment, and can improve the accuracy of current sensing. Therefore, the power supply circuit 1A equipped with the power protection circuit PCa according to the second embodiment can limit the output current with high accuracy compared to the first embodiment. Furthermore, similar to the first embodiment, the power protection circuit PCa according to the second embodiment can simplify the testing process and reduce the manufacturing cost of the power supply circuit 1.

[0087] <3> Third implementation method

[0088] The power protection circuit PCb according to the third embodiment is a variation of the power protection circuit PCb according to the second embodiment. Hereinafter, the details of the power protection circuit PCb according to the third embodiment will be described, mainly focusing on the differences from the first and second embodiments.

[0089] <3-1> Composition

[0090] Figure 10 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit 1B that includes the power protection circuit PCb according to the third embodiment. For example... Figure 10 As shown, the power protection circuit PCb according to the third embodiment has the following configuration: Compared to the power protection circuit PCa according to the second embodiment, the correction operational amplifier section AMPa is replaced by the correction operational amplifier section AMPb. The correction operational amplifier section AMPb has the following configuration: Compared to the correction operational amplifier section AMPa, transistors M25 and M26, constant current source CS2, and node N23 are omitted, and resistors R4 and R5, constant current sources CS3 and CS4, transistor M31, and nodes N31 and N32 are added. Transistor M31 is, for example, an N-type high-voltage MOSFET.

[0091] A constant current source CS3 is connected between the source of transistor M23 and the ground node GND. A constant current source CS4 is connected between the source of transistor M24 and the ground node GND. The switch S11 of the third embodiment is connected between nodes N3 and N31. The switch S21 of the third embodiment is connected between nodes N2 and N31. The source of transistor M21 of the third embodiment is connected to node N31 via resistor R4. The source of transistor M22 of the third embodiment is connected to node N32. Node N32 is connected to node N3 via resistor R5. The drain of transistor M31 is connected to node N32. The source of transistor M31 is connected to the ground node GND. Node N24 of the third embodiment is connected to the gate of transistor M31.

[0092] <3-2> Actions

[0093] Next, the operation of the power protection circuit PCb according to the third embodiment will be described. The control method of switches S11, S12, S21, and S22 in the power protection circuit PCb according to the third embodiment is the same as that used in the first embodiment. Figure 7 The control methods described are the same.

[0094] Figure 11 This is a schematic diagram illustrating the operation of the power protection circuit PCb according to the third embodiment, representing a first example. Figure 11The operation of the power protection circuit PCb is illustrated when switches S11 and S12 are in the ON state and switches S21 and S22 are in the OFF state. The calibration operational amplifier section AMPb adjusts the voltage at node N24, i.e., the gate voltage of transistor M31, so that the difference between the voltage of resistor R5 and the voltage of resistor R4 is close to zero.

[0095] In this example, such as Figure 11 As shown in (1), the voltage (larger) across resistor R5 is higher than the voltage (smaller) across resistor R4. In this case, in the calibration operational amplifier section AMPb, as... Figure 11 As shown in (2), the voltage at node N24 increases (largely). Therefore, as... Figure 11 As shown in (3), the gate voltage of transistor M31 increases, the current flowing through transistor M31 increases (becomes larger), and the voltage at node N32 decreases. On the other hand, although the diagram is omitted, when the voltage across resistor R5 is lower than the voltage across resistor R4, the voltage at node N24 in the correction operational amplifier section AMPb decreases. Consequently, the gate voltage of transistor M31 decreases, the current flowing through transistor M31 decreases, and the voltage at node N32 increases.

[0096] As explained above, the calibration operational amplifier section AMPa, used as a calibration amplifier, can be calibrated by adjusting the gate voltage of transistor M31. Furthermore, as... Figure 11 As shown in (4), capacitor C1 can store the charge flowing through node N24. The amount of charge stored in capacitor C1 can vary depending on the voltage across resistors R4 and R5.

[0097] Figure 12 This is a schematic diagram illustrating a second example of the operation of the power protection circuit PCb according to the third embodiment. Figure 12 The operation of the power protection circuit PCb is illustrated during the period when switches S11 and S12 are in the off state (OFF) and switches S21 and S22 are in the on state (ON).

[0098] In this example, current flows from node N3 into node N25 via resistor R5, transistors M22 and M24, and switch S22, allowing node N25 to be charged. Furthermore, capacitor C2 stores the charge flowing into node N25. Additionally, current flows from node N2 into ground node GND via switch S21, resistor R4, and transistors M21 and M23. The operational amplifier section AMPb then adjusts the voltage at node N25, i.e., the gate voltage of transistor M16, to bring the voltage difference between node N3 and node N2 close to zero.

[0099] Specifically, when the voltage at node N3 is higher than the voltage at node N2, the operational amplifier section AMPb for correction increases the voltage at node N25. As a result, the current flowing through transistor M16 increases, and the gate voltage of transistor M3 decreases. Consequently, the current flowing through transistor M3 increases, and the voltage at node N3 decreases. On the other hand, when the voltage at node N3 is lower than the voltage at node N2, the operational amplifier section AMPb for correction decreases the voltage at node N25. As a result, the current flowing through transistor M16 decreases, and the gate voltage of transistor M3 increases. Consequently, the current flowing through transistor M3 decreases, and the voltage at node N3 increases.

[0100] As explained above, the current sensing circuit (transistors M11 to M14) can be calibrated during the period when switches S11 and S12 are in the off state (OFF) and switches S21 and S22 are in the on state (ON). Furthermore, during the period when switches S11 and S12 are in the on state (ON) and switches S21 and S22 are in the off state (OFF), the voltage at node N24 becomes a voltage based on the charge stored in capacitor C1.

[0101] <3-3> Effects of the third implementation method

[0102] The power protection circuit PCb in the third embodiment is the same as that in the second embodiment, and can suppress (reduce) the deviation of the current IMON flowing through the transistor M3, thereby improving the accuracy of current sensing. Therefore, the power supply circuit 1B equipped with the power protection circuit PCb in the third embodiment can limit the output current with higher accuracy compared to the first embodiment. Furthermore, since the power protection circuit PCb in the third embodiment is the same as that in the first embodiment, it simplifies the testing process and reduces the manufacturing cost of the power supply circuit 1B.

[0103] <4> Implementation Method 4

[0104] The power protection circuit PCc according to the fourth embodiment is configured to perform calibration of the current sensing circuit using two calibration operational amplifier sections AMP. Hereinafter, details of the power protection circuit PCc according to the fourth embodiment will be described, focusing on the differences from the first to third embodiments.

[0105] <4-1> Composition

[0106] Figure 13 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit 1C equipped with the power protection circuit PCc according to the fourth embodiment. For example... Figure 13As shown, the power protection circuit PCc according to the fourth embodiment has the following configuration: Compared to the power protection circuit PCa according to the second embodiment, the correction operational amplifier section AMPa is replaced by two correction operational amplifier sections AMPc1 and AMPc2. The correction operational amplifier section AMPc1 has the same configuration as the correction operational amplifier section AMPa. The correction operational amplifier section AMPc2 includes, for example, transistors M41 to M46, capacitor C3, switches S13, S14, S23 and S24, a constant current source CS5, and nodes N41 to N44. Transistors M41 and M42 are P-type high-voltage MOSFETs. Transistors M43 and M44 are N-type high-voltage MOSFETs. Transistors M45 and M46 are, for example, N-type low-voltage MOSFETs. The groups of switches S11 to S14 and the groups of switches S21 to S24 are, for example, controlled complementaryly.

[0107] The source of transistor M41 is connected to node N2 via switch S13 and to node N3 via switch S23. The drain of transistor M41 is connected to the drain of transistor M43 via node N41. The source of transistor M42 is connected to node N3. The drain of transistor M42 is connected to the drain of transistor M44. The gates of transistors M41 and M42 are each connected to node N41. The dimensions of transistor M41 and transistor M42 are approximately the same. Transistors M41 and M42 form a current mirror circuit.

[0108] The source of transistor M43 is connected to the drain of transistor M45. The source of transistor M44 is connected to the drain of transistor M46 via node N42. A clamping voltage VCL is applied to the gates of transistors M43 and M44, respectively. Transistor M43 reduces the source-side voltage based on the clamping voltage VCL. Transistor M44 reduces the source-side voltage based on the clamping voltage VCL. The dimensions of transistors M43 and M44 are approximately the same. By clamping the voltage using transistors M43 and M44, low-voltage MOSFETs can be used as transistors connected to the source-side node.

[0109] The sources of transistors M45 and M46 are connected to node N43. A reference voltage VREF is applied to the gate of transistor M45. The dimensions of transistor M45 and transistor M46 are approximately the same.

[0110] A constant current source CS5 is connected between node N43 and ground node GND. As a result, the constant current source CS5 operates such that the total current flowing from node N2 or N3 to node N43 through transistors M41, M43, and M45, and the total current flowing from node N3 to node N43 through transistors M42, M44, and M46, is constant.

[0111] Furthermore, node N42 is connected to node N25 via switch S14 and to node N44 via switch S24. Node N44 is connected to the gate of transistor M46. One end of capacitor C3 is connected to node N44. The other end of capacitor C3 is connected to ground node GND. That is, capacitor C3 is configured to store charge based on the voltage of node N44.

[0112] <4-2> Actions

[0113] Next, the operation of the power protection circuit PCc according to the fourth embodiment will be described. The control method of switches S11, S12, S21, and S22 in the power protection circuit PCc according to the fourth embodiment is the same as that used in the first embodiment. Figure 7 The control methods described are the same. Furthermore, the control methods for switches S13 and S14 in the fourth embodiment are the same as those for switches S11 and S12. The control methods for switches S23 and S24 in the fourth embodiment are the same as those for switches S21 and S22.

[0114] Figure 14 This is a schematic diagram illustrating the operation of the first example of the power protection circuit PCc according to the fourth embodiment. Figure 14 The operation of the power protection circuit PCc is illustrated during the period when switches S11-S14 are in the ON state and switches S21-S24 are in the OFF state. Furthermore, in this example, the operation of the calibration operational amplifier section AMPc1 is the same as that used in the second embodiment. Figure 8 The operation of the AMPb section of the calibration amplifier is the same as that described above.

[0115] like Figure 14 As shown, in this example, in the calibration operational amplifier section AMPc2, switches S13 and S23 are in the ON and OFF states, respectively. Therefore, current flows from node N2 through transistors M41, M43, and M45, and current flows from node N3 through transistors M42, M44, and M46 into node N43. Furthermore, in this example, since switches S14 and S24 are in the ON and OFF states, respectively, current flows from node N42 into node N25 through switch S14, allowing node N25 to be charged. Capacitor C2 can then store the charge flowing into node N24. Subsequently, the calibration operational amplifier section AMPc2 adjusts the voltage of node N25, i.e., the gate voltage of transistor M16, so that the voltage difference between node N3 and node N2 approaches zero.

[0116] That is, during the period when switches S11 to S14 are in the ON state and switches S21 to S24 are in the OFF state, the calibration operational amplifier section AMPc1 performs self-calibration, and the calibration operational amplifier section AMPc2 performs calibration of the current sensing circuit.

[0117] Figure 15 This is a schematic diagram illustrating the second example of the operation of the power protection circuit PCc according to the fourth embodiment. Figure 15 The operation of the power protection circuit PCc is illustrated during the period when switches S11-S14 are in the off state (OFF) and switches S21-S24 are in the on state (ON). Furthermore, in this example, the operation of the calibration operational amplifier section AMPc1 is the same as that used in the second embodiment. Figure 9 The operation of the AMPb section of the calibration amplifier is the same as that described above.

[0118] like Figure 15 As shown, in this example, in the calibration operational amplifier section AMPc2, switches S13 and S23 are in the off state (OFF) and the on state (ON), respectively. Therefore, current flows from node N3 through transistors M41, M43, and M45, and current flows through transistors M42, M44, and M46 into node N43. Furthermore, in this example, since switches S14 and S24 are in the off state (OFF) and the on state (ON), respectively, current flows from node N42 into node N44 through switch S24, and node N44 can be charged. Furthermore, capacitor C3 can store the charge flowing into node N44. Then, the calibration operational amplifier section AMPc2 adjusts the voltage of node N24, i.e., the gate voltage of transistor M46, so that the difference between the source voltage of transistor M41 and the source voltage of transistor M42 is close to zero.

[0119] That is, during the period when switches S11 to S14 are in the off state (OFF) and switches S21 to S24 are in the on state (ON), the calibration operational amplifier section AMPc1 performs calibration of the current sensing circuit, and the calibration operational amplifier section AMPc2 performs self-calibration.

[0120] <4-3> Effects of the fourth implementation method

[0121] In the power protection circuit PCc according to the fourth embodiment, when the power circuit 1C is in the on state, one of the calibration operational amplifier sections AMPc1 and AMPc2 performs self-calibration, and the other of the calibration operational amplifier sections AMPc1 and AMPc2 performs calibration of the current sensing circuit. That is, the calibration operational amplifier sections AMPc1 and AMPc2 alternately perform self-calibration and calibration of the current sensing circuit.

[0122] Therefore, compared to the second embodiment, the power protection circuit PCc according to the fourth embodiment can better suppress (reduce) the deviation of the gate voltage of the transistor M16 used in adjusting the gate voltage of the transistor M3, and can further improve the accuracy of current sensing. Thus, the power supply circuit 1C equipped with the power protection circuit PCc according to the fourth embodiment can limit the output current with higher accuracy compared to the second embodiment. Furthermore, the power protection circuit PCc according to the fourth embodiment is the same as that in the first embodiment, which simplifies the testing process and reduces the manufacturing cost of the power supply circuit 1C.

[0123] Furthermore, the total capacitance of capacitors C1 to C3 in the power protection circuit PCc according to the fourth embodiment can be designed to be smaller than the total capacitance of capacitors C1 and C2 in the power protection circuit PC1. That is, compared to the power protection circuit PCa according to the second embodiment, the total capacitor capacitance can be reduced in the power protection circuit PCc according to the fourth embodiment. This is because, in the power protection circuit PCc according to the fourth embodiment, capacitor C2 is charged at a higher frequency than in the second embodiment, allowing for a reduction in the capacitance of capacitor C2 used in controlling the gate voltage of transistor M16. As a result, compared to the second embodiment, the power protection circuit PCc according to the fourth embodiment can reduce chip size and suppress manufacturing costs.

[0124] <5> Fifth Implementation

[0125] The power protection circuit PCd according to the fifth embodiment has a configuration in which a common-source, common-gate transistor is added to the power protection circuit PCc according to the fourth embodiment. Hereinafter, the details of the power protection circuit PCd according to the fifth embodiment will be described, mainly focusing on the differences from the first to fourth embodiments.

[0126] <5-1> Composition

[0127] Figure 16 This is a circuit diagram illustrating an example of the circuit configuration of a power supply circuit 1D that includes the power protection circuit PCd according to the fifth embodiment. For example... Figure 16 As shown, the power protection circuit PCd according to the fifth embodiment has the following configuration: compared with the power protection circuit PCc according to the fourth embodiment, transistors M51 to M56, M61 to M68, constant current sources CS6 to CS8, and nodes N51 to N54, N61, and N62 are added. Transistors M51 to M56 and M61 are, for example, low-voltage PMOS transistors. Transistors M62 to M68 are, for example, low-voltage NMOS transistors.

[0128] The source of transistor M51 is connected to node N1. The drain of transistor M51 is connected to node N53. In the fifth embodiment, the gates of transistors M21 and M22 are not connected to node N21 but to node N53. A constant current source CS6 is connected between node N53 and ground node GND. The constant current source CS6 operates to keep the amount of current flowing through transistor M51 constant.

[0129] The source of transistor M52 is connected to node N1. The drain of transistor M52 is connected to node N54. In the fifth embodiment, the gates of transistors M41 and M42 are not connected to node N41 but to node N54. A constant current source CS7 is connected between node N54 and ground node GND. The constant current source CS7 operates to keep the amount of current flowing through transistor M52 constant.

[0130] The source of transistor M53 is connected to node N3 via switch S11 and to node N2 via switch S21. The drain of transistor M53 is connected to the source of transistor M21. The source of transistor M54 is connected to node N3. The drain of transistor M53 is connected to the source of transistor M22 via node N51. Node N51 is connected to the gate of transistor M51. The gates of transistors M53 and M54 are each connected to node N21.

[0131] The source of transistor M55 is connected to node N3 via switch S23 and to node N2 via switch S13. The drain of transistor M55 is connected to the source of transistor M41. The source of transistor M56 is connected to node N3. The drain of transistor M56 is connected to the source of transistor M42 via node N52. Node N52 is connected to the gate of transistor M52. The gates of transistors M55 and M56 are each connected to node N41.

[0132] The gates of transistors M23, M24, M43, and M44, and the source of transistor M61, are connected to node N61. A clamping voltage VCL is applied to node N61. The drain and gate of transistor M61 are connected to node N62. The drain and gate of transistor M62 are also connected to node N62. Node N62 is connected to the gates of transistors M63 through M68. A constant current source CS8 is connected between the source of transistor M62 and the ground node GND. The constant current source CS8 operates to ensure that the amount of current flowing through transistor M62 remains constant.

[0133] Transistor M63 is connected between transistors M13 and M15. Specifically, the drain of transistor M63 is connected to the source of transistor M13, and the source of transistor M63 is connected to the drain of transistor M15. Transistor M64 is connected between transistors M14 and M16. Specifically, the drain of transistor M64 is connected to the source of transistor M14, and the source of transistor M64 is connected to the drain of transistor M16. The dimensions of transistor M63 and transistor M64 are approximately the same.

[0134] Transistor M65 is connected between transistors M23 and M25. Specifically, the drain of transistor M65 is connected to the source of transistor M23, and the source of transistor M65 is connected to the drain of transistor M25. Transistor M66 is connected between transistors M24 and M26. Specifically, the drain of transistor M66 is connected to the source of transistor M24, and the source of transistor M66 is connected to the drain of transistor M26. The dimensions of transistor M65 and transistor M66 are approximately the same.

[0135] Transistor M67 is connected between transistors M43 and M45. Specifically, the drain of transistor M67 is connected to the source of transistor M43, and the source of transistor M67 is connected to the drain of transistor M45. Transistor M68 is connected between transistors M44 and M46. Specifically, the drain of transistor M68 is connected to the source of transistor M44, and the source of transistor M68 is connected to the drain of transistor M46. The dimensions of transistor M67 and transistor M68 are approximately the same.

[0136] <5-2> Actions

[0137] The operation of the power protection circuit PCd in the fifth embodiment is the same as that in the fourth embodiment.

[0138] <5-3> Effects of the 5th Embodiment

[0139] In the power protection circuit PCd according to the fifth embodiment, transistors M51 to M56 and M61 to M68 are connected in a common-source, common-gate configuration. Therefore, compared to the fourth embodiment, the power protection circuit PCd according to the fifth embodiment can further reduce the deviation of the current IMON flowing through transistor M3, and can improve the accuracy of current sensing. Consequently, the power circuit 1D equipped with the power protection circuit PCd according to the fifth embodiment can limit the output current with higher accuracy compared to the fourth embodiment.

[0140] <6> other

[0141] The circuit configurations described in the above embodiments are merely examples. For instance, transistors M13 and M14 may be omitted from the power protection circuit PC according to the first embodiment. Transistors M13, M14, M23, and M24 may also be omitted from the power protection circuit PCa according to the second embodiment. Transistors M13, M14, M23, and M24 may also be omitted from the power protection circuit PCb according to the third embodiment. Transistors M13, M14, M23, M24, M43, and M44 may also be omitted from the power protection circuit PCc according to the fourth embodiment. Transistors M13, M14, M23, M24, M43, M44, and M61 to M68 may also be omitted from the power protection circuit PCd according to the fifth embodiment.

[0142] Furthermore, the types of transistors used in the circuit configuration described in the above embodiments can also be other combinations. Any type of transistor, either N-type or P-type, can be used as long as it can operate in the same way as the above embodiments. The fifth embodiment can also be combined with embodiments 2 to 4. That is, multiple transistors configured with a common-source, common-gate connection can be added to the power protection circuits PC, PCa, and PCb respectively. This further improves the deviation of the current IMON flowing through transistor M3. The reference voltage VREF input to operational amplifier 14 can also be different from the reference voltage VREF used in operational amplifier section 13.

[0143] In this specification, "connection" refers to an electrical connection, even if it involves other components in between. An "electrical connection" can also be via an insulator, provided it operates in the same manner as an electrical connection. Word lines (WL), select gate lines (SGD), and SGS can also be referred to as "wiring". A node connecting elements to each other can also be called a "connection node". In this specification, one of the source and drain terminals of a transistor can be referred to as "one end" and the other as "the other end". In this specification, the switch (S) can also be referred to as a "switching element". In this specification, transistor dimensions can also be compared based on gate length, gate width, etc.

[0144] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention described in the claims and its equivalents.

Claims

1. A semiconductor circuit comprising: The first transistor has one end connected to the first node; The second transistor has one end connected to a second node that is different from the first node described above, and a gate connected to the gate of the first transistor and the other end. The third transistor has one end connected to the other end of the first transistor and a gate that is input with a first reference voltage. The fourth transistor has one end connected to the other end of the second transistor and another end connected to the other end of the third transistor. The fifth transistor has one end connected to the first node and a gate connected to the other end of the second transistor; and The operational amplifier section has a first input terminal connected to the first node and a second input terminal connected to the second node, and is configured to input a voltage corresponding to the voltage difference between the voltage of the first input terminal and the voltage of the second input terminal to the gate of the fourth transistor.

2. The semiconductor circuit according to claim 1 further comprises: The first resistor has one end connected to the first node mentioned above; The second resistor has one end connected to the second node and another end connected to the other end of the first resistor; and The first constant current source is connected between the other end of the third transistor and the ground node.

3. The semiconductor circuit according to claim 1, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor mentioned above are all P-type MOSFETs.

4. A power supply circuit, comprising: The semiconductor circuit according to claim 2; A sixth transistor is connected between an input terminal and an output terminal, wherein the input terminal is connected to the other end of the first resistor; and The seventh transistor has one end connected to the second node, the other end connected to the output terminal, and a gate connected to the gate of the sixth transistor.

5. The power supply circuit according to claim 4, further comprising: The control circuit is configured to input a voltage based on the input voltage input to the input terminal to the gate of the sixth transistor and the gate of the seventh transistor. The third resistor is connected between the other end of the fifth transistor and the ground node; and An operational amplifier having a first input terminal connected to the other end of the fifth transistor and a second input terminal to which a second reference voltage is input, is configured to input a voltage corresponding to the voltage difference between the voltage of the first input terminal and the voltage of the second input terminal to the gate of the sixth transistor and the gate of the seventh transistor, respectively.

6. The semiconductor circuit according to claim 1, wherein, The aforementioned operational amplifier section includes switches 1 to 4, transistors 8 to 11, and capacitors 1 and 2. One end of the aforementioned eighth transistor is connected to the aforementioned first node via the aforementioned first switch and to the aforementioned second node via the aforementioned second switch. One end of the aforementioned 9th transistor is connected to the aforementioned 1st node, and its gate is connected to the gate of the aforementioned 8th transistor and the other end thereof. The 10th transistor has one end connected to the other end of the 8th transistor and a gate that is input with the first reference voltage. The 11th transistor has one end connected to the other end of the 9th transistor and another end connected to the other end of the 10th transistor. The first capacitor is connected to the gate of the eleventh transistor and is also connected to one end of the eleventh transistor via the third switch. The second capacitor is connected to the gate of the fourth transistor and is connected to one end of the eleventh transistor via the fourth switch.

7. The semiconductor circuit according to claim 6, wherein, The first switch and the third switch are controlled based on the first clock signal. The second switch and the fourth switch are controlled by a second clock signal that is inversely phase to the first clock signal.

8. The semiconductor circuit according to claim 6, further comprising: The first resistor has one end connected to the first node mentioned above; The second resistor has one end connected to the second node and another end connected to the other end of the first resistor. The first constant current source is connected between the other end of the third transistor and the ground node; and The second constant current source is connected between the other end of the 11th transistor and the ground node.

9. The semiconductor circuit according to claim 6, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are all P-type MOSFETs.

10. The semiconductor circuit according to claim 1, wherein, The aforementioned operational amplifier section includes switches 1 through 4, resistors 3 and 4, transistors 8, 9, and 12, and capacitors 1 and 2. One end of the third resistor is connected to the first node via the first switch, and to the second node via the second switch. One end of the fourth resistor is connected to the first node. One end of the aforementioned eighth transistor is connected to the other end of the aforementioned third resistor. The aforementioned ninth transistor has one end connected to the other end of the aforementioned fourth resistor, and a gate connected to the gate and the other end of the aforementioned eighth transistor. One end of the aforementioned 12th transistor is connected to the other end of the aforementioned 4th resistor. The first capacitor is connected to the gate of the 12th transistor and is connected to the other end of the 9th transistor via the third switch. The second capacitor is connected to the gate of the fourth transistor and is connected to the other end of the ninth transistor via the fourth switch.

11. The semiconductor circuit according to claim 10, wherein, The first switch and the third switch are controlled based on the first clock signal. The second switch and the fourth switch are controlled by a second clock signal that is inversely phase to the first clock signal.

12. The semiconductor circuit according to claim 10, further comprising: The first resistor has one end connected to the first node mentioned above; The second resistor has one end connected to the second node and another end connected to the other end of the first resistor. The first constant current source is connected between the other end of the third transistor and the ground node. A third constant current source is connected between the other end of the eighth transistor and the ground node; and The fourth constant current source is connected between the other end of the ninth transistor and the ground node.

13. The semiconductor circuit according to claim 10, wherein, The first, second, third, fourth, fifth, eighth, and ninth transistors mentioned above are all P-type MOSFETs. The 12th transistor mentioned above is an N-type MOSFET.

14. The semiconductor circuit according to claim 6, wherein, The aforementioned operational amplifier section also includes switches 5 through 8, transistors 13 through 16, and capacitor 3. One end of the aforementioned 13th transistor is connected to the aforementioned 1st node via the aforementioned 5th switch and to the aforementioned 2nd node via the aforementioned 6th switch. The aforementioned 14th transistor has one end connected to the aforementioned 1st node, and a gate connected to the gate of the aforementioned 13th transistor and the other end. The aforementioned 15th transistor has one end connected to the other end of the aforementioned 13th transistor, and a gate into which the aforementioned first reference voltage is input. The aforementioned 16th transistor has one end connected to the other end of the aforementioned 14th transistor and connected to the gate of the aforementioned 4th transistor via the aforementioned 7th switch, and another end connected to the other end of the aforementioned 15th transistor. The third capacitor is connected to the gate of the 16th transistor and is connected to one end of the 16th transistor via the eighth switch.

15. The semiconductor circuit according to claim 14, wherein, The first switch, the third switch, the sixth switch, and the seventh switch are controlled based on the first clock signal. The second switch, the fourth switch, the fifth switch, and the eighth switch are controlled based on the second clock signal that is inversely phase to the first clock signal.

16. The semiconductor circuit according to claim 14, further comprising: The first resistor has one end connected to the first node mentioned above; The second resistor has one end connected to the second node and another end connected to the other end of the first resistor. The first constant current source is connected between the other end of the third transistor and the ground node. A second constant current source is connected between the other end of the 11th transistor and the ground node; and The third constant current source is connected between the other end of the 16th transistor and the ground node.

17. The semiconductor circuit according to claim 14, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are all P-type MOSFETs.

18. The semiconductor circuit according to claim 16, wherein, The aforementioned operational amplifier section includes a common-source, common-gate connection.

19. The semiconductor circuit according to claim 18, wherein, The aforementioned operational amplifier section also includes transistors 17 through 22. The aforementioned 17th transistor is connected between the aforementioned 1st switch and the aforementioned 2nd switch, respectively, and the aforementioned 8th transistor. The aforementioned 18th transistor is connected between the aforementioned first node and the aforementioned 9th transistor, and the gate of the aforementioned 18th transistor is connected to the gate of the aforementioned 17th transistor and the other end of the aforementioned 8th transistor. The aforementioned 19th transistor has one end connected to the other end of the aforementioned first resistor, and a gate connected to the connection node of the aforementioned 9th transistor and the aforementioned 18th transistor. The aforementioned 20th transistor is connected between the aforementioned 5th switch and the aforementioned 6th switch and the aforementioned 13th transistor. The aforementioned 21st transistor is connected between the aforementioned 1st node and the aforementioned 14th transistor, and the gate of the aforementioned 21st transistor is connected to the gate of the aforementioned 20th transistor and the other end of the aforementioned 13th transistor. The 22nd transistor has one end connected to the other end of the first resistor and a gate connected to the connection node of the 14th transistor and the 21st transistor. The gate of the 8th transistor and the gate of the 9th transistor are respectively not connected to the other end of the 8th transistor, but are connected to the other end of the 19th transistor. The gate of the 13th transistor and the gate of the 14th transistor are not connected to the other end of the 13th transistor, but are connected to the other end of the 22nd transistor.

20. The semiconductor circuit according to claim 19, wherein, The first, second, third, fourth, fifth, eighth, ninth, tenth, eleventh, thirteenth, fourth, fifth, fifteenth, and sixteenth transistors mentioned above are all P-type MOSFETs. The 17th, 18th, 19th, 20th, 21st and 22nd transistors mentioned above are all N-type MOSFETs.

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