De-modularization and de-wiring harness power module preparation method

Abstract

The invention provides a de-modularization and de-wiring harness power module preparation method, and belongs to the technical field of power module preparation, and the method comprises the steps: forming a chip embedding cavity in a PCB substrate, constructing a thick copper heat conduction layer, and arranging a gradient thermal matching transition layer between a power chip and the chip embedding cavity, performing thermal via hole array optimization on the thick copper heat-conducting layer and forming a thermal via hole array, constructing a three-dimensional staggered busbar structure above the power chip, establishing a process parameter constraint model containing curing temperature, curing pressure and curing time, and solving a parameter combination by adopting an arc consistency propagation algorithm; and carrying out segmented curing treatment on the gradient thermal matching transition layer and then carrying out a lamination curing process to complete integral preparation. The technical problem that the interface thermal resistance in the power chip embedded PCB structure is difficult to stably control is solved.

Description

Technical Field

[0001] This invention belongs to the field of power module fabrication technology, and more specifically, relates to a method for fabricating a power module that is modularized and wire harness-free. Background Technology

[0002] In the field of power electronics, embedded PCB power modules are widely used in new energy vehicles, power converters, and industrial drive systems to achieve high power density and system integration. Existing technologies typically embed power chips within the PCB substrate, relying on copper foil diffusion and thermally conductive vias for heat dissipation, while using epoxy-based thermally conductive interface materials for thermal bonding between the chip and the substrate. However, in these applications, the silicon power chip and the PCB substrate have significantly different coefficients of thermal expansion, leading to substantial thermal stress at the interface during temperature cycling. Existing technologies often employ a single thermally conductive filler material or a one-time integral curing method, making it difficult to simultaneously ensure interface bonding strength, stress relief capability, and thermal conductivity continuity. Furthermore, due to insufficient thermal matching capabilities of the interface materials and a lack of targeted control over the curing process, the interface thermal resistance fluctuates significantly with service time and temperature cycling, indicating a technical problem of insufficient interface thermal resistance stability in existing technologies. Summary of the Invention

[0003] In view of this, the present invention provides a method for manufacturing a power module that is modular and wire harness-free, which can solve the technical problem in the prior art that the interface thermal resistance is difficult to control stably due to the mismatch of thermal expansion coefficients in the embedded PCB structure of power chips.

[0004] This invention is implemented as follows: A method for fabricating a modular and wire-harness-free power module includes: fabricating a PCB substrate and forming a chip embedding cavity; fabricating a thick copper thermally conductive layer at the bottom of the chip embedding cavity; coating a gradient thermal matching transition layer between the bottom surface of the power chip and the bottom of the chip embedding cavity, the gradient thermal matching transition layer consisting of a polyimide composite material layer and a nano-silver paste filling layer from bottom to top; collecting the planar dimensions of the thick copper thermally conductive layer and the heat dissipation data of the power chip, dividing the planar dimensions into candidate position grids, and using a biomimetic ant colony algorithm to optimize the output thermal via array distribution coordinates, forming a thermal via array in the thick copper thermally conductive layer; fabricating a three-dimensional staggered busbar structure between PCB layers above the power chip; establishing a process parameter constraint model and using an arc consistency propagation algorithm to solve for the parameter combination; performing segmented curing treatment on the gradient thermal matching transition layer; placing the power chip in the chip embedding cavity and measuring the interface thermal resistance value; when the interface thermal resistance value exceeds the interface thermal resistance threshold, recalculating to obtain the adjustment parameter combination; and performing a lamination curing process.

[0005] The thick copper thermal conductive layer is prepared at the bottom of the chip embedding cavity by an electroplating process.

[0006] The gradient thermal matching transition layer is used to alleviate the mismatch in thermal expansion coefficients between the silicon chip and the PCB substrate.

[0007] The polyimide composite layer is made of a composite material of polyimide and epoxy resin.

[0008] The nano-silver paste filling layer is composed of nano-silver particles and an organic carrier, and has the characteristics of high thermal conductivity and low elastic modulus.

[0009] Among them, the biomimetic ant colony algorithm uses virtual ants to move and release pheromones according to the temperature gradient, and selects grid points with pheromone concentrations exceeding a set threshold as locations for thermal via placement.

[0010] The thermal via array is distributed according to a tree-like network topology, with the main thermal vias located in the central region of the heat source.

[0011] In the three-dimensional staggered busbar structure, the positive busbar layer and the negative busbar layer are located on different PCB layers and are staggered in the vertical projection direction, and are connected by interlayer vias.

[0012] The process parameter constraint model includes curing temperature variables, curing pressure variables, and curing time variables.

[0013] Among them, the arc consistency propagation algorithm uses the AC-3 iterative deletion algorithm to check variable pairs and delete values ​​that do not meet the constraints.

[0014] The segmented curing process involves first pre-curing the polyimide composite layer, followed by heating to fully cure the nano-silver paste filling layer. The candidate location grid is a set of locations obtained by dividing the planar region of the thick copper thermally conductive layer into a regular grid. The heat dissipation data is a set of data describing the heat dissipation power density at various locations on the power chip surface. The positive and negative busbar layers generate magnetic fields in opposite directions when current flows in opposite directions, resulting in magnetic field cancellation in space. Interfacial thermal resistance is the thermal resistance generated when heat passes through the interface between two materials, caused by incomplete interface contact. The temperature profile of the lamination curing process includes a heating stage, a holding stage, and a cooling stage.

[0015] This invention constructs a multi-layered, collaborative interface heat transfer structure by employing a chip-embedded structure, a gradient thermal matching transition layer, a segmented curing process, and a parameter constraint solution method, thereby achieving stable control of interface thermal resistance in embedded power modules. By introducing a multi-layered composite structure with different coefficients of thermal expansion and thermal conductivity between the power chip and the PCB substrate, and utilizing segmented curing to establish a continuous and stress-released interface bonding state, the concentrated accumulation of interface mismatch stress during temperature cycling is effectively avoided. In summary, this invention solves the technical problem mentioned in the background art of the difficulty in stably controlling interface thermal resistance in embedded PCB structures for power chips. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention.

[0017] Figure 2 The result diagram shows the optimized distribution of the thermal via array.

[0018] Figure 3 This is a diagram showing the magnetic field distribution of a three-dimensional staggered busbar structure.

[0019] Figure 4 Diagram of the pruning process for searching the space for process parameters. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below.

[0021] like Figure 1 The diagram shows a flowchart of a method for fabricating a modular and wire-harness-free power module according to the present invention. This method includes the following steps:

[0022] S01. Prepare a PCB substrate and form a chip embedding cavity on the PCB substrate by mechanical milling. The depth of the chip embedding cavity is matched with the thickness of the power chip. Prepare a thick copper thermal conductive layer at the bottom of the chip embedding cavity by electroplating. The thickness of the thick copper thermal conductive layer is 105μm to 210μm.

[0023] S02. A gradient thermal matching transition layer is coated between the bottom surface of the power chip and the bottom of the chip embedding cavity. The gradient thermal matching transition layer consists of a polyimide composite material layer and a nano-silver paste filling layer from bottom to top. The thickness of the polyimide composite material layer is 20μm to 40μm, the thickness of the nano-silver paste filling layer is 10μm to 25μm, and the thermal conductivity of the nano-silver paste filling layer is greater than 80W / m·K.

[0024] S03. Collect the planar dimensions of the thick copper thermal conductive layer and the heat dissipation data of the power chip, divide the planar dimensions into candidate position grids, use the biomimetic ant colony algorithm to optimize the position calculation of the thermal vias in the candidate position grids, output the distribution coordinates of the thermal via array, and drill holes in the thick copper thermal conductive layer and electroplate according to the distribution coordinates of the thermal via array to form a thermal via array.

[0025] S04. A three-dimensional staggered busbar structure is prepared between PCB layers above the power chip by copper foil etching process. The three-dimensional staggered busbar structure includes a positive busbar layer and a negative busbar layer. The positive busbar layer and the negative busbar layer are located on different PCB layers and are staggered in the vertical projection direction. The positive busbar layer and the negative busbar layer are connected by interlayer vias.

[0026] S05. Establish a process parameter constraint model, which includes curing temperature variable, curing pressure variable, and curing time variable. Use the arc consistency propagation algorithm to solve the process parameter constraint model to obtain the initial parameter combination, which includes the initial curing temperature, initial curing pressure, and initial curing time.

[0027] S06. The gradient thermal matching transition layer is subjected to segmented curing treatment using the initial parameter combination. First, the polyimide composite material layer is pre-cured at a temperature of 120°C to 140°C for 30 to 50 minutes, and then the temperature is raised to 180°C to 200°C to completely cure the nano silver paste filling layer for 40 to 70 minutes.

[0028] S07. Place the power chip that has completed the segmented curing process into the chip embedding cavity, measure the interface thermal resistance value, and when the interface thermal resistance value exceeds the interface thermal resistance threshold, recalculate the adjustment parameter combination using the arc consistency propagation algorithm. The adjustment parameter combination includes adjusting the curing temperature and adjusting the curing pressure.

[0029] S08. Perform the lamination and curing process using the initial parameter combination or the adjusted parameter combination. The temperature curve of the lamination and curing process includes a heating stage, a holding stage, and a cooling stage. The heating stage heats up to the holding temperature at a rate of 5℃ / min to 10℃ / min. The holding stage maintains the holding temperature for 60 minutes to 90 minutes. The cooling stage cools down to room temperature at a rate of 3℃ / min to 8℃ / min, thus completing the fabrication of the modularized and wire-harness-free power module.

[0030] The gradient thermal matching transition layer is a multi-layered composite interface structure used to alleviate the thermal expansion coefficient mismatch between the silicon chip and the PCB substrate. The thermal expansion coefficient of the silicon chip is 2.6 ppm / °C, while that of the PCB substrate is 14 ppm / °C to 17 ppm / °C, representing a mismatch of more than five times. The gradient thermal matching transition layer achieves a gradual transition by setting material layers with different thermal expansion coefficients. The polyimide composite material layer, made of polyimide and epoxy resin, has a thermal expansion coefficient of 6 ppm / °C to 9 ppm / °C, forming an intermediate transition in thermal expansion coefficient between the silicon chip and the PCB substrate. The nano-silver paste filling layer, composed of nano-silver particles and an organic carrier, possesses high thermal conductivity and low elastic modulus. During temperature cycling, it releases interfacial shear stress through its own deformation, preventing interfacial delamination and increased thermal resistance caused by the thermal expansion coefficient mismatch.

[0031] The segmented curing process refers to a process in which different material layers in the gradient thermal matching transition layer undergo a phased curing reaction. The polyimide composite material layer is first pre-cured at a lower temperature to establish initial interfacial bonding strength, while still retaining some fluidity. Then, the temperature is increased to fully cure the nano-silver paste filling layer. During curing, the nano-silver paste filling layer fills the micropores on the surface of the polyimide composite material layer, forming continuous thermally conductive channels. The segmented curing process avoids excessive temperature gradients and internal stress concentration caused by simultaneously heating all material layers, improving interfacial bonding quality and reducing interfacial thermal resistance.

[0032] The biomimetic ant colony algorithm is an optimization algorithm that simulates the foraging behavior of ants in nature, used to solve the problem of heat flow network topology optimization. In the heat dissipation design of power modules, it is necessary to determine the optimal location distribution of the thermal via array to form an efficient heat conduction network. The biomimetic ant colony algorithm achieves optimization through the following process: First, a candidate location grid is established based on the planar dimensions of the thick copper thermal conductive layer. Each grid point in the candidate location grid represents a possible thermal via placement location. Then, the heat source location and heat flux density distribution are determined based on the heat generation power distribution data of the power chip. Multiple virtual ants are created, each representing a heat transfer unit, starting from the heat source location. The virtual ants select their movement direction based on the temperature gradient at their current location, prioritizing movement towards directions with larger temperature gradients. When a virtual ant passes through a grid point of the candidate location grid during its movement, it releases pheromones at that grid point. The pheromone concentration is proportional to the local thermal conductivity of the grid point. The local thermal conductivity is determined by the distance from the grid point to the heat source and the temperature distribution around the grid point. Grid points closer to the heat source and with larger temperature gradients receive higher pheromone concentrations. After multiple iterations of exploration by multiple virtual ants, the pheromone concentration accumulated at each grid point in the candidate location grid forms a distribution map. After each iteration, the pheromone concentration distribution map is updated, reducing the pheromone concentration at grid points with low heat dissipation path efficiency and increasing it at grid points with high heat dissipation path efficiency. Simultaneously, a dynamic evaporation coefficient is applied to the pheromone concentration of all grid points. This dynamic evaporation coefficient causes the pheromone concentration to decay exponentially over time, with the decay rate proportional to the current pheromone concentration. Introducing this dynamic evaporation coefficient prevents suboptimal paths obtained in early exploration from being limited by excessive pheromone accumulation, thus maintaining the algorithm's global search capability. The iteration process continues until the pheromone concentration distribution converges. Grid points with pheromone concentrations exceeding a set threshold are selected from the pheromone concentration distribution map as locations for thermal via placement, and the thermal via array distribution coordinates are output. The thermal via array distribution coordinates are organized according to a tree-like network topology, with the main thermal vias located in the central region of the heat source, branch thermal vias radiating outwards to the surrounding areas, and terminal thermal vias extending to the edge regions, forming a hierarchical heat dissipation network covering the entire heat source.

[0033] The biomimetic ant colony algorithm is suitable for power module heat dissipation optimization because it can adapt to the non-uniform characteristics of the heat dissipation power distribution data. The heat dissipation power distribution on the surface of power chips is usually non-uniform, with high heat dissipation power in densely packed transistor areas and low heat dissipation power in interconnect areas. Traditional uniform via placement methods waste resources by placing too many thermal vias in low-heat-power areas and insufficient thermal vias in high-heat-power areas, resulting in inadequate heat dissipation. In the biomimetic ant colony algorithm, virtual ants start from high-heat-power areas and move along the temperature gradient, automatically accumulating higher pheromone concentrations in high-heat-power areas and lower pheromone concentrations in low-heat-power areas. The resulting thermal via array distribution coordinates match the heat dissipation power distribution. The dynamic evaporation coefficient ensures that the algorithm maintains its ability to explore new paths during iteration, avoiding convergence to local optima due to pheromone locking of early suboptimal solutions. The biomimetic ant colony algorithm solves the technical problems of traditional heat dissipation design relying on human experience and low optimization efficiency. The resulting technical effect is the formation of an adaptive tree-like heat conduction network based on heat dissipation power distribution, reducing overall thermal resistance and improving temperature distribution uniformity.

[0034] The three-dimensional staggered busbar structure is a conductor layout method used to reduce loop inductance and suppress electromagnetic interference. In PCB-embedded power modules, the voltage and current change rates generated by the high-speed switching of power devices induce parasitic oscillations and generate electromagnetic radiation in the busbar circuit. In traditional planar busbar structures, the positive and negative busbars are arranged parallel to each other in the same plane, resulting in a large loop area and high loop inductance. The three-dimensional staggered busbar structure places the positive and negative busbar layers on different PCB layers, achieving vertical connection through interlayer vias, thus creating a spatially staggered distribution. When current flows in opposite directions in the positive and negative busbar layers, the magnetic field generated by the positive busbar layer is opposite to that generated by the negative busbar layer, resulting in magnetic field cancellation in space. By optimizing the staggered angle and interlayer distance between the positive and negative busbar layers, the magnetic field cancellation effect is maximized, thereby reducing the equivalent loop inductance. The technical effect of the three-dimensional staggered busbar structure is to reduce the circuit inductance and suppress voltage spikes and oscillations during the switching process, thereby reducing the intensity of electromagnetic radiation.

[0035] The arc consistency propagation algorithm is a pruning algorithm for solving constraint satisfaction problems, used to quickly screen feasible combinations of process parameters under multiple constraints. In the power module fabrication process, there are coupled constraints among the curing temperature, curing pressure, and curing time variables, determined by material physical properties and process window limitations. Excessive curing temperature leads to material decomposition, while insufficient curing temperature results in incomplete curing. Excessive curing pressure causes chip cracking, while insufficient pressure leads to poor interface bonding. Excessive curing time reduces production efficiency, while insufficient curing time leads to inadequate reaction. These coupled constraints cause the feasible domain of the parameters to exhibit a non-convex polyhedral shape, resulting in a computationally intensive traversal search method. The arc consistency propagation algorithm achieves parameter screening through the following process: First, the curing temperature, curing pressure, and curing time variables are used as variables to be solved, and material physical laws and process window limitations are used as constraints to construct the process parameter constraint model. Each variable to be solved has a discrete value domain containing all possible values. The constraints define the legal relationships between the variables to be solved. Then, the AC-3 iterative deletion algorithm is used for processing. This algorithm checks each pair of variables with constraints. For a first value of the first variable, if there is no second value in the discrete domain of the second variable that satisfies the constraint, the first value is deleted from the discrete domain of the first variable. A queue is used to manage all pairs of variables to be checked. After deleting a value of a variable, all other pairs of variables related to that variable are added back to the queue for checking to ensure all constraints are verified. The iterative deletion process continues until an arc-consistent state is reached, where each value of all variables has at least one set of values ​​from other variables that satisfies all constraints, and no more values ​​are deleted. After processing by the AC-3 iterative deletion algorithm, the discrete domain of the variables is reduced, and the search space is decreased. Finally, backtracking search is used in the reduced search space to find parameter combinations that satisfy all constraints, and the initial parameter combination or the adjusted parameter combination is output.

[0036] The arc consistency propagation algorithm is suitable for power module process parameter optimization because it can efficiently handle multi-constraint coupled scenarios. Power module fabrication involves constraints from multiple physical fields such as materials science, thermodynamics, and mechanics, with numerous parameters and intertwined constraint relationships. Blindly searching leads to a significant waste of computational resources on parameter combinations that do not meet the constraints. The arc consistency propagation algorithm eliminates parameter values ​​that do not meet the constraints in advance through a constraint propagation mechanism, thus pruning the search space. This constraint propagation mechanism utilizes the transitivity of constraints; when a value of a variable to be solved is deleted, the discrete value range of other variables related to that variable is correspondingly reduced, forming a cascaded pruning. The arc consistency propagation algorithm solves the technical problems of large computational load and long time consumption in parameter optimization under multi-constraint conditions. The resulting technical effect is to shorten the feasible solution search time, enabling process parameter adjustments to be completed within the actual production cycle, supporting agile manufacturing and rapid iteration.

[0037] The thick copper thermal conductive layer refers to a conductive and thermally conductive layer with a copper foil thickness exceeding the standard thickness, which serves a heat dissipation function in PCB-embedded power modules. The standard PCB copper foil thickness is 35μm, and the thermal conductivity of this standard thickness is insufficient to meet the heat dissipation requirements of the power chip. The heat flux density generated by the power chip during operation reaches 200... Heat needs to dissipate outwards through the PCB layer structure. The thick copper thermal conductive layer uses copper foil with a thickness of 105μm to 210μm. Copper has a thermal conductivity of 400W / m·K. The increased thickness increases the lateral thermal conductivity cross-sectional area, improving heat dissipation capability. The thick copper thermal conductive layer, together with the thermal via array, forms a three-dimensional heat dissipation channel. Heat is conducted from the power chip to the thick copper thermal conductive layer and then diffuses laterally, before being conducted to the outer layers of the PCB through the thermal via array.

[0038] The thermal via array is a heat dissipation structure formed by multiple thermally conductive vias distributed according to the array's coordinates. Thermally conductive vias are metallized through-holes penetrating multiple layers of the PCB, filled with a high thermal conductivity material, such as copper or thermally conductive adhesive. The function of the thermally conductive vias is to establish heat conduction channels in the vertical direction of the PCB, transferring heat from the inner layers to the outer layers for heat dissipation. The distribution density and position of the thermal via array affect heat dissipation efficiency; increasing the density of thermally conductive vias in high-heat-generating areas improves heat dissipation capacity. The thermal via array optimized using the biomimetic ant colony algorithm exhibits a tree-like distribution, with the main thermal vias located at the center of the heat source, and branch thermal vias radiating outwards, forming a hierarchical heat dissipation network.

[0039] The loop inductance refers to the parasitic inductance in the current loop, which causes voltage spikes and oscillations during power switching. At the moment of power device turn-off, the current drops rapidly, generating a rate of change of current. According to the law of electromagnetic induction, an induced voltage is generated in the loop inductance, which is superimposed on the switching voltage to form an overvoltage spike. The magnitude of the loop inductance is directly proportional to the loop area; reducing the loop area reduces the loop inductance. The three-dimensional staggered busbar structure reduces the loop inductance by shortening the distance between the positive and negative busbar layers and by utilizing magnetic field cancellation.

[0040] The interfacial thermal resistance refers to the thermal resistance generated when heat passes through the interface between two materials, caused by incomplete interface contact and differences in the thermal properties of the materials. Ideally, the interface should be perfectly fitted and continuous; however, in reality, microscopic roughness and air gaps at the interface result in a contact area smaller than the nominal area. Heat must bypass the air gap region when passing through the interface, extending the heat transfer path and increasing thermal resistance. Filling with a high thermal conductivity material reduces the interfacial thermal resistance; this material fills the air gap and provides a continuous heat conduction path. The interfacial thermal resistance threshold is determined based on the heat dissipation requirements of the power chip. When the interfacial thermal resistance value exceeds the threshold, it indicates that the interface bonding quality is substandard, requiring adjustment of process parameters to improve the interface quality.

[0041] The lamination and curing process is a process of bonding multiple layers of materials into a single unit under temperature and pressure. In the fabrication of PCB embedded power modules, the power chip, the gradient thermal matching transition layer, and the PCB substrate, among other multi-layer structures, need to be integrated using this lamination and curing process. The lamination equipment provides a controllable temperature and pressure field, executing the heating and pressurization process according to the temperature and pressure curves. The temperature curve includes a heating stage, a holding stage, and a cooling stage. The heating rate during the heating stage affects the temperature uniformity within the material; excessively rapid heating leads to a large temperature difference between the surface and the interior, generating thermal stress. The holding stage maintains the temperature required for the curing reaction and sustains it for a sufficient time to ensure complete reaction. The cooling stage controls the cooling rate to avoid thermal shock caused by rapid cooling. The pressure curve coordinates with the temperature curve, applying pressure when the material is in a flow state to promote filling, and maintaining pressure after basic curing to prevent springback deformation.

[0042] The candidate location grid is a set of locations obtained by dividing the planar region of the thick copper thermal conductive layer into a regular grid. It is used for the discretization representation of the thermal via locations in the biomimetic ant colony algorithm. The grid size of the candidate location grid is determined based on the minimum spacing of the thermal vias, ensuring that the distance between adjacent grid points meets manufacturing process requirements. The total number of grid points in the candidate location grid affects the computational complexity and optimization accuracy of the algorithm; too few grid points result in insufficient optimization accuracy, while too many grid points prolong the computation time.

[0043] The heat dissipation power distribution data is a dataset describing the heat dissipation power density at various locations on the surface of the power chip, obtained through thermal simulation analysis or actual measurement. This data provides heat source information for the biomimetic ant colony algorithm, guiding the movement direction and pheromone release concentration of the virtual ants. The accuracy of the heat dissipation power distribution data affects the optimization effect of the thermal via array distribution coordinates; accurate data ensures that the thermal via array distribution coordinates match actual heat dissipation requirements.

[0044] The AC-3 iterative deletion algorithm is the core execution process of the arc consistency propagation algorithm. It reduces the search space by iteratively checking constraints and deleting inconsistent values. The AC-3 iterative deletion algorithm maintains a queue of variable pairs to be checked. Initially, all variable pairs with constraints are added to the queue. Each time, a variable pair is taken from the queue for checking. If a value is found to be inconsistent with the constraint, it is deleted, and the relevant variable pair is added back to the queue. The AC-3 iterative deletion algorithm ensures that all constraints are repeatedly checked until the arc consistency state is reached.

[0045] The insulation temperature refers to the temperature maintained during the insulation stage of the lamination curing process, determined based on the activation energy and reaction rate of the curing reaction. The insulation temperature needs to be higher than the glass transition temperature of the material to maintain sufficient reactivity, while remaining lower than the decomposition temperature to avoid material performance degradation. The selection of the insulation temperature affects the degree of curing and interfacial bonding strength; too low an insulation temperature leads to incomplete curing, while too high an insulation temperature results in excessive cross-linking and brittleness.

[0046] The specific implementation methods of the above steps are described in detail below.

[0047] The specific implementation of step S01 involves first using a CNC milling machine to precisely machine the PCB substrate. The milling depth is set according to the dimensions and thickness parameters of the power chip, and the matching error between the milling depth and the power chip thickness is controlled within ±5μm. This ensures that the power chip is flush with the PCB substrate surface after embedding, avoiding uneven subsequent lamination due to height differences. Then, copper plating is performed on the bottom of the machined chip embedding cavity using a copper sulfate plating solution, with the current density controlled at 2... Up to 4 The electroplating time is adjusted according to the target thickness to form a thick copper thermally conductive layer with a thickness of 105μm to 210μm. The function of this thick copper thermally conductive layer is to provide lateral heat conduction channels, utilizing the high thermal conductivity of copper to achieve rapid lateral heat diffusion, and providing a receiving surface for the subsequent longitudinal heat conduction of the thermal via array. The electroplating process employs pulse electroplating technology, which improves the density of the plating layer by periodically switching the current, reducing the micro-porosity inside the plating layer, and enhancing thermal conductivity.

[0048] The specific implementation of step S02 involves first coating a polyimide composite material layer onto the bottom surface of the power chip using a screen printing process. This screen printing process precisely controls the coating thickness by adjusting the mesh size and squeegee pressure, achieving a thickness of 20 μm to 40 μm. Then, a nano-silver paste filling layer is coated onto the surface of the polyimide composite material layer. This nano-silver paste filling layer is applied using drop-coating or spin-coating methods, with a thickness controlled to be 10 μm to 25 μm. The design principle of the gradient thermal matching transition layer is to alleviate interfacial stress by utilizing the gradual transition of the material's thermal expansion coefficient. The thermal expansion coefficient of the polyimide composite material layer is between that of the silicon chip and the PCB substrate, forming a buffer zone for thermal stress. The high thermal conductivity of the nano-silver paste filling layer ensures minimal interfacial thermal resistance, while its low elastic modulus allows it to absorb shear stress through its own elastic deformation during temperature cycling, protecting the interfacial integrity between the silicon chip and the polyimide composite material layer. The coating process is performed in a clean environment to avoid interfacial defects caused by particulate contamination.

[0049] The specific implementation of step S03 involves first measuring the length and width of the thick copper thermal conductive layer, and then dividing the candidate location grid according to the minimum process spacing of the thermal vias. This minimum process spacing is typically 0.5mm to 1.0mm to ensure no electrical short circuits occur between adjacent thermal vias. Next, steady-state thermal analysis of the power chip is performed using finite element thermal simulation software to extract the heat generation power density data at each location, generating a heat generation power distribution data file. Then, a biomimetic ant colony algorithm is used to optimize the thermal via locations. The input parameters of the biomimetic ant colony algorithm include the coordinates of the candidate location grid, the heat generation power distribution data, and the total number of thermal vias. The output parameter is the coordinates of the thermal via array distribution. The core principle of the biomimetic ant colony algorithm is to achieve global optimization through the random exploration of virtual ants and a pheromone positive feedback mechanism. The virtual ants choose their movement direction based on the local temperature gradient and pheromone concentration. High-temperature areas attract more virtual ants to pass through and accumulate pheromones, ultimately forming a thermal via layout that matches the heat source distribution. After optimization, drilling positions are marked on the thick copper thermally conductive layer according to the output thermal via array distribution coordinates. Thermal vias are then fabricated using laser drilling or mechanical drilling, with a diameter of 0.2mm to 0.4mm. The via walls are then metallized and filled with thermally conductive adhesive to complete the fabrication of the thermal via array. The number of iterations for the biomimetic ant colony algorithm is set to 50 to 100, and the pheromone evaporation coefficient is set to 0.1 to 0.3 to ensure that the algorithm converges to the global optimum.

[0050] The specific implementation of step S04 involves first planning the layout of a three-dimensional staggered busbar structure in PCB design software. The positive busbar layer is placed on the second copper layer, and the negative busbar layer is placed on the fourth copper layer, with the two layers isolated by an insulating dielectric layer. Then, busbar patterns are fabricated on each copper layer using photolithography and chemical etching processes. The photolithography process employs a positive photoresist coating, exposure, and development process to transfer the busbar pattern to the copper foil surface. Chemical etching removes the copper foil from non-busbar areas. Next, holes are drilled and electroplated at the connection points of the positive and negative busbar layers to form interlayer vias. These interlayer vias enable electrical connections between different busbar layers. The design principle of the three-dimensional staggered busbar structure utilizes the spatial cancellation effect of magnetic fields to reduce loop inductance. When reverse currents flow through the positive and negative busbar layers, they generate magnetic fields in opposite directions in space. By optimizing the interlayer distance and staggered layout, the magnetic fields cancel each other out around the loop, reducing the equivalent loop inductance. The interlayer distance is preferably 0.1mm to 0.3mm. The staggered layout ensures that the overlap between the positive and negative busbar layers in the vertical projection direction reaches more than 80%, maximizing the magnetic field cancellation effect. The three-dimensional staggered busbar structure also reduces the parasitic capacitance of the busbars and improves the switching waveform quality.

[0051] The specific implementation of step S05 involves first establishing a process parameter constraint model. This model includes three variables to be solved, a curing temperature variable, a curing pressure variable, and a curing time variable. The constraints include constraints on the material's glass transition temperature, material decomposition temperature, chip pressure resistance, minimum degree of curing, and production cycle. Then, the arc consistency propagation algorithm is used to solve the process parameter constraint model. This algorithm reduces the search space by iteratively deleting parameter values ​​that do not meet the constraints. Specifically, each variable to be solved is first assigned an initial discrete value range. The initial discrete value range for the curing temperature variable is 100℃ to 250℃ in 5℃ intervals, and the initial discrete value range for the curing pressure variable is 0.5℃. Up to 3.0 And with 0.1 The initial discrete value range of the fixed time variable is 20 to 120 minutes, with 5-minute intervals. A variable pair queue is then established, adding all variable pairs with constraints. Each variable pair is sequentially retrieved for arc consistency checks. If a value of the first variable to be solved cannot satisfy the constraint under all values ​​of the second variable to be solved, that value is deleted. After deletion, the relevant variable pair is re-added to the queue for further checks. This iterative process continues until the queue is empty and no more values ​​can be deleted. Finally, a depth-first backtracking search is used in the reduced search space to find the parameter combination that satisfies all constraints as the initial parameter combination. The advantage of the arc consistency propagation algorithm lies in utilizing the transitivity of constraints to achieve cascading pruning. When a value of a variable is deleted, it triggers a reduction in the value range of other related variables, significantly reducing search complexity.

[0052] The specific implementation of step S06 involves placing the power chip coated with a gradient thermal matching transition layer on a heating stage. First, a pre-curing stage is performed on the polyimide composite material layer. The heating stage temperature is set to 120°C to 140°C and maintained for 30 to 50 minutes. This pre-curing stage causes partial cross-linking of the polyimide composite material layer, forming a preliminary network structure while still retaining some fluidity. Then, the complete curing stage of the nano-silver paste filling layer begins. The heating stage temperature is increased to 180°C to 200°C and maintained for 40 to 70 minutes. This complete curing stage causes the organic carrier in the nano-silver paste to volatilize and the nano-silver particles to sinter, forming a continuous conductive and thermally conductive network. The principle of segmented curing is to avoid thermal stress concentration caused by simultaneous curing of all material layers. The first-cured polyimide composite material layer provides a supporting substrate for the subsequently cured nano-silver paste filling layer. During the flow process, the subsequently cured nano-silver paste filling layer fills the micropores on the surface of the previous layer, improving interfacial contact. Temperature control employs a PID closed-loop regulation algorithm, monitoring the heating stage temperature in real time and adjusting the heating power, keeping temperature fluctuations within ±2°C. The curing process is carried out under a protective atmosphere to avoid material property degradation caused by high-temperature oxidation.

[0053] The specific implementation of step S07 involves first placing the power chip, after segmented curing, into the chip embedding cavity. A transient thermal resistance test is then used to measure the interface thermal resistance. This transient thermal resistance test involves applying a step power to the power chip and measuring the temperature rise response curve, extracting the interface thermal resistance value based on a thermal resistance network model. The measured interface thermal resistance value is then compared with a preset interface thermal resistance threshold. This threshold is calculated based on the maximum junction temperature limit and heat dissipation requirements of the power chip, with a typical value of 0.5. Up to 1.0 When the interfacial thermal resistance value exceeds the interfacial thermal resistance threshold, the interfacial quality is deemed unqualified, requiring adjustment of curing parameters and re-processing. At this point, the arc consistency propagation algorithm is re-invoked, and an interfacial thermal resistance constraint condition is added to the process parameter constraint model. This constraint condition correlates the interfacial thermal resistance with curing temperature and curing pressure. Increasing the curing temperature promotes material flow and improves interfacial contact, while increasing the curing pressure removes interfacial bubbles and reduces thermal resistance. The re-solved model outputs an adjusted parameter combination, in which the adjusted curing temperature and pressure are improved compared to the initial parameter combination. Real-time monitoring of the interfacial thermal resistance and parameter adjustment form a closed-loop control, ensuring that the final product's interfacial quality meets design requirements.

[0054] The specific implementation of step S08 involves placing the multilayer structure of the power chip, gradient thermal matching transition layer, and PCB substrate into a laminator, and setting the lamination process parameters according to the initial parameter combination or adjusted parameter combination. The lamination process is divided into three stages: a heating stage, a holding stage, and a cooling stage. During the heating stage, the heating rate is controlled at 5°C / min to 10°C / min to slowly increase the temperature and avoid excessive temperature differences between the inside and outside of the material, which could generate thermal stress. Once the temperature reaches the holding temperature, the holding stage begins. The holding stage maintains the holding temperature for 60 to 90 minutes, with the holding temperature being 160°C to 220°C. During this stage, the curing reaction of the material is fully carried out, the resin flows and fills all voids, and cross-linking is completed. Simultaneously, a lamination pressure of 1... Up to 2 The lamination pressure is applied via a hydraulic system to ensure tight adhesion of each layer of material and to expel residual gas. After the heat preservation stage, a cooling stage begins, with the cooling rate controlled at 3°C / min to 8°C / min. Slow cooling avoids material cracking or delamination due to thermal shock. Once the temperature reaches room temperature, the pressure is released, completing the fabrication of the modularized and wire-harness-free power module. Temperature and pressure during the lamination process are monitored in real time using multi-point sensors, and the entire process curve is recorded through a data acquisition system, providing a basis for quality traceability.

[0055] It should be noted that the key technical ideas of this invention include a segmented curing technology for gradient thermal matching transition layers, a thermal via array topology optimization technology based on a biomimetic ant colony algorithm, and an adaptive adjustment technology for process parameters based on an arc consistency propagation algorithm. The segmented curing technology for gradient thermal matching transition layers, by setting material layers with different thermal expansion coefficients and adopting a staged curing strategy, achieves the layer-by-layer release of thermal stress between the silicon chip and the PCB substrate. Compared with traditional single interface materials and synchronous curing methods, this segmented curing technology significantly reduces the peak value of interface shear stress during temperature cycling, avoids interface delamination and thermal resistance degradation, and improves the thermal cycle life and reliability of the power module. The thermal via array topology optimization technology based on a biomimetic ant colony algorithm simulates the pheromone feedback mechanism of ants foraging in nature, achieving adaptive layout of thermal via positions. Compared with the traditional uniform mesh via method, the biomimetic ant colony algorithm dynamically adjusts the thermal via density according to the non-uniform characteristics of the heat power distribution, increasing heat dissipation channels in high-heat areas and reducing resource waste in low-heat areas, forming a tree-like heat conduction network that matches the heat source distribution, significantly improving overall heat dissipation efficiency and making the temperature distribution more uniform. The process parameter adaptive adjustment technology based on the arc consistency propagation algorithm achieves rapid reduction of the feasible parameter space under multiple constraints through constraint propagation and cascade pruning mechanisms. Compared with traditional trial-and-error methods and global traversal search methods, the arc consistency propagation algorithm utilizes the coupling constraint relationship between parameters to eliminate infeasible solutions in advance, shortening the parameter optimization time from hours to minutes, and supporting real-time parameter adjustment and process closed-loop control based on interface thermal resistance feedback. The synergistic effect of the above three key technical ideas forms a complete technology chain from interface stress control and heat dissipation path optimization to process parameter regulation. The gradient thermal matching transition layer ensures reliable bonding between the chip and the substrate, the thermal via array topology optimization provides an efficient heat dissipation channel, and the adaptive adjustment of process parameters ensures the quality stability of the fabrication process. The three work together to achieve high reliability and high heat dissipation performance of the modular and wire harness-free power module, significantly reducing parasitic inductance and thermal resistance compared with traditional discrete power modules, and improving power density and system integration.

[0056] It should be noted that this invention also solves the technical problem that heat dissipation structures in embedded PCBs for power chips are difficult to adapt to non-uniform heat generation power distribution. Traditional thermal vias are usually arranged in a regular array, without considering the differences in power density on the chip surface, resulting in insufficient heat dissipation or low material utilization in local areas. This invention introduces a biomimetic ant colony algorithm based on heat generation power distribution to achieve adaptive optimization of the thermal via array position, thus matching the heat conduction channels with the heat source distribution.

[0057] It should be noted that this invention also solves the technical problem of difficulty in reducing busbar loop inductance in embedded power modules. Planar busbar structures tend to form large loop areas under high-frequency switching conditions, leading to parasitic oscillations. This invention constructs a three-dimensional staggered busbar structure within different PCB layers, creating a spatial magnetic field cancellation relationship between the positive and negative busbar layers, thus suppressing the accumulation of loop inductance at the structural level.

[0058] Specifically, the principle of this invention is as follows: The fundamental reason why this invention can solve the above-mentioned technical problems lies in its reconstruction of the interfacial heat conduction and stress transfer paths through the synergistic effect of material gradient design and process parameter constraints. The gradient thermal matching transition layer forms a step-by-step transition in the coefficient of thermal expansion, allowing thermal stress to be dispersed and released in the multi-layer interface, avoiding a single interface bearing all the mismatch deformation. The segmented curing process allows different material layers to complete the curing process separately under suitable reaction conditions, ensuring both initial interfacial bonding and the formation of continuous heat conduction channels in subsequent curing, reducing thermal resistance fluctuations caused by interfacial micro-defects. By combining the arc consistency propagation algorithm to screen process parameters, the curing process is always kept within the stable range allowed by material and structural constraints, thereby logically achieving controllable and stable interfacial thermal resistance.

[0059] The following provides a specific embodiment 1 of the present invention, and the specific implementation of each step in this embodiment 1 is described in detail below.

[0060] The specific implementation methods of steps S01, S02, S04 and S06 are the same as those described above, and will not be repeated in detail here.

[0061] The specific implementation of step S03 is as follows: First, the planar dimensional parameters of the thick copper heat-conducting layer and the heat dissipation data of the power chip are collected, and the planar region of the thick copper heat-conducting layer is divided into... The specification of the candidate location grid, where This refers to the number of horizontal grid lines. The vertical grid number is represented as: (Grid point coordinates are shown below) , , When using a biomimetic ant colony algorithm to optimize the location of thermal vias in candidate mesh locations, virtual ants... At grid points The concentration of pheromones released at the site The calculation formula is expressed as follows:

[0062] ;

[0063] In the formula, For virtual ants At grid points The concentration of pheromones released at the site is dimensionless. For grid points Local heating power at the location, in units of ; For reference heating power, the value is taken as 100. ; For grid points Distance to the heat source center, in units of ; For reference distance, the value is 1. ; For grid points Temperature gradient at point, in units of ; The maximum temperature gradient in the entire plane, in units of . ; and These are weighting coefficients, with empirical values ​​of 0.6 and 0.4 respectively. Virtual ants From grid points Move to adjacent grid point transition probability The calculation formula is expressed as follows:

[0064] ;

[0065] In the formula, For virtual ants From grid points Move to adjacent grid point The transition probability is dimensionless. For the first Grid points in the next iteration The pheromone concentration is dimensionless. The reference pheromone concentration is set to 1. For grid points Temperature gradient at point, in units of ; This is the normalized temperature gradient, with a value of 1. ; The pheromone importance factor has an empirical value of 1. The empirical value for the heuristic information importance factor is 2; For grid points The set of adjacent grid points; For the first Grid points in the next iteration The pheromone concentration is dimensionless. For grid points Temperature gradient at point, in units of The pheromone concentration is updated after each iteration, and the update formula is expressed as follows:

[0066] ;

[0067] In the formula, For the first Grid points in the next iteration The pheromone concentration is dimensionless. For the first Grid points in the next iteration The pheromone concentration is dimensionless. The dynamic volatility coefficient; For all virtual ants in this iteration at the grid points The increase in pheromone concentration released at a given location is dimensionless. The calculation formula is expressed as follows:

[0068] ;

[0069] In the formula, This represents the total number of virtual ants; For virtual ants At grid points The concentration of pheromones released at the site, dimensionless. Dynamic volatility coefficient. The calculation formula is expressed as follows:

[0070] ;

[0071] In the formula, This is the initial volatility coefficient, which defaults to 0.1. This is the attenuation adjustment parameter, typically set to 0.05; For the first The average pheromone concentration of all grid points at the next iteration, dimensionless; The initial pheromone concentration is set to 1. After the iteration converges, the pheromone concentration is selected. Greater than the set threshold The grid points are used as the locations for the thermal vias, and the output set of coordinates for the thermal via array distribution is generated. ,in Total number of thermal vias. Pheromone concentration threshold. Based on the required density of thermal vias, the calculation formula is as follows:

[0072] ;

[0073] In the formula, This is the threshold coefficient, with an empirical value of 1.5; This is the average value of the pheromone concentration at all grid points after the iteration converges; it is dimensionless.

[0074] The specific implementation of step S05 is that, when establishing the process parameter constraint model, the curing temperature variable is included. Solidification pressure variables and curing time variables As variables to be solved, each variable has a discrete range, including the solidification temperature variable. The discrete range is Solidified pressure variables The discrete range is Curing time variable The discrete range is .in, The number of elements in the discrete range of curing temperature; The number of elements in the discrete range of curing pressure; This represents the number of elements in the discrete range of curing time. Constraints include material physics constraints and process window limitations. The AC-3 iterative deletion algorithm within the arc consistency propagation algorithm is used for solving this problem. This algorithm maintains a queue of pairs of variables to be checked. Initially, all variable pairs with existing constraints are added to the queue. For variable pairs... ,examine a certain value Is it in There exists at least one value in the discrete range of . Make the constraints If satisfied, then from Delete from discrete range Constraints This is represented as a combined judgment of material curing integrity constraints and mechanical stress constraints, where the curing integrity constraint is expressed as... and Mechanical stress constraint is expressed as .in, For reference temperature, the value is taken as 200℃; The desired degree of curing is dimensionless and is typically taken as 0.95. The value is set to 1 to indicate the degree of curing. The reference pressure is set to 1. ; The required interfacial bonding force, in units of ; For reference bonding force, the value is taken as 100. ; The yield stress of the material is given by units of 1000 kJ / m². The value is usually 50. Mechanical stress The process involves obtaining the data through finite element simulation analysis, including: Step 1: Establishing a three-dimensional geometric model of the power chip and the PCB substrate, and setting material property parameters including elastic modulus, Poisson's ratio, and coefficient of thermal expansion; Step 2: Applying a temperature field to the model. and pressure field As a load boundary condition; Step 3: Solve for the thermal stress distribution and extract the maximum equivalent stress at the chip-substrate interface as... The numerical value is determined. The iterative deletion process continues until an arc-consistent state is reached. At this point, the discrete value range of all variables to be solved is reduced. In the reduced search space, a backtracking search is used to find parameter combinations that satisfy all constraints. The output initial parameter combinations include the initial curing temperature. Initial curing pressure and initial curing time .

[0075] The specific implementation of step S07 is as follows: after placing the power chip that has completed the segmented curing process into the chip embedding cavity, the interface thermal resistance value is measured by a thermal resistance tester. Interfacial thermal resistance threshold The value is determined based on the heat dissipation requirements of the power chip, and is typically between 0.2 and 0.5. When the measured interfacial thermal resistance value Exceeding the interfacial thermal resistance threshold If this occurs, it indicates that the interface bonding quality is substandard, and the arc consistency propagation algorithm needs to be used again to calculate and adjust the parameter combination. The calculation process for the adjusted parameter combination is similar to step S05, but an interface thermal resistance feedback constraint condition is added to the constraint model, and the output adjusted parameter combination includes adjusting the curing temperature. and adjusting curing pressure .

[0076] The specific implementation of step S08 is as follows: when performing the lamination and curing process using the initial parameter combination or the adjusted parameter combination, the temperature rise rate during the temperature rise phase of the temperature curve is... The heating rate is 5–10℃ / min, increasing the temperature to the holding temperature. Maintain the insulation temperature during the insulation stage. The cooling time is 60–90 minutes, and the cooling rate during the cooling phase is [not specified]. The lamination and curing process is completed by cooling at a rate of 3–8℃ / min to room temperature. Insulation temperature. The selection of temperature should meet the requirements of curing reaction kinetics, and is usually taken as 180-220℃.

[0077] The specific implementation of the gradient thermal matching transition layer is as follows: The gradient thermal matching transition layer achieves a gradual transition by setting material layers with different coefficients of thermal expansion, thus mitigating the thermal expansion mismatch problem between the silicon chip and the PCB substrate. The coefficient of thermal expansion of the silicon chip is 2.6. The coefficient of thermal expansion of the PCB substrate is 14–17. The coefficient of thermal expansion of the polyimide composite layer is 6–9. It forms an intermediate transition in thermal expansion coefficient between the silicon chip and the PCB substrate. The nano-silver paste filling layer has a high thermal conductivity greater than 80. With its low elastic modulus, it releases interfacial shear stress through its own deformation during temperature cycling, avoiding interfacial delamination and increased thermal resistance caused by mismatch in thermal expansion coefficients.

[0078] The specific implementation of the biomimetic ant colony algorithm is as follows: It simulates the foraging behavior of ants in nature to optimize the heat flow network topology. Virtual ants start from the heat source and choose their movement direction based on the temperature gradient at their current location, prioritizing directions with larger temperature gradients. During their movement, they release pheromones when passing through grid points of candidate locations. The pheromone concentration is directly proportional to the local thermal conductivity of the grid point. Local thermal conductivity... The calculation formula is expressed as follows:

[0079] ;

[0080] In the formula, The local thermal conductivity is dimensionless. The thermal conductivity of copper is 400. ; For reference thermal conductivity, a value of 400 is used. ; The cross-sectional area of ​​a single thermal via, in units of ; The reference cross-sectional area is set to 1. ; The reference temperature gradient is set to 10. The dynamic evaporation coefficient causes the pheromone concentration to decay exponentially over time, preventing suboptimal paths obtained in the early exploration from being limited by excessive pheromone accumulation and maintaining the algorithm's search capability on a global scale.

[0081] It should be noted that the arc consistency propagation algorithm preemptively eliminates parameter values ​​that do not meet the constraints through constraint propagation, thus pruning the search space. The AC-3 iterative deletion algorithm checks each pair of variables with constraints. For a certain first value of the first variable to be solved, if there is no second value in the discrete domain of the second variable to be solved that satisfies the constraint, then the first value is deleted from the discrete domain of the first variable to be solved. The iterative deletion process continues until the arc consistency state is reached, shortening the search time for feasible solutions and enabling the adjustment of process parameters to be completed within the actual production cycle. Specifically, it is expressed as follows:

[0082] The formula for the arc consensus propagation algorithm is as follows:

[0083] For the set of variables to be solved Each variable With discrete value range Constraint Set The conditions for determining arc consistency are stated as follows:

[0084] ;

[0085] In the formula, For the first One variable to be solved; For the first One variable to be solved; For variables The discrete range of ; For variables The discrete range of ; For variables The first in the discrete range One possible value; For variables The first in the discrete range One possible value; For variables and variables The binary constraint relationship between them; For variables The number of discrete value range elements; This represents the total number of variables to be solved. To constrain the total number.

[0086] The queue update rules of the AC-3 iterative deletion algorithm are described as follows:

[0087] ;

[0088] In the formula, For the first The queue of variable pairs to be checked in the next iteration; For the first The queue of variable pairs to be checked in the next iteration; For variables A flag indicating whether the discrete value range has been modified; For variables Other variables that have constraints; For variables and variables The constraints between them.

[0089] The operation of reducing the discrete range of a variable is described as follows:

[0090] ;

[0091] In the formula, For the reduced variables The discrete range of ; This is the set difference operator; This is a non-existent quantifier.

[0092] The criteria for arc consistency are stated as follows:

[0093] ;

[0094] In the formula, This is a Boolean variable indicating whether the system has reached an arc-consistent state. For logical AND operator; It is a universal quantifier.

[0095] Search space reduction rate The calculation formula is expressed as follows:

[0096] ;

[0097] In the formula, Search space reduction rate; For variables The number of discrete range elements before reduction; For variables The number of elements in the reduced discrete range.

[0098] It should be noted that the variables involved in this embodiment are explained in detail in Tables 1 and 2.

[0099] Table 1. Variable Explanation Table (Part 1)

[0100]

[0101] Table 2. Variable Explanation Table (Part Two)

[0102]

[0103] To better understand and implement this invention, a specific application scenario of the invention is provided below as Example 2: To verify the effectiveness of the invention, technicians set up a test environment and tested the feasibility of the method by actually manufacturing a power module for an on-board motor driver. This power module uses six IGBT chips as the main power devices. Each IGBT chip is 12 mm × 12 mm in size, has a rated current of 300 amps, an operating voltage of 750 volts, and a maximum heat dissipation power of 180 watts per chip.

[0104] Technicians first fabricated a PCB substrate using FR-4 material, with a total thickness of 3.2 mm and an 8-layer structure. A chip embedding cavity was formed on the third layer of the substrate through mechanical milling, with a cavity depth set at 180 micrometers, consistent with the thickness of the IGBT chips. A thick copper thermal conductive layer was then prepared at the bottom of the chip embedding cavity using an electroplating process. The electroplating solution was copper sulfate, the current density was controlled at 2.5 amperes per square decimeter, and the electroplating time was 8 hours, ultimately resulting in a 150-micrometer-thick copper thermal conductive layer. This thick copper thermal conductive layer has a planar dimension of 20 mm × 20 mm, covering the area where all six IGBT chips are arranged.

[0105] Subsequently, technicians prepared a gradient thermal matching transition layer. First, a polyimide composite material layer was coated onto the bottom surface of the IGBT chip. The composite material was prepared by mixing polyimide and epoxy resin at a mass ratio of 7:3. A uniform thin layer was formed on the bottom surface of the chip using a spin-coating process at a speed of 1500 rpm for 45 seconds, resulting in a polyimide composite material layer with a thickness of 30 micrometers. Then, a nano-silver paste filling layer was coated onto the surface of the polyimide composite material layer. The nano-silver paste was prepared by mixing silver particles with an average particle size of 50 nanometers with an organic carrier, with a silver particle mass fraction of 75%. The nano-silver paste was coated onto the surface of the polyimide composite material layer using a screen printing process at a printing pressure of 0.3 MPa and a printing speed of 20 mm / s, resulting in a nano-silver paste filling layer with a thickness of 18 micrometers. Tests showed that the thermal conductivity of the nano-silver paste filling layer reached 95 watts per meter per Kelvin.

[0106] Next, technicians collected data on the planar dimensions of the thick copper thermal conductive layer and the heat dissipation data of the IGBT chips. Using finite element thermal simulation software, the temperature field of the six IGBT chips under rated operating conditions was simulated to obtain the heat dissipation distribution on the surface of each chip. The simulation results showed that the heat dissipation distribution on the IGBT chip surface was uneven, with a heat dissipation density of 220 watts per square centimeter in the concentrated transistor area, while the heat dissipation density in the edge area was only 85 watts per square centimeter. Technicians divided the 20 mm × 20 mm thick copper thermal conductive layer plane into a candidate location grid with a grid spacing of 0.5 mm, obtaining a total of 1600 candidate grid points.

[0107] Technicians used a biomimetic ant colony algorithm to optimize the placement of thermal vias. The algorithm used 100 virtual ants, 200 iterations, an initial pheromone concentration of 1.0, and a pheromone evaporation coefficient of 0.15. During the algorithm's execution, the virtual ants started from the high-heat-generating power areas of the six IGBT chips, choosing their direction of movement based on the temperature gradient, and releasing pheromones at candidate grid points they passed. After 200 iterations, the pheromone concentration distribution converged, and the technicians selected grid points with pheromone concentrations exceeding 2.8 as the placement locations for the thermal vias, outputting the coordinates of a total of 86 thermal via arrays. Figure 2 As shown, the thermal via array exhibits a tree-like distribution, with the main thermal vias located at the center of the six chips, and the branch thermal vias radiating outwards, covering the entire heat-generating area. Technicians drilled holes with a diameter of 0.3 mm in the thick copper thermal conductive layer according to the thermal via array distribution coordinates, and then filled the holes with copper through an electroplating process, forming a thermal via array that penetrates the multi-layer PCB.

[0108] A three-dimensional staggered busbar structure is fabricated on layers 4 and 5 of the PCB above the power chip. The positive busbar layer, located on layer 4, is fabricated using a copper foil etching process, with a width of 8 mm and a thickness of 105 μm. The negative busbar layer, located on layer 5, also has a width of 8 mm and a thickness of 105 μm. The positive and negative busbar layers are staggered in the vertical projection direction at an angle of 45 degrees, with a distance of 0.4 mm between the two layers. Electrical connections are achieved by placing 12 interlayer vias between the positive and negative busbar layers, with a via diameter of 0.6 mm. The three-dimensional staggered busbar structure allows positive and negative currents to approach each other in space and flow in opposite directions, resulting in mutually canceling magnetic fields, such as... Figure 3 As shown, the loop inductance is reduced from 28 nanohenries in a conventional planar busbar to 8 nanohenries.

[0109] Technicians established a process parameter constraint model, using curing temperature, curing pressure, and curing time as the variables to be solved. The discrete range of curing temperature was set to 10 values ​​in 10-degree intervals between 120℃ and 210℃; the discrete range of curing pressure was set to 6 values ​​in 0.5 MPa intervals between 0.5 MPa and 3.0 MPa; and the discrete range of curing time was set to 10 values ​​in 10-minute intervals between 30 minutes and 120 minutes. Constraints included that the curing temperature of the polyimide composite material must be within the range of 120℃ to 150℃, the curing temperature of the nano-silver paste must be within the range of 180℃ to 210℃, the curing pressure must not exceed the chip's tolerance limit of 2.5 MPa, and the curing time must meet the minimum time requirement for complete reaction. Technicians used the arc consistency propagation algorithm to solve the process parameter constraint model and pruned the discrete ranges of the variables using the AC-3 iterative deletion algorithm. The algorithm maintains a queue of all variable pairs to be checked. Each time, a variable pair is taken from the queue for constraint checking, and values ​​that do not meet the constraints are deleted. After 15 iterations, an arc-consistent state is reached. The feasible values ​​for curing temperature are reduced to four: 130℃, 140℃, 190℃, and 200℃; the feasible values ​​for curing pressure are reduced to three: 1.0 MPa, 1.5 MPa, and 2.0 MPa; and the feasible values ​​for curing time are reduced to four: 40 minutes, 50 minutes, 60 minutes, and 70 minutes. Backtracking search is used in the reduced search space, ultimately outputting the initial parameter combinations: a curing temperature of 130℃, a curing pressure of 1.5 MPa, and a curing time of 45 minutes for pre-curing the polyimide composite layer; and a curing temperature of 190℃, a curing pressure of 1.5 MPa, and a curing time of 55 minutes for complete curing of the nano-silver paste filling layer.

[0110] Technicians employed an initial parameter combination to perform segmented curing of the gradient thermal matching transition layer. The IGBT chip coated with the gradient thermal matching transition layer was placed in a vacuum curing oven. First, the polyimide composite layer was pre-cured at 130°C and 1.5 MPa for 45 minutes. During the pre-curing stage, the polyimide composite material underwent partial cross-linking, establishing initial interfacial bonding strength, while maintaining a certain degree of fluidity to accommodate subsequent processes. After pre-curing, the temperature was increased to 190°C, and the nano-silver paste filling layer was fully cured at 1.5 MPa for 55 minutes. During the curing process, the silver particles in the nano-silver paste sintered to form a continuous conductive and thermally conductive network, simultaneously filling the micropores on the surface of the polyimide composite layer.

[0111] After the segmented curing process, technicians placed the IGBT chip into the chip embedding cavity and used a transient thermal resistance tester to measure the interface thermal resistance. The test method involved applying a heating power of 100 watts to the IGBT chip, measuring the temperature difference between the chip surface and the bottom surface of the thick copper thermally conductive layer, and calculating the interface thermal resistance based on Fourier's law of thermal conductivity. The test results showed an interface thermal resistance of 0.18 Kelvin per watt, lower than the set interface thermal resistance threshold of 0.25 Kelvin per watt, indicating that the interface bonding quality meets the requirements and no adjustment of process parameters is necessary.

[0112] Finally, technicians performed a lamination and curing process, integrally laminating and curing the IGBT chip, gradient thermal matching transition layer, thick copper thermal conductive layer, and multi-layer PCB structure. The temperature profile of the lamination equipment was set as follows: during the heating phase, the temperature was increased from room temperature to 180°C at a rate of 8°C per minute; during the holding phase, the temperature was maintained at 180°C for 75 minutes; and during the cooling phase, the temperature was decreased to room temperature at a rate of 5°C per minute. The pressure profile was set as follows: during the heating phase, the pressure gradually increased to 2.0 MPa; during the holding phase, the pressure was maintained at 2.0 MPa; and during the cooling phase, the pressure was gradually released. After lamination and curing, the various layers of the power module were integrated, forming a modular and wire-harness-free integrated structure.

[0113] Technicians conducted performance tests on the completed power module. Under rated operating conditions, the highest junction temperature of the power module was 105°C, and the junction-to-case thermal resistance was 0.42 Kelvin per watt. The busbar circuit inductance was measured using an impedance analyzer, and the measured value was 8.2 nanohenries. Power cycling tests were performed at a switching frequency of 20 kHz. After 50,000 cycles, the interface thermal resistance increase was less than 15%, and no delamination or cracking was observed.

[0114] The technological advancements of this invention compared to traditional power module fabrication methods are reflected in the following aspects: Traditional power modules employ modular packaging, where power chips are first packaged into independent modules and then connected to the busbar via wires. The parasitic inductance and thermal resistance introduced by these wires severely limit performance improvement. This invention eliminates parasitic parameters from module packaging and wire connections by directly embedding the power chip into the PCB substrate and tightly bonding it with a thick copper thermal conductive layer. The gradient thermal matching transition layer achieves a gradual transition by setting material layers with different coefficients of thermal expansion, effectively mitigating the mismatch in coefficients of thermal expansion between the silicon chip and the PCB substrate, and avoiding interface failure caused by stress concentration during temperature cycling in traditional soldered connections. The biomimetic ant colony algorithm simulates ant foraging behavior to optimize the location of thermal vias, making the distribution of thermal vias adaptable to the heat dissipation characteristics of the chip. Compared to the traditional uniform via placement method, it concentrates more thermal vias in high-heat areas and reduces the number of thermal vias in low-heat areas, achieving optimized allocation of heat dissipation resources. The three-dimensional staggered busbar structure utilizes the physical mechanism of magnetic field cancellation generated by the reverse flow of positive and negative currents, significantly reducing loop inductance without increasing the PCB area. The arc consistency propagation algorithm quickly solves the optimization problem of multi-constraint coupled process parameters through constraint propagation and search space pruning, avoiding the blindness and inefficiency of traditional trial-and-error methods. Segmented curing treatment applies temperature and pressure in stages according to the curing characteristics of different material layers, avoiding excessive temperature gradients and internal stress concentration caused by simultaneous curing, thus improving the interface bonding quality.

[0115] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a demodularized and de-wiring-harnessed power module, characterized in that, include: A PCB substrate is fabricated and a chip embedding cavity is formed. A thick copper thermally conductive layer is fabricated at the bottom of the chip embedding cavity. A gradient thermal matching transition layer is coated between the bottom surface of the power chip and the bottom of the chip embedding cavity. The gradient thermal matching transition layer consists of a polyimide composite material layer and a nano-silver paste filling layer from bottom to top. The planar dimensions of the thick copper thermally conductive layer and the heat dissipation data of the power chip are collected. The planar dimensions are divided into candidate position grids. A biomimetic ant colony algorithm is used to optimize the output thermal via array distribution coordinates to form a thermal via array in the thick copper thermally conductive layer. A three-dimensional staggered busbar structure is fabricated between the PCB layers above the power chip. A process parameter constraint model is established, and the parameter combination is obtained by using the arc consistency propagation algorithm. The gradient thermal matching transition layer is segmented and cured; the power chip is placed in the chip embedding cavity and the interface thermal resistance value is measured. When the interface thermal resistance value exceeds the interface thermal resistance threshold, the adjustment parameter combination is recalculated; and the lamination curing process is performed.

2. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 1, characterized in that, A thick copper thermal conductive layer is prepared at the bottom of the chip embedding cavity by an electroplating process.

3. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 2, characterized in that, The gradient thermal matching transition layer is used to alleviate the mismatch in thermal expansion coefficients between the silicon chip and the PCB substrate.

4. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 3, characterized in that, The polyimide composite layer is made of a composite material of polyimide and epoxy resin.

5. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 4, characterized in that, The nano-silver paste filling layer is composed of nano-silver particles and an organic carrier, and has the characteristics of high thermal conductivity and low elastic modulus.

6. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 5, characterized in that, The biomimetic ant colony algorithm uses virtual ants to move and release pheromones according to the temperature gradient, and selects grid points with pheromone concentrations exceeding a set threshold as locations for thermal via placement.

7. The method for fabricating a demodularized and wire-harness-free power module according to claim 6, characterized in that, The thermal via array is distributed according to a tree-like network topology, with the main thermal vias located in the central region of the heat source.

8. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 7, characterized in that, In the three-dimensional staggered busbar structure, the positive busbar layer and the negative busbar layer are located on different PCB layers and are staggered in the vertical projection direction, connected by interlayer vias.

9. The method for fabricating a demodularized and wire-harness-free power module according to claim 8, characterized in that, The process parameter constraint model includes curing temperature variables, curing pressure variables, and curing time variables.

10. The method for fabricating a demodularized and de-wiring-harnessed power module according to claim 9, characterized in that, The arc consistency propagation algorithm uses the AC-3 iterative deletion algorithm to check variable pairs and delete values ​​that do not meet the constraints.

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