Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a reading instruction stream from a host system, wherein the reading instruction stream comprises a plurality of logic addresses; analyzing distribution characteristics of a plurality of logic addresses in the reading instruction stream, and generating a pre-reading strategy based on the distribution characteristics; reading the pre-read data from the memory module and storing the pre-read data to the buffer memory according to the pre-read strategy; when a target reading instruction is received from the host system, judging whether target data corresponding to the target reading instruction exists in the buffer memory or not; and if the target data exists in the buffer memory, directly transmitting the target data from the buffer memory to the host system to respond to the target reading instruction. By analyzing the distribution characteristics of the reading instruction stream and generating the pre-reading strategy, the storage device can prepare the data in advance, so that the response time of data reading is shortened.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory management method and a memory controller, and more specifically to an interrupt response optimization technique based on the Fast Non-Volatile Memory Interface Standard (NVMe, NVM Express). Background Technology

[0002] In the architecture of modern solid-state drives (SSDs), data read speeds are often limited by hardware conditions. On the one hand, the inherent read speed of low-cost NAND flash memory chips has a physical bottleneck; on the other hand, the processing performance of the controller chip also directly affects data transfer efficiency. With these two hardware limitations, the read speed of storage devices struggles to reach the level of similar products on the market, failing to meet users' demands for high-speed data access.

[0003] Traditional memory management methods typically employ a passive response approach, meaning the memory controller only begins reading data from the flash memory chip after receiving a read command from the host system. This "just-in-time" mode forces the host system to wait for the flash memory chip to complete the data read operation, resulting in response latency. This is particularly problematic in scenarios involving random small file reads, where the data is distributed across different locations within the flash memory chip, requiring independent addressing and data movement operations for each read, further exacerbating the latency issue.

[0004] Furthermore, while existing read-ahead techniques can predict continuous read behavior to some extent, they lack adaptability to non-continuous, discrete read patterns. User read behavior during operating system startup, program loading, web browsing, and other scenarios often exhibits discrete distribution characteristics, making traditional continuous read-ahead strategies ill-suited for these situations. Summary of the Invention

[0005] In view of this, this disclosure provides a memory management method and a memory controller. By analyzing the distribution characteristics of the read command stream from the host system, a corresponding pre-fetch strategy is generated. Before the host system actually issues a read command, the predicted data required is pre-fetched from the memory module into a buffer memory. When the host system issues a target read command, the memory controller can directly retrieve the target data from the buffer memory to respond, avoiding waiting for the memory module to perform an immediate read operation, thereby shortening the data read response time.

[0006] This disclosure provides one or more embodiments of a memory management method applied to a memory controller for managing a storage device configured with a memory module and a buffer memory. The method includes: acquiring a read instruction stream from a host system, wherein the read instruction stream contains multiple logical addresses; analyzing the distribution characteristics of the multiple logical addresses in the read instruction stream and generating a pre-read strategy based on the distribution characteristics; reading pre-read data from the memory module and storing the pre-read data in the buffer memory according to the pre-read strategy; when a target read instruction is received from the host system, determining whether the target data corresponding to the target read instruction exists in the buffer memory; and if the target data exists in the buffer memory, directly transferring the target data from the buffer memory to the host system in response to the target read instruction.

[0007] This disclosure provides a memory controller in one or more embodiments for controlling a storage device configured with a memory module. The memory controller includes: a buffer memory; a memory interface control circuit electrically connected to the memory module; a data management circuit electrically connected to a host system; a separate logic module; and a processor electrically connected to the memory interface control circuit, the buffer memory, the data management circuit, and the separate logic module. The processor is configured to acquire a read instruction stream from the host system via a data management circuit, the read instruction stream containing multiple logical addresses; an independent logic module is configured to analyze the distribution characteristics of the multiple logical addresses in the read instruction stream and generate a prefetch strategy based on the distribution characteristics; the processor is also configured to read prefetch data from the memory module via a memory interface control circuit according to the prefetch strategy and store the prefetch data in a buffer memory; the independent logic module is also configured to manage the retention and eviction of all prefetch data in the buffer memory; the processor is also configured to determine whether the target data corresponding to the target read instruction exists in the buffer memory when a target read instruction is received from the host system; and the processor is also configured to transfer the target data from the buffer memory to the host system via the data management circuit if the target data exists in the buffer memory in response to the target read instruction.

[0008] Based on the above, the memory management method and memory controller provided in this disclosure can accurately identify the current read pattern and predict the subsequent read needs of the host system by acquiring and analyzing the distribution characteristics of multiple logical addresses in the read instruction stream from the host system in real time. The system then generates a pre-read strategy and actively reads the pre-read data from the memory module and stores it in the buffer memory. When the host system actually sends the target read instruction, the memory controller can directly determine and retrieve the prepared target data from the buffer memory to respond. This mechanism transforms the originally serial data read process into a prediction-based parallel preparation process, enabling the host system to obtain a "zero-wait" response experience when initiating a read request. This effectively overcomes the hardware performance limitations on read speed without upgrading hardware specifications such as NAND flash memory or the main controller processor, improving the overall data throughput of the storage device and the user experience. Furthermore, through the analysis of distribution characteristics, this method can adapt to various scenarios such as continuous and random reads, improving the accuracy of the pre-read strategy and the utilization efficiency of the cache space. Attached Figure Description

[0009] Figure 1 This is a block diagram of a host system and storage device according to embodiments of the present disclosure;

[0010] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure;

[0011] Figure 3 A flowchart generated according to the read-ahead strategy shown in the embodiments of this disclosure;

[0012] Figure 4 This is a schematic diagram of the structure of a hash map table according to an embodiment of the present disclosure;

[0013] Figure 5 This is a timing diagram of a memory management method according to an embodiment of the present disclosure;

[0014] Figure 6 A flowchart illustrating the first pre-read strategy triggering a judgment according to an embodiment of this disclosure;

[0015] Figure 7 A flowchart illustrating the second pre-read strategy triggering a judgment according to an embodiment of this disclosure;

[0016] Figure 8 This is a flowchart illustrating the historical access sequence matching determination according to embodiments of the present disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0019] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0023] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0026] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0027] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, it acquires a read instruction stream from the host system 10 via a data management circuit 212, wherein the read instruction stream contains multiple logical addresses. Notably, the memory controller 210 also includes an independent logic module 215, to which the processor 211 is electrically connected. The independent logic module 215 is configured to analyze the distribution characteristics of the multiple logical addresses in the read instruction stream and generate a pre-read strategy based on the distribution characteristics. According to the pre-read strategy, the processor 211 reads pre-read data from the memory module 220 via a memory interface control circuit 213 and stores the pre-read data in a buffer memory 214. In addition, the processor 211 is also configured to, when receiving a target read instruction from the host system 10, determine whether the target data corresponding to the target read instruction exists in the buffer memory 214; and if the target data exists in the buffer memory 214, transfer the target data from the buffer memory 214 to the host system 10 via the data management circuit 212 in response to the target read instruction.

[0028] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0029] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0030] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data into the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation based on a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data into the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212 assists the processor 211 in acquiring the read instruction stream from the host system 10 and assists in transferring the target data stored in the buffer memory 214 to the host system 10.

[0031] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0032] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0033] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0034] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store prefetch data required by this disclosure. Independent logic module 215 is also configured to manage the retention and eviction of all prefetch data in buffer memory 214.

[0035] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 stores data corresponding to multiple logical addresses, serving as the source for the processor 211 to read prefetch data according to a prefetch strategy.

[0036] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0037] Independent logic module 215 is electrically connected to processor 211 and buffer memory 214, and operates independently of processor 211. Independent logic module 215 is configured to analyze the distribution characteristics of multiple logical addresses in the read instruction stream and generate a prefetch strategy based on these characteristics. Furthermore, independent logic module 215 is also configured to manage the retention and eviction of prefetched data in buffer memory 214. Through this architecture design, where independent logic module 215 operates independently of processor 211, distribution characteristic analysis and prefetch strategy generation can be completed without occupying the computing resources of processor 211, thereby avoiding impact on other operations of memory controller 210.

[0038] More specifically, in one embodiment, the independent logic module 215 may be implemented as an Application Specific Integrated Circuit (ASIC). Specifically, the independent logic module 215 includes specially designed digital logic circuits configured to perform specific operations such as distributed feature analysis, prefetch strategy generation, and cache management. Because the circuit architecture of an ASIC is optimized for specific functions, the independent logic module 215 can perform these operations without relying on the computing resources of the processor 211.

[0039] In another embodiment, the independent logic module 215 can be implemented as a Field-Programmable Gate Array (FPGA). An FPGA includes configurable logic blocks and programmable interconnect resources. By programming the configurable logic blocks, functions such as distribution feature analysis, prefetch strategy generation, and cache management can be implemented. The implementation using an FPGA allows for adjustment of the functional logic of the independent logic module 215 as needed during product development or after product deployment.

[0040] In another embodiment, the independent logic module 215 can be implemented as a hardware accelerator integrated with the processor 211 on the same chip. The hardware accelerator has independent arithmetic units and registers, and exchanges data with the processor 211 through a dedicated bus or a shared bus. After receiving the start instruction from the processor 211, the hardware accelerator can independently perform operations such as distributed feature analysis and prefetch strategy generation, and feed the operation results back to the processor 211 or write them directly to the buffer memory 214.

[0041] In other embodiments, the independent logic module 215 may also be configured with dedicated storage circuit elements, such as a register bank or cache (e.g., SRAM), for storing the aforementioned "hash map," "historical access sequence," and related parameters of the "read-ahead strategy" (such as read-ahead length, threshold, etc.). By storing these frequently accessed data structures in the dedicated storage circuit elements of the independent logic module 215, rather than occupying the main system memory of the processor 211, the bandwidth pressure on the system bus is further reduced and the response speed is improved.

[0042] In one embodiment, the independent logic module 215 contains multiple functional sub-modules that work together to perform functions such as distributed feature analysis, pre-read strategy generation, and cache management. These modules can also be implemented in hardware or software (program modules).

[0043] Specifically, in one embodiment, the independent logic module 215 includes a feature extraction submodule, a pattern recognition submodule, a policy generation submodule, and a cache management submodule. The feature extraction submodule is configured to extract multiple logical addresses and their corresponding data lengths from the read instruction stream and pass the extracted information to the pattern recognition submodule. The pattern recognition submodule is configured to analyze the distribution characteristics of the multiple logical addresses, determine whether the distribution characteristics belong to a continuously increasing pattern or a discrete distribution pattern, and pass the recognition result to the policy generation submodule. The policy generation submodule is configured to generate a corresponding pre-read policy based on the recognition result of the pattern recognition submodule; if the pattern is identified as a continuously increasing pattern, a first pre-read policy is generated; if the pattern is identified as a discrete distribution pattern, a second pre-read policy is generated. The cache management submodule is configured to manage the retention and eviction of pre-read data in the buffer memory 214, including performing cache replacement operations and maintaining the status information of the pre-read data.

[0044] In one embodiment, the independent logic module 215 is further configured to perform address merging operations. The address merging operation is performed after the independent logic module 215 generates a prefetch strategy and determines multiple prefetch logical addresses to be prefetched. Specifically, the independent logic module 215 includes an address merging circuit configured to check whether the multiple prefetch logical addresses are adjacent or partially overlapping. If multiple prefetch logical addresses are adjacent or partially overlapping, the address merging circuit merges these prefetch logical addresses into a single merged read request. The starting logical address of the merged read request is the smallest logical address among the multiple prefetch logical addresses, and the data length of the merged read request covers the logical address range corresponding to the multiple prefetch logical addresses.

[0045] The following example illustrates the execution process of address merging. Assume that independent logic module 215, based on the matching results between the current read instruction stream distribution and the hash map, predicts that the subsequently accessed pre-read logical addresses include LBA_1000, LBA_1001, LBA_1002, LBA_1003, LBA_1050, and LBA_1051. After analyzing these six pre-read logical addresses, the address merging circuit identifies LBA_1000 to LBA_1003 as four consecutive adjacent logical addresses, and LBA_1050 to LBA_1051 as two consecutive adjacent logical addresses. Therefore, the address merging circuit merges the original six pre-read logical addresses into two merged read requests: the first merged read request starts at LBA_1000 with a data length of 16KB (assuming each logical address corresponds to 4KB of data), and the second merged read request starts at LBA_1050 with a data length of 8KB. Based on the two merge read requests mentioned above, processor 211 can obtain all the pre-read data from memory module 220 by performing two read operations through memory interface control circuit 213. Compared to the six read operations required without address merging, only two read operations are required after address merging, thereby reducing the number of accesses to memory module 220.

[0046] In another embodiment, the independent logic module 215 is also configured to perform a priority sorting operation. Specifically, the independent logic module 215 includes a priority sorting circuit configured to assign a priority value to each prefetch logical address based on the predicted access probabilities of multiple prefetch logical addresses predicted by the prefetch strategy, and sequentially perform the operation of reading the corresponding prefetch data from the memory module 220 according to the order of the priority values.

[0047] The hardware implementation of the priority sorting circuit may include a priority queue and a sorting network. The priority queue is configured to store multiple pre-read logical addresses to be pre-read and their corresponding priority values. The sorting network is configured to sort the multiple pre-read logical addresses in the priority queue, so that the pre-read logical addresses with higher priority values ​​are placed at the front of the queue. When performing a pre-read operation, the processor 211 sequentially retrieves the pre-read logical addresses from the front of the priority queue and performs the corresponding read operation.

[0048] In one embodiment, the priority sorting operation is performed after multiple logical addresses in the current read instruction stream are matched with historical access sequences in the hash map table. Specifically, the independent logic module 215 first analyzes the distribution pattern of multiple logical addresses in the current read instruction stream and matches the distribution pattern with multiple historical access sequences recorded in the hash map table. When the distribution pattern partially matches multiple historical access sequences, the independent logic module 215 calculates the predicted access probability for each of these successfully matched historical access sequences and assigns priority values ​​to the predicted subsequent associated logical addresses for each historical access sequence accordingly.

[0049] The following example illustrates the execution process of the priority sorting operation. Assume the current read instruction stream contains three consecutively received read instructions with logical addresses LBA_100, LBA_205, and LBA_310, corresponding to data lengths of 4KB, 8KB, and 4KB, respectively. After analyzing the distribution of these three logical addresses, the independent logic module 215 determines that the multiple logical addresses exhibit a non-contiguous discrete distribution, thus entering random read mode and matching them with the hash map table. Assume the hash map table records historical access sequence A, historical access sequence B, and historical access sequence C. The logical addresses associated with historical access sequence A are LBA_100, LBA_205, LBA_310, LBA_415, and LBA_520 in sequence; the logical addresses associated with historical access sequence B are LBA_100, LBA_205, LBA_310, LBA_400, and LBA_500 in sequence; and the logical addresses associated with historical access sequence C are LBA_100, LBA_200, LBA_300, LBA_400, and LBA_500 in sequence.

[0050] After matching the logical address distribution of the current read instruction stream with the three historical access sequences, the independent logic module 215 determines that the first three associated logical addresses of historical access sequences A and B are completely consistent with the current read instruction stream, thus determining that historical access sequences A and B are successfully matched. The second and third associated logical addresses of historical access sequence C are inconsistent with the current read instruction stream, thus determining that historical access sequence C is unmatched. Based on the above matching results, the independent logic module 215 calculates the predicted access probability only for the successfully matched historical access sequences A and B.

[0051] Assume that historical access sequence A has an access frequency of 25 times and a weight of 0.9, and historical access sequence B has an access frequency of 40 times and a weight of 0.6. Independent logic module 215 calculates the predicted access probability of each successfully matched historical access sequence according to the following formula: the predicted access probability equals the access frequency multiplied by the weight value, then divided by the sum of the weighted access counts of the successfully matched historical access sequences. For example, historical access sequence A has a weighted access count of 25 multiplied by 0.9, which equals 22.5. Historical access sequence B has a weighted access count of 40 multiplied by 0.6, which equals 24. The sum of the weighted access counts is 22.5 plus 24, which equals 46.5. Therefore, the predicted access probability of historical access sequence A is 22.5 divided by 46.5, resulting in approximately 0.48. The predicted access probability of historical access sequence B is 24 divided by 46.5, resulting in approximately 0.52.

[0052] Based on the above calculation results of the predicted access probabilities, the predicted access probability of historical access sequence B is slightly higher than that of historical access sequence A. Therefore, the predicted subsequent associated logical address LBA_400 of historical access sequence B will be sorted before the predicted subsequent associated logical address LBA_415 of historical access sequence A. After the sorting network sorts the pre-read logical addresses in the priority queue according to the predicted access probabilities from high to low, the processor 211 first reads the pre-read data corresponding to logical address LBA_400 from the memory module 220 and stores it in the buffer memory 214, and then reads the pre-read data corresponding to logical address LBA_415. It should be noted that in other embodiments, the comparison results of weighted access counts can also be used directly for sorting.

[0053] In another embodiment, priority value allocation can also incorporate a time-weighted mechanism. The time-weighted mechanism is based on matching the access timestamps of each historical access sequence recorded in the hash map table with the current system time to filter out candidate historical access sequences related to the current time.

[0054] Specifically, the hash map table records a corresponding access timestamp for each historical access sequence. The access timestamp is the system time when the historical access sequence was last accessed. When the independent logic module 215 executes the time weighting mechanism, it first obtains the current system time, and then compares the current system time with the access timestamps of each historical access sequence in the hash map table to determine whether each historical access sequence matches the current time.

[0055] In one embodiment, the independent logic module 215 determines whether the access timestamp matches the current system time by determining whether the access timestamp and the current system time belong to the same time segment. The time segment can be predefined as multiple fixed time ranges, such as dividing a day into a morning period (06:00 to 12:00), an afternoon period (12:00 to 18:00), and an evening period (18:00 to 24:00), etc. When the time segment to which the access timestamp belongs is the same as the time segment to which the current system time belongs, the independent logic module 215 determines that the historical access sequence matches the current time.

[0056] In another embodiment, the independent logic module 215 determines whether the access timestamp matches the current system time by calculating the time difference between the access timestamp and the current system time, and determining whether the time difference is less than a preset time difference threshold. When the time difference is less than the time difference threshold, the independent logic module 215 determines that the historical access sequence matches the current time. The time difference threshold can be set according to the actual application scenario, for example, set to 1 hour, 2 hours, or other appropriate values.

[0057] The following example illustrates the execution process of the time-weighted mechanism. Continuing the previous example, assume the current system time is 09:30 (9:30 AM), the access timestamp of historical access sequence A is 08:45 (8:45 AM), and the access timestamp of historical access sequence B is 15:20 (3:20 PM). In the embodiment using the time segment judgment method, since the current system time 09:30 belongs to the morning period (06:00 to 12:00), the access timestamp of historical access sequence A 08:45 also belongs to the morning period, while the access timestamp of historical access sequence B 15:20 belongs to the afternoon period, the independent logic module 215 determines that historical access sequence A matches the current time, while historical access sequence B does not match the current time.

[0058] In another embodiment using a time difference threshold method, assume the preset time difference threshold is 2 hours. The time difference between the current system time 09:30 and the access timestamp of historical access sequence A 08:45 is 45 minutes, which is less than the time difference threshold of 2 hours. Therefore, the independent logic module 215 determines that historical access sequence A matches the current time. The time difference between the current system time 09:30 and the access timestamp of historical access sequence B 15:20 is 5 hours and 50 minutes, which is greater than the time difference threshold of 2 hours. Therefore, the independent logic module 215 determines that historical access sequence B does not match the current time.

[0059] Based on the results of the time matching judgment, the independent logic module 215 adjusts the priority values ​​of the successfully matched historical access sequences. Specifically, the priority value of historical access sequence A, which matches the current time, is increased; the priority value of historical access sequence B, which does not match the current time, is decreased. Continuing the previous example, even if the predicted access probability (0.52) of historical access sequence B is slightly higher than that of historical access sequence A (0.48), after time-weighted adjustment, since historical access sequence A matches the current time, the independent logic module 215 adjusts the order of the predicted subsequent associated logical address LBA_415 of historical access sequence A before the predicted subsequent associated logical address LBA_400 of historical access sequence B. When the processor 211 performs the pre-read operation, it first reads the pre-read data corresponding to logical address LBA_415 from the memory module 220, and then reads the pre-read data corresponding to logical address LBA_400.

[0060] Through the aforementioned time-weighted mechanism, the independent logic module 215 can identify historical access sequences related to the current time and prioritize the pre-reading of the subsequent associated logical addresses predicted by these sequences. This mechanism is suitable for application scenarios where users have regular usage habits, such as when a user launches a specific application at a fixed time every morning; the historical access sequences corresponding to that application will have a higher pre-reading priority during the same time period.

[0061] Through the priority sorting mechanism based on the distribution pattern matching results of the current read instruction stream, the independent logic module 215 can comprehensively consider the access frequency, weight value and time matching degree of each matching sequence when multiple historical access sequences match the current read instruction stream, and assign appropriate priority values ​​to the subsequent associated logic addresses predicted by each matching sequence, so that data with a higher probability of prediction hit is pre-read into the buffer memory 214.

[0062] In another embodiment, the independent logic module 215 is further configured to perform cache replacement operations. Specifically, the independent logic module 215 includes cache replacement circuitry configured to calculate the eviction priority of each cached data in the buffer memory 214 based on the Least Recently Used (LRU) rule when the remaining space in the buffer memory 214 is insufficient to store new pre-read data. The circuitry then adjusts the eviction priority of each cached data based on the access probability predicted by the pre-read strategy, and evicts the cached data with the highest adjusted eviction priority to free up space for new pre-read data.

[0063] The hardware implementation of the cache replacement circuit may include an access counter array, a timestamp register, and a eviction decision logic unit. The access counter array is configured to record the number of accesses to each cached data in the buffer memory 214. The timestamp register is configured to record the most recent access time of each cached data. The eviction decision logic unit is configured to combine the information from the access counter array and the timestamp register, along with the access probability predicted by the pre-read strategy, to calculate the eviction priority of each cached data and select the eviction target.

[0064] In one embodiment, if the candidate eviction data belongs to the data that the prefetch strategy predicts will be accessed soon, the cache replacement circuit exempts the candidate eviction data and identifies another candidate eviction data from the buffer memory 214 to perform a cache eviction operation. This mechanism avoids prematurely eviction of prefetch data with a high predicted hit probability, thereby maintaining the effectiveness of the prefetch mechanism.

[0065] To illustrate with a specific example: Suppose the target historical access sequence predicts that LBA_815 and LBA_920 will be accessed subsequently, and the candidate eviction data block corresponds to LBA_815. Since LBA_815 falls within the prediction range, the independent logic module 215 exempts this data block and instead selects the next oldest data block as a new candidate. If the new candidate (such as LBA_200) is not within the prediction range, then it is evictioned.

[0066] In another embodiment, if the status of candidate elimination data is marked as a read-ahead protection status, the independent logic module 215 can be directly exempted without performing logical address comparison, thereby reducing computational overhead.

[0067] In this embodiment, the independent logic module 215 and the processor 211 communicate via dedicated control signals and a data bus. Specifically, after the processor 211 obtains the read instruction stream from the host system 10 through the data management circuit 212, it transmits multiple logical addresses and corresponding data lengths from the read instruction stream to the independent logic module 215. After completing the distribution feature analysis and pre-read strategy generation, the independent logic module 215 transmits the generated pre-read strategy to the processor 211. According to the pre-read strategy, the processor 211 reads the pre-read data from the memory module 220 through the memory interface control circuit 213 and stores it in the buffer memory 214.

[0068] It is worth noting that while the independent logic module 215 is performing operations such as distribution feature analysis, prefetch strategy generation, and cache management, the processor 211 can simultaneously perform other operations, such as processing write instructions from the host system 10 or performing garbage collection operations. Since the independent logic module 215 operates independently of the processor 211, it does not occupy any of the processor 211's computation cycles, thus enabling the memory controller 210 to maintain its responsiveness to other instructions while performing prefetch-related operations.

[0069] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure.

[0070] Reference Figure 2 First, in step S210, the memory controller 210 acquires a stream of read commands from the host system 10. Specifically, the processor 211 receives a series of read commands sent by the host system 10 in real time via the data management circuit 212. These read command streams contain multiple logical block addresses (LBAs) and / or corresponding data lengths, which reflect the current sequence of data access requests from the host system 10. Notably, this acquisition process is continuous so that the system can accumulate sufficient behavioral data for analysis.

[0071] Next, in step S220, the distribution characteristics of multiple logical addresses in the read instruction stream are analyzed, and a pre-read strategy is generated based on these characteristics. In this embodiment, this crucial step is primarily executed by the independent logic module 215. The independent logic module 215 monitors and calculates the captured LBA stream in real time, identifying whether these addresses exhibit a continuously increasing trend (corresponding to large file reading) or a specific discrete jump pattern (corresponding to random small file reading). Based on the identified distribution characteristics, the independent logic module 215 predicts the logical addresses that the host system 10 may access subsequently, and generates a pre-read strategy that includes the pre-read start address and pre-read length accordingly. Since this step is completed independently by the independent logic module 215, it does not consume the computing resources of the processor 211, ensuring the efficiency of the memory controller 210 in processing other core tasks.

[0072] Subsequently, in step S230, according to the pre-read strategy, pre-read data is read from the memory module and stored in the buffer memory. Specifically, after receiving the pre-read strategy generated by the independent logic module 215, the processor 211 monitors the interface transmission status between the storage device 20 and the host system 10, as well as the operating status of the memory module 220. Preferably, the processor 211 utilizes the instruction transmission gap or the system's idle time slice to send an asynchronous read instruction to the memory module 220 through the memory interface control circuit 213. In response to this instruction, the memory module 220 reads out the predicted pre-read data and temporarily stores it in the buffer memory 214. Through this "advance preparation" mechanism, data is moved from the low-speed NAND flash memory to the high-speed DRAM or SRAM cache.

[0073] When a target read instruction is received from the host system, step S240 is entered to determine whether the target data corresponding to the target read instruction exists in the buffer memory. In this step, when the host system 10 actually issues a new read request (i.e., a target read instruction), the processor 211 will not directly access the memory module 220, but will first look up the index table of the buffer memory 214 to check whether the logical address requested by the instruction matches the data pre-read in step S230.

[0074] Finally, in step S250, if the target data exists in the buffer memory, the target data is directly transferred from the buffer memory to the host system in response to the target read instruction. If the judgment result of step S240 is "yes" (i.e., prediction hit), the processor 211 will immediately instruct the data management circuit 212 to transfer the target data prepared in the buffer memory 214 to the host system 10 through the connection interface circuit 230. Since the physical read time (tR) and transfer time required to access the memory module 220 (flash memory) are eliminated, the host system 10 can obtain a data response experience with almost "zero wait", thereby significantly improving the overall read speed of the system. Conversely, if the target data does not exist in the buffer memory 214, the processor 211 reads the data from the memory module 220 according to the normal process. Hereinafter, using Figure 3 The generation mechanism of the pre-read strategy in step S220 will be explained in detail.

[0075] Figure 3 A flowchart generated for a read-ahead strategy shown in an embodiment of this disclosure.

[0076] Please refer to Figure 1 and Figure 3 The process of analyzing distribution characteristics and generating a pre-read strategy in step S220 can be further subdivided into judgment and processing logic for different reading modes.

[0077] Specifically, firstly, in step S310, the independent logic module 215 monitors and calculates multiple logical addresses received consecutively in the read instruction stream in real time to determine whether they exhibit an increasing trend. Specifically, the system checks whether the difference between multiple adjacent logical addresses is equal to the data length of the previous read instruction. For example, if the previous instruction read a data block starting at LBA 100 with a length of 4, and the current instruction reads a data block starting at LBA 104, it is determined to conform to an increasing trend (LBA increases). If the judgment result of step S310 is yes, it indicates that the current host system 10 is in a state of sequential large file reading, and at this time, it proceeds to step S320 to generate the first pre-read strategy.

[0078] In this first pre-read strategy, the independent logic module 215 directly obtains the pre-read logical address and pre-read data length through arithmetic operations based on the data length of the corresponding multiple read instructions and the last logical address among the multiple consecutively received logical addresses. For example, adding the data length to the last logical address yields the starting address for the next prediction. This processing method has extremely low computational overhead and is very suitable for sequential reading scenarios such as video streams or large file copying.

[0079] However, if the judgment result of step S310 is negative, that is, if the multiple logical addresses in the read instruction stream exhibit a non-contiguous discrete distribution, it indicates that the current situation may be a random read scenario such as system startup or application loading. At this time, the process proceeds to step S330, where a pre-established hash map table is used for pattern matching. In this embodiment, the memory controller 210 (especially the internal memory or buffer memory 214 of the independent logic module 215) maintains a hash map table, which records multiple historical access sequences. Each historical access sequence contains the order of multiple historical logical addresses that appeared in a specific scenario in the past, as well as the corresponding multiple data lengths. In step S330, the independent logic module 215 compares and matches the multiple logical addresses and corresponding multiple data lengths captured in the current read instruction stream with the multiple historical access sequences recorded in the hash map table.

[0080] If, in step S330, the current discrete address sequence is found to match a portion of a target historical access sequence in the hash map table (for example, the currently received LBA A and LBA B sequences match the beginning of the historical sequence LBA A  LBA B  LBA C), then the judgment result is yes, and the process proceeds to step S340 to generate a second pre-read strategy. Under this strategy, the system predicts the associated logical address and associated data length (i.e., predicts LBA C) that the host system 10 will access next, based on the subsequent nodes recorded in the target historical access sequence (each read instruction is considered a node in the sequence). Conversely, if the comparison in step S330 fails, the process proceeds to step S350, where this new set of access sequences is recorded as a new behavior pattern in the hash map table. Through this mechanism, this disclosure can effectively address seemingly disordered but actually traceable random read behavior.

[0081] Figure 4 This is a schematic diagram of the structure of a hash map table according to an embodiment of the present disclosure.

[0082] In one embodiment, please refer to Figure 4 To achieve the aforementioned accurate prediction of random access patterns, the memory controller 210 (specifically, the independent logic module 215) establishes and maintains a hash map table HMT. This hash map table HMT records multiple historical access sequences (e.g., entries shown by indices A and B), where each historical access sequence contains a set of sequentially arranged associated logical addresses (e.g., A1, A2, A3, A4...) and corresponding multiple data lengths (e.g., AL1, AL2, AL3, AL4...). These records reflect the non-continuous read behavior patterns exhibited by the host system 10 during past operation, under specific application startup or operational scenarios.

[0083] For example, when the independent logic module 215 finds in real-time analysis that the current read instruction stream matches the first part (e.g., A1, A2) of a certain set of associated logic addresses recorded in the table, it can use the subsequent associated logic addresses (e.g., A3, A4) recorded in the table as the basis for prediction to generate a second pre-read strategy.

[0084] In another embodiment, further, to improve the dimensionality and accuracy of the prediction, this disclosure provides advanced optional mechanisms. For example... Figure 4As shown, the hash map table HMT can also optionally be configured with an "access timestamp" field and a "weight value" field. In embodiments that include access timestamps, when recording historical access sequences, the system synchronously records the system time (e.g., AT1, AT2) at which the sequence occurred. This allows the independent logic module 215 to introduce a time-weighted mechanism when performing matching, i.e., obtaining the current system time and filtering candidate historical access sequences from the hash map table HMT based on the current system time, where the access timestamp matches the current system time. This enables more accurate pre-read judgment in scenarios with strong time regularity, such as morning power-on and midday backup.

[0085] Furthermore, in embodiments that include weight values, the hash map table (HMT) is also used to record the weight value (e.g., AW1, AW2) or access frequency of each historical access sequence. This weight value reflects the confidence or popularity of the corresponding historical access sequence. When the system finds that multiple historical access sequences can partially match the current read instruction stream, or when the buffer memory 214 has limited space and pre-read data selection is required, the independent logic module 215 can, based on this weight value, prioritize the subsequent data corresponding to historical access sequences with higher weight values ​​(i.e., those that have historically appeared more frequently or have been recently verified) for pre-reading, thereby optimizing the cache hit rate and utilization efficiency.

[0086] Building upon the aforementioned hash-mapped matching mechanism, this disclosure further introduces intelligent analysis based on the time dimension to further improve prediction accuracy. In one embodiment, the process of establishing the hash-mapped table involves not only recording address sequences but also synchronously recording the access timestamp for each historical access sequence. Under this architecture, the generation process of the second pre-read strategy becomes more comprehensive: the independent logic module 215 first obtains the current system time (e.g., by reading the system clock or a time synchronization signal sent by the host). Then, instead of blindly searching the entire massive hash-mapped table, the system first filters out a set of candidate historical access sequences whose access timestamps match the current system time. For example, if the current time is 9:00 AM, the system will prioritize sequences that frequently occurred between 8:30 AM and 9:30 AM. Subsequently, the system compares multiple logical addresses and corresponding data lengths in the current read instruction stream with this set of time-filtered candidate historical access sequences. This "time-based filtering followed by content matching" mechanism can effectively eliminate interference items that have similar address patterns but completely different times (for example, excluding similar read patterns that only appear during nighttime backups), thereby accurately locking in the target historical access sequence that best fits the current context.

[0087] It should be noted that, to ensure the prediction model can evolve with changes in user habits, this disclosure also provides a feedback-based dynamic weight optimization mechanism. In another embodiment, after the system performs prefetching according to a time-weighted mechanism and transmits the target data to the host system, the independent logic module 215 continuously tracks the actual usage of this prefetched data and calculates the data utilization rate of the prefetched data in the buffer memory (e.g., if 10 pages were prefetched, how many were actually read by the host). If the data utilization rate is found to be lower than a low utilization threshold (e.g., 30%), it indicates that the prediction model for that time period is no longer accurate (possibly due to changes in user schedules or workflows), and the system will automatically reduce the weight value of the target historical access sequence associated with the current system time, reducing its probability of being selected again in the future. Conversely, if the data utilization rate is higher than a high utilization threshold (e.g., 90%), it indicates that the prediction is very accurate, and the system will increase the weight value of the target historical access sequence. This closed-loop feedback mechanism ensures that the system can always adapt to the latest usage environment.

[0088] When faced with a situation where multiple historical access sequences can partially match the current instruction stream, access frequency becomes a key decision-making criterion. In another embodiment, the hash map table is also used to record the access frequency of each historical access sequence (i.e., the total number of times the sequence has been triggered historically). When generating the second prefetch strategy, the independent logic module 215 checks the statistical data of each candidate sequence and prioritizes the subsequent data corresponding to historical access sequences whose access frequency exceeds a preset frequency threshold for prefetching. For example, if the prefixes of sequences A and B both match the current instruction, but sequence A appeared 100 times in the past week while sequence B only appeared 2 times, the system will decisively choose sequence A as the prediction basis. This reflects the statistical principle of "prioritizing high-probability events," which can significantly improve the overall expected value of cache hits.

[0089] Finally, for cases where predictions fail, this disclosure designs a comprehensive learning and updating mechanism. In another embodiment, if the processor 211 determines that the target data requested by the host does not exist in the buffer memory (i.e., prediction fails), the system first performs conventional remedial measures, namely, directly reading the target data from the memory module according to the target read instruction and transmitting it to the host system to ensure the continuity of data services. Simultaneously, the independent logic module 215 performs a model update operation in the background: it concatenates the target logical address and target data length of the target read instruction that caused the current miss with the address information of several adjacent read instructions to form a new access sequence. Subsequently, the system checks the hash map table: if a record matching the new access sequence already exists in the table, it indicates a known but low-weight pattern, and the system increases the weight value of this historical access sequence to make it easier to trigger in the future; if the sequence does not exist in the table, it is recorded as a completely new behavior pattern in the hash map table. Through this "failure-to-learn" mechanism, the memory controller can continuously enrich its behavioral knowledge base, gradually covering various uncommon or newly emerging read patterns.

[0090] It is worth noting that as the system runs, the historical access sequences accumulated in the hash map table (HMT) may continuously increase, thus consuming a large amount of storage resources. To ensure the long-term stable operation of the system, this disclosure also provides an intelligent maintenance and aging mechanism. In another embodiment, the independent logic module 215 monitors the storage space occupancy rate of the hash map table in real time. When the occupancy rate exceeds a preset threshold (e.g., 80%), the system automatically triggers a cleanup procedure. At this time, the independent logic module 215 evaluates the historical access sequences based on their access timestamps or access frequencies, identifies those historical access sequences with the oldest access timestamps (i.e., the longest unused) or the lowest access frequency (i.e., the least frequent), and removes them from the hash map table. This "survival of the fittest" mechanism ensures that limited storage space is always used to retain the most predictable behavioral patterns, thereby maintaining the efficient operation of the system.

[0091] In order to achieve efficient lookup and storage with limited hardware resources, this disclosure optimizes the internal management structure of the hash mapping table and the buffer memory.

[0092] Specifically, in one embodiment, the independent logic module 215 uses a hash algorithm based on the first logical address to construct a hash mapping table. Specifically, the system extracts the starting logical address (Start LBA) of the first read instruction in the historical access sequence and performs a modulo operation or an XOR operation on it to generate a hash index value. For potential hash collisions (i.e., different LBAs generating the same index value), the system uses chaining, maintaining a linked list in the hash bucket to link the nodes of the colliding access sequences sequentially. In terms of storage format, each entry is designed as a compact bit-field structure, containing a "sequence signature (4 bytes)," a "predicted target pointer (2 bytes)," a "timestamp (4 bytes)," and a "weight (1 byte)," thus storing thousands of high-frequency access patterns with minimal SRAM space (e.g., only a few hundred KB).

[0093] It is worth noting that although the foregoing embodiments use a "hash map table" as the main data structure for storing historical access sequences and performing matching, this is only a preferred implementation of this disclosure, and not the only limitation on the technical solution. Those skilled in the art should understand that any data structure capable of establishing a mapping relationship between "historical behavior patterns" and "prediction targets" can be applied to the independent logic module 215 of this disclosure to achieve the same technical spirit.

[0094] It should be noted that this disclosure establishes a hierarchical indexing and status marking mechanism for the management of prefetched data in buffer memory 214. Buffer memory 214 maintains a "prefetched data index table", which establishes a mapping relationship between logical addresses and physical cache addresses. More importantly, the index table is configured with status bits for each cache page. The status bits include at least: "prefetch protected state (01)", indicating that the data has just been prefetched and has not yet been read by the host, and enjoys the privilege of exemption from being evicted; "normal cache state (10)", indicating that the data has been read by the host and has been switched to normal LRU management; and "invalid state (00)", indicating that the data has expired or has been written overwritten. In terms of space allocation strategy, the system can adopt a dynamic sharing mechanism to set an upper limit threshold for the total capacity of the buffer memory occupied by prefetched data (e.g., a maximum of 40%), to ensure that prefetching operations do not crowd out normal read and write cache space.

[0095] Figure 5 This is a timing diagram of a memory management method according to an embodiment of the present disclosure.

[0096] Please refer to Figure 5 , Figure 5 The interaction flow between the host system 10, processor 211, independent logic module 215, memory module 220 and buffer memory 214 is shown. The whole process can be divided into three main stages.

[0097] In Phase 1, "Behavior Analysis and Policy Generation," the host system 10 first sends a read instruction stream to the processor 211 (step S510), which contains multiple logical addresses. Upon receiving the instructions, the processor 211 does not perform complex analysis directly, but instead transmits this logical address information to the independent logic module 215 (step S511). The independent logic module 215 then performs distribution feature analysis on these addresses, identifies the current read pattern, and generates a pre-read strategy accordingly, while determining the specific pre-read data (step S512). After generating the strategy, the independent logic module 215 feeds back the pre-read strategy to the processor 211 (step S512), and may selectively send instructions to the buffer memory 214 to pre-protect the data space to be pre-read (step S513) to prevent it from being occupied by other processes.

[0098] Entering Phase Two, "Pre-reading using idle time," the processor 211 begins monitoring the system status. When it detects that the interface transmission or memory module 220 is in an idle state (step S520), the processor 211 initiates a pre-read operation to the memory module 220 according to the received pre-read strategy (step S521). The memory module 220 responds to the instruction and transmits the pre-read data to the buffer memory 214 (step S522).

[0099] Regarding "prefetching during idle time," more specifically, in one embodiment, the processor 211 monitors the interface transmission status and the operating status of the memory module 220 before performing the prefetch operation. In embodiments using the NVMe protocol, the interface is determined to be idle when neither the submission queue nor the completion queue has any pending items. In embodiments using the SATA protocol, the interface is determined to be idle when the instruction queue is empty and the data transmission line is not occupied.

[0100] Regarding the operating status of memory module 220, memory interface control circuit 213 reads the ready / busy bits in the status registers of each NAND flash memory chip. When all chips indicate ready, memory module 220 is determined to be in a non-busy state. In another embodiment, prefetching can be performed using at least one chip as long as it is ready.

[0101] Processor 211 performs prefetch operations using the command interval between adjacent read commands sent by host system 10. For example, if the command interval is 500 microseconds and reading a single 4KB data page takes approximately 50 microseconds, then approximately 10 data pages can be prefetched within this interval. Furthermore, when processor 211 transmits data to host system 10, it can also simultaneously prefetch data from memory module 220 to another area of ​​buffer memory 214, achieving parallel operation.

[0102] Once the data writing is complete, the buffer memory 214 sends an acknowledgment signal to the processor 211 (step S523), marking the completion of the pre-read process. This stage makes full use of the system's idle resources, achieving "seamless" data transfer.

[0103] Finally, there is stage three, "Target Instruction Response and Status Update." When the host system 10 sends a target read instruction requesting target data (step S530), the processor 211 first queries the buffer memory 214 (step S531). If the judgment result is "Prediction Hit," the buffer memory 214 confirms the existence of target data, and the processor 211 immediately transmits the data directly to the host system 10, achieving zero-wait response (step S532). At the same time, the processor 211 notifies the independent logic module 215 of the successful prediction (step S533), and the independent logic module 215 then updates the status of the data in the buffer memory 214, such as removing protection or increasing its weight (step S534). Conversely, if the judgment result is "Prediction Miss," the buffer memory 214 confirms that the target data does not exist, and the processor 211 must read the data from the memory module 220 and transmit it back to the host (step S535). Subsequently, the processor 211 notifies the independent logic module 215 of the prediction failure (step S536), and the independent logic module 215 adjusts its strategy accordingly, such as recording the number of misses or updating the prediction model (e.g., reducing the weight value of the corresponding historical access sequence, etc.) (step S537) to optimize the prediction accuracy of the next time.

[0104] It is worth mentioning that, in order to further improve the accuracy and adaptability of the prediction model, this disclosure also establishes a dynamic adjustment mechanism based on "prediction result feedback". This mechanism performs positive reinforcement or negative correction processes depending on whether the target data is hit in the buffer memory 214.

[0105] Specifically, when processor 211 determines that the target data exists in buffer memory 214 (i.e., a prediction hit), in addition to immediately transmitting the data to host system 10 to achieve zero-wait response, independent logic module 215 also simultaneously performs state update and model reinforcement operations. First, for the target data in buffer memory 214, the system changes its state from "read-ahead protection" to "normal cache" or adds it to the regular Least Recently Used (LRU) management queue. This means that the data has fulfilled its "instant response" mission, allowing it to be naturally evicted when subsequent cache space is insufficient, thereby freeing up valuable cache resources. Second, for the target historical access sequence for which the data was successfully predicted, independent logic module 215 increases its weight value in the hash map table and updates its access timestamp to the current time. This positive reinforcement mechanism ensures that sequences that truly match the user's current behavior patterns will have higher priority and retention rates in the future.

[0106] Conversely, when processor 211 determines that the target data does not exist in buffer memory 214 (i.e., prediction miss), the system first performs a remedial measure, that is, processor 211 directly reads the target data from memory module 220 and transmits it to the host to ensure the continuity of data access. Subsequently, independent logic module 215 performs model correction operations. On the one hand, if the miss is due to a previous incorrect prefetch strategy (for example, the system predicted data X based on sequence A, but the host actually read data Y), the system will reduce the weight value of the historical access sequence (sequence A) that was misjudged to suppress the recurrence of incorrect predictions. On the other hand, the system will combine the actual read behavior (i.e., the logical address and data length of the target read instruction) with the preceding instruction to form a new access sequence. If the actual sequence already exists in the hash map, its weight value is increased; if it does not exist, it is added as a new entry. This "failure-to-learn" mechanism allows the memory controller to continuously correct deviations and gradually cover various newly emerging read patterns.

[0107] In one embodiment, in a real-world random read scenario, the distribution characteristics of the read instruction stream may exhibit ambiguity, meaning the current address sequence may simultaneously match multiple records in the hash map table. For example, when host system 10 consecutively reads logical addresses A and B, the hash map table may simultaneously contain two historical access sequences: "Sequence 1: ABC" and "Sequence 2: ABD". In this case, the independent logic module 215 does not select randomly, but instead executes a weighted optimization decision mechanism. The system reads the weight values ​​recorded in the table for these two candidate sequences (the weight values ​​are calculated by combining historical access frequency and time matching degree). Assuming the weight value of sequence 1 is 0.9 and the weight value of sequence 2 is 0.4, the independent logic module 215 will determine that sequence 1 has higher credibility, thus prioritizing sequence 1 with the higher weight value as the target historical access sequence, and predicting the subsequent access to logical address C accordingly. This mechanism effectively solves the pattern conflict problem, ensuring that the system always tends to execute the pre-read operation with the highest probability.

[0108] Besides the accuracy of the prediction, the appropriateness of the "amount" of prefetched data is also crucial to system efficiency. Therefore, this disclosure introduces a dynamic window optimization mechanism based on data utilization. In another embodiment, after the processor 211 transfers the target data from the buffer memory 214 to the host system 10, the independent logic module 215 initiates a post-evaluation process to calculate the actual data utilization of this batch of prefetched data in the buffer memory 214. If the calculation result shows that the data utilization is lower than a low utilization threshold (e.g., 128KB of data was prefetched, but the host only read 4KB before stopping), the system determines that the current prefetch strategy is too aggressive, resulting in a waste of bandwidth and cache space. In response, the system will automatically reduce the length of the prefetched data (e.g., halve it) when generating the next prefetch strategy. Conversely, if the data utilization is higher than a high utilization threshold (e.g., 95%), and the host system 10 continues to request data following the prefetched data after reading this data, the system determines that the current prefetch amount is insufficient to cover the host's needs. In this case, the system will appropriately increase the length of the prefetched data when generating the next prefetch strategy. Through this dynamic adjustment, the system can adaptively find the optimal balance between pre-read benefits and resource consumption.

[0109] To ensure data consistency and security, this disclosure also includes a cache management mechanism specifically designed for write operations. In one embodiment, during the operation of the memory controller 210, an independent logic module 215 (or in conjunction with the processor 211) monitors write commands from the host system 10 in real time. When a new write command is received, the system immediately performs an address conflict detection to determine whether the write logic address targeted by the write command overlaps with the address of the pre-read data currently stored in the buffer memory 214. Once an address overlap is detected, it means that the data the host is trying to modify is exactly the old data that the system has just pre-read. To prevent the host from reading outdated or incorrect data, the independent logic module 215 immediately takes action to mark the corresponding pre-read data in the buffer memory 214 as invalid or discard it directly. This "write invalidation" mechanism ensures that regardless of how the pre-read strategy is executed, the data obtained by the host system 10 is always up-to-date, thereby guaranteeing the integrity of the file system.

[0110] To illustrate with a specific example: Assume that the pre-read data area stores pre-read data blocks P1 (corresponding to LBA_1000 to LBA_1003). The host system 10 sends a write command to overwrite LBA_1002 to LBA_1003. The independent logic module 215 detects address overlap and determines that a conflict has occurred. After detecting the conflict, the independent logic module 215 can adopt two processing methods. The "mark as invalid" method only updates the status of the data block to invalid, and prioritizes its removal during subsequent eviction operations. This method has low operation latency. The "discard" method immediately removes the data block from the index table and releases the storage space. This method is suitable for scenarios where buffer memory space is tight. In another embodiment, the independent logic module 215 can dynamically select based on the space occupancy rate: "mark as invalid" when it is below a threshold, and "discard" when it is above a threshold.

[0111] In one embodiment, the buffer memory 214 is divided into a prefetch data area and a normal cache area, the space ratio of which can be configured (e.g., 30% and 70%), and can also be dynamically adjusted according to the prefetch hit rate.

[0112] Independent logical module 215 establishes a read-ahead data index table to manage the data in the read-ahead data area. This index table records the logical address, data length, storage location, status flag, and associated sequence identifier for each read-ahead data block. The status flag includes four status values: read-ahead protected status indicates that the data has just been read and has not yet been accessed, and is given priority exemption in the eviction process; valid status indicates that the data has been accessed and is included in the regular least recently used management; pending eviction status indicates that the data has been identified as an eviction candidate; and invalid status indicates that the logical address corresponding to the data has been written to, and the content is outdated.

[0113] When the target data is hit, the processor 211 locates the data according to the storage location field in the index table and transmits it to the host system 10. At the same time, the independent logic module 215 updates the status flag and the most recent access timestamp, and adds the weight value of the corresponding historical access sequence to the hash mapping table according to the associated sequence identifier.

[0114] The following uses Figure 6 , Figure 7 Let's explain the details of the triggering conditions for the first and second pre-read strategies.

[0115] Figure 6 This is a flowchart illustrating the first pre-read strategy triggering a judgment according to an embodiment of the present disclosure.

[0116] Please refer to Figure 6 In order to accurately identify the sequential reading behavior of large files and avoid misjudgment due to accidental address contiguousness, the independent logic module 215 executes a threshold judgment mechanism.

[0117] First, in steps S610 and S620, the independent logic module 215 continuously obtains multiple logical addresses from the read instruction stream and calculates in real time whether the continuously received logical addresses show an increasing trend. Specifically, the judgment logic is as follows: check whether the starting logical address of the current read instruction is exactly equal to the starting logical address of the previous read instruction plus the data length of the previous read instruction. If this condition is met, it is determined that the two are contiguous in physical or logical storage space.

[0118] However, two consecutive instructions are insufficient to establish a "sequential read mode," as file system metadata reads or defragmentation operations can also generate brief consecutive addresses. Therefore, the process proceeds to step S630, where a critical threshold filtering is performed. In this step, the independent logic module 215 maintains a consecutive counter to determine if the number of consecutive increments reaches a preset threshold (e.g., set to 4 consecutive times). If the result is "no," the system resets the counter and returns to step S610 to continue monitoring without triggering a pre-read action. Only when the result is "yes," meaning the cumulative number of consecutively incrementing instructions reaches the preset threshold, does the system confirm that the host system 10 has indeed entered a stable sequential read state.

[0119] Once the preset threshold is reached, the process proceeds to step S640, where the independent logic module 215 formally generates the first pre-read strategy (continuous mode). Subsequently, in step S650, the system performs a simplified arithmetic prediction: based on the last logical address among multiple consecutively received logical addresses and its corresponding data length, the pre-read start logical address is calculated (i.e., pre-read start address = last address + data length), and the pre-read data length is determined according to the current state of the buffer memory 214. This threshold-triggered mechanism ensures efficient response to large file reading (such as video playback) while effectively filtering noise interference from random operations, avoiding unnecessary bandwidth waste.

[0120] Figure 7 This is a flowchart illustrating the second pre-read strategy triggering a judgment according to an embodiment of the present disclosure.

[0121] Please refer to Figure 7 When the independent logic module 215 identifies in step S710 that the distribution pattern of the read instruction stream is a non-continuous discrete distribution, the system determines that it is currently in random read mode and starts the prediction process based on historical behavior.

[0122] To improve retrieval efficiency and prediction accuracy in large-scale historical data, this embodiment introduces a time-based priority filtering mechanism. In step S720, the independent logic module 215 first extracts the current access sequence, which includes multiple currently received logical addresses and their corresponding data lengths. Simultaneously, the system obtains the current system time. Next, in step S730, the independent logic module 215 does not immediately perform a full search of all records in the hash map table. Instead, based on the current system time, it first filters candidate historical access sequences from the hash map table that match the access timestamps of the current time. For example, if it is currently a weekday morning, the system will prioritize locking startup sequences that frequently occurred during past morning periods.

[0123] More specifically, in the embodiments of this disclosure, the operation of "filtering out candidate historical access sequences whose access timestamps match the current system time" performed by the independent logic module 215 in step S730 can be implemented based on a variety of different time matching logics to adapt to different user behavior patterns.

[0124] The following are some specific matching patterns:

[0125] 1. Time Difference Matching: In one embodiment, independent logic module 215 calculates the absolute time difference between the current system time and the access timestamps of each historical access sequence in the hash map. The system presets a time tolerance threshold (e.g., set to 30 minutes or 1 hour). If the calculated time difference is less than or equal to the time tolerance threshold, the two are considered to match.

[0126] For example, suppose the current system time is 9:00 AM, while the timestamp of historical sequence A in the hash map is 8:45 AM (a difference of 15 minutes), and the timestamp of historical sequence B is 10:30 AM (a difference of 90 minutes). Under this setting, the system will determine that sequence A matches, while sequence B does not. This method is suitable for capturing regular user actions performed at roughly the same time each day (such as opening the email client after arriving at work).

[0127] 2. Fixed Time Slot Attribution: In another embodiment, the independent logic module 215 divides a day into several predefined fixed time slots, such as: morning slot (06:00-09:00), work slot (09:00-18:00), evening entertainment slot (18:00-24:00), and late night slot (00:00-06:00). The system determines whether the current system time and the historical access timestamp fall into the same predefined time slot ID.

[0128] For example, if the current time is 2:00 PM (which falls within working hours), the system will filter out all historical sequences with timestamps also marked as "working hours," while ignoring sequences marked as "evening entertainment hours." This approach blurs the specific time points and focuses more on capturing the user's macro-level behavioral patterns in specific life scenarios.

[0129] 3. Calendar Cycle Matching: In another embodiment, the time matching logic also incorporates date attributes, specifically distinguishing between "weekdays" and "weekends / holidays." A separate logic module 215 checks the attributes of the current date. For example, if it is currently Saturday (weekend), the system prioritizes historical access sequences recorded on Saturdays or Sundays, while filtering out sequences that only appeared from Monday to Friday (weekdays). This helps differentiate between users' different reading needs—using office software on weekdays and running large games on weekends—and avoids incorrectly applying weekday pre-reading strategies to weekend scenarios.

[0130] 4. Relative Uptime Matching: In another embodiment, the so-called "system time" does not refer to the wall-clock time, but rather to the "system uptime" of the host system since this startup.

[0131] For example, the system focuses on the time window of "within 5 minutes after power-on". Regardless of whether the user powers on at 8:00 AM or 2:00 PM, as long as the user is in the initial stage after power-on, the system will filter out all historical access sequences marked as "startup stage" (such as operating system loading, startup program loading). This matching method is particularly accurate for predicting fixed read behaviors related to system initialization.

[0132] After obtaining the candidate historical access sequences selected based on time, in step S740, the independent logic module 215 determines whether the current access sequence matches the aforementioned candidate historical access sequences filtered by time, based on the distribution pattern of the current read instruction stream. If the determination result is "yes," it means that the current behavior not only matches in address pattern but also conforms to historical patterns in occurrence time, possessing extremely high prediction confidence. At this point, the process proceeds to step S750, where the system generates a second pre-read strategy, directly predicting subsequent associated logical addresses based on the matched historical access sequence and initiating pre-reading. This mechanism ensures the most accurate acceleration experience at specific time points (such as daily routine tasks).

[0133] However, user behavior is not always static. If the result of step S740 is "no," meaning no matching sequence was found within the current time period, the system will not immediately give up. The process will proceed to step S760, executing a fallback general matching query. In this step, the independent logic module 215 expands the search scope, determining whether the current access sequence matches other historical access sequences in the hash map table (i.e., ignoring timestamp restrictions, searching for records with consistent patterns despite different times). If a match is found in step S760 (for example, the user opened a frequently used software at an infrequently used time), the system can still generate a second pre-read strategy, but it may be assigned a lower priority weight.

[0134] Finally, if the judgment result of step S760 is also "no", it indicates that the currently captured read behavior is a completely new one that the system has never learned before. At this time, proceed to step S770, where the independent logic module 215 records the current access sequence as a new behavior pattern in the hash mapping table and records the current access timestamp. Through this hierarchical matching and recording mechanism, the memory controller 210 can continuously expand its behavior knowledge base, achieving continuous learning and adaptation to user habits.

[0135] The following uses Figure 8 To explain in detail the matching mechanism of the access sequence disclosed herein.

[0136] Figure 8 This is a flowchart illustrating the historical access sequence matching determination according to embodiments of the present disclosure.

[0137] Please refer to Figure 8 The process of determining whether the current access sequence matches the candidate historical access sequence in the aforementioned step S740 involves comparing multiple read instruction nodes within the sequence one by one.

[0138] First, in step S810, the independent logic module 215 acquires multiple logical addresses and corresponding data lengths (i.e., the current access sequence) from the read instruction stream, as well as candidate historical access sequences filtered by time or other conditions. Next, it proceeds to the cyclic comparison phase in steps S820 and S830. Based on the logical address and data length of each read instruction in the current access sequence, the independent logic module 215 sequentially compares the corresponding historical logical addresses and historical data lengths in the candidate historical access sequences that have not yet been compared. During this process, the system rigorously determines whether the current logical address is completely consistent with the logical address in the historical record, and whether the data length requested this time is equal to the data length in the historical record. This double verification ensures the rigor of the prediction and avoids misjudgments caused by coincidental addresses but different read granularities.

[0139] If the judgment result of step S830 is yes, meaning the two are completely consistent, the process proceeds to step S840. Independent logic module 215 increments the matching count and points the comparison pointer to the next set of historical logical addresses in the candidate historical access sequence, preparing for the next round of comparison. Subsequently, in step S850, the system determines whether the current matching count has reached a preset matching depth threshold (e.g., set to match 3 consecutive nodes). If the judgment result is no, it means that although the current node matches, a sufficiently reliable sequence pattern has not yet been formed. Therefore, the process returns to step S820 to continue comparing the next set of unmatched instruction nodes in the sequence.

[0140] Only when the number of consecutively matched nodes reaches the matching depth threshold will the judgment result of step S850 be "yes," and the process will proceed to step S860, determining that the match is successful and identifying the candidate historical access sequence as the target historical access sequence, thereby generating the second pre-read strategy. Conversely, if the judgment result of step S830 is "no" (i.e., an inconsistency is found) at any stage of the cyclic comparison, the process will directly jump to step S870, determining that the candidate historical access sequence has failed to match, and the system will abandon the sequence and attempt to compare the next candidate sequence in the hash mapping table.

[0141] To understand more intuitively Figure 8 The multi-node deep verification mechanism is illustrated below with a specific example. Assume that the independent logic module 215 sets the "matching depth threshold" to 3, meaning that three consecutive matching instruction nodes are required for a valid prediction.

[0142] Currently, host system 10 is launching a large image processing software, and the "current access sequence" captured by processor 211 contains three read instructions in sequence:

[0143] 1. Instruction A: Logical address LBA_1000, data length 4KB;

[0144] 2. Instruction B: Logical address LBA_5000, data length 8KB;

[0145] 3. Instruction C: Logical address LBA_8080, data length 4KB.

[0146] At the same time, the independent logic module 215 selects a "candidate historical access sequence" from the hash map table. The nodes recorded in this sequence are as follows:

[0147] 1. Historical Node 1: Historical logical address LBA_1000, historical data length 4KB;

[0148] 2. Historical Node 2: Historical logical address LBA_5000, historical data length 8KB;

[0149] 3. Historical Node 3: Historical logical address LBA_8080, historical data length 4KB;

[0150] 4. Historical Node 4 (Prediction Target): Historical logical address LBA_9000, historical data length 16KB.

[0151] In execution Figure 8 During the process, the independent logic module 215 first compares the first group of nodes (instruction A and historical node 1) in step S820. Since LBA_1000 equals LBA_1000 and 4KB equals 4KB, a match is determined in step S830, and the matching count is incremented to 1. At this point, the threshold 3 has not been reached, and the process returns.

[0152] Next, the system compares the second set of nodes (instruction B with historical node 2). Since LBA_5000 equals LBA_5000 and 8KB equals 8KB, they are considered to be a match, and the match count is incremented to 2. At this point, the threshold of 3 has not yet been reached, and the process returns again.

[0153] Finally, the system compares the third group of nodes (instruction C with historical node 3). Since LBA_8080 equals LBA_8080 and 4KB equals 4KB, they are determined to be a match, and the match count is incremented to 3.

[0154] At this point, in step S850, the system determines that the matching count has reached the preset matching depth threshold (3), and therefore proceeds to step S860, determining that the matching is successful. The independent logic module 215 then locks the candidate historical access sequence as the target historical access sequence, and generates a pre-read strategy based on its subsequent "historical node 4" to read the data of LBA_9000 in advance.

[0155] Conversely, if in any of the above steps, for example, the data length of instruction B is 16KB while that of historical node 2 is 8KB, the system will immediately determine the inconsistency in step S830 and terminate the comparison of the sequence, thereby avoiding incorrect predictions.

[0156] Simply put, Figure 8 The core technology of the matching process described lies in the introduction of a "multi-node deep verification mechanism." This disclosure does not rely solely on occasional overlaps of single logical addresses for hasty predictions. Instead, it requires that the current access sequence continuously match historical records in both logical address and data length dimensions, and that the matching length reaches a depth threshold sufficient to establish statistical significance. This verification logic effectively filters out interference from random noise, avoiding erroneous pre-reads caused by "false positive" matches. Thus, while ensuring prediction accuracy, it minimizes the pollution and bandwidth waste caused by invalid data to the buffer memory.

[0157] It is worth mentioning that, in another embodiment of this disclosure, the “matching depth threshold” in step S850 is not a fixed value, but a variable that is dynamically adjusted by the independent logic module 215 according to the attributes of the current historical access sequence or the system state.

[0158] Specifically, the independent logic module 215 is configured to perform a threshold dynamic adjustment operation. This operation determines the current matching depth threshold based on at least one of the following parameters:

[0159] 1. Weight Values ​​of Candidate Historical Access Sequences: The system follows the principle of "high confidence, low threshold." If the weight value (or access frequency) recorded in the hash map table for the currently compared candidate historical access sequence exceeds a high weight threshold, it indicates that the sequence is a stable pattern that occurs very frequently. In this case, the independent logic module 215 can reduce the matching depth threshold (e.g., from the default 3 to 2) to trigger pre-reading earlier and maximize the time advantage. Conversely, if the weight value of the candidate sequence is low, it indicates that it may be an occasional or unstable pattern, and the system increases the matching depth threshold (e.g., to 4) to prevent false positives through more rigorous comparison.

[0160] 2. Remaining Space in the Buffer Memory: The system adheres to the principle of "strict control over resource scarcity." An independent logic module 215 monitors the remaining space in the buffer memory 214 in real time. When there is sufficient remaining space, the system can maintain a lower default threshold and adopt a more aggressive pre-read strategy. When the remaining space is insufficient (e.g., below 20%), to prevent low-value pre-read data from crowding out valuable buffer space, the system automatically increases the matching depth threshold, allowing only sequences that have undergone depth verification to trigger pre-reads.

[0161] 3. Recent Pre-read Hit Rate: The system follows the principle of "error feedback suppression." Independent logic module 215 will calculate the recent pre-read hit rate. If a recent decrease in the hit rate is found, it indicates that simple matching in the current environment is prone to errors. The system will then globally increase the matching depth threshold to improve the rigor of the prediction.

[0162] The following example illustrates weight-based dynamic threshold adjustment. Assume the system's default matching depth threshold is 3.

[0163] Scenario 1: Independent logic module 215 is comparing a "boot sequence" with a weight value as high as 0.95. Because this sequence is extremely stable, the system dynamically adjusts its matching depth threshold to 2. When the current access sequence consecutively matches the first two nodes of this historical sequence, the system determines a successful match and initiates pre-reading. This allows the pre-reading operation to be performed one instruction cycle earlier than the default setting, providing the host with more time to prepare data.

[0164] Scenario 2: Independent logic module 215 is comparing an "occasional sequence" with a weight value of only 0.2. The system dynamically adjusts its matching depth threshold to 4. Even if the current access sequence matches the first 3 nodes consecutively, the system does not trigger a pre-read until the 4th node also matches successfully. This conservative strategy effectively avoids erroneous pre-reads caused by accidental overlap of the first 3 nodes.

[0165] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0166] Based on the above, the memory management method and memory controller provided in this disclosure, by introducing an independent logic module separate from the processor to analyze the distribution characteristics of the read instruction stream in real time, can effectively solve the read speed bottleneck problem of traditional solid-state drives under hardware performance limitations. Specifically, this disclosure utilizes an independent logic module to perform feature extraction and strategy generation in parallel in the background, combined with pre-read operations performed during system idle time, to realize the pre-moving of data from low-speed memory modules to high-speed cache memory, thereby providing a near-zero wait response speed when the host system actually initiates a read request. In addition, by distinguishing between continuous read mode and random read mode, and combining hash mapping tables, time weighting mechanisms, and multi-node deep verification logic, this disclosure can accurately predict user behavior in various complex scenarios, effectively improving the accuracy of pre-read hits. At the same time, with the addition of dynamic window adjustment and write invalidation mechanisms based on data utilization, this disclosure improves read performance while also taking into account the utilization efficiency of cache resources and data consistency and security, providing users with a smoother and more reliable data access experience.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method applied to a memory controller, the memory controller being used to manage a storage device configured with memory modules and buffer memory, characterized in that, The method includes: Acquire a read instruction stream, wherein the read instruction stream contains multiple logical addresses; Analyze the distribution characteristics of the multiple logical addresses, and generate a pre-read strategy based on the distribution characteristics; According to the pre-read strategy, pre-read data is read from the memory module and stored in the buffer memory; Receive target read command; If the target data corresponding to the target read instruction exists in the buffer memory, the target data is transferred from the buffer memory to the host system in response to the target read instruction.

2. The method according to claim 1, characterized in that, The memory controller also includes an independent logic module that operates independently of the memory controller's processor. The independent logic module is used to analyze the distribution characteristics of the multiple logical addresses in the read instruction stream and generate the pre-read strategy based on the distribution characteristics.

3. The method according to claim 1, characterized in that, The step of reading the pre-read data from the memory module according to the pre-read strategy includes: Monitor the interface transmission status between the storage device and the host system, as well as the operational status of the memory module; and If the interface transmission state is idle, and / or the memory module is in a non-busy state, the operation of reading the pre-read data is performed.

4. The method according to claim 1, characterized in that, The method further includes: A hash mapping table is established to record multiple historical access sequences, wherein each historical access sequence contains an arrangement of multiple historical logical addresses and corresponding multiple data lengths.

5. The method according to claim 4, characterized in that, The step of analyzing the distribution characteristics of the multiple logical addresses in the read instruction stream and generating the pre-read strategy based on the distribution characteristics includes: Determine whether the multiple logical addresses received consecutively in the read instruction stream show an increasing trend, and whether the difference between adjacent multiple logical addresses is equal to the data length of the previous read instruction; If the judgment result is yes, then the first pre-read strategy is generated. The first pre-read strategy includes: obtaining the pre-read logical address and pre-read data length of the pre-read data based on the data length of the corresponding multiple read instructions and the last logical address among the multiple logical addresses received consecutively; If the judgment result is negative, a second pre-read strategy is generated; The second pre-read strategy includes: matching the plurality of logical addresses and corresponding data lengths in the read instruction stream with the plurality of historical access sequences recorded in the hash map table; and If the plurality of logical addresses and their corresponding data lengths match a portion of the target historical access sequence among the plurality of historical access sequences, then the subsequent associated logical addresses and associated data lengths are predicted based on the target historical access sequence.

6. The method according to claim 5, characterized in that, The step of establishing the hash mapping table further includes recording the corresponding access timestamps for the multiple historical access sequences; wherein the second pre-read strategy further includes: Get the current system time; Based on the current system time, multiple candidate historical access sequences whose access timestamps match the current system time are selected from the hash mapping table; and The multiple logical addresses and corresponding data lengths in the read instruction stream are matched with the multiple candidate historical access sequences to determine the target historical access sequence.

7. The method according to claim 6, characterized in that, The method further includes: After transmitting the target data to the host system, the data utilization rate of the pre-read data in the buffer memory is calculated; If the data utilization rate is lower than the low utilization threshold, then the weight value of the target historical access sequence associated with the current system time is reduced; and If the data utilization rate is higher than the high utilization threshold, then the weight value of the target historical access sequence associated with the current system time is increased.

8. The method according to claim 5, characterized in that, The hash map table is also used to record the access frequency of each historical access sequence, wherein the second pre-read strategy further includes: Prioritize the subsequent data corresponding to the historical access sequence whose pre-read access frequency exceeds a preset frequency threshold.

9. The method according to claim 5, characterized in that, The method further includes: If the target data does not exist in the buffer memory, the target data is read directly from the memory module according to the target read instruction and transmitted to the host system; The target logical address and target data length of the target read instruction are combined with the multiple logical addresses and corresponding data lengths of the preceding multiple read instructions to form a new access sequence; and The new access sequence is recorded in the hash map table, or if a historical access sequence that matches the new access sequence already exists in the hash map table, the weight value of the historical access sequence is increased.

10. The method according to claim 1, characterized in that, The method further includes: After transmitting the target data to the host system, the data utilization rate of the pre-read data in the buffer memory is calculated; If the data utilization rate is lower than the low utilization threshold, it is determined that the pre-read data is wasted, and the length of the pre-read data is reduced when the pre-read strategy is generated next time; and If the data utilization rate is higher than the high utilization threshold and the host system continues to request data following the pre-read data, then the pre-read data is determined to be insufficient, and the pre-read data length is increased when the pre-read strategy is generated next time.

11. The method according to claim 1, characterized in that, The method further includes: Real-time monitoring of write commands from the host system; When the write instruction is received, it is determined whether the write logical address targeted by the write instruction overlaps with the address of the pre-read data stored in the buffer memory; and If an overlap occurs, the corresponding pre-read data in the buffer memory is immediately marked as invalid or discarded to ensure data consistency.

12. The method according to claim 1, characterized in that, The method further includes: When the remaining space in the buffer memory is insufficient, a cache eviction operation is performed, the cache eviction operation including: Candidate eviction data are identified from the buffer memory based on the least recently used rule; Determine whether the candidate discarded data belongs to the data that the pre-read strategy predicts will be accessed soon; and If the determination result is yes, then the candidate eviction data is exempted, and another candidate eviction data is identified from the buffer memory to perform the cache eviction operation.

13. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: Buffer memory; A memory interface control circuit is electrically connected to the memory module; Data management circuitry, used for electrical connection to the host system; Independent logic modules; and The processor is electrically connected to the memory interface control circuit, the buffer memory, the data management circuit, and the independent logic module. The processor is configured to acquire a read instruction stream from the host system via the data management circuitry, wherein the read instruction stream contains a plurality of logical addresses; The independent logic module is configured to analyze the distribution characteristics of the multiple logical addresses in the read instruction stream and generate a pre-read strategy based on the distribution characteristics. The processor is further configured to read prefetch data from the memory module via the memory interface control circuit according to the prefetch strategy, and store the prefetch data in the buffer memory; The independent logic module is also configured to manage the retention and eviction of all pre-read data in the buffer memory; The processor is further configured to, upon receiving a target read instruction from the host system, determine whether target data corresponding to the target read instruction exists in the buffer memory; and The processor is further configured to, if the target data exists in the buffer memory, transfer the target data from the buffer memory to the host system via the data management circuit in response to the target read instruction.

14. The memory controller according to claim 13, characterized in that, When reading the pre-read data according to the pre-read strategy, the processor is configured to: Monitor the interface transmission status between the storage device and the host system, as well as the operating status of the memory module; as well as The operation of reading the pre-read data is performed only when the interface transmission state is detected to be idle and / or the memory module is in a non-busy state.

15. The memory controller according to claim 13, characterized in that, When analyzing the distribution characteristics and generating the pre-read strategy, the independent logic module is configured to: Determine whether the multiple logical addresses received consecutively in the read instruction stream show an increasing trend, and whether the difference between adjacent multiple logical addresses is equal to the data length of the previous read instruction; If the determination result is yes, a first pre-read strategy is generated, wherein the first pre-read strategy includes obtaining the pre-read logical address and the pre-read data length based on the data length of the corresponding multiple read instructions and the last logical address among the multiple logical addresses received consecutively.

16. The memory controller according to claim 15, characterized in that, The independent logic module is also configured to establish and maintain a hash mapping table to record multiple historical access sequences; If the judgment result is negative, the independent logic module generates a second pre-read strategy, the second pre-read strategy including: Match the plurality of logical addresses and corresponding data lengths in the read instruction stream with the plurality of historical access sequences recorded in the hash map table; and If the plurality of logical addresses and their corresponding data lengths match a portion of the target historical access sequence among the plurality of historical access sequences, then the subsequent associated logical addresses and associated data lengths are predicted based on the target historical access sequence.

17. The memory controller according to claim 16, characterized in that, The hash mapping table also records the access timestamps corresponding to the multiple historical access sequences; The independent logic module, when generating the second pre-read strategy, is further configured to: Get the current system time; Based on the current system time, multiple candidate historical access sequences whose access timestamps match the current system time are selected from the hash mapping table; and The multiple logical addresses and corresponding data lengths in the read instruction stream are matched with the multiple candidate historical access sequences to determine the target historical access sequence.

18. The memory controller according to claim 17, characterized in that, The independent logic module is also configured to: After the processor transmits the target data to the host system, it calculates the data utilization rate of the pre-read data in the buffer memory; as well as If the data utilization rate is lower than the low utilization threshold, reduce the weight value of the target historical access sequence associated with the current system time; or If the data utilization rate is higher than the high utilization threshold, increase the weight value of the target historical access sequence associated with the current system time.

19. The memory controller according to claim 13, characterized in that, The independent logic module is also configured to: Real-time monitoring of write commands from the host system; When the write instruction is received, it is determined whether the write logical address targeted by the write instruction overlaps with the address of the pre-read data stored in the buffer memory; as well as If an overlap occurs, the corresponding pre-read data in the buffer memory is immediately marked as invalid or discarded to ensure data consistency.

20. The memory controller according to claim 13, characterized in that, The independent logic module is configured to: manage the eviction of the pre-read data in the buffer memory. When the remaining space in the buffer memory is insufficient, candidate data to be evicted is identified from the buffer memory based on the least recently used rule; Determine whether the candidate elimination data belongs to the data that the pre-read strategy predicts will be accessed soon; as well as If the determination result is yes, the candidate eviction data is exempted, and another candidate eviction data is identified from the buffer memory to perform a cache eviction operation.

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