Chip anomaly detection method and device and storage medium

Abstract

The embodiment of the invention provides a chip anomaly detection method and device and a computer readable storage medium. The chip anomaly detection method according to the embodiment of the invention comprises the following steps: acquiring a chip pressure welding image; electrode plate parameters of an electrode plate of the chip and an initial abnormal type of the electrode plate are obtained according to the chip pressure welding image, wherein the electrode plate parameters comprise electrode plate size parameters, welding ball parameters and welding wire parameters; and calculating the parameters of the electrode plate, correcting the initial abnormal type of the electrode plate according to a calculation result, and obtaining the corrected abnormal type of the electrode plate.

Description

Technical Field

[0001] This invention relates to the field of image processing, and more particularly to a chip anomaly detection method, a chip anomaly detection device, and a computer-readable storage medium. Background Technology

[0002] Semiconductor chip anomaly detection can be broadly divided into pre-packaging chip anomaly detection and post-packaging package anomaly detection, based on the semiconductor chip manufacturing process. Pre-packaging chip anomaly detection typically uses an image of the entire chip as the detection source. In practice, soldering is a crucial pre-packaging process. Currently, the soldering images exported from the soldering machine are generally only used for anomaly detection to check for misaligned solder balls. Furthermore, because existing technologies often employ traditional image processing methods, such as template matching, the false alarm rate for anomaly detection can reach over 95% due to various factors such as ambient lighting, equipment vibration, and obstructions.

[0003] Therefore, there is a need for a chip anomaly detection method, device, and medium that can perform precise detection of chip anomalies, reduce false alarm rates, and improve positive detection rates. Summary of the Invention

[0004] To address the aforementioned technical problems, according to one aspect of the present invention, a chip anomaly detection method is provided, comprising: acquiring a chip bonding image; acquiring electrode plate parameters and an initial anomaly type of the electrode plate based on the chip bonding image, wherein the electrode plate parameters include electrode plate size parameters, solder ball parameters, and bonding wire parameters; performing calculations on the electrode plate parameters; correcting the initial anomaly type of the electrode plate based on the calculation results; and acquiring a corrected anomaly type of the electrode plate.

[0005] According to another aspect of the present invention, a chip anomaly detection device is provided, comprising: an acquisition unit configured to acquire a chip bonding image; a detection unit configured to acquire electrode plate parameters of the electrode plate of the chip and an initial anomaly type of the electrode plate based on the chip bonding image, the electrode plate parameters including electrode plate size parameters, solder ball parameters and bonding wire parameters; and a correction unit configured to perform calculations on the electrode plate parameters, correct the initial anomaly type of the electrode plate based on the calculation results, and acquire a corrected anomaly type of the electrode plate.

[0006] According to another aspect of the present invention, a chip anomaly detection device is provided, comprising: a processor; and a memory, wherein computer program instructions are stored in the memory, wherein when the computer program instructions are executed by the processor, the processor performs the following steps: acquiring a chip bonding image; acquiring electrode plate parameters of the electrode plate of the chip and an initial anomaly type of the electrode plate based on the chip bonding image, the electrode plate parameters including electrode plate size parameters, solder ball parameters, and bonding wire parameters; performing calculations on the electrode plate parameters, correcting the initial anomaly type of the electrode plate based on the calculation results, and acquiring a corrected anomaly type of the electrode plate.

[0007] According to another aspect of the present invention, a computer-readable storage medium is provided, having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, perform the following steps: acquiring a chip bonding image; acquiring electrode plate parameters of the electrode plate of the chip and an initial anomaly type of the electrode plate based on the chip bonding image, the electrode plate parameters including electrode plate size parameters, solder ball parameters, and bonding wire parameters; performing calculations on the electrode plate parameters, correcting the initial anomaly type of the electrode plate based on the calculation results, and acquiring a corrected anomaly type of the electrode plate.

[0008] According to the chip anomaly detection method, chip anomaly detection apparatus, and computer-readable storage medium of the present invention, electrode plate parameters and initial anomaly types can be obtained from the acquired chip bonding image, and the initial anomaly type can be corrected by calculation results based on the electrode plate parameters to obtain more accurate chip anomaly detection results. The chip anomaly detection method, apparatus, and computer-readable storage medium of the present invention can reduce the false alarm rate of chip anomaly detection and effectively improve the positive detection rate. Attached Figure Description

[0009] The above and other objects, features, and advantages of the present invention will become clearer from the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings.

[0010] Figure 1 A flowchart illustrating a chip anomaly detection method according to an embodiment of the present invention is shown;

[0011] Figure 2 An image of a chip bonding process is shown as an example according to an embodiment of the present invention;

[0012] Figure 3 An example of a chip bonding image originally acquired from a bonding machine, illustrating an embodiment of the present invention;

[0013] Figure 4An example of labeling an original acquired chip bonding image is shown according to an embodiment of the present invention;

[0014] Figure 5 An example of a chip bonding image obtained by data augmentation of an original chip bonding image according to an embodiment of the present invention is shown;

[0015] Figure 6 A schematic diagram illustrating the acquisition of wire arrangement direction statistics according to an embodiment of the present invention is shown.

[0016] Figure 7 A schematic diagram illustrating the acquisition of wire arrangement direction statistics according to another example of an embodiment of the present invention;

[0017] Figure 8 A schematic diagram illustrating the acquisition of the average position of the solder ball center according to an embodiment of the present invention is shown.

[0018] Figure 9 A schematic diagram illustrating the acquisition of the average position of the solder ball center in another example according to an embodiment of the present invention;

[0019] Figure 10 A schematic diagram illustrating the acquisition of the average radius of a solder ball according to an embodiment of the present invention is shown.

[0020] Figure 11 A flowchart illustrating an example of electrode plate anomaly type determination according to an embodiment of the present invention is shown.

[0021] Figure 12 A block diagram of a chip anomaly detection device according to an embodiment of the present invention is shown;

[0022] Figure 13 A block diagram of a chip anomaly detection device according to an embodiment of the present invention is shown. Detailed Implementation

[0023] The chip anomaly detection method, chip anomaly detection apparatus, and computer-readable storage medium according to embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements throughout. It should be understood that the embodiments described herein are merely illustrative and should not be construed as limiting the scope of the invention.

[0024] Figure 1 A flowchart of a chip anomaly detection method 100 according to an embodiment of the present invention is shown. Referring below... Figure 1 A chip anomaly detection method according to an embodiment of the present invention is described.

[0025] In step S101, a chip bonding image is obtained.

[0026] In this step, the chip bonding images generated during the bonding process can be obtained by exporting them from the bonding machine. Figure 2 An example chip bonding image is shown according to an embodiment of the present invention. Figure 2 As shown, a chip bonding image may include at least one electrode plate, each electrode plate may have solder balls, and solder wires may be connected to it. During the bonding process, the size and position of the electrode plate, as well as the condition of the solder balls and / or solder wires on the electrode plate, as presented in the chip bonding image, can be used to determine whether the electrode plate is abnormal.

[0027] In step S102, the electrode plate parameters and the initial fault type of the electrode plate of the chip are obtained based on the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters, and bonding wire parameters.

[0028] In this embodiment of the invention, the various contents of the electrode plate parameters can be represented in various ways. Optionally, the electrode plate size parameter in the electrode plate parameters can be represented using the center coordinates and width and height of the rectangular bounding box of the electrode plate, or it can be represented using the coordinates of each corner point of the electrode plate. Furthermore, optionally, the solder ball parameters in the electrode plate parameters can include the coordinates of the solder ball center and parameters such as the radius / diameter of the solder ball. Optionally, the weld line parameters in the electrode plate parameters can include the coordinates of each endpoint of the weld line on the electrode plate. For example, when the weld line is a straight line segment, the weld line parameters can include the coordinates of the two endpoints of the line segment; furthermore, when the weld line is bent or folded, the weld line parameters can also include one or more coordinates at the bending point or fold point of the weld line. The above representation methods for the various contents of the electrode plate parameters are merely examples. In practical applications, any appropriate electrode plate parameters can be selected for representation according to the application scenario, and no limitation is imposed here.

[0029] In this embodiment of the invention, electrode plate parameters and initial anomaly type detection can be performed using a neural network. For example, an end-to-end deep learning network model can be built to obtain the electrode plate parameters and initial anomaly types of the chip's electrode plate based on the chip bonding image. Optionally, during this process, a trained chip bonding image and its labeled electrode plate parameters and anomaly types can be input into the neural network. Specifically, for the trained chip bonding image, labeled electrode plate parameters, including electrode plate size parameters, solder ball parameters, and solder wire parameters, can be input simultaneously, and anomaly types can be labeled for them. After obtaining the trained chip bonding image and its labeled electrode plate parameters and anomaly types, the neural network can be trained accordingly, and the parameters of the neural network can be adjusted to make the loss function of the neural network converge.

[0030] In this embodiment of the invention, the chip bonding image used for training the neural network can be either the original chip bonding image or a chip bonding image obtained by data augmentation of the original chip bonding image. For example, the chip bonding image used for training can be obtained by performing at least one transformation on the original chip bonding image, including scaling, translation, flipping, and brightness adjustment. If the data augmentation process involves modifications to the geometric structure of the labeled electrode plate parameters corresponding to the original chip bonding image, the labeled electrode plate parameters corresponding to the data-augmented chip bonding image need to be recalculated. Data augmentation of the original chip bonding image can effectively expand the image data used to train the neural network, providing a large number of samples to improve the detection accuracy of the neural network and increase the accuracy of chip anomaly detection. The acquisition and expansion methods of the chip bonding images used for training in this embodiment of the invention are merely examples. In practical applications, any method that can expand the chip bonding images used for training can be used, and no limitations are imposed here.

[0031] After training the neural network, optionally, the trained neural network can be used to detect the input chip bonding image to obtain the electrode plate parameters and the initial anomaly type of the electrode plate. Optionally, the initial anomaly type and the corrected anomaly type of the electrode plate in this embodiment can include various normal / abnormal behaviors generated during the bonding process. For example, the initial anomaly type and / or the corrected anomaly type can include at least one of the following: normal, probe mark, detachment, dry contact, foreign object, peeling, and misalignment. Among these types, "normal" indicates that the solder balls, solder wires, and other components on the electrode plate of the chip are without abnormalities during the bonding process; a probe mark indicates a contact mark left by a probe contacting the chip under test, which is also a type of normal electrode plate. In addition, "detachment" indicates an abnormality where both solder balls and wires are present on the electrode plate, but the solder ball / wire has detached; "dry welding" indicates an abnormality where the solder ball on the electrode plate was not successfully welded; "foreign matter" indicates an abnormality where foreign matter is present in the solder ball on the electrode plate; "peeling" indicates an abnormality where the solder ball on the electrode plate detaches after welding; and "off-center welding" indicates an abnormality where the solder ball on the electrode plate is not welded to its normal position. The above list and explanation of various electrode plate abnormality types are only examples. In practical applications, different normal / abnormal electrode plate types can be distinguished according to different specific pressure welding scenarios and pressure welding requirements, and no restrictions are imposed here.

[0032] In this embodiment of the invention, optionally, a trained neural network can be used to determine different initial anomaly types of the electrode plate based on the electrode plate parameters of the acquired chip bonding image. Specifically, the initial anomaly type of the electrode plate can be derived by using the neural network to make various comprehensive judgments on the electrode plate parameters in the chip bonding image. Furthermore, in one example, different initial anomaly types of the electrode plate can also be derived by various simple classifications and judgments of the electrode plate parameters. For example, it can first be determined whether there are bonding wires on the electrode plate. If there are bonding wires, it can then be determined whether the bonding wires are broken or have an incorrect orientation, or further, it can be determined whether the solder balls have detached. For cases such as broken bonding wires, incorrect bonding wire orientation, and detached solder balls, the initial anomaly type of the electrode plate can be considered as detachment. Furthermore, if the electrode plate does not have solder lines, the condition of the solder balls can be further assessed: an initial anomaly where the center of the solder ball deviates from a predetermined position on the electrode plate can be identified as misalignment; an initial anomaly where the shape of the solder ball is close to a predetermined shape (such as a concentric circle) or the radius of the solder ball exceeds a predetermined threshold can be identified as dry soldering; an initial anomaly where the shape of the solder ball is irregular can be identified as foreign matter; an initial anomaly where the shape and position of the solder ball are close to the normal shape of a solder ball but there are no solder lines can be identified as peeling; other situations can be considered normal, and if they are identified as an anomaly, there may be a false alarm. The above specific judgment methods for various electrode plate anomaly types are only examples. In practical applications, different electrode plate anomaly type judgment methods can be adopted for different specific pressure welding scenarios and pressure welding requirements, and no restrictions are imposed here.

[0033] In step S103, the parameters of the electrode plate are calculated, and the initial abnormality type of the electrode plate is corrected according to the calculation results to obtain the corrected abnormality type of the electrode plate.

[0034] In this embodiment of the invention, optionally, the electrode plate parameters of a normal electrode plate can be statistically calculated based on the electrode plate parameters. Considering that a group of electrode plates on a chip in a chip bonding image may often have the same or similar electrode plate size, solder ball size, solder ball position, and dominant arrangement direction of the bonding wires, the electrode plate parameters of a normal electrode plate can be inferred from statistical and averaging results of the electrode plate parameters. In one example, the electrode plate parameters of a normal electrode plate may include at least one of the following: statistical analysis or dominant arrangement direction of the bonding wires on the normal electrode plate, average position of the solder ball center, and average radius of the solder ball. For example, the arrangement direction of the bonding wires can be obtained by statistically analyzing the number of bonding wires intersecting with the endpoints of the bonding wires away from the solder balls and the various boundaries (such as top, bottom, left, and right boundaries) of the electrode plate or chip bonding image, or the direction with the most bonding wires can be taken as the dominant arrangement direction of the bonding wires on the normal electrode plate. For example, the average distance from the center of the solder ball to each boundary of the corresponding electrode plate can be used as the average position of the center of the solder ball on the normal electrode plate. Alternatively, the average ratio of the distance from the center of the solder ball to each boundary of the corresponding electrode plate to the size of the electrode plate in the corresponding direction can be used as the average position of the center of the solder ball on the normal electrode plate. Another example is that the average radius of each solder ball on each electrode plate in the chip bonding image can be used as the average radius of the solder ball on the normal electrode plate. The above types and calculation methods of electrode plate parameters for various normal electrode plates are merely examples. In practical applications, different electrode plate parameters for normal electrode plates can be used for different specific bonding scenarios and bonding requirements, and no restrictions are placed here.

[0035] After calculating the electrode parameters of a normal electrode plate, optionally, the initial anomaly type of the electrode plate can be corrected based on the deviation between the electrode plate parameters and the calculated electrode plate parameters. The correction process using the electrode plate parameters of a normal electrode plate can effectively avoid errors and confusion in judging various similar anomalies of the electrode plate. In one example, the aforementioned classification and judgment of electrode plate parameters can be combined with a comparison with the electrode plate parameters of a normal electrode plate to further correct various anomaly types of the electrode plate, resulting in corrected anomaly types. For example, comparing the presence of solder lines and the dominant arrangement direction of solder lines on a normal electrode plate with the arrangement direction of solder lines on a certain electrode plate in the chip bonding image can effectively distinguish between anomalies such as detachment; comparing the average position of the solder ball center with the center position of the solder ball on a certain electrode plate in the chip bonding image can effectively distinguish between anomalies such as misalignment or foreign objects; comparing the average radius of the solder ball with the radius of the solder ball on a certain electrode plate in the chip bonding image can effectively distinguish between anomalies such as dry contact, foreign objects, and peeling. The above correction methods for various electrode plate anomaly types are only examples. In practical applications, different correction methods for different anomaly types can be adopted for different specific pressure welding scenarios and pressure welding requirements. No restrictions are imposed here.

[0036] The chip anomaly detection method according to embodiments of the present invention can obtain electrode plate parameters and initial anomaly types from acquired chip bonding images, and then correct the initial anomaly type using calculation results based on the electrode plate parameters to obtain more accurate chip anomaly detection results. The chip anomaly detection method, apparatus, and computer-readable storage medium of the present invention can reduce the false alarm rate of chip anomaly detection and effectively improve the positive detection rate.

[0037] The following describes an example of a chip anomaly detection method according to an embodiment of the present invention.

[0038] In this example, the chip bonding image generated during the bonding process is first obtained from the bonding machine.

[0039] Subsequently, based on the chip bonding image, the electrode plate parameters and the initial anomaly type of the electrode plate are obtained. The electrode plate parameters include electrode plate size parameters, solder ball parameters, and bonding wire parameters. The electrode plate size parameters can be represented using the coordinates of each corner point of the electrode plate, for example, P1(x1, y1), P2(x2, y2), P3(x3, y3), and P4(x4, y4). Furthermore, the solder ball parameters can be represented using the coordinates of the solder ball center P5(x5, y5) and the solder ball radius R, and the bonding wire parameters can be represented using the coordinates of the two endpoints of the bonding wire P6(x6, y6) and P7(x7, y7). The initial anomaly type and / or the subsequent corrected anomaly type can include at least one of the following: normal, probe mark, detachment, dry-punch, foreign object, peeling, and misalignment.

[0040] In this example, electrode plate parameters and initial anomaly type detection can be performed using a neural network. Optionally, a trained chip bonding image, along with labeled electrode plate parameters and labeled anomaly types, can be input into the neural network first. The labeled electrode plate parameters can be represented in various ways similar to those described above, and the anomaly type classification is similar to the initial / corrected anomaly type classification described above. Subsequently, the neural network can be trained accordingly, adjusting its parameters until the loss function converges.

[0041] In this embodiment of the invention, the chip bonding image used for training the neural network can be the original chip bonding image or a chip bonding image obtained by performing data enhancement such as scaling, translation, flipping, and brightness adjustment on the original chip bonding image. Figure 3 An example of a chip bonding image originally acquired from a bonding machine is shown, according to an embodiment of the present invention. Figure 3 As shown, the chip bonding image may include multiple electrode plates, each of which may have corresponding solder balls and / or solder lines. Figure 4 An example of annotation is shown for an original acquired chip bonding image according to an embodiment of the present invention. Figure 4 In this process, electrode plate parameters, including electrode plate size parameters, solder ball parameters, and solder wire parameters, can be annotated based on the original chip bonding image, and the annotation anomaly type of each electrode plate can be further annotated. Figure 5 An example of a chip bonding image obtained by data augmentation of an original chip bonding image according to an embodiment of the present invention is shown. Figure 5 In China, targeting Figure 3The original chip bonding image shown was partially cropped and flipped to obtain a data-augmented chip bonding image for neural network training. Furthermore, Figure 5 The data-enhanced chip bonding images also include annotations of electrode plate parameters and anomaly types for each electrode plate.

[0042] After training the neural network, optionally, the trained neural network can be used to detect the input chip bonding image to obtain the electrode plate parameters of the chip's electrode plate and the initial anomaly type of the electrode plate.

[0043] After using a neural network to obtain the electrode plate parameters of the chip bonding image and the initial anomaly type of the electrode plate, further calculations can be performed on the electrode plate parameters, and the initial anomaly type of the electrode plate can be corrected based on the calculation results to obtain the corrected anomaly type of the electrode plate.

[0044] In this example, optionally, the electrode plate parameters of a normal electrode plate can be statistically calculated based on the electrode plate parameters. Considering that a group of electrode plates on a chip in a chip bonding image may often have the same or similar electrode plate size, solder ball size, solder ball position, and dominant solder line arrangement direction, the electrode plate parameters of a normal electrode plate can be inferred from statistical and averaging results of the electrode plate parameters. In one example, the electrode plate parameters of a normal electrode plate may include at least one of the following: statistical or dominant solder line arrangement direction on the normal electrode plate, average position of the solder ball center, and average radius of the solder ball.

[0045] In one example, the direction with the most solder lines can be determined by counting the number of solder lines that intersect with the boundaries (such as the top, bottom, left, and right boundaries) of the electrode plate or chip bonding image. For instance, the direction of solder line arrangement in the chip bonding image can be obtained by comparing the ratio of the number of intersections between the solder lines and the top, bottom, left, and right boundaries of the chip bonding image to the total number of solder lines. Specifically, the ratios of the number of intersections between the solder lines and the top, bottom, left, and right boundaries of the chip bonding image to the total number of solder lines can be represented as [Pt, Pd, Pl, Pr]. For example, Pt can be represented as: Pt = Number(top wirelines) / Number (total wire lines), where Number(top wire lines) represents the number of intersections between the endpoints of the bonding wires furthest from the solder ball and the upper boundary of the chip bonding image, and Number (total wire lines) represents the total number of intersections between the chip bonding image and each boundary of the chip bonding image. Similarly, Pd, Pl, and Pr represent the arrangement direction statistics of the lower boundary, left boundary, and right boundary, respectively.

[0046] Figure 6 A schematic diagram illustrating the acquisition of solder wire arrangement direction statistics is shown as an example according to an embodiment of the present invention. Figure 6 In the image, the total number of wire lines intersecting with all boundaries of the chip bonding image is 4 (the wires extending downwards do not intersect with the lower boundary of the chip bonding image; only the downward direction is shown in the figure), and the total number of wire lines intersecting with the upper boundary of the chip bonding image is also 4. Therefore, Pt can be calculated to be 1. Similarly, it can be deduced that... Figure 6 The values ​​Pd, Pl, and Pr shown are all 0, and the arrangement direction represented by the above ratios can be statistically recorded as [1.0, 0, 0, 0].

[0047] Figure 7 A schematic diagram illustrating the acquisition of wire arrangement direction statistics is shown in another example according to an embodiment of the present invention. Figure 7 In the image, the total number of wire lines intersecting with each boundary of the chip bonding image is 3, while the total number of wire lines intersecting with the top and right boundaries of the chip bonding image is 0, the total number of wire lines intersecting with the left boundary is 2, and the total number of wire lines intersecting with the bottom boundary is 1. Therefore, the arrangement direction represented by the above ratios can be statistically recorded as [0.0, 0.33, 0.67, 0.0].

[0048] In another example, the average ratio of the distance from the solder ball center to the top, bottom, left, and right boundaries of the corresponding electrode plate to the electrode plate size in the corresponding direction can be used as the average position of the solder ball center on a normal electrode plate. For example, the distance from the solder ball center to the corresponding top boundary of an electrode plate can be represented as Distance (Ball Center, PAD Top line), and the height of the corresponding electrode plate can be represented as Height of PAD. Therefore, the position Dt of the solder ball center from the corresponding top boundary of the electrode plate can be represented as Dt = Distance (Ball Center, PAD Topline) / Height of PAD. The average value of the corresponding Dt values ​​across all electrode plates in the chip bonding image can be used as the average position of the solder ball center from the corresponding top boundary of the electrode plate on a normal electrode plate. Furthermore, similarly, the average position of the solder ball center from the lower, left, and right boundaries of the electrode plate can be expressed as follows: , , .

[0049] Figure 8 A schematic diagram illustrating the acquisition of the average position of the solder ball center, according to an embodiment of the present invention, is shown. Figure 8 In the chip bonding image, the average distance Dt from the center of the corresponding solder ball to the upper boundary of the corresponding electrode plate in all electrode plates is taken as the average distance Dt from the center of the solder ball to the upper boundary of the electrode plate on the normal electrode plate. The calculated value is 0.51. Furthermore, similarly, the average position of the solder ball center from the lower, left, and right boundaries of the electrode plate can be expressed as follows: , , The values ​​are recorded as 0.49, 0.52, and 0.48 respectively. Therefore, the average position of the solder ball center can be recorded as [0.51, 0.49, 0.52, 0.48].

[0050] Figure 9 A schematic diagram illustrating the acquisition of the average position of the solder ball center in another example according to an embodiment of the present invention is shown. Figure 9 In the chip bonding image, the distance between the solder ball center and the outer edge of the electrode plate can be either close or far. The average values ​​can be calculated separately for each case. Specifically, the average values ​​of the two distances (Dt) between the solder ball center and the outer edge of the corresponding electrode plate in all electrode plates within the chip bonding image can be used as the average distance between the solder ball center and the outer edge of the electrode plate on the normal electrode plate. The calculated values ​​are 0.26 and 0.75. Furthermore, similarly, the average positions of the solder ball center from the lower, left, and right boundaries of the electrode plate can be expressed as follows: , , The values ​​are denoted as 0.74 / 0.25, 0.51 / 0.50, and 0.49 / 0.50, respectively. Therefore, the average position of the solder ball center can be denoted as [0.26, 0.74, 0.51, 0.49] and [0.75, 0.25, 0.50, 0.50], respectively, which are closer to the boundary of the electrode plate.

[0051] Furthermore, the statistical average radius of each solder ball on each electrode plate in the chip bonding image can be used as the average radius of the solder balls on the normal electrode plate. This can be expressed as the ratio of the total radius Sum(R) of all solder balls to the number of electrode plates (PADs), i.e., expressed as... = Sum(R) / Number of PAD. Figure 10 A schematic diagram illustrating the acquisition of the average radius of a solder ball according to an embodiment of the present invention is shown. Figure 10 In this process, the radius of each solder ball on the electrode plate can be calculated separately, and the average radius of the solder ball can be obtained. It is 25.

[0052] After calculating the electrode plate parameters of a normal electrode plate, optionally, the initial anomaly type of the electrode plate can be corrected based on the deviation between the electrode plate parameters and the calculated electrode plate parameters. In one example, various anomaly types of the electrode plate can be derived by combining various classifications and judgments of the electrode plate parameters with the deviations from the electrode plate parameters of a normal electrode plate. Figure 11 This diagram illustrates a flowchart of an electrode plate anomaly type determination method according to an embodiment of the present invention. Figure 11As shown, we can first determine whether there are solder lines on the electrode plate. If there are solder lines, we can then determine whether the solder lines are broken or the solder line direction is incorrect, or further determine whether the solder balls have come off. Solder line breakage, solder line direction error, solder ball detachment, etc. can all be considered as the abnormal type of the electrode plate being detachment. (Here, we can combine the solder line arrangement direction statistics or dominant arrangement direction in the electrode plate parameters of a normal electrode plate to determine whether there are solder line breakage or solder line direction errors, and correct the initial abnormal type judgment of the electrode plate when it is incorrect.) Furthermore, if there are no solder lines on the electrode plate, the condition of the solder balls can be further assessed: An initial anomaly where the solder ball center deviates from a predetermined position on the electrode plate can be identified as misalignment (this can be determined by combining the average position of the solder ball center in the electrode plate parameters of a normal electrode plate, and corrected if the initial anomaly type is incorrectly identified); an initial anomaly where the solder ball shape is close to a predetermined shape (such as a concentric circle) or the solder ball radius exceeds a predetermined threshold can be identified as dry soldering (this can be determined by combining the average radius of the solder balls in the electrode plate parameters of a normal electrode plate, and inferred if the solder ball is too large). Anomalies such as "blank firing" are corrected when the initial anomaly type for the electrode plate is incorrectly identified. An initial anomaly of irregular solder ball shape can be identified as foreign matter (here, the average position of the solder ball center and / or the average radius of the solder ball in the electrode plate parameters of a normal electrode plate can be used to determine whether it should be corrected to solder ball misalignment or blank firing). An initial anomaly where the solder ball shape and position are close to the normal solder ball shape but there is no solder line can be identified as peeling (here, the average radius of the solder ball in the electrode plate parameters of a normal electrode plate can be used to determine whether it should be corrected to solder ball blank firing). Other situations can be considered normal; if judged as an anomaly, it may be a false alarm.

[0053] Below, refer to Figure 12 The following describes a chip anomaly detection device 1200 according to an embodiment of the present invention. Figure 12 A block diagram of a chip anomaly detection apparatus 1200 according to an embodiment of the present invention is shown. Figure 12 As shown, the chip anomaly detection device 1200 includes an acquisition unit 1210, a detection unit 1220, and a correction unit 1230. Besides these units, the chip anomaly detection device 1200 may also include other components; however, since these components are irrelevant to the content of this embodiment, their illustrations and descriptions are omitted here. Furthermore, the specific details of the following operations performed by the chip anomaly detection device 1200 according to this embodiment are consistent with those described above. Figure 1 The details described are the same, so repeated descriptions of the same details are omitted here to avoid repetition.

[0054] Figure 12The chip anomaly detection device 1200 in the middle acquires chip bonding images through its acquisition unit 1210.

[0055] The acquisition unit 1210 can acquire chip bonding images generated during the bonding process by exporting them from the bonding machine. Figure 2 An example chip bonding image is shown according to an embodiment of the present invention. Figure 2 As shown, a chip bonding image may include at least one electrode plate, each electrode plate may have solder balls, and solder wires may be connected to it. During the bonding process, the size and position of the electrode plate, as well as the condition of the solder balls and / or solder wires on the electrode plate, as presented in the chip bonding image, can be used to determine whether the electrode plate is abnormal.

[0056] The detection unit 1220 obtains the electrode plate parameters of the electrode plate of the chip and the initial abnormality type of the electrode plate based on the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters and bonding wire parameters.

[0057] In this embodiment of the invention, the various contents of the electrode plate parameters can be represented in various ways. Optionally, the electrode plate size parameter in the electrode plate parameters can be represented using the center coordinates and width and height of the rectangular bounding box of the electrode plate, or it can be represented using the coordinates of each corner point of the electrode plate. Furthermore, optionally, the solder ball parameters in the electrode plate parameters can include the coordinates of the solder ball center and parameters such as the radius / diameter of the solder ball. Optionally, the weld line parameters in the electrode plate parameters can include the coordinates of each endpoint of the weld line on the electrode plate. For example, when the weld line is a straight line segment, the weld line parameters can include the coordinates of the two endpoints of the line segment; furthermore, when the weld line is bent or folded, the weld line parameters can also include one or more coordinates at the bending point or fold point of the weld line. The above representation methods for the various contents of the electrode plate parameters are merely examples. In practical applications, any appropriate electrode plate parameters can be selected for representation according to the application scenario, and no limitation is imposed here.

[0058] In this embodiment of the invention, the detection unit 1220 can acquire electrode plate parameters and detect initial anomaly types using a neural network. For example, an end-to-end deep learning network model can be built to acquire the electrode plate parameters and initial anomaly types of the electrode plate based on the chip bonding image. Optionally, during this process, a trained chip bonding image and labeled electrode plate parameters and anomaly types of the trained chip bonding image can be input into the neural network. Specifically, for the trained chip bonding image, labeled electrode plate parameters including electrode plate size parameters, solder ball parameters, and solder wire parameters can be input simultaneously, and anomaly types can be labeled for them. After acquiring the trained chip bonding image and its labeled electrode plate parameters and anomaly types, the neural network can be trained accordingly, and the parameters of the neural network can be adjusted to make the loss function of the neural network converge.

[0059] In this embodiment of the invention, the chip bonding image used for training the neural network can be either the original chip bonding image or a chip bonding image obtained by data augmentation of the original chip bonding image. For example, the chip bonding image used for training can be obtained by performing at least one transformation on the original chip bonding image, including scaling, translation, flipping, and brightness adjustment. If the data augmentation process involves modifications to the geometric structure of the labeled electrode plate parameters corresponding to the original chip bonding image, the labeled electrode plate parameters corresponding to the data-augmented chip bonding image need to be recalculated. Data augmentation of the original chip bonding image can effectively expand the image data used to train the neural network, providing a large number of samples to improve the detection accuracy of the neural network and increase the accuracy of chip anomaly detection. The acquisition and expansion methods of the chip bonding images used for training in this embodiment of the invention are merely examples. In practical applications, any method that can expand the chip bonding images used for training can be used, and no limitations are imposed here.

[0060] After training the neural network, optionally, the detection unit 1220 can use the trained neural network to detect the input chip bonding image to obtain the electrode plate parameters and the initial anomaly type of the electrode plate. Optionally, the initial anomaly type and the corrected anomaly type of the electrode plate in this embodiment can include various normal / abnormal behaviors generated during the bonding process. For example, the initial anomaly type and / or the corrected anomaly type can include at least one of the following: normal, probe mark, detachment, dry contact, foreign object, peeling, and misalignment. Among these types, "normal" indicates that the solder balls, solder wires, and other components on the electrode plate of the chip are without abnormalities during the bonding process; a probe mark indicates a contact mark left by a probe contacting the chip under test, which is also a type of normal electrode plate. In addition, "detachment" indicates an abnormality where both solder balls and wires are present on the electrode plate, but the solder ball / wire has detached; "dry welding" indicates an abnormality where the solder ball on the electrode plate was not successfully welded; "foreign matter" indicates an abnormality where foreign matter is present in the solder ball on the electrode plate; "peeling" indicates an abnormality where the solder ball on the electrode plate detaches after welding; and "off-center welding" indicates an abnormality where the solder ball on the electrode plate is not welded to its normal position. The above list and explanation of various electrode plate abnormality types are only examples. In practical applications, different normal / abnormal electrode plate types can be distinguished according to different specific pressure welding scenarios and pressure welding requirements, and no restrictions are imposed here.

[0061] In this embodiment of the invention, optionally, a trained neural network can be used to determine different initial anomaly types of the electrode plate based on the electrode plate parameters of the acquired chip bonding image. Specifically, the initial anomaly type of the electrode plate can be derived by using the neural network to make various comprehensive judgments on the electrode plate parameters in the chip bonding image. Furthermore, in one example, different initial anomaly types of the electrode plate can also be derived by various simple classifications and judgments of the electrode plate parameters. For example, it can first be determined whether there are bonding wires on the electrode plate. If there are bonding wires, it can then be determined whether the bonding wires are broken or have an incorrect orientation, or further, it can be determined whether the solder balls have detached. For cases such as broken bonding wires, incorrect bonding wire orientation, and detached solder balls, the initial anomaly type of the electrode plate can be considered as detachment. Furthermore, if the electrode plate does not have solder lines, the condition of the solder balls can be further assessed: an initial anomaly where the center of the solder ball deviates from a predetermined position on the electrode plate can be identified as misalignment; an initial anomaly where the shape of the solder ball is close to a predetermined shape (such as a concentric circle) or the radius of the solder ball exceeds a predetermined threshold can be identified as dry soldering; an initial anomaly where the shape of the solder ball is irregular can be identified as foreign matter; an initial anomaly where the shape and position of the solder ball are close to the normal shape of a solder ball but there are no solder lines can be identified as peeling; other situations can be considered normal, and if they are identified as an anomaly, there may be a false alarm. The above specific judgment methods for various electrode plate anomaly types are only examples. In practical applications, different electrode plate anomaly type judgment methods can be adopted for different specific pressure welding scenarios and pressure welding requirements, and no restrictions are imposed here.

[0062] The correction unit 1230 calculates the parameters of the electrode plate, corrects the initial abnormality type of the electrode plate according to the calculation results, and obtains the corrected abnormality type of the electrode plate.

[0063] In this embodiment of the invention, optionally, the correction unit 1230 can statistically calculate the electrode plate parameters of the normal electrode plate based on the electrode plate parameters. Considering that a group of electrode plates on a chip in a chip bonding image may often have the same or similar electrode plate size, solder ball size, solder ball position, and dominant arrangement direction of the bonding wires, the electrode plate parameters of the normal electrode plate can be inferred from statistical and averaging results of the electrode plate parameters. In one example, the electrode plate parameters of the normal electrode plate may include at least one of the following: statistical analysis or dominant arrangement direction of the bonding wires on the normal electrode plate, the average position of the solder ball center, and the average radius of the solder ball. For example, the arrangement direction of the bonding wires can be obtained by statistically analyzing the number of bonding wires intersecting the endpoints of the bonding wires away from the solder balls and the various boundaries (such as the top, bottom, left, and right boundaries) of the electrode plate or chip bonding image, or the direction with the most bonding wires can be taken as the dominant arrangement direction of the bonding wires on the normal electrode plate. For example, the average distance from the center of the solder ball to each boundary of the corresponding electrode plate can be used as the average position of the center of the solder ball on the normal electrode plate. Alternatively, the average ratio of the distance from the center of the solder ball to each boundary of the corresponding electrode plate to the size of the electrode plate in the corresponding direction can be used as the average position of the center of the solder ball on the normal electrode plate. Another example is that the average radius of each solder ball on each electrode plate in the chip bonding image can be used as the average radius of the solder ball on the normal electrode plate. The above types and calculation methods of electrode plate parameters for various normal electrode plates are merely examples. In practical applications, different electrode plate parameters for normal electrode plates can be used for different specific bonding scenarios and bonding requirements, and no restrictions are placed here.

[0064] After calculating the electrode plate parameters of a normal electrode plate, optionally, the correction unit 1230 can correct the initial abnormality type of the electrode plate based on the deviation between the electrode plate parameters and the calculated electrode plate parameters of the normal electrode plate. The correction process using the electrode plate parameters of the normal electrode plate can effectively avoid errors and confusion in judging various similar abnormalities of the electrode plate. In one example, the aforementioned classification and judgment of electrode plate parameters can be combined with a comparison with the electrode plate parameters of the normal electrode plate to further correct various abnormality types of the electrode plate, resulting in corrected abnormality types. For example, comparing the presence of solder lines and the dominant arrangement direction of solder lines on a normal electrode plate with the arrangement direction of solder lines on a certain electrode plate in the chip bonding image can effectively distinguish whether it is an abnormality type such as detachment; comparing the average position of the solder ball center with the center position of the solder ball on a certain electrode plate in the chip bonding image can effectively distinguish abnormalities such as misalignment or foreign matter; comparing the average radius of the solder ball with the radius of the solder ball on a certain electrode plate in the chip bonding image can effectively distinguish abnormalities such as dry-blow, foreign matter, and peeling. The above correction methods for various electrode plate anomaly types are only examples. In practical applications, different correction methods for different anomaly types can be adopted for different specific pressure welding scenarios and pressure welding requirements. No restrictions are imposed here.

[0065] The chip anomaly detection apparatus according to embodiments of the present invention can obtain electrode plate parameters and initial anomaly types from acquired chip bonding images, and then correct the initial anomaly type using calculation results based on the electrode plate parameters to obtain more accurate chip anomaly detection results. The chip anomaly detection method, apparatus, and computer-readable storage medium of the present invention can reduce the false alarm rate of chip anomaly detection and effectively improve the positive detection rate.

[0066] Below, refer to Figure 13 This describes a chip anomaly detection device according to an embodiment of the present invention. Figure 13 A block diagram of a chip anomaly detection apparatus 1300 according to an embodiment of the present invention is shown. Figure 13 As shown, the device 1300 can be a computer or a server.

[0067] like Figure 13 As shown, the chip anomaly detection device 1300 includes one or more processors 1310 and a memory 1320. In addition, the chip anomaly detection device 1300 may also include input devices, output devices (not shown), etc., and these components can be interconnected via a bus system and / or other forms of connection mechanisms. It should be noted that... Figure 13 The components and structure of the chip anomaly detection device 1300 shown are merely exemplary and not limiting. The chip anomaly detection device 1300 may also have other components and structures as needed.

[0068] The processor 1310 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may utilize computer program instructions stored in memory 1320 to perform desired functions, including: acquiring a chip bonding image; acquiring electrode plate parameters and initial fault types of the electrode plate based on the chip bonding image, the electrode plate parameters including electrode plate size parameters, solder ball parameters, and bonding wire parameters; performing calculations on the electrode plate parameters, correcting the initial fault types of the electrode plate based on the calculation results, and acquiring the number of corrected fault types of the electrode plate.

[0069] The memory 1320 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1310 may execute the program instructions to implement the functions of the chip anomaly detection apparatus according to the embodiments of the present invention described above, and / or other desired functions, and / or to execute the chip anomaly detection method according to the embodiments of the present invention. Various application programs and various data may also be stored in the computer-readable storage medium.

[0070] The following describes a computer-readable storage medium according to an embodiment of the present invention, which stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, perform the following steps: acquiring a chip bonding image; acquiring electrode plate parameters of the electrode plate of the chip and an initial anomaly type of the electrode plate based on the chip bonding image, the electrode plate parameters including electrode plate size parameters, solder ball parameters, and bonding wire parameters; performing calculations on the electrode plate parameters, correcting the initial anomaly type of the electrode plate based on the calculation results, and acquiring a corrected anomaly type of the electrode plate.

[0071] Of course, the specific embodiments described above are merely examples and not limitations. Those skilled in the art can combine and integrate some steps and devices from the various embodiments described separately above to achieve the effects of the present invention. Such combined and integrated embodiments are also included in the present invention, but will not be described one by one here.

[0072] Note that the advantages, benefits, and effects mentioned in this invention are merely examples and not limitations, and should not be considered as essential features of every embodiment of the invention. Furthermore, the specific details described above are for illustrative and illustrative purposes only, and are not intended to limit the invention. These details do not limit the invention from being implemented solely by employing these specific details.

[0073] The block diagrams of devices, apparatuses, devices, and systems involved in this invention are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0074] The flowcharts and method descriptions in this invention are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. As those skilled in the art will recognize, the steps in the above embodiments can be performed in any order. Words such as "then," "next," etc., are not intended to limit the order of steps; these words are only used to guide the reader through the description of these methods. Furthermore, any reference to a singular element, such as the use of the articles "a," "one," or "the," is not to be construed as limiting that element to the singular.

[0075] Furthermore, the steps and apparatus in the various embodiments herein are not limited to any one embodiment. In fact, new embodiments can be conceived by combining relevant steps and apparatus in the various embodiments herein with the concepts of the present invention, and these new embodiments are also included within the scope of the present invention.

[0076] Each operation described above can be performed by any suitable means capable of performing the corresponding function. Such means may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors.

[0077] The various exemplified logic blocks, modules, and circuits described herein can be implemented or performed using a general-purpose processor, digital signal processor (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, it may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0078] The steps of the methods or algorithms described in this invention can be directly embedded in hardware, in a software module executed by a processor, or a combination of both. The software module can reside in any form of tangible storage medium. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, etc. The storage medium can be coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integral with the processor. The software module can be a single instruction or many instructions, and can be distributed across several different code segments, different programs, and across multiple storage media.

[0079] The method of this invention includes one or more actions for implementing the method. The methods and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions may be modified without departing from the scope of the claims.

[0080] The described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions on a physical computer-readable medium. The storage medium can be any available physical medium that can be accessed by a computer. By way of example, and not limitation, such a computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other physical medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, a disc includes a compact disc (CD), a laser disc, an optical disc, a digital universal disc (DVD), a floppy disk, and a Blu-ray disc.

[0081] Therefore, a computer program product can perform the operations described herein. For example, such a computer program product can be a computer-readable tangible medium having instructions tangibly stored (and / or encoded) thereon, which can be executed by one or more processors to perform the operations described herein. The computer program product may include packaging materials.

[0082] Software or instructions can also be transmitted via a transmission medium. For example, software can be transmitted from a website, server, or other remote source using transmission media such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave.

[0083] Furthermore, modules and / or other suitable means for carrying out the methods and techniques described herein can be downloaded and / or obtained by user terminals and / or base stations as appropriate. For example, such a device can be coupled to a server to facilitate the transmission of means for carrying out the methods described herein. Alternatively, the various methods described herein can be provided via storage components (e.g., RAM, ROM, physical storage media such as CDs or floppy disks) so that user terminals and / or base stations can obtain the various methods when coupled to the device or when providing storage components to the device. Furthermore, any other suitable techniques for providing the methods and techniques described herein to the device can be utilized.

[0084] Other examples and implementations are within the scope and spirit of this invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various places, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein, including as used in the claims, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the described examples are preferred or better than other examples.

[0085] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims is not limited to the specific aspects of the processes, machines, manufacturing processes, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufacturing processes, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufacturing processes, events, means, methods, or actions within their scope.

[0086] The above description of aspects of the invention is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features of the invention herein.

[0087] The above description has been given for illustrative and descriptive purposes. Furthermore, this description is not intended to limit the embodiments of the invention to the forms described herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A chip anomaly detection method, comprising: Acquire chip bonding images; The electrode plate parameters and the initial fault type of the electrode plate are obtained from the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters, and bonding wire parameters. The electrode plate parameters are calculated, and the initial anomaly type of the electrode plate is corrected based on the calculation results to obtain the corrected anomaly type of the electrode plate.

2. The method according to claim 1, wherein, The electrode plate parameters of the chip's electrode plate and the initial anomaly type of the electrode plate are obtained from the chip bonding image, including: The electrode plate parameters and the initial anomaly type of the electrode plate are obtained from the chip bonding image using a neural network.

3. The method according to claim 2, wherein, The neural network is trained using the following steps: Acquire training chip bonding images, and obtain the labeled electrode plate parameters and labeled anomaly types of the electrode plates in the training chip bonding images; The neural network is trained based on the labeled electrode plate parameters and labeled anomaly types of the electrode plate in the trained chip bonding image, and the parameters of the neural network are adjusted to make the loss function of the neural network converge.

4. The method according to claim 3, wherein, The trained chip bonding images are obtained by data augmentation of the original chip bonding images.

5. The method according to claim 1, wherein, The electrode plate size parameters include the coordinates of each corner point of the electrode plate; The solder ball parameters include the center coordinates of the solder ball on the electrode plate and the radius of the solder ball; and / or The bonding wire parameters include the coordinates of each endpoint of the bonding wire on the electrode plate.

6. The method according to claim 1, wherein, The calculation of the electrode plate parameters includes: Calculate the electrode plate parameters of the normal electrode plate based on the electrode plate parameters.

7. The method according to claim 6, wherein, The electrode plate parameters of the normal electrode plate include at least one of the following: Statistics on the arrangement direction of solder wires on a normal electrode plate, or the dominant arrangement direction, the average position of the solder ball center, and the average radius of the solder ball.

8. The method according to claim 6, wherein, The initial anomaly type of the electrode plate is corrected based on the calculation results, including: The initial abnormality type of the electrode plate is corrected based on the deviation between the electrode plate parameters and the calculated electrode plate parameters of the normal electrode plate.

9. The method according to any one of claims 1 to 8, wherein, The initial anomaly type and / or the corrected anomaly type include at least one of the following: Normal, probe mark, detachment, dry shot, foreign object, peeling, misalignment.

10. A chip anomaly detection device, comprising: The acquisition unit is configured to acquire chip bonding images; The detection unit is configured to obtain the electrode plate parameters of the electrode plate of the chip and the initial abnormality type of the electrode plate based on the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters and bonding wire parameters. The correction unit is configured to calculate the parameters of the electrode plate, correct the initial abnormality type of the electrode plate according to the calculation results, and obtain the corrected abnormality type of the electrode plate.

11. A chip anomaly detection device, comprising: processor; and a memory, in which computer program instructions are stored. When the computer program instructions are executed by the processor, the processor performs the following steps: Acquire chip bonding images; The electrode plate parameters and the initial fault type of the electrode plate are obtained from the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters, and bonding wire parameters. The electrode plate parameters are calculated, and the initial anomaly type of the electrode plate is corrected based on the calculation results to obtain the corrected anomaly type of the electrode plate.

12. A computer-readable storage medium having stored thereon computer program instructions, wherein, When the computer program instructions are executed by the processor, the following steps are performed: Acquire chip bonding images; The electrode plate parameters and the initial fault type of the electrode plate are obtained from the chip bonding image. The electrode plate parameters include the electrode plate size parameters, solder ball parameters, and bonding wire parameters. The electrode plate parameters are calculated, and the initial anomaly type of the electrode plate is corrected based on the calculation results to obtain the corrected anomaly type of the electrode plate.

Images