High-density interconnection circuit board and processing method thereof

Abstract

The invention relates to the technical field of circuit boards, and discloses a high-density interconnection circuit board and a processing method thereof, and the high-density interconnection circuit board comprises a plurality of circuit layers which are insulated from each other up and down; every two adjacent circuit layers are conducted through a plurality of laser blind hole interconnection structures; each laser blind hole interconnection structure comprises a plurality of laser blind holes with target apertures, so that each two adjacent circuit layers are conducted by the laser blind hole interconnection structure according to a preset contact area; and the laser blind holes in each laser blind hole interconnection structure are distributed at a target inter-hole distance and are fixedly connected to a bonding pad. According to the high-density interconnection circuit board, the plurality of laser blind holes with the target aperture are selected to form the laser blind hole interconnection structure, the conduction area between the circuit layers can be effectively improved, the situation that the circuit board fails due to the fact that signal transmission cannot be carried out due to the fact that the blind holes are separated from pads is avoided, and the production cost of the high-density interconnection circuit board is low.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a high-density interconnect circuit board and its processing method. Background Technology

[0002] In the manufacturing of existing high-density interconnect circuit boards, laser-drilled blind vias (DVs) are a key structure for interlayer interconnection, and their reliability directly affects the electrical performance and long-term stability of the product. However, with the increasing density of electronic products, DV detachment has become a common failure mode. Especially after repeated reflow soldering or thermal shock, material CTE (Coefficient of Thermal Expansion) mismatch leads to separation of the bottom interface of the DV, inducing cracks, which in turn affects the signal transmission of the upper and lower layers, and in severe cases, causes open circuit failure, resulting in low circuit board reliability. Existing technologies mainly improve reliability by selecting dielectric materials with high Tg (Glass Transition Temperature) and low coefficient of thermal expansion, and optimizing key process parameters such as laser drilling, plasma resist removal, copper plating, and via filling. Although the above methods can reduce the risk of detachment to some extent, they cannot completely eliminate failure, and they rely on strict process control, resulting in high production costs and large fluctuations in yield. Summary of the Invention

[0003] In view of this, embodiments of this application provide a high-density interconnect circuit board and its processing method, which can effectively solve problems such as the risk of blind via detachment in high-density interconnect circuit boards.

[0004] In a first aspect, embodiments of this application provide a high-density interconnect circuit board, comprising: a plurality of circuit layers disposed with upper and lower insulation; Each pair of adjacent circuit layers is connected by a number of laser blind via interconnect structures; Each of the laser blind via interconnect structures includes a plurality of laser blind vias with a target aperture, so that the laser blind via interconnect structure can conduct each of the two adjacent circuit layers with a preset contact area; Each of the laser blind vias in each of the laser blind via interconnect structures is fixedly connected to a pad with the target hole distances distributed between them.

[0005] In a first possible embodiment of the first aspect, each of the laser blind hole interconnect structures is provided with three laser blind holes, and the aperture of the laser blind holes in each laser blind hole interconnect structure is in the range of [0.15 mm, 0.20 mm]. In a second possible embodiment of the first aspect, the distance between the target holes ranges from [0.15 mm to 0.25 mm].

[0006] In a third possible embodiment of the first aspect, it further includes: laser drilling alignment marks and circuit pattern alignment marks; Both the laser drilling alignment mark and the circuit pattern alignment mark are located in the non-functional area of ​​the high-density interconnect circuit board.

[0007] In a fourth possible embodiment of the first aspect, the laser drilling alignment mark is a burn-in target hole, and the circuit pattern alignment mark is a laser annular hole.

[0008] Secondly, embodiments of this application provide a method for processing a high-density interconnect circuit board, comprising: The circuit pattern is transferred and etched onto the current copper foil layer of the substrate to form a tested circuit layer, resulting in the substrate after the current pattern transfer and etching. After the current pattern transfer etching substrate is laminated with the insulating layer and the next copper foil layer, laser drilling is performed using the target laser processing parameters to form a plurality of laser blind via interconnection structures; the target laser processing parameters are used to process laser blind vias that conform to the target aperture. After the laser blind via interconnect structure is cleaned, metallized and filled in sequence, the circuit pattern is transferred and etched on the next copper foil layer to obtain the substrate board after the next pattern transfer and etching, wherein the circuit patterns are aligned with each other. The substrate board after the next pattern transfer etching is laminated and drilled again until the high-density interconnect circuit board with the target number of layers described above is obtained.

[0009] In a first possible embodiment of the second aspect, the high-density interconnect circuit board circuitry further includes pattern alignment marks disposed in a non-functional area of ​​the high-density interconnect circuit board. The method further includes, during multiple transfer etching of the circuit pattern onto the copper foil layer: A spatial coordinate system is established using the graphic alignment mark as a positioning reference, and the coordinate information of the circuit pattern of the initial transfer etching in the spatial coordinate system is obtained; Based on the coordinate information, the circuit pattern of subsequent transfer etching is aligned with the circuit pattern of the initial transfer etching.

[0010] In a second possible embodiment of the second aspect, the high-density interconnect circuit board further includes a laser drilling alignment mark, the laser drilling alignment mark being disposed in a non-functional area of ​​the high-density interconnect circuit board; the step of laser drilling with target laser processing parameters to form a plurality of the laser blind via interconnect structures includes: The laser blind via interconnect structure is set at the target pad position using the laser drilling alignment mark as the positioning reference.

[0011] In a third possible embodiment of the second aspect, when the laser blind via interconnect structure is filled, the method further includes: The laser blind via interconnect structure is subjected to the filling process using the target electroplating filling parameters to obtain the processed laser blind via interconnect structure, wherein the depression value of the processed laser blind via interconnect structure is less than or equal to the minimum depression value.

[0012] In a fourth possible embodiment of the second aspect, the target laser processing parameters include laser aperture size, laser energy, laser pulse duration during copper breaking, and ablation parameters of the insulating layer.

[0013] The embodiments of this application have the following beneficial effects: This embodiment of a high-density interconnect circuit board includes: multiple circuit layers with top and bottom insulation; each pair of adjacent circuit layers is connected by a plurality of laser-connected blind via structures; each laser-connected blind via structure includes a plurality of laser-connected blind vias with target apertures, so that the laser-connected blind via structure connects each pair of adjacent circuit layers with a preset contact area; each laser-connected blind via in each laser-connected blind via structure is fixedly connected to a pad with the target aperture spacing. Based on the above scheme, selecting a plurality of laser-connected blind vias with target apertures to form a laser-connected blind via structure can effectively increase the conduction area between circuit layers, avoid blind via detachment, which would prevent signal transmission and cause circuit board failure, and the high-density interconnect circuit board has a low manufacturing cost. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A schematic diagram of a high-density interconnect circuit board according to an embodiment of this application is shown; Figure 2 This paper shows a schematic diagram of a laser blind via interconnect structure with three holes according to an embodiment of this application. Figure 3 This paper shows a schematic diagram of the layout structure of the laser blind via interconnect structure with three holes according to an embodiment of this application; Figure 4 A schematic diagram of the bottom pad of the laser blind hole according to an embodiment of this application is shown; Figure 5 A schematic diagram of a laser annular hole according to an embodiment of this application is shown; Figure 6A flowchart illustrating a method for fabricating a high-density interconnect circuit board according to an embodiment of this application is shown; Figure 7 The diagram shows the improved effect of laser blind hole alignment in an embodiment of this application.

[0016] Explanation of key component symbols: 100 - High-density interconnect circuit board; 110 - Line layer; 120 - Laser blind via interconnect structure. Detailed Implementation

[0017] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0020] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] First, this application provides a high-density interconnect circuit board 100. Please refer to... Figure 1 This is a structural block diagram of a high-density interconnect circuit board 100 provided in an embodiment of this application. The high-density interconnect circuit board 100 includes multiple circuit layers 110 with top and bottom insulation, and each pair of adjacent circuit layers is connected by a plurality of laser-drilled blind via interconnect structures 120. An insulating layer is provided between each pair of adjacent circuit layers to achieve insulation.

[0023] In one embodiment, each laser-guided via interconnect 120 includes a plurality of laser-guided vias with target apertures, such that the laser-guided via interconnect 120 connects each pair of adjacent circuit layers with a preset conductive area. Each laser-guided via in each laser-guided via interconnect 120 is fixedly connected to a pad with a target aperture spacing. The preset conductive area is the product of the effective conductive area at the bottom of a single laser-guided via and the number of vias, wherein the effective conductive area at the bottom of a single laser-guided via is related to the via aperture; the larger the via aperture, the larger the effective conductive area at the bottom.

[0024] In this embodiment, traditional interconnection methods often employ mechanical drilling or single laser-drilled blind vias to achieve interlayer interconnection. However, single blind vias suffer from limited current carrying capacity, heat concentration, and low reliability, and are particularly prone to breakage or burnout under high current or long-term operating conditions, affecting the reliable conduction of the circuit board. Therefore, this application proposes a laser blind via interconnection structure 120 composed of multiple laser blind vias. The laser blind via interconnection structure 120 achieves stable conduction between circuit layers, effectively solving the technical problems of insufficient conductivity and low reliability in the prior art.

[0025] In one embodiment, each laser blind hole interconnect structure 120 is provided with three laser blind holes, and the aperture range of the laser blind holes in each laser blind hole interconnect structure 120 is [0.15mm, 0.20mm].

[0026] In one embodiment, multiple sets of high-density interconnect circuit boards (HDPCBs) are provided. Each set of HDPCBs includes multiple identical HDPCBs, and the laser-guided via interconnect structures 120 of each set have different apertures and numbers of vias. Each set of HDPCBs undergoes multiple reflow soldering, thermal stress cycling, and low-resistance tests, and the resistance value of the conductive path of each HDPCB is recorded. After multiple reflow soldering cycles, the number of failed circuit boards in each set is determined based on the resistance value of each HDPCB.

[0027] In this embodiment, multiple reflow soldering is used to simulate the multiple soldering processes experienced by a PCB in actual use. The DC resistance of the blind via connection path is measured to determine the presence of microcracks or poor contact. The resistance value is measured after each reflow soldering cycle. If the resistance value exceeds a preset threshold, the high-density interconnect circuit board is considered unusable. Thermal stress cycling involves immersing the sample in a molten solder bath at a preset temperature for a preset time, then quickly removing and cooling it. For example, the preset temperature could be 288°C and the preset time could be 10 seconds. The resistance value is measured after each thermal stress cycle. If the resistance value exceeds a preset threshold, the high-density interconnect circuit board is considered unusable.

[0028] In one embodiment, the aperture of the laser blind via interconnect structure 120 of the test high-density interconnect circuit board with the smallest number of failed circuit boards is taken as the target aperture; the number of holes in the laser blind via interconnect structure 120 of the test high-density interconnect circuit board with the smallest number of failed circuit boards is taken as the target number of holes.

[0029] In this embodiment, based on the aforementioned reliability test results, the parameters of the high-reliability laser blind via interconnect structure 120 suitable for mass production are further determined. The number of failed circuit boards in each group of tested high-density interconnect circuit boards after multiple thermal stress cycles is compared, and the laser blind via diameter corresponding to the group with the smallest number of failures is selected as the target diameter, and the corresponding number of holes is selected as the target number of holes. Based on this optimal result, applying the target diameter and target number of holes to the engineering design of the actual high-density interconnect circuit board 100 product can effectively improve the thermal fatigue resistance of the blind via interconnect structure, reduce the risk of pad detachment, and achieve a higher level of product reliability.

[0030] For example, in one embodiment, five laser blind via apertures of 0.10mm, 0.125mm, 0.15mm, 0.175mm, and 0.20mm were designed, and laser blind via interconnect structures 120 with single, double, and triple vias were set up. The impact of different aperture sizes on the reliability of the blind via interconnect was tested, and the aperture with better reliability was selected. After each group of high-density interconnect circuit boards underwent 20 reflow soldering cycles, 12 thermal stress cycles, and 15 thermal stress cycles, the number of failures in each group of high-density interconnect circuit boards was recorded, as shown in Tables 1 and 2. Table 1: Test Results After 20 Reflow Soldering Cycles, 12 Thermal Stress Cycles, and 15 Thermal Stress Cycles

[0031] Table 2: Statistical Table of Failure Count for Each Group of High-Density Interconnect Circuit Boards

[0032] As mentioned above, repeated reflow soldering has little impact on the reliability of high-density interconnect circuit boards. However, after a certain number of thermal stress tests, failures occur. The test results for different aperture sizes show that slightly larger apertures slightly improve interconnect reliability, with a test range of 7. This indicates that aperture size is a secondary factor in reliability, with apertures ≥ 0.15mm performing optimally. The test results for the number of designed holes show that 3-hole interconnects ≥ 2-hole interconnects ≥ 1-hole interconnects, with a test range of 32. This indicates that the number of holes is a primary factor in reliability. Therefore, considering all factors, the optimal solution for high reliability of blind via interconnects is: a target aperture range of [0.15mm, 0.20mm] and a target number of three holes. Specifically, the spacing between each laser blind via in the laser blind via interconnect structure 120 is set to [0.15mm, 0.25mm].

[0033] For example, such as Figure 2 The diagram shown illustrates one structural design of a laser blind via interconnect structure 120 with three-hole interconnects. The laser blind via interconnect structure 120 includes various laser blind via layouts, allowing different layouts to be connected to the same pad, such as... Figure 3 The diagram shows the layout of a three-hole laser blind via interconnect structure 120. The three blind vias can be distributed equidistantly in the same row along the horizontal direction, which is a linear layout. The three blind vias can also be distributed at right angles (two horizontally arranged on the upper layer and one on the lower left side), forming an L-shaped right-angled layout. The three blind vias can also be densely distributed within a circular area, which is a centralized layout within the circular area.

[0034] In this embodiment, as Figure 4 As shown, since the upper and lower conductive layers are connected through blind vias, pad detachment can cause cracks at the bottom of the blind vias, affecting signal transmission between the upper and lower layers and ultimately impacting product reliability. However, such reliability issues cannot be completely avoided, and require significant investment of manpower and resources. This application primarily increases the conductive area and improves conductivity by optimizing the via diameter and designing blind via interconnects, thus preventing cracks at the bottom of the blind vias from significantly affecting signal transmission and further enhancing the reliability of the circuit board.

[0035] In one embodiment, the high-density interconnect circuit board further includes laser drill alignment marks and circuit pattern alignment marks. Exemplarily, both the laser drill alignment marks and the circuit pattern alignment marks are located in non-functional areas of the high-density interconnect circuit board.

[0036] In this embodiment, the laser drilling alignment marker is called a burn-in hole. A burn-in hole is a small through-hole or blind via pre-processed on the circuit board using a laser, serving as a high-precision visual alignment reference point for subsequent laser drilling. The burn-in hole is not a functional hole for electrical connection, but rather a purely process-aided marker. For example... Figure 5As shown, the alignment marker for the circuit pattern is a laser-drilled annular hole. This annular hole is a ring structure composed of multiple laser holes, concentric with the film aperture. For example, 16 laser holes are added around the film aperture; the laser holes maintain a safe distance of 1.0 mm from the edge of the film aperture; the diameter of each laser hole remains consistent; the laser annular hole is formed using a double-drilling method, that is, two laser impacts are performed at the same location to increase the material removal depth and hole diameter, avoiding electroplating filling.

[0037] For ease of understanding, the following embodiments of this application will be described in terms of... Figure 1 Taking the high-density interconnect circuit board 100 shown as an example, and in conjunction with the accompanying drawings, the processing method of the high-density interconnect circuit board provided in the embodiments of this application will be described.

[0038] Please refer to Figure 6 , Figure 6 A flowchart illustrating a method for fabricating a high-density interconnect circuit board according to an embodiment of this application is shown. The method for fabricating the high-density interconnect circuit board may include the following steps: S210, the circuit pattern is transferred and etched onto the current copper foil layer of the substrate to form an inspected circuit layer, resulting in the substrate after the current pattern transfer and etching.

[0039] As an example, a copper-clad laminate can be cut into a substrate of a preset size, and a preset circuit pattern can be transferred onto the copper foil surface of the substrate. The unprotected copper foil on the surface of the substrate is then removed by etching to form a circuit layer. An automated optical inspection device can be used to inspect the circuit layer for defects. If no defects are found, an inspected circuit layer is formed.

[0040] S220, after the current pattern transfer etching substrate is laminated with the insulating layer and the next copper foil layer, laser drilling is performed with the target laser processing parameters to form a number of laser blind hole interconnection structures 120; the target laser processing parameters are used to process laser blind holes that conform to the target hole diameter.

[0041] In this embodiment, the inspected circuit layer, insulating layer, and next copper foil layer are laminated to form an interlayer structure. Laser drilling is then performed on the outer layer of the interlayer structure to form a laser blind via interconnect structure 120. The next copper foil layer is a copper foil layer that has undergone copper layer thinning. The target laser processing parameters include laser aperture size, laser energy, laser pulse duration during copper breaking, and ablation parameters of the insulating layer.

[0042] In one embodiment, to ensure that laser blind holes conforming to the target aperture are produced, the influence of different laser processing parameters on the aperture is tested to produce the target aperture and aperture shape that meet the quality requirements. Table 3 shows the results of the influence of different laser processing parameters on the aperture.

[0043] Table 3: Results of the Influence of Different Laser Processing Parameters on Aperture

[0044] As shown in Table 3, when a laser blind hole interconnect structure with an aperture of 150 μm is selected, the target laser processing parameters are a laser aperture size of 2.6 mm, a laser energy of 20 mJ, and a laser pulse duration of 13 μs to penetrate the copper foil layer. Multiple laser pulses are applied to the exposed insulating layer for progressive ablation. The multiple pulses include three main ablation pulses and one trimming pulse to form a blind hole structure with smooth hole walls, which can meet the requirement of a target aperture of 150 μm.

[0045] In one embodiment, laser drilling is performed multiple times using target laser parameters, and the laser drilling alignment mark is used as a positioning reference to set the laser blind via interconnect structure 120 at the target pad position. In this embodiment, the high-precision vision system of the laser drilling machine captures the inner layer target image through the burning target hole, calculates the deviation between the actual position and the design position, and automatically corrects the interlayer offset, rotation, and scaling errors to ensure that the drilling coordinates are accurately aligned with the inner layer circuit. After the correction is completed, the laser drilling machine uses the burning target hole as a reference to perform the formal laser drilling operation, ensuring that the blind vias accurately hit the inner layer pads.

[0046] S230, after cleaning, metallizing and filling the laser blind via interconnect structure 120 in sequence, the circuit pattern is transferred and etched onto the next copper foil layer to obtain the substrate board after the next pattern transfer and etching, wherein the circuit patterns are aligned with each other.

[0047] As an example, plasma can be used to clean and activate the surface of the interlayer structure and blind vias; a conductive copper layer can be deposited on the wall of the blind via for metallization, and then the blind vias can be filled with copper by electroplating to achieve a filling process.

[0048] In one embodiment, when the laser blind via interconnect structure 120 is subjected to a filling process, the laser blind via interconnect structure 120 is filled using target electroplating filling processing parameters to obtain a processed laser blind via interconnect structure 120, wherein the recess value of the processed laser blind via interconnect structure 120 is less than or equal to the minimum recess value. The target electroplating filling processing parameters include the electroplating current density and conveying speed of the flash plating process (electrode copper flash plating), the electroplating current density, conveying speed, and number of filling operations during the filling process.

[0049] In one embodiment, the depression value of the laser blind via interconnect structure 120 after processing can be tested for different electroplating filling parameters. Electroplating filling parameters that satisfy a depression value less than or equal to the minimum depression value requirement are selected; for example, the minimum depression value is set to 10 μm. After testing, the target electroplating filling parameters can be determined as follows: a current density of 20 ASF (Amperes per Square Foot) and a conveyor speed of 0.60 m / min during the flash plating process; and an electroplating current density of 16 ASF and a conveyor speed of 0.27 m / min during the filling process, with one filling operation.

[0050] In one embodiment, when transferring and etching the circuit pattern onto the copper foil layer multiple times, a spatial coordinate system is established using the pattern alignment mark as a positioning reference to obtain the coordinate information of the circuit pattern transferred and etched in the spatial coordinate system during the initial transfer and etching. Based on the coordinate information, the circuit patterns transferred and etched subsequently are aligned with the circuit patterns transferred and etched in the initial transfer and etching.

[0051] In this embodiment, the center point of the laser annular hole is used as the origin of the coordinate system. The direction of the coordinate axis is determined by combining the distribution characteristics of each laser hole in the laser annular hole, and a spatial coordinate system is established. Then, the coordinate information of the circuit pattern of the initial transfer etching is defined on the circuit layer, and the aligned circuit pattern is generated on the next circuit layer based on the symmetry rule. The laser annular hole alignment can correct errors such as substrate deformation and mechanical misalignment, and accurately transfer the circuit pattern to the copper foil surface.

[0052] It's understandable that if the circuit pattern on a certain layer is misaligned, the circuitry or pads on the inner and outer layers will be misaligned after lamination. This will prevent the laser-drilled blind holes from hitting the pads, disrupt interlayer circuitry, and directly lead to circuit board failure. For example... Figure 7 As shown, before the improvement, the upper and lower laser blind holes were misaligned, but after the improvement, the laser blind holes were no longer misaligned.

[0053] S240, the substrate board after the next pattern transfer etching is laminated and drilled again until the high-density interconnect circuit board 100 of the above embodiment with the target number of layers is obtained.

[0054] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0055] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0056] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application.

[0057] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A high-density interconnect circuit board, characterized in that, include: Multiple circuit layers with upper and lower insulation; Each pair of adjacent circuit layers is connected by a number of laser blind via interconnect structures; Each of the laser blind via interconnect structures includes a plurality of laser blind vias with a target aperture, so that the laser blind via interconnect structure can conduct each of the two adjacent circuit layers with a preset contact area; Each of the laser blind vias in each of the laser blind via interconnect structures is fixedly connected to a pad with the target hole distances distributed between them.

2. The high-density interconnect circuit board according to claim 1, characterized in that, Each of the laser blind hole interconnect structures is provided with three laser blind holes, and the aperture of the laser blind holes in each laser blind hole interconnect structure is in the range of [0.15mm, 0.20mm].

3. The high-density interconnect circuit board according to claim 1, characterized in that, The range of the target hole distance is [0.15mm, 0.25mm].

4. The high-density interconnect circuit board according to claim 1, characterized in that, Also includes: Laser drilling alignment marks and circuit pattern alignment marks; Both the laser drilling alignment mark and the circuit pattern alignment mark are located in the non-functional area of ​​the high-density interconnect circuit board.

5. The high-density interconnect circuit board according to claim 4, characterized in that, The laser drilling alignment mark is the target hole, and the circuit pattern alignment mark is the laser annular hole.

6. A method for fabricating a high-density interconnect circuit board, characterized in that, include: The circuit pattern is transferred and etched onto the current copper foil layer of the substrate to form a tested circuit layer, resulting in the substrate after the current pattern transfer and etching. After the current pattern transfer etching substrate is laminated with the insulating layer and the next copper foil layer, laser drilling is performed using the target laser processing parameters to form a plurality of laser blind via interconnection structures; the target laser processing parameters are used to process laser blind vias that conform to the target aperture. After the laser blind via interconnect structure is cleaned, metallized and filled in sequence, the circuit pattern is transferred and etched on the next copper foil layer to obtain the substrate board after the next pattern transfer and etching, wherein the circuit patterns are aligned with each other. The substrate after the next pattern transfer etching is laminated and drilled again until a high-density interconnect circuit board with the target number of layers as described in any one of claims 1-5 is obtained.

7. The method for processing a high-density interconnect circuit board according to claim 6, characterized in that, The high-density interconnect circuit board also includes pattern alignment marks, which are disposed in non-functional areas of the high-density interconnect circuit board. The method further includes, during multiple transfer etching of the circuit pattern onto the copper foil layer: A spatial coordinate system is established using the graphic alignment mark as a positioning reference, and the coordinate information of the circuit pattern of the initial transfer etching in the spatial coordinate system is obtained; Based on the coordinate information, the circuit pattern of subsequent transfer etching is aligned with the circuit pattern of the initial transfer etching.

8. The method for processing a high-density interconnect circuit board according to claim 6, characterized in that, The high-density interconnect circuit board also includes laser drilling alignment marks, which are disposed in a non-functional area of ​​the high-density interconnect circuit board; the process of laser drilling with target laser processing parameters to form a plurality of laser blind via interconnect structures includes: The laser blind via interconnect structure is set at the target pad position using the laser drilling alignment mark as the positioning reference.

9. The method for processing a high-density interconnect circuit board according to claim 6, characterized in that, When performing a fill-in process on the laser blind hole interconnect structure, the method further includes: The laser blind via interconnect structure is subjected to the filling process using the target electroplating filling parameters to obtain the processed laser blind via interconnect structure, wherein the depression value of the processed laser blind via interconnect structure is less than or equal to the minimum depression value.

10. The method for processing a high-density interconnect circuit board according to claim 6, characterized in that, The target laser processing parameters include laser aperture size, laser energy, laser pulse duration during copper breaking, and ablation parameters of the insulating layer.

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