Gate-all-around integrated circuit structure with source or drain structure including regrown center portion

Abstract

A gate-all-around integrated circuit structure having a source or drain structure including a regrowth center portion, and methods of fabricating a gate-all-around integrated circuit structure having a source or drain structure including a regrowth center portion, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures have a central portion within the outer portion, and an interface between the central portion and the outer portion.

Description

[0001] This application is a divisional application of application No. 202211473362.3, filed on November 21, 2022, with the title “Full Ring Gate Integrated Circuit Structure with Source or Drain Structure Including Regrown Center Portion”. TECHNICAL FIELD

[0002] Embodiments of the present disclosure are in the field of integrated circuit structures and processes, and in particular, full ring gate integrated circuit structures with source or drain structures including regrown center portions, and methods of fabricating full ring gate integrated circuit structures with source or drain structures including regrown center portions. BACKGROUND

[0003] Over the past several decades, the shrinking of features in integrated circuits has been the driving force behind the growing semiconductor industry. Shrinking to smaller and smaller features enables an increase in the density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in products with increased capacity. However, the drive for ever greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly significant.

[0004] In the fabrication of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors, such as tri-gate transistors, have become more prevalent. In traditional processes, tri-gate transistors are typically fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate fabrication processes. On the other hand, as microelectronic device sizes shrink to below the 10 nanometer (nm) node, maintaining improvements in mobility and short channel control present challenges in device fabrication. Nanowire devices for fabricating devices provide improved short channel control.

[0005] However, shrinking multi-gate and nanowire transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits is reduced, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on photolithography processes used to pattern these building blocks have become overwhelming. In particular, there can be a tradeoff between the minimum size (critical dimension) of features patterned in a semiconductor stack and the spacing between these features. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1-3 Cross-sectional views representing various operations in a method of fabricating a full ring gate integrated circuit structure with source or drain structures including regrown center portions, in accordance with embodiments of the present disclosure, are shown.

[0007] Figure 4A cross-sectional view of a full ring gate integrated circuit structure representing a source or drain structure including a regrowth center portion is shown in accordance with an embodiment of the present disclosure.

[0008] Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line is shown in accordance with an embodiment of the present disclosure.

[0009] Figure 6 Cross-sectional views taken through nanowire and fin of a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) are shown in accordance with an embodiment of the present disclosure.

[0010] Figure 7 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure having a full ring gate device are shown in accordance with an embodiment of the present disclosure.

[0011] Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure is shown in accordance with an embodiment of the present disclosure.

[0012] Figure 8B A cross-sectional source or drain view of a nanowire-based integrated circuit structure of Figure 8A in accordance with an embodiment of the present disclosure taken along the a-a' axis.

[0013] Figure 8C A cross-sectional channel view of a nanowire-based integrated circuit structure of Figure 8A in accordance with an embodiment of the present disclosure taken along the b-b' axis.

[0014] Figure 9 A computing device in accordance with an embodiment of the present disclosure is shown.

[0015] Figure 10 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0016] Full ring gate integrated circuit structures having source or drain structures including a regrowth center portion, and methods of fabricating full ring gate integrated circuit structures having source or drain structures including a regrowth center portion are described. In the following description, numerous specific details are set forth such as specific integrated and material systems, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure can be practiced without such specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Also, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0017] Certain terminology can also be used in the following description for the purposes of reference only, and thus is not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and / or position of portions of a component relative to one another when the component is in an orientation consistent with the text and accompanying drawings describing the component. Such terminology can include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0018] Embodiments described herein can relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers all cases up to, but not including, the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0019] Embodiments described herein can relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectric), metal layers, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication phase, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL.

[0020] Embodiments described below can apply to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, while example processing schemes are illustrated using a FEOL processing context, such methods can also apply to BEOL processing. Likewise, while example processing schemes are illustrated using a BEOL processing context, such methods can also apply to FEOL processing.

[0021] One or more embodiments described herein relate to anisotropic etching and regrowth of epitaxial source or drain material to improve growth quality and enhance channel strain in a gate-all-around transistor. Embodiments include a gate-all-around (GAA) integrated circuit or FinFET transistor architecture. It should be understood that reference to nanowires herein can mean nanowires or nanoribbons, unless otherwise indicated.

[0022] To provide context, conventional GAA transistors do not have a continuous surface for epi growth. Conformal epi growth can potentially include defects and reduce channel strain.

[0023] According to one or more embodiments of the present disclosure, a number of operations for epi formation are implemented. First, a conformal epi chemical reaction is used to fill the source / drain space. Then, an anisotropic etch is used to create a trench in the middle of the epi. Finally, a bottom-up epi chemical reaction is used to fill the trench (or, alternatively, a conformal epi chemical reaction is used to fill the trench). In an embodiment, the anisotropic etch provides a continuous surface for the second epi to grow from. In one such embodiment, this results in better quality growth and stronger channel strain to improve device performance.

[0024] As an example process flow, Figures 1-3 Cross-sectional views representing various operations in a method of fabricating a full ring gate integrated circuit structure having a source or drain structure including a regrown center portion are shown according to embodiments of the present disclosure. Figure 4 Cross-sectional views representing a full ring gate integrated circuit structure having a source or drain structure including a regrown center portion are shown according to embodiments of the present disclosure. It should be understood that, more generally, the described source or drain structure can be adjacent to a nanowire stack, a nanoribbon stack, or a fin.

[0025] Referring to Figure 1 , the starting structure 100 includes a substrate 102, such as a silicon substrate, having a subfin 104 protruding through an isolation structure 106, such as a silicon oxide or silicon oxide isolation structure. In an alternative embodiment, the illustrated isolation structure 106 is an epi extension. A plurality of nanowires 108, such as silicon nanowires, are over the subfin 104. A sacrificial material 110, such as silicon germanium, is interleaved with the plurality of nanowires 108. A dummy gate structure 114, such as a polysilicon dummy gate structure, is over the sacrificial material 110 and the plurality of nanowires 108. A dielectric cap 112, such as a silicon nitride cap, can be between the dummy gate structure 114 and the top sacrificial material 110. In another embodiment, the dielectric cap 112 is not included. A gate spacer, such as a dielectric gate spacer 116A and an inner spacer 116B, is included at this stage.

[0026] Referring again to Figure 1 An initial epitaxial source or drain structure 118 is formed at the ends of the plurality of nanowires 108. In one embodiment, the initial epitaxial source or drain structure 118 is formed using conformal epi growth from the plurality of silicon facets, which can result in defects.

[0027] Referring to Figure 2, a directional etch is performed to remove epi from the middle or center of the initial epitaxial source or drain structure 118 to form an etched epitaxial source or drain structure 118A having cavities 120 formed therein. In embodiments, as shown, each cavity 120 is within a lateral portion and above a bottom portion of the respective etched epitaxial source or drain structure 118A. In one embodiment, each lateral portion has a lateral width substantially the same as a vertical width of the bottom portion, as shown. In another embodiment, each lateral portion has a lateral width greater than a vertical width of the bottom portion. In yet another embodiment, each lateral portion has a lateral width less than a vertical width of the bottom portion.

[0028] Referring to Figure 3 , an epitaxial growth is performed to fill the cavities 120 with epitaxial material 122. In one embodiment, the “second” epi growth is on a continuous surface, e.g., the surface of the first epi growth exposed by the cavities 120. The second epitaxial growth forms source or drain structures 124. Each source or drain structure 124 includes a central portion 122 within the outer portion 118A.

[0029] Referring to Figure 4 , a replacement gate process and nanowire release process are used to remove the sacrificial material 110 and form permanent gate structures. The permanent gate structures can include a high-k gate dielectric layer 126 and a metal gate electrode 128. Additionally, the processing can include forming conductive contacts 130 and / or additional spacer or interlevel dielectric material 132. In one embodiment, the conductive contacts 130 are only on the central portions 122 of the corresponding source or drain structures 124, as shown. In alternative embodiments, the conductive contacts 130 are on both the central portions 122 and the outer portions 118a of the corresponding source or drain structures 124.

[0030] Referring again to Figure 4 , according to embodiments of the disclosure, the integrated circuit structure 400 includes a vertical arrangement of nanowires 108. A gate stack 126 / 128 is over the vertical arrangement of nanowires 108. A first epitaxial source or drain structure (left 124) at a first end of the vertical arrangement of nanowires 108. A second epitaxial source or drain structure (right 124) at a second end of the vertical arrangement of nanowires 108. One or both of the first or second epitaxial source or drain structures 124 has a central portion 122 within an outer portion 118A.

[0031] In embodiments, there is an interface between the central portion 122 and the outer portion 118A, which can be revealed as a seam in cross-sectional analysis. In one embodiment, a continuous interface is formed within the epitaxial source or drain structure 124.

[0032] In an embodiment, the central portion 122 has an uppermost surface that is coplanar with an uppermost surface of the outer portion 118A, as shown. In another embodiment, the central portion 122 has an uppermost surface that is above an uppermost surface of the outer portion 118A. In yet another embodiment, the central portion 122 has an uppermost surface that is below an uppermost surface of the outer portion 118A.

[0033] In an embodiment, the central portion 122 and the outer portion 118a comprise the same semiconductor material. In another embodiment, the central portion 122 is composed of a different semiconductor material than the outer portion 118A. In another embodiment, the central portion 122 and the outer portion 118A have different dopant densities.

[0034] More generally, in an embodiment, the nanowire 108 is a silicon nanowire, a silicon germanium nanowire, a germanium nanowire, or a germanium tin nanowire. In an embodiment, the source or drain structure 124 is a silicon source or drain structure 124, a silicon germanium source or drain structure 124, a germanium source or drain structure 124, or a germanium tin source or drain structure 124. In a particular embodiment, the vertical arrangement of the nanowire 108 includes silicon, and the first and second epitaxial source or drain structures 124 include silicon and germanium. In another particular embodiment, the vertical arrangement of the nanowire 108 includes silicon and germanium, and the first and second epitaxial source or drain structures 124 include silicon and germanium.

[0035] As used throughout, a silicon layer can be used to describe a silicon material that is composed of a very large amount, if not all, of silicon. However, it should be understood that in practice, 100% pure Si can be difficult to form, and thus can include a minute percentage of carbon, germanium, or tin. Such impurities can be included as unavoidable impurities or components during Si deposition, or can “pollute” the Si as it diffuses during post-deposition processing. Thus, embodiments described herein that refer to a silicon layer can include a silicon layer that contains a relatively small amount (e.g., “impurity” level) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be understood that a silicon layer as described herein can be un-doped or can be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0036] As used throughout, a germanium layer can be used to describe a germanium material consisting of a very large amount (if not all) of germanium. However, it should be understood that in practice, 100% pure Ge may be difficult to form and may therefore include minute percentages of silicon, carbon, or tin. Such impurities may be included as unavoidable impurities or components during Ge deposition, or may “contaminate” Ge during post-deposition processing. Therefore, embodiments involving germanium layers described herein may include germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge atoms or substances (e.g., carbon, silicon, or tin). It should be understood that germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0037] As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed of a substantial portion of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon-germanium (commonly referred to as SiGe) may be difficult to form and may therefore include minute percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during post-deposition processing. Therefore, the embodiments involving silicon-germanium layers described herein may include silicon-germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon-germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0038] As used throughout, a germanium-tin layer can be used to describe a germanium-tin material consisting of a substantial portion of both germanium and tin (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of tin. In other embodiments, the amount of tin is greater than the amount of germanium. It should be understood that, in practice, 100% pure germanium-tin (commonly referred to as GeSn) may be difficult to form and may therefore include a small percentage of carbon or silicon. Such impurities may be included as unavoidable impurities or components during GeSn deposition, or may “contaminate” GeSn during diffusion during post-deposition processes. Therefore, the embodiments involving germanium-tin layers described herein may contain relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Sn atoms or substances, such as carbon or silicon. It should be understood that the germanium-tin layer described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0039] In another aspect, the nanowire release process can be performed by replacing the gate trench. Examples of such a release process are described below. Additionally, in yet another aspect, back end (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to enable front and back interconnect integration of nanowire transistors. Embodiments described herein can provide methods to enable relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. Embodiments can be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0040] In another aspect, to enable access to two conductive contact structures of an asymmetric source and drain contact structure pair, the integrated circuit structures described herein can be fabricated using a backside reveal fabrication method of a frontside structure. In some example embodiments, the reveal of the backside of a transistor or other device structure requires wafer level backside processing. The reveal of the backside of a transistor as described herein can be performed at the density of device cells and even within sub-areas of a device compared to conventional TSV type techniques. Furthermore, such a reveal of the backside of a transistor can be performed to substantially remove all of the donor substrate on which the device layers were disposed during frontside device processing. Thus, micrometer deep TSVs become unnecessary in cases where the semiconductor thickness in the device cells after the reveal of the backside of a transistor can be only tens or hundreds of nanometers.

[0041] The reveal techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer that is used for frontside fabrication, revealed from the backside, and used again for backside fabrication. Processing of both the frontside and the revealed backside of a device structure can address many of the challenges associated with fabricating 3D ICs when relying primarily on frontside processing.

[0042] For example, the reveal method of the backside of a transistor can be employed to remove at least a portion of a carrier layer and an intermediate layer of a donor-host substrate assembly. The process flow begins with an input donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any polishing, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be employed. For example, where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be employed. Likewise, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be employed.

[0043] In some embodiments, prior to the above, the carrier layer is cleaved along a cleave plane substantially parallel to the intermediate layer. The cleaving or fracturing process can be utilized to remove a substantial portion of the carrier layer as a bulk material, thereby reducing the polishing or etching time required to remove the carrier layer. For example, where the thickness of the carrier layer is 400-900 μιη, 100-700 μιη can be cleaved off by performing any blanket implant known to promote wafer level fracture. In some example embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer to a uniform target depth of the desired fracture plane. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-matrix substrate assembly can be polished or etched to completion. Alternatively, where the carrier layer does not fracture, a grinding, polishing, and / or etching operation can be employed to remove a greater thickness of the carrier layer.

[0044] Next, the exposure of the intermediate layer is detected. The detection is used to identify the point at which the back surface of the donor substrate has progressed to near the device layer. Any known endpoint detection technique suitable for detecting a transition between the materials used for the carrier layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorption or emission of the back surface of the donor substrate during the polishing or etching. In some other embodiments, the endpoint criteria are associated with a change in optical absorption or emission of a byproduct during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with a carrier layer etching byproduct can change depending on the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with a change in the mass of a species in a byproduct of polishing or etching the back surface of the donor substrate. For example, the byproduct of the process can be sampled by a quadrupole mass analyzer, and a change in the mass of the species can be correlated to the different compositions of the carrier layer and the intermediate layer. In another example embodiment, the endpoint criteria are associated with a change in friction between the back surface of the donor substrate and a polishing surface in contact with the back surface of the donor substrate.

[0045] Where the removal process is selective to the carrier layer relative to the intermediate layer, detection of the intermediate layer can be enhanced, as non-uniformities in the carrier removal process can be mitigated by the difference in etch rate between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operation removes the intermediate layer at a rate substantially lower than the rate at which the carrier layer is removed, detection can even be skipped. If no endpoint criteria are employed, a predetermined fixed duration of the grinding, polishing, and / or etching operation can be stopped on the intermediate layer material, where the thickness of the intermediate layer is sufficient to enable selectivity of the etching. In some examples, the carrier etch rate: intermediate layer etch rate is 3: 1 - 10: 1 or greater.

[0046] When the intermediate layer is exposed, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be removed uniformly, such as by polishing. Alternatively, the thickness of the intermediate layer can be removed using a mask or blanket etch process. This process can employ the same polishing or etching process as employed for thinning the carrier, or can be a different process with different process parameters. For example, where the intermediate layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more conducive to removal of the intermediate layer than to removal of the device layer. Where less than a few hundred nanometers of the intermediate layer thickness is to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and controlled more precisely than the process used to remove the carrier layer. The CMP process employed can, for example, employ a slurry that provides very high selectivity (e.g., 100: 1 - 300: 1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) that surrounds the device layer and is embedded within the intermediate layer (e.g., as electrical isolation between adjacent device regions).

[0047] For embodiments in which the device layer is exposed by complete removal of the intermediate layer, backside processing can be initiated on the exposed backside of the device layer or particular device regions therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and device regions (e.g., source or drain regions) previously fabricated in the device layer.

[0048] In some embodiments in which the carrier layer, intermediate layer, or device layer is recessed backside using wet and / or plasma etching, such etching can be a patterned etch or material-selective etch that imparts significant non-planarity or topography to the device layer backside surface. As further described below, the patterning can be within device cells (i.e., “in-cell” patterning) or can span device cells (i.e., “inter-cell” patterning). In some patterned etch embodiments, the at least partially thick intermediate layer is employed as a hard mask for backside device layer patterning. Thus, the mask etch process can serve as a starting point for the corresponding masked device layer etching.

[0049] The above-described processing schemes can yield a donor-matrix substrate assembly that includes an IC device having an exposed backside of the intermediate layer, a backside of the device layer, and / or a backside and / or frontside metallization of one or more semiconductor regions within the device layer. Then, during downstream processing, additional backside processing can be performed on any of these exposed regions.

[0050] It is to be understood that the structures resulting from the above exemplary processing schemes can be used in subsequent processing operations in the same or similar form to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of a completed device, Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line is shown in accordance with an embodiment of the present disclosure.

[0051] Referring to Figure 5 , the semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In another embodiment, instead of a solid fin, the non-planar active region is split into nanowires (e.g., nanowires 504A and 504B) over the sub-fin region 505, as represented by the dashed lines. In either case, for ease of describing the non-planar integrated circuit structure 500, the non-planar active region 504 is referred to below as a protruding fin portion. In an embodiment, the fabrication process involves a process scheme that uses to provide a full ring gate integrated circuit structure having an epitaxial source or drain structure including a regrown center portion.

[0052] A gate line 508 is disposed over the protruding portion 504 of the non-planar active region (including around the nanowires 504A and 504B, if applicable), as well as over a portion of the trench isolation region 506. As shown, the gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate line 508 can also include a dielectric cap layer 554. Also visible from this perspective are the gate contact 514 and the overlying gate contact via 516, as well as the overlying metal interconnect 560, all of which are disposed in an interlayer dielectric stack or layer 570. Also visible from Figure 5 Also visible from this perspective is that, in one embodiment, the gate contact 514 is disposed over the trench isolation region 506, but not over the non-planar active region. In another embodiment, the gate contact 514 is over the non-planar active region.

[0053] In an embodiment, the semiconductor structure or device 500 is a non-planar device, such as but not limited to a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds a top surface and a pair of sidewalls of the three-dimensional body.

[0054] As Figure 5Also shown in the embodiment is that there is an interface 580 between the protruding fin portion 504 and the sub-fin region 505. The interface 580 can be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid state dopant layer at the location of the sub-fin. In a particular such embodiment, each fin is less than 10 nanometers in width.

[0055] Although not shown in Figure 5 the source or drain region of the protruding fin portion 504 or adjacent to the source or drain region of the protruding fin portion is on either side of the gate line 508, i.e., within and outside the page. In one embodiment, the material in the source or drain location of the protruding fin portion 504 is removed and replaced with another semiconductor material, such as by epitaxial deposition to form a source or drain structure including a regrown central portion. The source or drain region can extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of the present disclosure, the more heavily doped sub-fin region, i.e., the doped portion of the fin below the interface 580, inhibits source to drain leakage through that portion of the body semiconductor fin.

[0056] Referring again to Figure 5 In embodiments, the fins 504 / 505 (and possibly nanowires 504a and 504b) are composed of a crystalline silicon germanium layer, which can be doped with charge carriers, such as but not limited to phosphorus, arsenic, boron, gallium, or combinations thereof.

[0057] In embodiments, the trench isolation region 506 and trench isolation regions described throughout (trench isolation structures or trench isolation layers) can be composed of a material suitable for ultimately electrically isolating or facilitating isolation of portions of the permanent gate structure from an underlying body substrate or isolation of active regions (e.g., isolation fin active regions) formed within the underlying body substrate. For example, in one embodiment, the trench isolation region 506 is composed of a dielectric material, such as but not limited to silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0058] The gate line 508 can be composed of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In embodiments, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. In addition, a portion of the gate dielectric layer can include a native oxide layer formed from the top several layers of the substrate fin portion 504. In embodiments, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0059] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In one specific embodiment, the gate electrode is composed of a non-work-function setting fill material formed over a metal work-function setting layer. The gate electrode layer can be composed of a P-type work-function metal or an N-type work-function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer can be composed of a stack of two or more metal layers, where one or more of the metal layers is a work-function metal layer and at least one of the metal layers is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer would be capable of forming a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer would be capable of forming an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode can be composed of a "U" shaped structure, which includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode can be a planar layer that is substantially parallel to the top surface of the substrate only, and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other implementations of the present disclosure, the gate electrode can be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode can be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0060] The spacer associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating or facilitating the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material, such as but not limited to silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0061] The gate contact 514 and the overlying gate contact via 516 can be composed of a conductive material. In embodiments, one or more of the contacts or vias is composed of a metal species. The metal species can be a pure metal, such as tungsten, nickel, or cobalt, or can be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0062] In embodiments (although not shown), a contact pattern is formed that is substantially completely aligned with the existing gate pattern 508, while eliminating the use of a photolithography step with a very tight registration budget. In other embodiments, all contacts are front-side connected and not asymmetric. In one such embodiment, a self-alignment method enables the use of a wet etch that is intrinsically highly selective (e.g., relative to a traditional implementation of a dry or plasma etch) to generate the contact openings. In embodiments, a contact pattern is formed by leveraging the existing gate pattern in conjunction with a contact plug photolithography operation. In one such embodiment, the method enables elimination of the need for a critical photolithography operation to generate the contact pattern that would otherwise be used in a conventional approach. In embodiments, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating is patterned, but before the gate grating is cut.

[0063] In embodiments, providing structure 500 involves fabricating the gate stack structure 508 through a replacement gate process. In this approach, dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, in contrast to being done by earlier processing, a permanent gate dielectric layer is also formed in this process. In embodiments, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed with a dry etch process that includes the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed with a wet etch process that includes the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed with a wet etch that includes water phosphoric acid.

[0064] Referring again to Figure 5 , the arrangement of the semiconductor structure or device 500 places gate contacts over the isolation region. This arrangement can be seen as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed over the active region (e.g., over the subfin 505) and formed in the same layer as the trench contact via.

[0065] It should be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. Moreover, the processes described herein can be used in the fabrication of one or more semiconductor devices. The semiconductor devices can be transistors or similar devices. For example, in embodiments, the semiconductor devices are metal oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Further, in embodiments, the semiconductor devices have a three-dimensional architecture, such as a tri-gate device, independently accessed dual gate device, or FIN-FET. One or more embodiments can be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10 nm) technology nodes.

[0066] In embodiments, as used throughout this specification, an interlayer dielectric (ILD) material is comprised of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si02)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0067] In embodiments, as also used throughout this specification, a metal line or interconnect line material (and via material) is comprised of one or more metal or other conductive structures. A common example is the use of copper lines and structures, which can or can not include a barrier layer between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line can include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack or alloy of different metals, etc. Thus, an interconnect line can be a single layer of material, or can be formed of several layers including a conductive liner and a fill layer. Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnect line. In embodiments, the interconnect line is comprised of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply as interconnects.

[0068] In embodiments, as also used throughout this specification, the hard mask material, cap layer, or plug is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials can be used in different regions in order to provide different growth or etch selectivities from each other and from the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap, or plug layer includes a nitride layer of silicon (e.g., silicon nitride) or an oxide layer of silicon, or both, or a combination thereof. Other suitable materials can include carbon-based materials. Other hard mask, cap, or plug layers known in the art can be used depending on the particular implementation. The hard mask, cap, or plug layer can be formed by CVD, PVD, or other deposition methods.

[0069] In embodiments, as also used throughout this specification, photolithography operations are performed using 193 nm immersion lithography (i193), EUV, and / or EBDW lithography, among others. A positive tone or negative tone resist can be used. In one embodiment, the photolithography mask is a three-layer mask composed of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0070] In another aspect, one or more embodiments are directed to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Particular embodiments can be directed to integrating multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In embodiments, nanowires / nanoribbons with multiple Wsi are integrated in the SAGE architecture portion of the front end process flow. Such a process flow can include integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions can be embedded (e.g., portions of the nanowires are removed, and then source or drain (S / D) growth is performed), and can be a regrown central portion or include a regrown central portion.

[0071] To provide further context, advantages of a self-aligned gate end cap (SAGE) architecture can include enabling higher layout density, and in particular, shrinking the diffusion to diffusion spacing. To provide an illustrative comparison, Figure 6 Cross-sectional views through nanowire and fin intercepts of a non-end cap architecture (left side (a)) versus a self-aligned gate end cap (SAGE) architecture (right side (b)) are shown in accordance with embodiments of the present disclosure.

[0072] Reference is made to Figure 6On the left side (a), the integrated circuit structure 600 includes a substrate 602 having fins 604 protruding a certain amount 606 above an isolation structure 608 laterally surrounding the lower portion of the fins 604. The upper portion of the fins may include a relaxation buffer layer 622 and a defect modification layer 620, as shown. Corresponding nanowires 605 are above the fins 604. A gate structure can be formed above the integrated circuit structure 600 to fabricate a device. However, interruptions in such a gate structure can be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0073] In comparison, reference Figure 6 On the right side (b), the integrated circuit structure 650 includes a substrate 652 having fins 654 protruding a certain amount 656 from an isolation structure 658 that laterally surrounds the lower portion of the fins 654. The upper portion of the fins may include a relaxation buffer layer 672 and a defect modification layer 670, as shown. Corresponding nanowires 655 are above the fins 654. Isolation SAGE walls 660 (as shown, which may include a hard mask thereon) are included within the isolation structure 658 and between adjacent pairs of fins 654 / nanowires 655. The distance between the isolation SAGE wall 660 and the nearest pair of fins 654 / nanowires 655 defines a gate cap spacing 662. A gate structure may be formed above the integrated circuit structure 650, between the isolation SAGE walls, to fabricate a device. Interruptions in such a gate structure are caused by the isolation SAGE walls. Because the isolation SAGE wall 660 is self-aligned, limitations from conventional methods can be minimized, allowing for more aggressive diffusion to the diffusion gap. Furthermore, since the gate structure includes interruptions at all locations, the individual gate structure portions can be layered via local interconnects formed above the isolation SAGE wall 660. In embodiments, as shown, each SAGE wall 660 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of this disclosure, for use with… Figure 6 The manufacturing process of the associated structure involves using a process scheme that provides an all-around gate integrated circuit structure having an epitaxial source or drain structure that may include a regrowth center portion.

[0074] The self-aligned gate endcap (SAGE) processing scheme involves forming a gate / trench contact endcap that is self-aligned with the fins, without requiring additional length to address mask misalignment. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate endcap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate endcap (SAGE) wall.

[0075] In an exemplary process scheme for structures having SAGE walls separating adjacent devices, Figure 7 Cross-sectional views illustrating various operations in a method of fabricating a self-aligned gate-all-around (SAGE) structure having a full-ring gate device, in accordance with an embodiment of the present disclosure, are shown.

[0076] Referring to Figure 7 part (a), the starting structure includes a nanowire-patterned stack 704 over a substrate 702. A litho-patterned stack 706 is formed over the nanowire-patterned stack 704. The nanowire-patterned stack 704 includes alternating sacrificial layers 710 and nanowire layers 712, which can be over a relaxation buffer layer 782 and a defect modification layer 780, as shown. A protective mask 714 is between the nanowire-patterned stack 704 and the litho-patterned stack 706. In one embodiment, the litho-patterned stack 706 is a three-layer mask consisting of a topography masking portion 720, an anti-reflective coating (ARC) layer 722, and a photoresist layer 724. In a particular such embodiment, the topography masking portion 720 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 722 is a silicon ARC layer.

[0077] Referring to Figure 7 part (b), the stack of part (a) is litho-patterned and then etched to provide an etched structure including a patterned substrate 702 and trenches 730.

[0078] Referring to Figure 7 part (c), the structure of part (b) has an isolation layer 740 and a SAGE material 742 formed in the trenches 730. The structure is then planarized to leave the patterned topography masking layer 720' as an exposed upper layer.

[0079] Referring to Figure 7 part (d), the isolation layer 740 is recessed below the upper surface of the patterned substrate 702, e.g., to define protruding fin portions and provide a trench isolation structure 741 under the SAGE walls 742.

[0080] Referring to Figure 7 part (e), the sacrificial layers 710 are removed at least in the channel regions to release the nanowires 712A and 712B. In one embodiment, the remaining portions of the protective mask 714 are removed after forming the structure of part (e). Figure 7 After the structure of part (e) of

[0081] Referring again to Figure 7 part (e), it should be appreciated that a channel view is shown in which the source or drain region is located outside the page. In embodiments, the channel region including nanowire 712B has a width that is less than the channel region including nanowire 712A. Thus, in embodiments, the integrated circuit structure includes multi-width (multi- Wsi) nanowires. Although the structures of 712B and 712A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to herein as nanowires. It should also be appreciated that references or illustrations to fin / nanowire pairs throughout the text can refer to structures including a fin and one or more overlying nanowires (e.g., as shown in Figure 7 Two overlying nanowires are shown in Figure 7 Manufacturing processes for structures associated with

[0082] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure can be composed of one or more materials suitable for ultimately electrically isolating or facilitating isolation of portions of the permanent gate structure from one another. Exemplary materials or combinations of materials include a single material structure, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include a multi-layer stack having a lower portion silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material, such as hafnium oxide.

[0083] To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to embodiments of the disclosure is shown. Figure 8B A cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A FIG. 1 1 is taken along the a-a' axis. Figure 8C A cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 8A FIG. 12 is taken along the b-b' axis.

[0084] Referring to Figure 8AThe integrated circuit structure 800 includes one or more vertically stacked nanowires (groups 804) above a substrate 802. In embodiments, as shown, a relaxation buffer layer 802C, a defect modification layer 802B, and a lower substrate portion 802A are included in the substrate 802. For illustrative purposes, and to emphasize the nanowire portion, optional fins formed by the substrate 802 below the bottommost nanowire are not shown. The embodiments herein are applicable to both single-wire and multi-wire devices. As an example, for illustrative purposes, a device based on three nanowires 804A, 804B, and 804C is shown. For ease of description, nanowire 804A is used as an example, with the description focusing on one of the nanowires. It should be understood that, while describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each of the nanowires.

[0085] Each of the nanowires 804 includes a channel region 806. The channel region 806 has a length (L). Reference Figure 8C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 8A and 8C A gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806. The gate electrode stack 808 includes a gate electrode and a gate dielectric layer between the channel regions 806 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 808 without any intermediate material, such as an underlying substrate material or an overlying channel fabrication material. Therefore, in embodiments having multiple nanowires 804, the channel regions 806 of the nanowires are also discrete relative to each other.

[0086] refer to Figure 8A and 8B The integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. This pair of non-discrete source or drain regions 810 / 812 is on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. Furthermore, this pair of non-discrete source or drain regions 810 / 812 is adjacent to the channel region 806 of the plurality of vertically stacked nanowires 804. In one embodiment not shown, this pair of non-discrete source or drain regions 810 / 812 is directly perpendicularly adjacent to the channel region 806 because epitaxial growth is performed on and between nanowire portions extending beyond the channel region 806, wherein the nanowire ends are shown within the source or drain structure. In another embodiment, as... Figure 8AAs shown, this pair of non-separate source or drain regions 810 / 812 indirectly vertically abut the channel region 806, as they are formed at the ends of the nanowires and not between the nanowires. In embodiments, the non-separate source or drain regions 810 / 812 are non-separate source or drain regions that include a regrown center portion.

[0087] In embodiments, as shown, the source or drain regions 810 / 812 are non-separate, in that there is not a separate and distinct source or drain region for each channel region 806 of the nanowires 804. Thus, in embodiments having multiple nanowires 804, the source or drain regions 810 / 812 of the nanowires are global or unified source or drain regions, rather than separate for each nanowire. That is, the non-separate source or drain regions 810 / 812 are global in the sense that a single unified feature serves as the source or drain region for multiple (in this case, 3) nanowires 804 (more specifically, for more than one separate channel region 806). In one embodiment, each of this pair of non-separate source or drain regions 810 / 812 is approximately rectangular in shape, with a bottom tapered portion and a top pointed portion, as viewed from a cross-section orthogonal to the length of the separate channel regions 806, as shown in Figure 8B .

[0088] According to embodiments of the present disclosure, and as shown in Figure 8A and 8B , the integrated circuit structure 800 further includes a pair of contacts 814, each contact 814 on one of this pair of non-separate source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds the corresponding non-separate source or drain region 810 / 812 in a vertical sense. In another aspect, the entire perimeter of the non-separate source or drain region 810 / 812 can not be available for contact with the contact 814, and thus the contact 814 only partially surrounds the non-separate source or drain region 810 / 812, as shown in Figure 8B . In a contrasting embodiment, not shown, the entire perimeter of the non-separate source or drain region 810 / 812, taken along the A-A’ axis, is surrounded by the contact 814.

[0089] Referring again to Figure 8A , in embodiments, the integrated circuit structure 800 further includes a pair of spacers 816. As shown, an outer portion of this pair of spacers 816 can overlap portions of the non-separate source or drain regions 810 / 812, thereby providing an “embedded” portion of the non-separate source or drain regions 810 / 812 under the pair of spacers 816. As also shown, the embedded portion of the non-separate source or drain regions 810 / 812 can not extend under the entire pair of spacers 816.

[0090] Substrate 802 can be composed of materials suitable for integrated circuit structure fabrication. In one embodiment, substrate 802 includes a lower bulk substrate composed of a single crystalline material that can include, but is not limited to, silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer composed of a material that can include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is on the lower bulk substrate. Thus, structure 800 can be fabricated from a starting semiconductor-on-insulator substrate. Alternatively, structure 800 is formed directly from a bulk substrate and local oxidation is used to form electrically insulating portions in place of the above-described upper insulator layer. In another alternative embodiment, structure 800 is formed directly from a bulk substrate and doping is used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., proximate to the substrate) is in the form of an omega-FET type structure.

[0091] In embodiments, nanowire 804 can be dimensioned as a wire or ribbon, as described below, and can have square or rounded corners. In embodiments, nanowire 804 is composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowire is single crystalline. For example, for a silicon nanowire 804, the single crystalline nanowire can be based on a (100) global orientation, e.g., with a <100> plane in the z-direction. Other orientations can also be considered, as described below. In embodiments, nanowire 804 is nanoscale in dimension from the perspective of a cross-section. For example, in particular embodiments, the smallest dimension of nanowire 804 is less than about 20 nanometers. In embodiments, nanowire 804 is composed of a strained material, particularly in channel region 806.

[0092] Referring to Figure 8C In embodiments, each of channel regions 806 has a width (Wc) and a height (Hc) that are approximately the same. That is, in both cases, the cross-sectional profile of channel region 806 is approximately square, or approximately circular if rounded, in another aspect, the width and height of a channel region need not be the same, e.g., as in the case of a nanoribbon as described throughout.

[0093] In embodiments, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a FinFET or tri-gate device with a corresponding one or more overlying nanowire structures. In such embodiments, a corresponding semiconductor channel region is composed of or formed in a three-dimensional body, with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, a gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0094] In embodiments, as described throughout, the following substrates can be composed of a semiconductor material capable of withstanding the manufacturing process and in which electrical charges can migrate. In embodiments, the substrate is a bulk substrate composed of a layer of crystalline silicon, silicon / germanium, or germanium doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof) to form an active region. In one embodiment, the bulk substrate has a concentration of silicon atoms greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (such as, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). The bulk substrate can alternatively be composed of a III-V material. In embodiments, the bulk substrate is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a III-V material and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0095] Embodiments disclosed herein can be used to manufacture various different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Further, the integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktop, laptop, server), cellular telephones, personal electronic devices, etc. The integrated circuits can be coupled with buses and other components in the system. For example, a processor can be coupled to memory, chipset, etc. by one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0096] Figure 9 A computing device 900 is shown in accordance with one implementation of embodiments of the disclosure. The computing device 900 houses a board 902. The board 902 can include a number of components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

[0097] Depending on its applications, computing device 900 can include other components that can or can not be physically and electrically coupled to board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, compact disk (CD), digital versatile disk (DVD), etc.).

[0098] Communication chip 906 enables wireless communications for the transfer of data to and from computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 906 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless

[0099] Processor 904 of computing device 900 includes an integrated circuit die packaged within processor 904. The integrated circuit die of processor 904 can include one or more structures, such as a full ring gate integrated circuit structure having a source or drain structure including a regrown center portion constructed in accordance with embodiments of the present disclosure. The term "processor" can refer to any device or portion of a device that manipulates electronic data based on instructions provided by a register and / or memory to transform that electronic data into other electronic data that can be stored in a register and / or memory.

[0100] The communication chips 906 also include integrated circuit dies that are housed within the communication chips 906. The integrated circuit dies of the communication chips 906 can include one or more structures, such as a full ring gate integrated circuit structure with a source or drain structure including a regrown center portion, constructed in accordance with embodiments of the present disclosure.

[0101] In further implementations, another component housed within the computing device 900 can contain an integrated circuit die that includes one or more structures, such as a full ring gate integrated circuit structure with a source or drain structure including a regrown center portion, constructed in accordance with embodiments of the present disclosure.

[0102] In various implementations, the computing device 900 can be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 can be any other electronic device that processes data.

[0103] Figure 10 An interposer 1000 including one or more embodiments of the present disclosure is shown. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 can be, for example, an integrated circuit die. The second substrate 1004 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the interposer 1000 is to either extend connections to a wider pitch or to rewire connections to different connections. For example, the interposer 1000 can couple an integrated circuit die to a ball grid array (BGA) 1006 that can then be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002 / 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of the interposer 1000. Also, in further embodiments, three or more substrates are interconnected by the interposer 1000.

[0104] The interposer 1000 can be formed of an epoxy, a fiberglass-reinforced epoxy, a ceramic material, or a polymeric material such as polyimide. In further implementations, the interposer 1000 can be formed of alternating rigid or flexible materials, which can include the same materials as described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0105] The interposer can include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 can also include embedded devices 1014, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices can also be formed on the interposer 1000, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices. In accordance with embodiments of the present disclosure, the apparatus or processes disclosed herein can be used to fabricate the interposer 1000 or to fabricate components included in the interposer 1000.

[0106] Accordingly, embodiments of the present disclosure include a full ring gate integrated circuit structure having a source or drain structure including a regrown center portion, and methods of fabricating a full ring gate integrated circuit structure having a source or drain structure including a regrown center portion.

[0107] The above description of illustrated embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

[0108] These modifications can be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the present disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of the present disclosure is to be determined entirely by the following claims, which are to be construed in accordance with the principles of claim interpretation.

[0109] Example Embodiment 1 : An integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a center portion within an outer portion, and an interface between the center portion and the outer portion.

[0110] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the center portion has an uppermost surface that is coplanar with an uppermost surface of the outer portion.

[0111] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the center portion and the outer portion comprise the same semiconductor material.

[0112] Example Embodiment 4: The integrated circuit structure of example embodiments 1, 2, or 3, wherein the vertical arrangement of nanowires comprises silicon, and the first and second epitaxial source or drain structures comprise silicon and germanium.

[0113] Example Embodiment 5: The integrated circuit structure of example embodiments 1, 2, or 3, wherein the vertical arrangement of nanowires comprises silicon and germanium, and the first and second epitaxial source or drain structures comprise silicon and germanium.

[0114] Example Embodiment 6: An integrated circuit structure comprises a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

[0115] Example Embodiment 7: The integrated circuit structure of example embodiment 6, wherein the central portion has an uppermost surface that is coplanar with an uppermost surface of the outer portion.

[0116] Example Embodiment 8: The integrated circuit structure of example embodiments 6 or 7, wherein the central portion and the outer portion comprise the same semiconductor material.

[0117] Example Embodiment 9: The integrated circuit structure of example embodiments 6, 7, or 8, wherein the vertical arrangement of nanowires comprises silicon, and the first and second epitaxial source or drain structures comprise silicon and germanium.

[0118] Example Embodiment 10: The integrated circuit structure of example embodiments 6, 7, or 8, wherein the vertical arrangement of nanowires comprises silicon and germanium, and the first and second epitaxial source or drain structures comprise silicon and germanium.

[0119] Example Embodiment 11: A computing device comprises a board and a component coupled to the board. The component comprises an integrated circuit structure comprising a vertical arrangement of nanowires. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

[0120] Example Embodiment 12: The computing device of example embodiment 11, further comprising a memory coupled to the board.

[0121] Example Embodiment 13: The computing device of example embodiments 11 or 12, further comprising a communication chip coupled to the board.

[0122] Example Embodiment 14: The computing device of example embodiments 11, 12, or 13, further comprising a battery coupled to the board.

[0123] Example Embodiment 15: The computing device of example embodiments 11, 12, 13, or 14, wherein the component is a packaged integrated circuit die.

[0124] Example Embodiment 16: A computing device comprising a board and a component coupled to the board. The component comprises an integrated circuit structure including a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

[0125] Example Embodiment 17: The computing device of example embodiment 16, further comprising a memory coupled to the board.

[0126] Example Embodiment 18: The computing device of example embodiments 16 or 17, further comprising a communication chip coupled to the board.

[0127] Example Embodiment 19: The computing device of example embodiments 16, 17, or 18, further comprising a battery coupled to the board.

[0128] Example Embodiment 20: The computing device of example embodiments 16, 17, 18, or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: Vertical arrangement of nanowires; A first source or drain structure and a second source or drain structure, wherein the first source or drain structure is located at a first end of the vertically arranged nanowire, and the second source or drain structure is located at a second end of the vertically arranged nanowire, the second end being laterally opposite to the first end, wherein each of the first source or drain structure and the second source or drain structure includes a central epitaxial portion within an outer epitaxial portion, the central epitaxial portion having a bottom surface below the bottom surface of the lowest nanowire of the vertically arranged nanowire; A gate stack above and around each of the vertically arranged nanowires, the gate stack having a portion laterally located between the first source or drain structure and the second source or drain structure; A first conductive contact, located on the first source or drain structure, is perpendicularly positioned above the top surface of the central epitaxial portion but not perpendicularly positioned above the top surface of the outer epitaxial portion of the first source or drain structure; and The second conductive contact is located on the second source or drain structure, and is perpendicular to the top surface of the central epitaxial portion but not perpendicular to the top surface of the outer epitaxial portion of the second source or drain structure.

2. The integrated circuit structure according to claim 1, further comprising: Sub-fins, which are arranged vertically below the nanowires.

3. The integrated circuit structure according to claim 1, further comprising: A first dielectric gate spacer is laterally located between the gate stack and the first conductive contact. as well as The second dielectric gate spacer is laterally located between the gate stack and the second conductive contact.

4. The integrated circuit structure according to claim 1, further comprising: A first internal spacer is laterally located between the gate stack and the first source or drain structure. as well as The second internal spacer is laterally located between the gate stack and the second source or drain structure.

5. The integrated circuit structure according to claim 1, wherein, The central epitaxial portion comprises a semiconductor material different from that of the outer epitaxial portion.

6. The integrated circuit structure according to claim 1, wherein, The central epitaxial portion and the outer epitaxial portion comprise the same semiconductor material.

7. An integrated circuit structure, comprising: First nanowire; A second nanowire, which is placed on top of the first nanowire; A third nanowire, which is placed on top of the second nanowire; A first source or drain structure and a second source or drain structure, wherein the first source or drain structure is located at a first end of each of the first nanowire, the second nanowire, and the third nanowire, and the second source or drain structure is located at a second end of each of the first nanowire, the second nanowire, and the third nanowire, the second end being laterally opposite to the corresponding first end, wherein each of the first source or drain structure and the second source or drain structure includes a first epitaxial portion and a second epitaxial portion, the second epitaxial portion being along the side and bottom of the first epitaxial portion, and the first epitaxial portion having a bottom surface below the bottom surface of the first nanowire, wherein there are no other nanowires below the first nanowire; A gate electrode is located on and around each of the first nanowire, the second nanowire, and the third nanowire, the gate electrode having a portion laterally located between the first source or drain structure and the second source or drain structure; A first conductive structure, wherein the first conductive structure exists only on the first epitaxial portion of the first source or drain structure; and The second conductive structure exists only on the first epitaxial portion of the second source or drain structure.

8. The integrated circuit structure according to claim 7, further comprising: Sub-fins, which are located below the first nanowire.

9. The integrated circuit structure according to claim 7, further comprising: A first dielectric gate spacer is laterally located between the gate electrode and the first conductive structure; as well as The second dielectric gate spacer is laterally located between the gate electrode and the second conductive structure.

10. The integrated circuit structure according to claim 7, further comprising: A first internal spacer is laterally located between the gate electrode and the first source or drain structure. as well as The second internal spacer is laterally located between the gate electrode and the second source or drain structure.

11. The integrated circuit structure according to claim 7, wherein, The first epitaxial portion comprises a semiconductor material different from that of the second epitaxial portion.

12. The integrated circuit structure according to claim 8, wherein, The first epitaxial portion and the second epitaxial portion comprise the same semiconductor material.

13. An integrated circuit structure, comprising: Vertical arrangement of nanowires; A first source or drain structure and a second source or drain structure, wherein the first source or drain structure is located at a first end of the nanowire arranged vertically, and the second source or drain structure is located at a second end of the nanowire arranged vertically, wherein each of the first source or drain structure and the second source or drain structure includes a central portion within an outer portion. A gate stack above a vertical arrangement of nanowires; A first conductive contact, wherein the first conductive contact is at least located on the central portion of the first source or drain structure; and The second conductive contact is located at least on the central portion of the second source or drain structure.

14. The integrated circuit structure according to claim 13, further comprising: Sub-fins, which are arranged vertically below the nanowires.

15. The integrated circuit structure according to claim 13 or 14, further comprising: A first dielectric gate spacer is laterally located between the gate stack and the first conductive contact. as well as The second dielectric gate spacer is laterally located between the gate stack and the second conductive contact.

16. The integrated circuit structure according to any one of claims 13-15, further comprising: A first internal spacer is laterally located between the gate stack and the first source or drain structure. as well as The second internal spacer is laterally located between the gate stack and the second source or drain structure.

17. The integrated circuit structure according to any one of claims 13-16, wherein, The central portion comprises a semiconductor material different from that of the outer portion.

18. The integrated circuit structure according to any one of claims 13-17, wherein, The central portion and the outer portion comprise the same semiconductor material.

19. The integrated circuit structure according to any one of claims 13-18, wherein: The central portion has a bottom surface below the bottom surface of the bottommost nanowire arranged vertically in the nanowires; The first conductive contact is located perpendicularly above the top surface of the central portion but not perpendicularly above the top surface of the outer portion of the first source or drain structure. and The second conductive contact is located perpendicularly above the top surface of the central portion but not perpendicularly above the top surface of the outer portion of the second source or drain structure.

20. A computing device, comprising: plate; as well as Components, the components coupled to the board, the components including an integrated circuit structure, the integrated circuit structure comprising: Vertical arrangement of nanowires; A first source or drain structure and a second source or drain structure, wherein the first source or drain structure is located at a first end of the vertically arranged nanowire, and the second source or drain structure is located at a second end of the vertically arranged nanowire, the second end being laterally opposite to the first end, wherein each of the first source or drain structure and the second source or drain structure includes a central epitaxial portion within an outer epitaxial portion, the central epitaxial portion having a bottom surface below the bottom surface of the lowest nanowire of the vertically arranged nanowire; A gate stack above and around each of the vertically arranged nanowires, the gate stack having a portion laterally located between the first source or drain structure and the second source or drain structure; A first conductive contact, located on the first source or drain structure, is perpendicularly positioned above the top surface of the central epitaxial portion but not perpendicularly positioned above the top surface of the outer epitaxial portion of the first source or drain structure; and The second conductive contact is located on the second source or drain structure, and is perpendicular to the top surface of the central epitaxial portion but not perpendicular to the top surface of the outer epitaxial portion of the second source or drain structure.

21. The computing device of claim 20, further comprising: A memory, which is coupled to the board.

22. The computing device of claim 20, further comprising: A communication chip, which is coupled to the board.

23. The computing device of claim 20, further comprising: A battery, which is coupled to the plate.

24. The computing device of claim 20, further comprising: A display, which is coupled to the board.

25. The computing device according to claim 20, wherein, The component is a packaged integrated circuit die.

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