Source or drain structure with vertical trenches having contacts therein

Abstract

The present disclosure describes source or drain structures with vertical trenches having contacts therein. An integrated circuit structure having a source or drain structure with a vertical trench having a contact therein is described. In an example, an integrated circuit structure includes a nanowire stack over a sub-fin. An epitaxial source or drain structure is located at an end of the nanowire stack, the epitaxial source or drain structure having a trench therein. A conductive contact in the trench and extending over the epitaxial source or drain structure; or an epitaxial layer is along the side and bottom of the trench, and a conductive contact is located within and extends over the epitaxial layer, where the epitaxial layer includes gallium.

Description

Background Technology

[0001] Over the past few decades, feature scaling in integrated circuits has been a driving force behind the ever-evolving semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of an increased number of memory or logic devices on a single chip, thus facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The necessity of optimizing the performance of each device becomes increasingly apparent.

[0002] The variability of conventional and currently known manufacturing processes may limit their potential for further expansion to the 10-nanometer or sub-10-nanometer node range. Therefore, the manufacture of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into or replacement of current manufacturing processes. Attached Figure Description

[0003] Figures 1A-1B The figures illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure having a source or drain structure with vertical trenches having contacts therein, according to embodiments of the present disclosure.

[0004] Figures 1C-1D The figure shows a cross-sectional view illustrating various operations in another method of manufacturing a gate-all-around integrated circuit structure having a source or drain structure with vertical trenches having contacts therein, according to another embodiment of the present disclosure.

[0005] Figures 2A-2E The figures illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure having a source or drain structure according to embodiments of the present disclosure, the source or drain structure having vertical trenches having contacts therein.

[0006] Figure 3A The figure shows a plan view of a plurality of gate lines above a pair of semiconductor fins according to another embodiment of the present disclosure.

[0007] Figure 3B The figure illustrates the path according to an embodiment of the present disclosure. Figure 3A A cross-sectional view taken from the a-a' axis.

[0008] Figure 4 The figure shows a cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to another embodiment of the present disclosure.

[0009] Figure 5The figure shows a cross-sectional view of an integrated circuit structure having conductive contacts on a raised source or drain region according to an embodiment of the present disclosure.

[0010] Figure 6A and Figure 6B The figures illustrate cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure, each integrated circuit structure having a trench contact including an overlying insulating cap and a gate stack including an overlying insulating cap.

[0011] Figure 7 The figure illustrates a computing device according to one implementation of the present disclosure.

[0012] Figure 8 The figure illustrates an intermediary layer that includes one or more embodiments of this disclosure.

[0013] Figure 9 This is an isometric view of a mobile computing platform manufactured using one or more processes described herein or including one or more features described herein, according to embodiments of this disclosure.

[0014] Figure 10 The figure shows a cross-sectional view of a flip-chip mounting die according to an embodiment of the present disclosure. Detailed Implementation

[0015] An integrated circuit structure having a source or drain structure with vertical trenches having contacts therein is described, as well as a method of manufacturing a source or drain structure having vertical trenches having contacts therein. In the following description, numerous specific details (such as specific integration and material schemes) are set forth in order to provide a complete understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Furthermore, it will be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0016] The following detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed description.

[0017] This specification includes references to "one embodiment" or "embodiment". The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0018] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims):

[0019] "Comprising". This term is open-ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0020] "Configured for". Various units or components can be described or claimed to be "configured for" to perform one or more tasks. In such a context, by indicating that a unit or component includes a structure that performs those one or more tasks during operation, "configured for" refers to the structure. Thus, a unit or component can be said to be configured for performing a task even when the specified unit or component is not currently operable (e.g., not turned on or active). The statement that a unit or circuit or component is "configured for" to perform one or more tasks is explicitly intended not to invoke paragraph 6 of 35 U.S.SC §112 for that unit or component.

[0021] "First," "second," etc., are used as labels for the nouns preceding them and do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0022] "Coupled". The following description refers to elements, nodes or features being "coupled" together. As used herein, unless otherwise expressly stated, "coupled" means that one element, node or feature is directly or indirectly connected to (or communicates directly or indirectly with) another element, node or feature, and not necessarily mechanically.

[0023] Furthermore, certain terms may be used for illustrative purposes only in the following description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientation in the referenced figures. Terms such as “front,” “rear,” “rear,” “side,” “outer,” and “inner” describe the orientation or position, or both orientation and position, of the parts of a component within a consistent but arbitrary frame of reference, which becomes clear by reference to the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0024] "Inhibition." As used herein, inhibition describes the reduction or minimization of an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent the result or consequence or future state. Additionally, "inhibition" may also refer to a reduction or mitigation of a consequence, performance, or effect that would otherwise have occurred. Accordingly, when a component, element, or feature is described as inhibiting a result or state, it is not necessary to completely prevent or eliminate the result or state.

[0025] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structure. FEOL is the first part of integrated circuit fabrication, in which various devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers all deposits up to (but not including) metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0026] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. During the BEOL portion of the manufacturing phase, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in the BEOL.

[0027] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. Specifically, although the exemplary processing scheme may be illustrated using a FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although the exemplary processing scheme may be illustrated using a BEOL processing scenario, such a method can also be applied to FEOL processing.

[0028] According to one or more embodiments of this disclosure, methods for forming three-dimensional (3D) contacts of a RibbonFET (strip field-effect transistor) are described. According to one or more embodiments of this disclosure, methods for forming high-conductivity 3D contacts of a PMOS RibbonFET are described. One or more embodiments described herein relate to a full-around-gate integrated circuit structure having a source or drain structure with vertical trenches having contacts therein. It should be understood that, unless otherwise indicated, references to nanowires herein can refer to nanowires, nanoribbons, nanosheets, or forksheets. One or more embodiments described herein relate to a fin-based integrated circuit structure having a source or drain structure with vertical trenches having contacts therein.

[0029] To provide context, for the RibbonFET architecture, some traditional device performance elements (such as channel strain) are unavailable, and new performance elements are required. Current two-dimensional (2D) contacts exhibit high external resistance due to the small contact area resulting from the scaled spacing. To continue scaling the cell area, 3D contact architectures have become a key process technology required to maintain the contact area as large as possible while preserving reasonable external resistance and improved device performance. In some cases, the amount of residual master epitaxy after 3D contact is very thin, leading to higher contact resistivity and potentially preventing the realization of the full benefits of the increased contact area.

[0030] In this embodiment, a sacrificial oxide liner is deposited prior to 3D contact etching. The additional oxide liner improves the ingress of the 3D contact etching, resulting in a better / thicker sidewall epitaxy after etching and giving a higher RL. ext Reduced. Furthermore, this oxide liner protects the trench contact (TCN) liner and spacers during etching, thus eliminating yield impact.

[0031] In another embodiment, a very thin B:SiGe layer is grown after 3D contact etching. The grown epitaxial layer is exposed in situ to a gallium-containing metal-organic precursor, such as triethylgallium or trimethylgallium. A 5 × 10⁻⁶ layer is then grown at the top surface of the B:SiGe. -19 Up to 5×10 20 cm -3Gallium doping within a certain range allows for an increase in carrier concentration at the contact surface. The presence of Ga, Ge, and B in the epitaxial growth layer within the trench contact region can be detected using secondary ion mass spectrometry (SIMS), atom probe tomography (APT), cross-sectional transmission electron microscopy (X-TEM), and energy-dispersive X-ray spectroscopy (EDX). SIMS can differentiate between epitaxially deposited Ge:B and B-implanted Ge by the relative amounts of B isotopes (implantation yields only B11, while epitaxial deposition yields both B11 and B10).

[0032] To provide further context, external resistance sources are often a major limiting factor for the performance and efficiency of highly scalable transistors. Reducing contact resistance can improve drive characteristics and enable improved control of the device. Previous efforts to minimize contact resistance have included including additional dopant at trench contact (TCN) locations. However, with the use of various thermal offsets for dopant activation and throughout device fabrication, this approach can be associated with losses in short-channel control due to dopant diffusion into the channel. The resulting drain-induced barrier reduction and high leakage current are some of the short-channel effects that have become increasingly important issues as modern devices scale.

[0033] In the first exemplary processing scheme, Figures 1A-1B The figures illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure having a source or drain structure with vertical trenches having contacts therein, according to embodiments of the present disclosure.

[0034] refer to Figure 1AIn part (a), the initial structure 100 includes a stack of nanowires 104 above corresponding sub-fins 102, such as silicon nanowires above silicon sub-fins. An internal dielectric gate spacer 106 is vertically positioned between adjacent nanowires in the nanowires 104. A gate stack 108, including a gate dielectric and a gate electrode, surrounds the corresponding nanowire in the stack of nanowires 104. An external dielectric gate spacer 110 runs along the upper side of the gate stack 108. A dielectric structure or isolation region 112 is located between adjacent sub-fins 102. An epitaxial source or drain structure 114 (such as an epitaxial silicon or silicon-germanium source or drain structure) is located at the end of the stack of nanowires 104. In one embodiment, the epitaxial source or drain structure 114 is shared between the ends of two adjacent nanowire 104 stacks, as depicted. The epitaxial source or drain structure 114 may include a seed portion 116 and a body portion 118, as depicted. A liner layer or structure 120 / 122 (such as a double-layer liner including portions 120 and 122) lies above the gate structure and partially fills the opening 126 between two adjacent nanowire stacks 104. A portion of the epitaxial source or drain structure 114 remains exposed, as depicted. An etched protective cap 124 is located on the top surface of the liner layer or structure 120 / 122.

[0035] refer to Figure 1A In part (b), an etching process is performed through the remaining opening 126 to form a trench 128 extending into the epitaxial source or drain structure 114, for example, to leave an etched epitaxial source or drain structure 114A with an etched body portion 118A. In one embodiment, the trench has substantially vertical sidewalls and is referred to as a vertical trench.

[0036] refer to Figure 1A Part (c), from Figure 1A Part (b) of the structure removes the etched protective cap 124.

[0037] refer to Figure 1B In part (d), a metal silicide layer 130 (such as a titanium silicide layer) is formed on the sides and bottom of trench 128. In one embodiment, the metal silicide layer 130 is formed by depositing a metal layer in the trench to enable the formation of the metal silicide and then removing the unreacted metal. The consumption of the epitaxial metal leaves an epitaxial source or drain structure 114B having a body portion 118B.

[0038] refer to Figure 1BIn portion (e), a conductive fill 132, such as tungsten fill, is formed in trenches 126 and 128. This structure can be planarized to leave a planarized liner portion 122A. It should be understood that, in other embodiments, the planarized liner portion 122A can be removed in an oxide pre-cleaning operation prior to Ti metal deposition for forming the metal silicide layer 130. It should also be understood that, although not depicted, subsequent [details can be omitted]. Figure 1B The structure of part (e) is processed by subsequent processes.

[0039] In the second exemplary processing scheme, Figures 1C-1D The figure shows a cross-sectional view illustrating various operations in another method of manufacturing a gate-all-around integrated circuit structure having a source or drain structure with vertical trenches having contacts therein, according to another embodiment of the present disclosure.

[0040] refer to Figure 1C Part (a), the initial structure 150 is Figure 1A The structure of part (c).

[0041] refer to Figure 1C In part (b), the liner 122 is removed, and an epitaxial layer 152, such as a boron-doped SiGe (B:SiGe) layer, is formed on the sides and bottom of the trench 126. In one embodiment, the epitaxial layer 152 is exposed in situ to a gallium-containing metal-organic precursor, such as triethylgallium or trimethylgallium. In one such embodiment, a 5 × 10⁻⁶ m² / g²·d⁻¹ ... -19 Up to 5×10 20 cm -3 Gallium is doped into the range of [specific components], which allows for an increase in carrier concentration at the contact surface. In other embodiments, such as for NMOS, P-doped Si is formed.

[0042] refer to Figure 1D In part (c), a metal silicide layer 154 (such as a titanium silicide layer) is formed on the epitaxial layer 152. In one embodiment, the metal silicide layer 154 is formed by depositing a metal layer to enable the formation of the metal silicide and then removing the unreacted metal. The consumption of the epitaxial metal leaves the epitaxial layer 152A.

[0043] refer to Figure 1D In part (d), a conductive filler 156, such as tungsten filler, is formed in the trench 126 and on the metal silicide layer 154. It should be understood that, although not depicted, this can subsequently be interpreted... Figure 1D The structure of part (d) is processed by subsequent processes.

[0044] It should be understood that, in certain embodiments, nanowires, fins, or source or drain structures may be made of silicon. As used throughout, silicon layers can be used to describe silicon materials composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form and may therefore include very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition or may “contaminate” Si during post-deposition processing. Therefore, embodiments involving silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances such as Ge, C, or Sn. It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0045] It should be understood that, in another specific embodiment, the nanowires, fins, or source or drain structures may be made of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material substantially composed of both silicon and germanium (such as at least 5% silicon and germanium). In some embodiments, the amount of germanium is greater than the amount of silicon. In a specific embodiment, the silicon-germanium layer comprises about 60% germanium and about 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises about 30% germanium and about 70% silicon (Si). 70 Ge 30 However, it should be understood that in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and may therefore include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during post-deposition processing. Therefore, the embodiments involving silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (such as carbon or tin). It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0046] It should also be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si). For example, Ge, SiGe, or III-V group materials may be used as channel materials.

[0047] It should be understood that device types other than nanowires (e.g., fins, planar surfaces) can incorporate contacts such as those described above.

[0048] As an example of the process flow for fins, Figures 2A-2EThe figures illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure having a source or drain structure according to an embodiment of the present disclosure, the source or drain structure having vertical trenches with contacts therein.

[0049] refer to Figure 2A Optionally, a channel material 204 is grown on a substrate 202, such as a silicon substrate or a doped silicon substrate. In embodiments, the channel material 204 comprises silicon, for example, the channel material 204 is a silicon layer or a doped silicon layer. In embodiments, the channel material 204 comprises germanium, for example, the channel material 204 is a germanium layer or a doped germanium layer. In embodiments, the channel material 204 comprises both silicon and germanium, for example, the channel material 204 is a silicon-germanium layer or a doped silicon-germanium layer. In embodiments, the channel material 204 is a group III-V material, for example, the channel material 204 is a group III-V material layer or a doped group III-V material layer. In other embodiments, instead of forming a specific channel material 204, the process operations described below are performed on the surface of the substrate 202.

[0050] refer to Figure 2B The channel material 204 is patterned into fins 206. Patterning can form recesses 208 extending into the substrate 202, as depicted.

[0051] refer to Figure 2C The trenches between the fins 206 are filled with a shallow trench isolation material, which is then polished and recessed to form an isolation structure 210. This process may further involve the deposition, patterning, and recessing of a dielectric isolation barrier. The process continues by depositing and patterning gate oxide and gate electrode materials (which may be dummy gate oxide and dummy gate electrode materials) and forming gate spacers to form a gate stack 212 and gate spacers 214.

[0052] refer to Figure 2D Fin 206 is etched at location 218 adjacent to the side of gate stack 212. The etching leaves a channel region 216 below the gate stack 212. The etching may be referred to as a recess at the source or drain location of the fin to form a recess in the source or drain location of the fin.

[0053] refer to Figure 2E A first source or drain structure having an epitaxial structure (left side 220) is embedded in a fin on a first side of the gate stack 212, for example, at position 218. A second source or drain structure including an epitaxial structure (right side 220) is embedded in a fin on a second side of the gate stack 212. Forming each of the first or second source or drain structures may include epitaxially growing silicon or silicon-germanium material in a recess.

[0054] Refer again Figure 2EA first conductive contact portion (left side 230A / 230B) is formed on the epitaxial structure (left side 220) of the first source or drain structure, and a second conductive contact portion (right side 230A / 230B) is formed on the epitaxial structure (right side 220) of the second source or drain structure. In one such embodiment, the first conductive contact portion 230A / 230B and the second conductive contact portion 230A / 230B are respectively formed in a vertical trench (e.g., portion 230B) in each of the epitaxial structures 220 of the first source or drain structure or the second source or drain structure. It should be understood that, although not depicted, subsequent descriptions may be made... Figure 2E The structure is processed in subsequent processes.

[0055] On the other hand, Figure 3A The figure shows a plan view of a plurality of gate lines above a pair of semiconductor fins according to another embodiment of the present disclosure.

[0056] refer to Figure 3A Multiple active gate lines 304 are formed above multiple semiconductor fins 300. Dummy gate lines 306 are located at the ends of the multiple semiconductor fins 300. The spacing 308 between the gate lines 304 / 306 is a location where trench contacts can be positioned to provide conductive contact to source or drain regions (such as source or drain regions 351, 352, 353, and 354). In embodiments, the pattern of the multiple gate lines 304 / 306 or the pattern of the multiple semiconductor fins 300 is described as a grid structure. In one embodiment, the grid pattern includes a pattern of multiple gate lines 304 / 306 and / or multiple semiconductor fins 300 spaced at a constant pitch and having a constant width, or both a pattern of multiple gate lines 304 / 306 and multiple semiconductor fins 300.

[0057] Figure 3B The figure illustrates the path according to an embodiment of the present disclosure. Figure 3A A cross-sectional view taken from the a-a' axis.

[0058] refer to Figure 3B Multiple active gate lines 364 are formed above semiconductor fins 362 formed above a substrate 360. Dummy gate lines 366 are located at the ends of semiconductor fins 362. A dielectric layer 370 is outside the dummy gate lines 366. Trench contact material 397 is between the active gate lines 364 and between the dummy gate lines 366 and the active gate lines 364. An embedded source or drain structure 368 is in the semiconductor fin 362, between the active gate lines 364, and between the dummy gate lines 366 and the active gate lines 364. The embedded source or drain structure 368 includes a vertical trench 369 centrally located therein. Trench contact material 397 is in the vertical trench 369 of the source or drain structure 368. The embedded source or drain structure 368 can be combined as follows: Figure 1B , Figure 1D and Figure 2E The source or drain structure is described.

[0059] The active gate line 364 includes a gate dielectric structure 398 / 399, a work function gate electrode portion 374, a filled gate electrode portion 376, and a dielectric capping layer 378. A dielectric spacer 380 is lining the sidewalls of the active gate line 364 and the dummy gate line 366.

[0060] On the other hand, a trench contact structure for, for example, the source or drain region is described. In the example, Figure 4 The figure shows a cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to another embodiment of the present disclosure.

[0061] refer to Figure 4 The integrated circuit structure 450 includes a fin 452, such as a silicon-germanium fin. A gate dielectric layer 454 is above the fin 452. A gate electrode 456 is above the gate dielectric layer 454. In an embodiment, the gate electrode 456 includes a conformal conductive layer 458 and a conductive fill 460. In an embodiment, a dielectric cap 462 is above the gate electrode 456 and above the gate dielectric layer 454. The gate electrode has a first side 456A and a second side 456B opposite to the first side 456A. ​​A dielectric spacer 463 is along the sidewall of the gate electrode 456. In one embodiment, the gate dielectric layer 454 is further positioned between a first dielectric spacer in the dielectric spacer 463 and the first side 456A of the gate electrode 456, and between a second dielectric spacer in the dielectric spacer 463 and the second side 456B of the gate electrode 456, as depicted. In an embodiment, although not depicted, a thin oxide layer (such as a thermal or chemical silicon oxide or silicon dioxide layer) is located between the fin 452 and the gate dielectric layer 454.

[0062] The first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 are adjacent to the first side 456A and the second side 456B of the gate electrode 456, respectively. In one embodiment, the first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 include embedded epitaxial regions formed in the recesses 465 and 467 of the fin 452, respectively, as depicted. Each of the epitaxial structures of the first source or drain structure and the second source or drain structure has a vertical trench centered therein. The contact structure may include a portion 495B or 497B within the vertical trench, and a portion 495A or 497A above the epitaxial structures of the first source or drain structure and the second source or drain structure, respectively. The embedded source or drain structure may be combined as follows Figure 1B , Figure 1D and Figure 2EThe source or drain structure is described.

[0063] The first trench contact structure 468 and the second trench contact structure 470 are respectively located above the first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 adjacent to the first side 456A and the second side 456B of the gate electrode 456. Both the first trench contact structure 468 and the second trench contact structure 470 include a U-shaped metal layer 472 and a T-shaped metal layer 474 on and over the entire U-shaped metal layer 472. In one embodiment, the U-shaped metal layer 472 and the T-shaped metal layer 474 have different compositions. In one such embodiment, the U-shaped metal layer 472 comprises titanium, and the T-shaped metal layer 474 comprises cobalt. In one embodiment, both the first trench contact structure 468 and the second trench contact structure 470 further include a third metal layer 476 on the T-shaped metal layer 474. In one such embodiment, the third metal layer 476 and the U-shaped metal layer 472 have the same composition. In a particular embodiment, the third metal layer 476 and the U-shaped metal layer 472 comprise titanium, and the T-shaped metal layer 474 comprises cobalt.

[0064] The first trench contact via 478 is electrically connected to the first trench contact 468. In a particular embodiment, the first trench contact via 478 is on and coupled to the third metal layer 476 of the first trench contact 468. The first trench contact via 478 is further located above and in contact with a portion of one of the dielectric spacers 463, and above and in contact with a portion of the dielectric cover 462. The second trench contact via 480 is electrically connected to the second trench contact 470. In a particular embodiment, the second trench contact via 480 is on and coupled to the third metal layer 476 of the second trench contact 470. The second trench contact via 480 is further located above and in contact with a portion of another dielectric spacer 463, and above and in contact with another portion of the dielectric cover 462.

[0065] In one embodiment, the metal silicide layer 482 is directly located between the first trench contact structure 468 and the first semiconductor source or drain region 464, and between the second trench contact structure 470 and the second semiconductor source or drain region 466. In one embodiment, the metal silicide layer 482 comprises titanium and silicon. In a particular embodiment of this kind, the first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 are a first N-type semiconductor source or drain region and a second N-type semiconductor source or drain region. In one embodiment, the metal silicide layer 482 further comprises phosphorus or arsenic, or both phosphorus and arsenic.

[0066] One or more embodiments described herein relate to the use of metal chemical vapor deposition (MCV) for all-around semiconductor contacts. Embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin film fabrication. Specific embodiments may include fabricating a titanium or similar metal layer using low-temperature (e.g., less than 500 degrees Celsius, or in the range of 400-500 degrees Celsius) CVD of the contact metal to provide conformal source or drain contacts. Such conformal source or drain contacts can improve the performance of three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS).

[0067] To provide context, sputtering can be used to deposit metal onto a semiconductor contact layer. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering solutions result in poor or incomplete metal-semiconductor junctions on the device contact surface with varying deposition incident angles. According to one or more embodiments of this disclosure, a low-temperature chemical vapor deposition process is implemented to fabricate contact metals to provide three-dimensional conformal properties and maximize the contact area of ​​the metal-semiconductor junction. The resulting larger contact area can reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having a non-planar topography, where the topography of the region refers to the surface shape and features themselves, and the non-planar topography includes non-planar surface shapes and features or non-planar portions of surface shapes and features, i.e., not perfectly flat surface shapes and features. In embodiments, deposition is performed on a semiconductor surface with a source or drain structure having a relatively high germanium content.

[0068] The embodiments described herein may include the fabrication of a surround contact structure. In one such embodiment, the use of pure metal conformally deposited onto the source-drain contact of a transistor via chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. This conformal deposition can be used to increase the usable area of ​​the metal-semiconductor contact and reduce resistance, thereby improving the performance of the transistor device. In the embodiment, the relatively low deposition temperature minimizes the junction resistance per unit area.

[0069] It should be understood that various integrated circuit structures can be fabricated using integration schemes involving metal layer deposition processes as described herein. According to embodiments of this disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having features thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method further includes reacting titanium tetrachloride (TiCl4) and hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate. In embodiments, the total atomic composition of the titanium layer comprises 98% or more titanium and 0.5-2% chlorine. In alternative embodiments, similar processes are used to fabricate high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V) molybdenum (Mo).

[0070] According to embodiments of this disclosure, the substrate is characterized by exposing source or drain contact trenches of a semiconductor source or drain structure. A titanium layer (or other high-purity metal layer) is used as the conductive contact layer for the semiconductor source or drain structure. The following is in conjunction with... Figure 5 An exemplary embodiment of this implementation is described.

[0071] Figure 5 The figure shows a cross-sectional view of an integrated circuit structure having conductive contacts on a raised source or drain region according to an embodiment of the present disclosure.

[0072] refer to Figure 5 The semiconductor structure 550 includes a gate structure 552 above a substrate 554. The gate structure 552 includes a gate dielectric layer 552A, a work function layer 552B, and a gate fill 552C. A source region 558 and a drain region 560 are located on opposite sides of the gate structure 552. A source or drain contact 562 is electrically connected to the source region 558 and the drain region 560, and is spaced from the gate structure 552 by one or both of an interlayer dielectric layer 564 or a gate dielectric spacer 566. The source region 558 and the drain region 560 include epitaxial or embedded lower material regions formed in an etch-removed region of the substrate 554. Each of the source region 558 and the drain region 560 includes a vertical trench centered therein. The trench contact material 502A / 502B includes a portion 502B in the vertical trench of the source region 558 and the drain region 560. The source region 558 and the drain region 560 can be combined as follows: Figure 1B , Figure 1D and Figure 2E The source or drain structure is described.

[0073] In one embodiment, the source or drain contact 562 includes a high-purity metal layer 562A (as described above) and a conductive trench filler material 562B. In one embodiment, the total atomic composition of the high-purity metal layer 562A comprises 98% or more titanium. In one such embodiment, the total atomic composition of the high-purity metal layer 562A further comprises 0.5-2% chlorine. In one embodiment, the high-purity metal layer 562A has a thickness variation of 30% or less. In another embodiment, the conductive trench filler material 562B is composed of a conductive material, such as, but not limited to, Cu, Al, W, Co, or alloys thereof.

[0074] In another aspect, contact over active gate (COAG) structures and processes are described. One or more embodiments of this disclosure relate to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed over the active portion of the gate electrode of the semiconductor structure or device. One or more embodiments of this disclosure relate to methods of manufacturing such semiconductor structures or devices having one or more gate contact structures formed over the active portion of the gate electrode of the semiconductor structure or device. The methods described herein can be used to reduce the standard cell area by enabling the formation of gate contacts over an active gate region. In one or more embodiments, the gate contact structure manufactured as a contact gate electrode is a self-aligned via structure.

[0075] In embodiments, the integrated circuit structure, semiconductor structure, or device is a non-planar device, such as, but not limited to, a finned FET or a tri-gate device. In such embodiments, the corresponding semiconductor channel region is composed of or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate lines at least surrounds the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is formed as a discrete three-dimensional body, such as in a fully surround gate device. In one such embodiment, each gate electrode stack of a plurality of gate lines completely surrounds the channel region.

[0076] More generally, one or more embodiments relate to a method for directly landing gate contact vias onto the gate of an active transistor and the resulting structure. This method eliminates the need for extending gate lines over isolation for contact purposes. It also eliminates the need for a separate gate contact (GCN) layer for conducting signals from the gate lines or structure. In embodiments, this elimination is achieved by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) during the process flow. The additional dielectric material is included as a trench contact dielectric capping layer, and its etch characteristics differ from the gate dielectric material capping layer (e.g., GILA) already used for trench contact alignment in a gate aligned contact process (GAP) scheme.

[0077] In embodiments, providing an integrated circuit structure involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to dry or plasma etching). In embodiments, the contact pattern is formed using an existing gate pattern by incorporating a contact plugging photolithography operation. In one such embodiment, the method enables the elimination of the need for what would otherwise be a critical photolithography step for generating the contact pattern, as used in other methods. In embodiments, the trench contact mesh is not patterned separately but formed between multiple (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after gate grating patterning but before gate grating dicing.

[0078] Furthermore, gate stack structures can be fabricated by replacing the gate process. In such embodiments, dummy gate materials, such as polysilicon or silicon nitride pillar materials, can be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed during this process, contrary to the use of earlier processing methods. In embodiments, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including an aqueous solution of phosphoric acid.

[0079] In the embodiments, one or more methods described herein essentially envision a combination of dummy and replacement gate processes with dummy and replacement contact processes to realize an integrated circuit structure. In one such embodiment, a replacement contact process is performed after the replacement gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, for instance, after the formation of the gate dielectric layer. The annealing is performed prior to the formation of the permanent contacts.

[0080] It should be understood that different structural relationships can be created between the insulating gate capping layer and the insulating trench contact capping layer. As an example, Figure 6A and Figure 6B The figures illustrate cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure, each integrated circuit structure having a trench contact including an overlying insulating cap and a gate stack including an overlying insulating cap.

[0081] refer to Figure 6A and 6B Integrated circuit structures 600A and 600B each include a fin 602, such as a silicon-germanium fin. Although depicted as a cross-sectional view, it should be understood that the fin 602 has a top 602A and sidewalls (entering and exiting the page shown in the view). A first gate dielectric layer 604 and a second gate dielectric layer 606 are located above the top 602A of the fin 602 and laterally adjacent to the sidewalls of the fin 602. A first gate electrode 608 and a second gate electrode 610 are located above the first gate dielectric layer 604 and the second gate dielectric layer 606, above the top 602A of the fin 602, and laterally adjacent to the sidewalls of the fin 602, respectively. The first gate electrode 608 and the second gate electrode 610 each include a conformal conductive layer 609A (such as a work function setting layer) and a conductive filler material 609B above the conformal conductive layer 609A. Both the first gate electrode 608 and the second gate electrode 610 have a first side 612 and a second side 614 opposite to the first side 612. The first gate electrode 608 and the second gate electrode 610 also have an insulating cover 616, which has a top surface 618.

[0082] refer to Figure 6A and 6B The first dielectric spacer 620 is adjacent to the first side 612 of the first gate electrode 608. The second dielectric spacer 622 is adjacent to the second side 614 of the second gate electrode 610. The semiconductor source or drain region 624 is adjacent to the first dielectric spacer 620 and the second dielectric spacer 622. In one embodiment, the semiconductor source or drain region 624 has a vertical trench centered therein. In another embodiment, the semiconductor source or drain region 624 has a combination as described above. Figure 1B , Figure 1D and Figure 2E And the structures described in other embodiments described herein.

[0083] refer to Figure 6A and Figure 6B The trench contact structure 626 is located above the semiconductor source or drain region 624, adjacent to the first dielectric spacer 620 and the second dielectric spacer 622. The trench contact structure 626 includes an insulating cap 628 on the conductive structure 630. The insulating cap 628 of the trench contact structure 626 has a top surface 629 that is substantially coplanar with the top surfaces 618 of the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610. In an embodiment, the insulating cap 628 of the trench contact structure 626 extends laterally into a recess 632 in the first dielectric spacer 620 and the second dielectric spacer 622. In such embodiments, the insulating cap 628 of the trench contact structure 626 hangs over the conductive structure 630 of the trench contact structure 626. However, in other embodiments, the insulating cap 628 of the trench contact structure 626 does not extend laterally into the recess 632 in the first dielectric spacer 620 and the second dielectric spacer 622, and therefore does not hang over the conductive structure 630 of the trench contact structure 626.

[0084] It should be understood that the conductive structure 630 of the trench contact structure 626 does not have to be rectangular, such as... Figure 6A and Figure 6B As depicted herein. For example, the conductive structure 630 of the trench contact structure 626 can have a design similar to that used for... Figure 6A The conductive structure 630A shown in the projection has a similar or identical cross-sectional geometry to the geometry shown.

[0085] In one embodiment, the insulating cap 628 of the trench contact structure 626 has components different from those of the insulating cap 616 of the first gate electrode 608 and the second gate electrode 610. In one such embodiment, the insulating cap 628 of the trench contact structure 626 comprises a carbide material, such as silicon carbide. The insulating cap 616 of the first gate electrode 608 and the second gate electrode 610 comprises a nitride material, such as silicon nitride.

[0086] In the embodiment, the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610 both have a bottom surface 617A below the bottom surface 628A of the insulating cap 628 of the trench contact structure 626, such as Figure 6A As depicted in the illustration. In another embodiment, the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610 both have a bottom surface 617B that is substantially coplanar with the bottom surface 628B of the insulating cap 628 of the trench contact structure 626, as shown in the illustration. Figure 6BAs depicted in the figure. In another embodiment, although not depicted, the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610 both have a bottom surface above the bottom surface of the insulating cap 628 of the trench contact structure 626.

[0087] In an embodiment, the conductive structure 630 of the trench contact structure 626 includes a U-shaped metal layer 634, a T-shaped metal layer 636 over and across the U-shaped metal layer 634, and a third metal layer 638 on the T-shaped metal layer 636. In an embodiment, the U-shaped metal layer 634 further includes an extension 634A in a vertical trench within a semiconductor source or drain region 624, as depicted. An insulating cap 628 of the trench contact structure 626 is on the third metal layer 638. In one such embodiment, the third metal layer 638 and the U-shaped metal layer 634 comprise titanium, and the T-shaped metal layer 636 comprises cobalt. In a particular such embodiment, the T-shaped metal layer 636 further comprises carbon.

[0088] In one embodiment, the metal silicide layer 640 is located directly between the conductive structure 630 of the trench contact structure 626 and the semiconductor source or drain region 624. In one such embodiment, the metal silicide layer 640 comprises titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 624 is an N-type semiconductor source or drain region.

[0089] As described throughout this application, the substrate may be composed of a semiconductor material capable of withstanding fabrication processes and in which charge can migrate. In embodiments, the substrate described herein is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof) for forming active regions. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate). The bulk substrate may alternatively be composed of a III-V material. In embodiments, the bulk substrate is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a III-V material, and the charge carrier dopant impurity atoms are charge carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0090] As described throughout this application, isolation regions (such as shallow trench isolation regions or sub-fin isolation regions) may be composed of materials suitable for ultimately electrically isolating portions of a permanent gate structure from an underlying bulk substrate, or facilitating the electrical isolation of portions of a permanent gate structure from an underlying bulk substrate, or isolating active regions (such as isolation fin active regions) formed within the underlying bulk substrate. For example, in one embodiment, the isolation region comprises one or more layers of dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or combinations thereof.

[0091] As described throughout this application, a gate line or gate structure can be formed by a gate electrode stack, which includes a gate dielectric layer and a gate electrode layer. In embodiments, the gate electrode in the gate electrode stack is formed by a metal gate, and the gate dielectric layer is formed by a high-k material. For example, in one embodiment, the gate dielectric layer is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a native oxide layer formed from the top layers of a semiconductor substrate. In embodiments, the gate dielectric layer is formed by a top high-k portion and a lower portion composed of an oxide of the semiconductor material. In one embodiment, the gate dielectric layer is formed by a hafnium oxide top portion and a silicon dioxide or silicon oxynitride bottom portion. In some implementations, the gate dielectric portion is a "U"-shaped structure, comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0092] In one embodiment, the gate electrode comprises a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-work function filling material formed over a metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a power function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and excluding the sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of this disclosure, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0093] As described throughout this application, spacers associated with gate lines or electrode stacks may be made of materials suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts) or facilitating the isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are made of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0094] In embodiments, the methods described herein may involve forming contact patterns that are very well aligned with existing gate patterns, while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to dry or plasma etching). In embodiments, the contact patterns are formed using existing gate patterns by incorporating contact plugging photolithography operations. In one such embodiment, the method enables the elimination of the need for otherwise critical photolithography operations used in other methods to generate contact patterns. In embodiments, the trench contact mesh is not patterned separately but formed between multiple (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after gate grating patterning but before gate grating dicing.

[0095] Spacing division and patterning schemes can be implemented to achieve the embodiments described herein, or can be included as part of the embodiments described herein. Spacing division patterning typically refers to spacing bisecting, spacing quarticing, etc. Spacing division schemes can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first performed to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) at predetermined spacing. Then, spacing division processing is implemented as a technique for increasing line density.

[0096] In embodiments, the term "grating structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a closely pitched grating structure. In one such embodiment, the close pitch cannot be directly achieved by a selected lithography. For example, a pattern based on the selected lithography can be formed first, but the pitch can be bisected by using spacer mask patterning, as is known in the art. Furthermore, the original pitch can be quartered by a second round of spacer mask patterning. Thus, the grating-like pattern described herein can have metal lines, ILD lines, or hard mask lines with substantially uniform pitch spacing and substantially uniform width. For example, in some embodiments, the pitch variation is within 10 percent and the width variation is within 10 percent, and in some embodiments, the pitch variation is within 5 percent and the width variation is within 5 percent. The pattern can be fabricated by pitch bisecting, pitch quartering, or other pitch division methods. In embodiments, the grating is not necessarily single-pitched.

[0097] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or by other deposition methods.

[0098] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack or alloy of different metals, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including a conductive liner layer and a filler layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0099] In embodiments, as used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivity toward each other and toward the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metallic substance. For example, the hard mask or other overlay material may comprise a layer of titanium nitride or a nitride of another metal (e.g., titanium nitride). One or more of these layers may potentially include smaller amounts of other materials, such as oxygen. Alternatively, depending on the specific implementation, other hard mask layers known in the art may be used. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0100] In embodiments, as used throughout this specification, lithography operations are performed using methods such as 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0101] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of this disclosure. For example, in one embodiment, a dummy gate is never required before the gate contact is fabricated over the active portion of the gate stack. The gate stack described above can actually be a permanently formed, initially constructed gate stack. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device can be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Furthermore, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, a dual-gate device with independent access, a FIN-FET, a nanowire device, or a nanoribbon device. One or more embodiments may be particularly useful for fabricating semiconductor devices at the 10-nanometer (10nm) technology node or sub-10-nanometer (10nm) technology node.

[0102] Additional or intermediate operations used for the fabrication of FEOL layers or structures may include standard microelectronics manufacturing processes such as photolithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other actions associated with the fabrication of microelectronic components. Furthermore, it should be understood that the process operations described for the foregoing process flow may be practiced in an alternative sequence; not every operation needs to be performed, or additional process operations may be performed.

[0103] It should be understood that in the exemplary FEOL embodiments described above, 10nm or sub-10nm node processing is directly implemented as a technology driver into the manufacturing process and the resulting structure. In other embodiments, FEOL is considered to be driven by BEOL 10nm or sub-10nm processing requirements. For example, the material selection and layout of the FEOL layer and devices may need to be adapted to BEOL processing. In one such embodiment, material selection and gate stack architecture are chosen to accommodate the high-density metallization of the BEOL layer, for example, to reduce edge capacitance in transistor structures formed in the FEOL layer but coupled together through the high-density metallization of the BEOL layer.

[0104] The embodiments disclosed herein can be used to manufacture various types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, they can be used in computer systems (e.g., desktop computers, laptops, servers), cellular phones, personal electronic products, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0105] Figure 7 The figure illustrates a computing device 700 according to one implementation of the present disclosure. The computing device 700 houses a board 702. The board 702 may include multiple components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, at least one communication chip 706 is also physically and electrically coupled to the board 702. In a further implementation, the communication chip 706 is part of the processor 704.

[0106] Depending on its application, computing device 700 may include other components that may be physically and electrically coupled to board 702 or may not be physically and electrically coupled to board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0107] Communication chip 706 implements wireless communication for transmitting data to and from computing device 700. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that enable data transmission through a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, but in some embodiments, the associated device may not contain any wires. Communication chip 706 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and higher generations. Computing device 700 may include multiple communication chips 706. For example, the first communication chip 706 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 706 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0108] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of embodiments of this disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures constructed according to implementations of this disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from registers or memory, or both registers and memory, to convert such electronic data into other electronic data that can be stored in registers or memory, or both registers and memory.

[0109] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. According to another implementation of this disclosure, the integrated circuit die of the communication chip is constructed according to an implementation of this disclosure.

[0110] In a further implementation, another component housed within the computing device 700 may comprise an integrated circuit die constructed according to an implementation of an embodiment of the present disclosure.

[0111] In various embodiments, the computing device 700 may be a laptop, netbook, notebook computer, ultrabook, smartphone, tablet device, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

[0112] Figure 8 The figure illustrates an interposer 800 including one or more embodiments of the present disclosure. The interposer 800 is an intermediate substrate for bridging a first substrate 802 to a second substrate 804. The first substrate 802 may be, for example, an integrated circuit die. The second substrate 804 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 800 is to extend connections to a wider pitch or to reroute connections to different connections. For example, the interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806, which may then be coupled to the second substrate 804. In some embodiments, the first substrate 802 and the second substrate 804 are attached to opposite sides of the interposer 800. In other embodiments, the first substrate 802 and the second substrate 804 are attached to the same side of the interposer 800. And in a further embodiment, three or more substrates are interconnected by means of the interposer 800.

[0113] Interposer 800 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (such as polyimide). In a further embodiment, interposer 800 may be formed of an alternative rigid or flexible material, including the same materials described above used in semiconductor substrates (such as silicon, germanium, and other Group III-V and Group IV materials).

[0114] Interposer 800 may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. Interposer 800 may further include embedded devices 814, which may include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 800. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used to manufacture interposer 800 or components included in interposer 800.

[0115] Figure 9 This is an isometric view of a mobile computing platform 900 manufactured using one or more processes described herein or including one or more features described herein, according to embodiments of this disclosure.

[0116] Mobile computing platform 900 can be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform 900 can be any of a tablet device, smartphone, laptop, etc., and includes a display 905, a chip-level (SoC) or package-level integrated system 910, and a battery 913. In an exemplary embodiment, display 905 is a touchscreen (capacitive, inductive, resistive, etc.). As illustrated, the higher the level of integration in system 910, achieved with higher transistor package density, the larger the portion of mobile computing platform 900 that can be occupied by battery 913 or non-volatile storage devices (such as solid-state drives), or the larger the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in system 910, the greater the functionality. Therefore, the techniques described herein can achieve performance and form factor improvements in mobile computing platform 900.

[0117] The integrated system 910 is further illustrated in expanded view 920. In an exemplary embodiment, package device 977 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) manufactured according to one or more processes described herein or including one or more features described herein. Package device 977, together with one or more of the following: power management integrated circuit (PMIC) 915, RF integrated circuit (RFIC) 925 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module, further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and controller 911, is further coupled to board 960. Functionally, PMIC 915 performs battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to battery 913 and an output that supplies current to all other functional modules. As further illustrated, in an exemplary embodiment, RFIC 925 has an output coupled to an antenna to provide for implementing any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols referred to as 3G, 4G, and higher generations. In an alternative implementation, each of these board-level modules may be integrated onto a separate IC coupled to the package substrate of package device 977, or integrated within a single IC (SoC) coupled to the package substrate of package device 977.

[0118] On the other hand, semiconductor packages are used to protect integrated circuit (IC) chips or dies and also provide electrical interfaces for the dies to external circuit systems. With the increasing demand for smaller electronic devices, semiconductor packages are being designed to be more compact and must support greater circuit density. Furthermore, the need for higher-performance devices has led to a demand for improved semiconductor packages that achieve thinner package profiles and lower overall warpage compatible with subsequent component handling.

[0119] In one embodiment, wire bonding is used with a ceramic or organic packaging substrate. In another embodiment, a C4 process is used to mount the die to a ceramic or organic packaging substrate. Specifically, C4 solder ball connections can be implemented to provide a flip-chip interconnect between the semiconductor device and the substrate. Flip-chip, or controlled collapse chip connection (C4), is a mounting type for semiconductor devices such as integrated circuit (IC) chips, MEMS, or components that utilizes solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads located on the top side of the substrate package. To mount the semiconductor device onto the substrate, it is flipped so that the active side is facing down on the mounting area. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0120] Figure 10 The figure shows a cross-sectional view of a flip-chip mounting die according to an embodiment of the present disclosure.

[0121] refer to Figure 10 According to embodiments of this disclosure, device 1000 includes a die 1002, such as an integrated circuit (IC) manufactured using one or more processes described herein or including one or more features described herein. Die 1002 includes metallized pads 1004 thereon. A package substrate 1006, such as a ceramic or organic substrate, includes connections 1008 thereon. Die 1002 and package substrate 1006 are electrically connected via solder balls 1010 coupled to the metallized pads 1004 and connections 1008. Underfill material 1012 surrounds the solder balls 1010.

[0122] Handling flip chips can be similar to conventional IC manufacturing, with some additional steps. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. A small dot of solder is then deposited on each metallized pad. The chip is then cut normally from the wafer. To attach the flip chip to the circuitry, the chip is inverted to bring the solder dots down onto the underlying electronics or connectors on the circuit board. The solder is then remelted to create the electrical connection, typically using ultrasonic welding or, alternatively, a reflow solder process. This also leaves a small gap between the chip's circuitry and the underlying mounting. In most cases, the electrical insulating adhesive is then "underfilled" to provide a stronger mechanical bond, provide thermal bridging, and ensure that the solder joints are not stressed due to the different heating of the chip and the rest of the system.

[0123] In other embodiments, according to embodiments of this disclosure, newer packaging and die-to-die interconnect methods (such as through-silicon vias (TSVs) and silicon interposers) are implemented to fabricate high-performance multi-chip modules (MCMs) and system-in-packages (SiPs) that incorporate integrated circuits (ICs) fabricated according to one or more processes described herein or including one or more features described herein.

[0124] Therefore, embodiments of this disclosure include: an integrated circuit structure having a source or drain structure with a vertical trench having a contact portion therein, and a method for manufacturing an integrated circuit structure having a source or drain structure with a vertical trench having a contact portion therein.

[0125] The above description of the illustrated implementations of this disclosure (including those described in the abstract) is not intended to be exhaustive, nor is it intended to limit this disclosure to the precise forms disclosed. Although specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be appreciated by those skilled in the art. These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific implementations disclosed in the specification and claims.

[0126] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment has been described for a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The foregoing description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art benefiting from this disclosure.

[0127] The scope of this disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. Specifically, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from individual independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0128] Various embodiments or aspects of this disclosure are described herein. In some implementations, different embodiments are practiced separately. However, embodiments are not limited to those practiced individually. For example, two or more different embodiments may be combined together to be practiced as a single device, process, structure, etc. In some instances, the entirety of the embodiments may be combined together. In other instances, portions of a first embodiment may be combined with portions of one or more different embodiments. For example, portions of a first embodiment may be combined with portions of a second embodiment, or portions of a first embodiment may be combined with portions of a second embodiment and portions of a third embodiment. The following examples relate to further embodiments. Various features of different embodiments can be combined in various ways with some included features and other excluded features to suit a variety of different applications.

[0129] Example 1: An integrated circuit structure comprising a nanowire stack above a sub-fin. An epitaxial source or drain structure is located at the end of the nanowire stack, and the epitaxial source or drain structure has a trench therein. Conductive contacts are located in the trench and extend above the epitaxial source or drain structure.

[0130] Example 2: The integrated circuit structure of Example 1 further includes: a layer comprising silicon and titanium, the layer being located in a trench and between an epitaxial source or drain structure and a conductive contact.

[0131] Example 3: The integrated circuit structure of Example 1 or 2 further includes a second nanowire stack, wherein an epitaxial source or drain structure is located at the end of the second nanowire stack.

[0132] Example 4: An integrated circuit structure of Example 1 or 2, wherein the conductive contact portion includes tungsten.

[0133] Example 5: An integrated circuit structure of Example 1, 2, 3 or 4, wherein the epitaxial source or drain structure includes silicon and germanium.

[0134] Example 6: An integrated circuit structure comprising a nanowire stack above a sub-fin. An epitaxial source or drain structure is located at the end of the nanowire stack, the epitaxial source or drain structure having a trench therein. An epitaxial layer comprising gallium runs along the sides and bottom of the trench. Conductive contacts are located within the epitaxial layer and extend above the epitaxial layer.

[0135] Example 7: The integrated circuit structure of Example 6 further includes: a layer comprising silicon and titanium, the layer being disposed between the epitaxial layer and the conductive contact.

[0136] Example 8: The integrated circuit structure of Example 6 or 7 further includes a second nanowire stack, wherein an epitaxial source or drain structure is located at the end of the second nanowire stack.

[0137] Example 9: An integrated circuit structure of Example 6, 7 or 8, wherein the conductive contacts include tungsten.

[0138] Example 10: An integrated circuit structure of Example 6, 7, 8 or 9, wherein the epitaxial source or drain structure comprises silicon and germanium, and wherein the epitaxial layer comprises silicon, germanium, boron and gallium.

[0139] Example 11: A computing device comprising: a board, and a component coupled to the board. The component includes an integrated circuit structure comprising a nanowire stack above a sub-fin. An epitaxial source or drain structure is located at the end of the nanowire stack, the epitaxial source or drain structure having a trench therein. A conductive contact is located in the trench and extends above the epitaxial source or drain structure; or an epitaxial layer runs along the sides and bottom of the trench, and the conductive contact is located within the epitaxial layer and extends above the epitaxial layer, wherein the epitaxial layer comprises gallium.

[0140] Example 12: The computing device of Example 11 includes a conductive contact located in a trench and extending over an epitaxial source or drain structure.

[0141] Example 13: The computing device of Example 11 includes an epitaxial layer along the sides and bottom of a trench, and a conductive contact located within and extending above the epitaxial layer.

[0142] Example 14: A computing device of Example 11, 12 or 13, further including a memory coupled to a board.

[0143] Example 15: A computing device of Example 11, 12, 13 or 14, further including a communication chip coupled to a board.

[0144] Example 16: The computing device of Example 11, 12, 13, 14 or 15, further includes a battery coupled to a plate.

[0145] Example 17: The computing device of Example 11, 12, 13, 14, 15 or 16, further includes a camera coupled to the board.

[0146] Example 18: The computing device of Example 11, 12, 13, 14, 15, 16 or 17, further includes a display coupled to the board.

[0147] Example 19: A computing device of Example 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0148] Example 20: A computing device of Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: Nanowire stacking above the sub-fins; An epitaxial source or drain structure located at the end of the nanowire stack, wherein the epitaxial source or drain structure has a trench therein; as well as A conductive contact located in the trench and extending above the epitaxial source or drain structure.

2. The integrated circuit structure according to claim 1, further comprising: A layer comprising silicon and titanium, the layer being located in the trench and between the epitaxial source or drain structure and the conductive contact.

3. The integrated circuit structure according to claim 1 or 2, further comprising: The second nanowire stack, wherein the epitaxial source or drain structure is located at the end of the second nanowire stack.

4. The integrated circuit structure according to claim 1 or 2, wherein, The conductive contact portion includes tungsten.

5. The integrated circuit structure according to claim 1 or 2, wherein, The epitaxial source or drain structure includes silicon and germanium.

6. An integrated circuit structure, comprising: Nanowire stacking above the sub-fins; An epitaxial source or drain structure located at the end of the nanowire stack, wherein the epitaxial source or drain structure has a trench therein; An epitaxial layer comprising gallium along the sides and bottom of the trench; and A conductive contact located within and extending above the epitaxial layer.

7. The integrated circuit structure according to claim 6, further comprising: A layer comprising silicon and titanium, the layer being situated between the epitaxial layer and the conductive contact portion.

8. The integrated circuit structure according to claim 6 or 7, further comprising: The second nanowire stack, wherein the epitaxial source or drain structure is located at the end of the second nanowire stack.

9. The integrated circuit structure according to claim 6 or 7, wherein, The conductive contact portion includes tungsten.

10. The integrated circuit structure according to claim 6 or 7, wherein, The epitaxial source or drain structure comprises silicon and germanium, and wherein the epitaxial layer comprises silicon, germanium, boron, and gallium.

11. A computing device, comprising: plate; as well as Components, coupled to the board, the components including an integrated circuit structure, the integrated circuit structure comprising: Nanowire stacking above the sub-fins; An epitaxial source or drain structure located at the end of the nanowire stack, the epitaxial source or drain structure having a trench therein; and A conductive contact located in the trench and extending above the epitaxial source or drain structure, or An epitaxial layer comprising gallium along the sides and bottom of the trench, and... A conductive contact located within and extending above the epitaxial layer.

12. The computing device of claim 11, comprising the conductive contact located in the trench and extending above the epitaxial source or drain structure.

13. The computing device of claim 11, comprising the epitaxial layer along the side and bottom of the trench, and the conductive contact located within and extending above the epitaxial layer.

14. The computing device according to claim 11, 12 or 13, further comprising: The memory is coupled to the board.

15. The computing device according to claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device according to claim 11, 12 or 13, further comprising: The battery is coupled to the plate.

17. The computing device according to claim 11, 12 or 13, further comprising: The camera is coupled to the plate.

18. The computing device according to claim 11, 12 or 13, further comprising: The display is coupled to the board.

19. The computing device according to claim 11, 12 or 13, wherein, The component in question is a packaged integrated circuit die.

20. The computing device according to claim 11, 12 or 13, wherein, The component is selected from a group consisting of a processor, a communication chip, and a digital signal processor.

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