Gate-all-around integrated circuit structure with differentiated release layer

Abstract

A gate-all-around integrated circuit structure with differentiated release layers is described. For example, an integrated circuit structure includes a first set of horizontal nanowires over a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. The second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. A dielectric spacer is adjacent to the first and second gate structures and is vertically between adjacent nanowires of the first and second sets of horizontal nanowires. Each of the dielectric spacers has a notch at a location vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

Description

Background Technology

[0001] For decades, the scaling of features in integrated circuits has been a driving force behind the ever-evolving semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of a greater number of memory or logic devices on a single chip, thus facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The necessity of optimizing the performance of each device becomes increasingly apparent.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors (such as tri-gate transistors) have become increasingly prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are generally fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and the less complex tri-gate fabrication process they enable. On the other hand, as the dimensions of microelectronic devices scale below the 10-nanometer (nm) node, maintaining improved mobility and short-channel control presents challenges in device fabrication. Nanowires used to fabricate devices offer improved short-channel control.

[0003] However, scaling up multi-gate and nanowire transistors has not been without consequences. As the size of these basic building blocks of microelectronic circuit systems decreases and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the photolithography processes used to pattern these building blocks become overwhelming. Specifically, there may be a trade-off between the minimum size (critical size) of the features patterned in a semiconductor stack and the spacing between such features. Attached Figure Description

[0004] Figure 1A The figures illustrate cross-sectional views of various operations in a method for fabricating an integrated circuit structure using a differential release layer, according to embodiments of the present disclosure.

[0005] Figure 1B The figure shows a cross-sectional view of an integrated circuit structure formed using a differential release layer according to an embodiment of the present disclosure.

[0006] Figures 2A-2D The figures illustrate cross-sectional views of various operations in a method for fabricating an integrated circuit structure using a differential release layer, according to embodiments of the present disclosure.

[0007] Figures 3A-3DThe figures illustrate cross-sectional views of various operations in a method of manufacturing another gate-all-around integrated circuit structure having a depopulated channel structure, according to embodiments of the present disclosure.

[0008] Figures 4A-4J The figures illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to embodiments of the present disclosure.

[0009] Figure 5 The figure shows a cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure.

[0010] Figure 6 The figure shows a cross-sectional view of nanowires and fins of a non-endcap architecture (left side (a)) relative to a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0011] Figure 7 The figures illustrate cross-sectional views of various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a fully surrounding gate device, according to embodiments of the present disclosure.

[0012] Figure 8A The figure shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure.

[0013] Figure 8B The figure illustrates a section taken along the a-a' axis according to an embodiment of the present disclosure. Figure 8A A cross-sectional source or drain view of a nanowire-based integrated circuit structure.

[0014] Figure 8C The figure illustrates a section taken along the b-b' axis according to an embodiment of the present disclosure. Figure 8A A cross-sectional channel view of a nanowire-based integrated circuit structure.

[0015] Figures 9A-9E The figures illustrate three-dimensional cross-sectional views of various operations in a method for manufacturing nanowire portions of a fin / nanowire structure according to embodiments of the present disclosure.

[0016] Figure 10 The figure illustrates a computing device according to one implementation of an embodiment of the present disclosure.

[0017] Figure 11 The figure illustrates an intermediary layer that includes one or more embodiments of this disclosure. Detailed Implementation

[0018] A gate-all-around integrated circuit structure with a differentiated release layer and a method for manufacturing such a structure are described. Numerous specific details, such as specific integration and material schemes, are set forth in the following description to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail so as not to unnecessarily obscure embodiments of this disclosure. Furthermore, it should be understood that the embodiments illustrated in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0019] Certain terms may also be used for illustrative purposes only in the foregoing description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “rear,” “rear,” and “side” describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, which is made clear by reference to the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0020] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structure. FEOL is the first part of integrated circuit (IC) fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any lines).

[0021] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. During the manufacturing phase, interconnects, vias, and dielectric structures are formed in the BEOL portion of the contacts (pads). For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0022] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. Specifically, although an FEOL processing scenario can be used to illustrate exemplary processing schemes, such methods can also be applied to BEOL processing. Similarly, although a BEOL processing scenario can be used to illustrate exemplary processing schemes, such methods can also be applied to FEOL processing.

[0023] One or more embodiments described herein relate to complementary field-effect transistors (CFETs) formed using differentiated release layers, such as complementary FET (CFET) double-release processing. One or more embodiments relate to double-release laminar flow for CFET fabrication. It should be understood that, unless otherwise indicated, the reference to nanowire herein may refer to a nanowire, nanoribbon, or nanosheet.

[0024] To provide context, a CFET architecture is one in which two transistors are stacked on top of each other. In a CFET architecture, the top device can be either an NMOS or a PMOS, and the bottom device typically uses the opposite type to the top device.

[0025] To provide further context, current nanowire release layer processing in CFETs uses a single round of nanowire release layer to handle both N / P. Each nanowire release process may have a yield / performance trade-off between N / P. A process with separate rounds of nanowire release layer to utilize different processes could be beneficial.

[0026] According to one or more embodiments of this disclosure, a carbon hard mask (CHM) recess and physical vapor deposition (PVD) protective liner scheme is used to first protect the upper stack (N or P) from the effects of sacrificial gate oxide (GOX) removal and nanowire release. After the desired wire is released, the structure is again covered with a CHM recess to remove the liner and the top sacrificial release layer (e.g., SiGe). The CHM is then removed to continue high-k (HK) pre-cleaning and deposition, and finally, gate electrode formation. In one embodiment, the release layer of the upper stack is formed using SiGe with a lower Ge concentration to enhance N / P separation during CFET patterned nanowire release.

[0027] The process flow is described as an example. Figure 1AThe figures illustrate cross-sectional views of various operations in a method for fabricating an integrated circuit structure using a differential release layer, according to embodiments of the present disclosure.

[0028] refer to Figure 1A In part (a), the initial structure 100 includes a first set of horizontal nanowires 104 (e.g., silicon nanowires above a silicon sub-fin) above a sub-fin structure 102, which is situated within a trench dielectric layer 103. A first release layer 106 (such as a first silicon-germanium layer) is interleaved with the first set of horizontal nanowires 104. A second set of horizontal nanowires 108 (such as a second set of silicon nanowires) is situated above the first set of horizontal nanowires 104. A second release layer 110 (such as a second silicon-germanium layer) is interleaved with the second set of horizontal nanowires 108. A sacrificial gate oxide layer 112 (such as a silicon oxide layer) is situated above the second set of horizontal nanowires 108 and the first set of horizontal nanowires 104.

[0029] Refer again Figure 1A In part (a) of the embodiment, the first set of horizontal nanowires 104 is ultimately used to form a P-device, and the second set of horizontal nanowires 108 is ultimately used to form an N-device, as depicted. In another embodiment, the first set of horizontal nanowires 104 is ultimately used to form an N-device, and the second set of horizontal nanowires 108 is ultimately used to form a P-device.

[0030] Refer again Figure 1A In part (a) of the embodiment, the first release layer 106 and the second release layer 110 have the same composition. In another embodiment, as depicted, the first release layer 106 and the second release layer 110 have different compositions. In one such embodiment, the second release layer 110 is a SiGe release layer with a germanium-to-silicon ratio less than that of the first release layer 106. In another such embodiment, the second release layer 110 is a SiGe release layer with a germanium-to-silicon ratio greater than that of the first release layer 106.

[0031] It should be understood that, although not described, it is in combination Figure 1A Prior to the processing described in part (b), the first release layer 106 and the second release layer 110 may be partially laterally recessed relative to the first set of horizontal nanowires 104 and the second set of horizontal nanowires 108, respectively. In one such embodiment, an inner gate spacer or an internal gate spacer or a recessed gate spacer may be formed in the recess or cavity created by the recess.

[0032] refer to Figure 1AIn part (b), the lower portion of the sacrificial gate oxide layer 112 is removed, and the first set of horizontal nanowires 104 is released by removing the first release layer 106. During the processing of the lower portion of this structure, the upper portion of the sacrificial gate oxide layer 112 and the second release layer 110 are protected by a protective liner 114.

[0033] refer to Figure 1A In part (c), a second sacrificial gate oxide layer 116 is formed around the released first set of horizontal nanowires 104. A hard mask 118 (such as a carbon hard mask) is formed by deposition and recess to protect the lower part of the structure. For the upper part of the structure, the protective liner 114 is removed, the upper part of the sacrificial gate oxide layer 112, and the second release layer 110 are removed to release the second set of horizontal nanowires 108.

[0034] Subsequent processing may include the removal of the hard mask 118 and the second sacrificial gate oxide layer 116, followed by the formation of a permanent gate dielectric and gate electrode, which can distinguish between N-devices and P-devices in a CFET stack.

[0035] Advantages of implementing the embodiments described herein may include providing flexibility to maximize yield and performance gains by utilizing optimal nanowire release processes for NMOS and PMOS. For example, a first release process may result in better performance for the resulting N-device, while a second release process may result in better performance for the resulting P-device.

[0036] The detectability of the embodiments described herein may include reverse engineering combined with TEM to observe NP boundaries with horizontal lines and spacer erosion. Such artifacts may be unavoidable because the boundaries are exposed to two dielectric etchings. Previous single-round etchings may not have exhibited such boundary features.

[0037] As an example of a release structure, Figure 1B The figure shows a cross-sectional view of an integrated circuit structure formed using a differential release layer according to an embodiment of the present disclosure.

[0038] refer to Figure 1B The intermediate integrated circuit structure 120 includes a first set of horizontal nanowires 124 (e.g., silicon nanowires above a silicon sub-fin) above a sub-fin structure 122. A second set of horizontal nanowires 126 (such as a second set of silicon nanowires) is positioned above the first set of horizontal nanowires 124. In an embodiment, a dual nanowire release scheme is used to release the first set of horizontal nanowires 124 and the second set of horizontal nanowires 126, such as combining... Figure 1A and Figures 2A-2D As described.

[0039] In one embodiment, the first set of horizontal nanowires 124 is ultimately used to form a P-device, and the second set of horizontal nanowires 126 is ultimately used to form an N-device. In another embodiment, the first set of horizontal nanowires 124 is ultimately used to form an N-device, and the second set of horizontal nanowires 126 is ultimately used to form a P-device.

[0040] Refer again Figure 1B A first epitaxial source or drain structure 128 is formed at the end of the first set of horizontal nanowires 124. A second epitaxial source or drain structure 130 is formed at the end of the second set of horizontal nanowires 126. As depicted, the first epitaxial source or drain structure 128 may have a different composition than the second epitaxial source or drain structure 130. As also depicted, a dielectric layer 131 may be included on and around the first epitaxial source or drain structure 128 and the second epitaxial source or drain structure 130.

[0041] Refer again Figure 1B Gate spacer 132 is situated above the first set of horizontal nanowires 124 and the second set of horizontal nanowires 126, and defines a gate trench 150. According to embodiments of this disclosure, a notch 134 is included in the spacer at the P / N boundary between the first set of horizontal nanowires 124 and the second set of horizontal nanowires 126, as depicted, due to dual-release flow. In one embodiment, the first set of horizontal nanowires 124 may have an associated roughness 138 different from the associated roughness 136 of the second set of horizontal nanowires 126, as also depicted, due to dual-release flow. In an embodiment, Figure 1B Structure 120 can be formed prior to the completion of the dual-release process flow by partially laterally recessing the release layer of the dual-release laminar flow relative to the first set of horizontal nanowires and the second set of horizontal nanowires, respectively. In one such embodiment, an inner gate spacer, an internal gate spacer, or a recessed gate spacer can be formed in the recess or cavity created by the recess.

[0042] Refer again Figure 1B Subsequent processing of structure 120 may include the formation of a permanent gate dielectric and a gate electrode in gate trench 150, either of which can distinguish between N-devices and P-devices in a CFET stack.

[0043] According to one or more embodiments of this disclosure, as a more detailed process, the process begins with a standard release stack (or a reduced Ge% stack on top). This process can utilize carbon hard mask (CHM) deposition and recessing to achieve CHM levels at the N / P boundary. PVD TiN can be sputtered on top of the exposed nanoribbon stack prior to CHM ashing, leaving TiN only on the upper half of the fins and gate sidewalls. Gate oxide removal and a first nanowire release are performed to remove sacrificial SiGe for the bottom stack. If a low Ge% is used, selectivity may prevent complete removal of SiGe from the bottom of the top stack. CHM deposition and recessing are performed again for landing at the N / P boundary. TiN is then removed from the top stack. Gate oxide removal and a second nanowire release can then be performed with the CHM blocking the bottom stack, thereby removing SiGe only in the top stack. Oxide passivation can be performed around the Si nanowires prior to CHM ashing to protect the interface. After CHM removal, the process can follow high-k pre-cleaning and deposition, as well as gate formation, etc.

[0044] As an example, here is a detailed process flow. Figures 2A-2D The figures illustrate cross-sectional views of various operations in a method for fabricating an integrated circuit structure using a differential release layer, according to embodiments of the present disclosure.

[0045] refer to Figure 2A In part (a), the initial structure 200 includes a first set of horizontal nanowires 204 (e.g., silicon nanowires above a silicon sub-fin) above a sub-fin structure 202 situated within a trench dielectric layer 203. A first release layer 206 (such as a first silicon-germanium layer) is interleaved with the first set of horizontal nanowires 204. A second set of horizontal nanowires 208 (such as a second set of silicon nanowires) is situated above the first set of horizontal nanowires 204. A second release layer 210 (such as a second silicon-germanium layer) is interleaved with the second set of horizontal nanowires 208. A sacrificial gate oxide layer 212 (such as a silicon oxide layer) is situated above the second set of horizontal nanowires 208 and the first set of horizontal nanowires 204.

[0046] Refer again Figure 2A In part (a) of the embodiment, the first set of horizontal nanowires 204 is ultimately used to form a P-device, and the second set of horizontal nanowires 208 is ultimately used to form an N-device, as depicted. In another embodiment, the first set of horizontal nanowires 204 is ultimately used to form an N-device, and the second set of horizontal nanowires 208 is ultimately used to form a P-device. In either case, the location of the PN junction is depicted by dashed lines.

[0047] Refer again Figure 2AIn part (a) of the embodiment, the first release layer 206 and the second release layer 210 have the same composition. In another embodiment, as depicted, the first release layer 206 and the second release layer 210 have different compositions. In one such embodiment, the second release layer 210 is a SiGe release layer with a germanium-to-silicon ratio less than that of the first release layer 206. In another such embodiment, the second release layer 210 is a SiGe release layer with a germanium-to-silicon ratio greater than that of the first release layer 206.

[0048] It should be understood that, although not described, it is in combination Figure 2A Prior to the processing described in part (b), the first release layer 206 and the second release layer 210 may be partially laterally recessed relative to the first set of horizontal nanowires 204 and the second set of horizontal nanowires 208, respectively. In one such embodiment, an inner gate spacer or an internal gate spacer or a recessed gate spacer may be formed in the recess or cavity created by the recess.

[0049] refer to Figure 2A In part (b), a hard mask 214 (such as a carbon hard mask) is formed on the starting structure 200.

[0050] refer to Figure 2A In part (c), the hard mask 214 is recessed near the P / N junction line to form a recessed hard mask 214A.

[0051] refer to Figure 2A Part (d), the protective lining 216 (e.g., by PVD) is formed in Figure 2A Above the structure of part (c).

[0052] refer to Figure 2A In part (e), the protective liner 216 is etched or patterned to form the protective liner 216A. The recessed hard mask 214A is then removed (e.g., by an ashing process).

[0053] refer to Figure 2B In part (f), the lower portion of the sacrificial gate oxide layer 212 is removed to form the sacrificial gate oxide layer 212A.

[0054] refer to Figure 2B In part (g), the first release layer 206 is removed to release the first set of horizontal nanowires 204.

[0055] refer to Figure 2B In part (h), the sacrificial gate oxide layer 218 is formed on the first set of horizontal nanowires 204.

[0056] refer to Figure 2B Part (i), hard mask 220 (such as a carbon hard mask) is formed in Figure 2B Above the structure of part (h).

[0057] refer to Figure 2B In part (j), the hard mask 220 is recessed near the P / N junction line to form a recessed hard mask 220A.

[0058] Reference Figure 2C Part (k) of the protective lining 216A was removed.

[0059] refer to Figure 2C In part (l), the sacrificial gate oxide layer 212A is removed, leaving the sacrificial gate oxide layer 218A.

[0060] refer to Figure 2C Part (m), the second release layer 210 is removed to release the second set of horizontal nanowires 208.

[0061] refer to Figure 2C In part (n), the recessed hard mask 220A is removed (e.g., by an ashing process). The sacrificial gate oxide layer 222 is then formed on the second set of horizontal nanowires 208, and the sacrificial gate oxide layer 218B remains on the first set of horizontal nanowires 204.

[0062] refer to Figure 2C Part (o) of the sacrificial gate oxide layer 222 and sacrificial gate oxide layer 218B are removed.

[0063] refer to Figure 2D In part (p), a permanent first gate oxide layer 224 (such as a silicon oxide layer formed by ozone treatment) is formed on a first set of horizontal nanowires 204 and on a second set of horizontal nanowires 208.

[0064] refer to Figure 2D Part (q), a permanent second gate oxide layer 226 (such as a high-k gate dielectric layer) is formed in Figure 2D The structure of the p portion. Subsequent processing may include the formation of a permanent gate electrode, which can distinguish between N-devices and P-devices in a CFET stack.

[0065] On the other hand, one or more embodiments described herein relate to self-aligned bottom-up oxidation for nanowire transistor channel removal and nanoribbon transistor channel removal.

[0066] To provide context, the integration of nanowire and / or nanoribbon complementary metal oxide semiconductor (CMOS) transistors faces the challenge of creating devices with varying strengths. In current FinFET technology, device strength granularity is achieved by varying the number of fins in the device channel. Unfortunately, this option is not readily available for nanowire and nanoribbon architectures because the channels are vertically stacked. This requirement is even more stringent for nanowire and / or nanoribbon (NW / NR) structures, in self-aligned stacked CMOS structures where NMOS and PMOS channels are patterned with the same width. Previous attempts to address these issues have included (1) integrating NW / NR devices with varying channel widths (only applicable to options requiring complexly patterned nanoribbons), or (2) reducing the removal of lines / ribbons from the source / drain or channel regions (a challenging option for stacked CMOS architectures).

[0067] To provide further context, different circuit types may require transistors with different drive currents. The embodiments disclosed herein aim to achieve different drive currents by de-popping the number of nanowire transistor channels in a device structure. One or more embodiments provide methods for removing a discrete number of wires from a transistor structure. Methods may be applicable to both ribbons and wires (RAW). Furthermore, transistor leakage current flowing through sub-fins must be controlled to obtain proper circuit functionality. The embodiments disclosed herein provide methods for sub-fin isolation of nanowire transistors. For de-pop, FinFET techniques can be used to remove the number of fins in each device to achieve different drive current intensities. For sub-fin isolation, sub-fin implants are used to dope the sub-fins to reduce leakage. However, because nanowires are stacked and self-aligned, they cannot be de-popped in the same way as fins. Additionally, the sub-fin dopant must be targeted and can diffuse back into the channel, thereby degrading carrier transport.

[0068] According to embodiments of this disclosure, a process flow described herein is for implementing self-aligned bottom-up oxidation for channel removal and / or sub-fin isolation of nanowire transistors. Embodiments may include channel removal for nanowire transistors to provide modulation of drive currents in different devices that may be required by different circuits. Embodiments may be implemented as self-aligned methods, thereby allowing for deep scaling of future nanowire technologies.

[0069] According to embodiments of this disclosure, the nanowire processing of alternating Si / SiGe stacks includes patterning the stacks into fins. A generic dummy gate (which may or may not be a polysilicon dummy gate) is patterned and etched. During subsequent operations, the NW / NR channel is released. After the NW / NR channel is released, a thin film oxide catalyst layer (e.g., Al2O3) is deposited on the NW / NR channel, for example using an atomic layer deposition (ALD) process. In a particular embodiment, a masking film (such as a carbon hard mask (CHM)) is then deposited to fill the gate trench, followed by recessed etching to leave the CHM covering the band to be converted to oxide. The oxide catalyst layer is then removed from the exposed band using a selective wet etchant such as dilute hydrogen fluoride or an aqueous solution of ammonium peroxide. The hard mask is subsequently removed by exposing it to oxygen plasma to leave an oxide catalyst layer (e.g., Al2O3) encapsulating only the bottom one or more NW / NR channels. Then, the bottom one or more NW / NR channels are selectively converted to oxides (e.g., silicon oxide from silicon oxide NW / NR channels) by wet oxidation annealing. The bottom one or more NW / NR channels are rapidly converted to oxides (e.g., SiO2) because the oxidation catalyst layer (e.g., Al2O3) promotes oxygen diffusion into silicon (Si). The selected oxidation conditions can be very mild, such that almost no oxidation occurs on the upper strips not encapsulated by the oxidation catalyst layer. In this way, Si nanowires are oxidized from the bottom up. Although some embodiments describe the use of Si (wires or strips) and SiGe (sacrificial) layers, other semiconductor material pairs that can be alloyed and epitaxially grown can be implemented to carry out the various embodiments described herein, such as InAs and InGaAs, or SiGe and Ge. The embodiments described herein enable the fabrication of self-aligned stacked transistors with a variable number of active nanowires or nanoribbons in the channels and make methods for realizing such structures possible.

[0070] It should be understood that the embodiments described herein can be implemented to fabricate nanowire and / or nanoribbon structures with varying numbers of active line / band channels. It should be understood that the embodiments described herein can relate to selective oxidation methods for realizing such structures. The embodiments described herein can be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0071] In this embodiment, to design and fabricate different devices with varying drive current intensities, a self-aligned de-pop process can be patterned using photolithography, causing the strip and line (RAW) to be removed only from specific devices. In this embodiment, removal can be performed uniformly across the entire wafer, so all devices have the same amount of RAW. It should be understood that when removal is performed through the gate trench, some epitaxial source or drain (S / D) material may be oxidized from near the gate electrode, unlike removal performed through the S / D location.

[0072] On the other hand, front-to-back vias can be fabricated using a removeable gate region. The embodiments described herein can provide a space-efficient way to transmit signals from a front interconnect to a back interconnect (or from a back interconnect to a front interconnect), which does not necessarily involve extreme etching or additional patterning operations.

[0073] To provide context, the fabrication of state-of-the-art vias, which transmit signals or power from one side of a wafer to the other, requires additional photolithographic patterning and harsh etching, which can damage the surrounding material. Such existing methods have designs that allow vias to short-circuit to adjacent source or drain regions. However, such short-circuiting may not be permitted in current designs of self-aligned transistors.

[0074] According to one or more embodiments of this disclosure, fins, nanowires, or nanoribbon structures are fabricated as conductive via structures including those used in self-aligned transistor technology. In a particular embodiment, front and rear vias occupy space in a gate region where all channels in the corresponding channel of the gate region have been removed. In one embodiment, the via is made of the same gate metal(s) as the surrounding active gate region. The via is connected to the front and rear interconnects in the same manner as the surrounding active gate region.

[0075] Advantages of implementing the embodiments described herein include the ability to fabricate front and rear vias without necessarily requiring additional photolithographic patterning operations (e.g., since removal processes are already required elsewhere in the self-aligned transistor process). Embodiments can also be implemented to allow front and rear vias that do not necessarily require extremely harsh etching that would otherwise damage surrounding materials (e.g., gate spacers, isolation caps / walls, plugs, etc.).

[0076] As an overview, in this embodiment, a self-aligned transistor is fabricated by removing a polysilicon (or other dummy) gate. The transistor channel is exposed in the gate region. After the transistor channel is exposed, portions of the channel can be removed as defined by photolithographic patterning. In this example, removal can be achieved by catalytic oxidation, for example, where a thin metal oxide is conformally deposited around certain channels to increase the oxidation rate relative to channels without metal oxide.

[0077] As an example of a double oxidation treatment scheme Figures 3A-3D The figures illustrate cross-sectional views of various operations in a method of fabricating another all-around gate integrated circuit structure having a removed channel structure, according to embodiments of the present disclosure. It should be understood that although two groups of three nanowires are shown in each transistor region, any number of groups, the number of channels in each group, or the channel geometry (e.g., nanoribbons, nanowires, fins) can be used. It should be understood that, according to one or more embodiments described herein, in conjunction with… Figures 3A-3D The described nanowire stacks or groups can be subject to differential release layer processes, such as binding. Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0078] refer to Figure 3A A method for fabricating an integrated circuit structure includes forming a vertical arrangement 300 of active nanowires or nanoribbons over a substrate 302. Several adjacent device sites (such as device sites 330A, 330B, and 330C) may be fabricated adjacent to each other. In an embodiment, a gate cap structure separates device sites 330A, 330B, and 330C. In one such embodiment, each gate cap structure is located in a trench isolation layer 320A and includes a liner dielectric layer 320B and a fill dielectric layer 320C. A dielectric cap 320D may be formed on each cap structure in the cap structure, examples of which will be described in more detail below.

[0079] In the embodiments, each of device locations 330A, 330B, and 330C includes an assembly of lower nanowires 304A, 304B, and 304C provided as a vertical stack, and an assembly of upper nanowires 314A, 314B, and 314C. A dielectric nanowire capping layer 314D is included on each of the nanowire assemblies, an example of which is formed as described below. As explained in more detail in other embodiments described below, the channel regions of the assembly of lower nanowires 304A, 304B, and 304C, and the assembly of upper nanowires 314A, 314B, and 314C, can be exposed during a replacement gate process, during which an opening trench 308A is formed to expose the channel regions. Trench 308A can be separated from other replacement gate trenches (e.g., 308B and 308C) by a sidewall spacer 310A, a trench-filling dielectric layer 310B, and a hard mask cap or safety cap 310C.

[0080] refer to Figure 3B In the first oxidation process, the lower nanowires 304A, 304B, and 304C at device locations 330A and 330B are removed. The lower nanowires 304A, 304B, and 304C at device location 330C are not removed. In an embodiment, an oxidation catalyst layer is used to remove the lower nanowires 304A, 304B, and 304C at device locations 330A and 330B. This oxidation catalyst layer is first formed on all nanowires and then patterned to confine the oxidation catalyst layer to the lower nanowires 304A, 304B, and 304C at device locations 330A and 330B. The first oxidation process is then performed to form oxide nanowires 350A, 350B, and 350C. The lower active nanowires 304A, 304B, and 304C are retained in device location 330C.

[0081] refer to Figure 3C In the second oxidation process, the bottommost nanowires 314A, 314B, and 314C of the upper nanowire assembly at device locations 330A and 330C are removed. The bottommost nanowires 314A, 314B, and 314C of the upper nanowire assembly at device location 330B are not removed. In an embodiment, an oxidation catalyst layer is used to remove the bottommost nanowires 314A, 314B, and 314C of the upper nanowire assembly at device locations 330A and 330C. This oxidation catalyst layer is first formed on all nanowires in the upper nanowire assembly and then patterned to confine the oxidation catalyst layer to the bottommost nanowires 314A, 314B, and 314C of the upper nanowire assembly at device locations 330A and 330C.

[0082] In this embodiment, the bottom nanowire assembly, previously constrained by the first oxidation process, is blocked by a lower masking layer, allowing the second selective oxidation process to be limited to the upper nanowire assembly, thereby permitting a second "bottom-up" oxidation removal method. The second oxidation process is then performed to form oxide nanowires 360A, 360B, and 360C. It should be understood that, compared to active nanowires, a specific example of removeable nanowires is that, for the lower nanowire assembly, the first oxidation removal method can be used to retain or oxidize any suitable number of nanowires to form oxide nanowires, and then, for the upper nanowire assembly, the second oxidation removal method is used to retain or oxidize any suitable number of nanowires to form oxide nanowires.

[0083] refer to Figure 3D A permanent gate structure can be fabricated in trench 308A. In one exemplary embodiment, the permanent gate structure includes a lower gate dielectric 370 and a lower P-type gate electrode 372 thereon, and an upper gate dielectric 370 and an upper N-type gate electrode 374 thereon. In another exemplary embodiment, the permanent gate structure includes a lower gate dielectric and a lower N-type gate electrode thereon, and an upper gate dielectric and an upper P-type gate electrode thereon. In embodiments, the permanent gate structure is formed around all nanowire / nanoribbon (NW / NR) channels, which include oxide NW / NR channels. In certain such embodiments, the oxide catalyst layer is not removed, and the remainder is included in the final structure. However, in other embodiments, the oxide catalyst layer is removed before the permanent gate structure is fabricated.

[0084] Refer again Figure 3D According to embodiments of this disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires (e.g., nanowires 350A, 350B, and 350C at device location 308B). The first vertical arrangement of nanowires has one or more oxide nanowires (e.g., nanowires 350A, 350B, and 350C). A first gate stack (e.g., 370 / 372) is positioned above the first vertical arrangement of nanowires and surrounds the one or more oxide nanowires arranged in the first vertical arrangement. A second vertical arrangement of nanowires is positioned above the first vertical arrangement of nanowires (e.g., nanowires 314A, 314B, and 314C at device location 308B). The second vertical arrangement of nanowires has one or more active nanowires. A second gate stack is positioned above the second vertical arrangement of nanowires and surrounds the one or more active nanowires arranged in the second vertical arrangement.

[0085] In one embodiment, one or more oxide nanowires have an oxidation catalyst layer thereon, for example, as a residual layer or artifact layer remaining from a bottom-up channel removal process. In one embodiment, the oxidation catalyst layer comprises aluminum oxide. In another embodiment, the oxidation catalyst layer comprises lanthanum oxide.

[0086] In an embodiment, the integrated circuit structure includes epitaxial source or drain structures at the ends of a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. In one such embodiment, the epitaxial source or drain structure is a discrete epitaxial source or drain structure, an example of which is described below. In another such embodiment, the epitaxial source or drain structure is a non-discrete epitaxial source or drain structure, an example of which is described below. In an embodiment, a first gate stack and a second gate stack have dielectric sidewall spacers, and the epitaxial source or drain structure is an embedded epitaxial source or drain structure extending below the dielectric sidewall spacers of the gate stack, an example of which is described below.

[0087] In an embodiment, the integrated circuit structure further includes paired conductive contact structures coupled to an epitaxial source or drain structure. In one such embodiment, the paired conductive contact structures are an asymmetrical pair of conductive contact structures, structural examples of which are described below.

[0088] In one embodiment, a first vertical arrangement of nanowires is positioned above a fin, and structural examples of the fin are described below. In another embodiment, a first gate stack includes a first high-k gate dielectric layer and a first metal gate electrode, and a second gate stack includes a second high-k gate dielectric layer and a second metal gate electrode.

[0089] It should be understood that the embodiments described herein can be implemented to fabricate nanowire and / or nanoribbon structures with varying numbers of active line / band channels. It should be understood that the embodiments described herein can relate to selective oxidation methods for realizing such structures. The embodiments described herein can be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0090] Refer again Figure 3DAccording to embodiments of this disclosure, the integrated circuit structure includes a first vertical arrangement of nanowires (e.g., nanowires at device location 308B) and a second vertical arrangement of nanowires (e.g., nanowires at device location 308C). The first vertical arrangement of nanowires has an active, uppermost nanowire (e.g., active nanowire 314C at device location 308B) and an active, lowermost nanowire (e.g., oxide nanowire 304A at device location 308C). The second vertical arrangement of nanowires has an active, uppermost nanowire (e.g., oxide nanowire 360C at device location 308C) and an active, lowermost nanowire (e.g., active nanowire 304C at device location 308C), and both the first and second vertical arrangements of nanowires have coplanar uppermost and coplanar lowermost nanowires. A first gate structure 370 / 372 is positioned above the first vertical arrangement of nanowires. A second gate structure 370 / 374 is positioned above the second vertical arrangement of nanowires.

[0091] In one embodiment, the horizontal width of the first vertical arrangement of nanowires is the same as the horizontal width of the second vertical arrangement of nanowires. In another embodiment, the horizontal width of the first vertical arrangement of nanowires is greater than the horizontal width of the second vertical arrangement of nanowires. In yet another embodiment, the horizontal width of the first vertical arrangement of nanowires is less than the horizontal width of the second vertical arrangement of nanowires.

[0092] Refer again Figure 3D According to one or more embodiments of this disclosure, the entire nanowire channel formed in device location 330A of the integrated circuit structure has been removed, for example, to provide a "completely" removed structure in device location 330A. In one embodiment, complete removal is achieved using two successive bottom-up oxidation methods. In an embodiment, the gate structure (e.g., 372 / 374) highlighted within the illustrated block 382 serves as a conductive via. In one embodiment, the conductive via is a front-and-back via.

[0093] Furthermore, in the embodiments, Figures 3A-3C The substrate 302 is replaced by a back-side interconnect layer. The back-side interconnect layer may include conductors 394 and conductive vias 396 formed in a dielectric layer 392 on the etch stop layer 398. In one embodiment, Figure 3C The substrate portion is removed in a back-side polishing process, an example of which is described in more detail below, and then an interconnect layer is formed on it. Additionally, Figure 3D The structure includes front gate contacts or vias 380A, 380B and 380C, which may include an insulating capping layer 390 formed thereon.

[0094] Refer again Figure 3DIn this embodiment, the integrated circuit structure 330A includes a vertically arranged array of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. All nanowires 350A, 350B, 350C, 360A, 360B, and 360C in the vertical array are oxide nanowires. Gate stacks 370 / 372 / 374 are positioned above the vertical array of nanowires, surrounding each of the oxide nanowires 350A, 350B, 350C, 360A, 360B, and 360C. Gate stacks 370 / 372 / 374 include conductive gate electrodes 372 / 374.

[0095] In an embodiment, the integrated circuit structure 330A further includes a gate contact 380A located above the vertically arranged nanowires 350A, 350B, 350C, 360A, 360B, and 360C. The gate contact 380A contacts the top surface of the conductive gate electrodes 372 / 374. Interconnect structures 394 / 396 are located below the vertically arranged nanowires 350A, 350B, 350C, 360A, 360B, and 360C. A conductive via 396 of the interconnect structures 394 / 396 contacts the bottom surface of the conductive gate electrodes 372 / 374. The conductive gate electrodes 372 / 374 serve as conductive vias between the gate contact 380A and the interconnect structures 394 / 396. In a particular embodiment, the oxide nanowires 350A, 350B, 350C, 360A, 360B, and 360C in the vertical arrangement of nanowires have an oxide catalyst layer thereon.

[0096] According to embodiments of this disclosure, the fabrication of the gate region that forms the front and rear vias does not necessarily require dedicated photolithographic patterning to define the vias. For example, in one embodiment, complete removal at selected locations is achieved by combining other removal operations. As described herein, such front and rear via fabrication may also not require harsh etching to remove the removal channel, preventing the surrounding material (e.g., gate spacers, isolation walls, etc.) from being eroded. However, in some embodiments, the removal channel is selectively removed in the front and rear via regions using a gentler etching process than that which might otherwise be associated with the opening of a similar via, prior to gate metallization.

[0097] As mentioned above, nanowire release processing can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, backend (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to enable front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wide interconnect pitches. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0098] One or more embodiments described herein are for oriented epitaxial (EPI) interconnects of nanowire or nanoribbon transistors using a portion of the source or drain (SD) and asymmetric trench contact (TCN) depth. In the embodiments, the integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. Deep trench formation on either the source or drain side enables direct contact to the back-side interconnect level.

[0099] In the exemplary process flow, Figures 4A-4J The figures illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to embodiments of the present disclosure. It should be understood that, based on one or more embodiments described herein, in conjunction with... Figures 4A-4J The described nanowire groups or stacks can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0100] refer to Figure 4A A method for fabricating an integrated circuit structure includes forming an initial stack 400 comprising alternating silicon-germanium layers 404 and silicon layers 406 over a fin 402 (such as a silicon fin). The silicon layers 406 may be referred to as vertically arranged silicon nanowires. As depicted, a protective cap 408 may be formed over the alternating silicon-germanium layers 404 and silicon layers 406.

[0101] refer to Figure 4B Gate stack 410 is formed on the vertical arrangement of nanowires 406. The vertically arranged portion of the nanowires 406 is then released by removing a portion of the silicon-germanium layer 404 to provide a recessed silicon-germanium layer 404' and cavity 412, as... Figure 4C As depicted in the text.

[0102] It should be understood that Figure 4CThe structure can be manufactured without first performing the following combined... Figure 4D The description includes deep etching and asymmetric contact treatment.

[0103] refer to Figure 4D An upper gate spacer 414 is formed at the sidewall of the gate structure 410. A cavity spacer 416 is formed in a cavity 412 below the upper gate spacer 414. Deep trench contact etching is then performed to form a trench 418 and a recessed nanowire 406'. A sacrificial material 420 is then formed in the trench 418, as... Figure 4E As depicted in the text.

[0104] refer to Figure 4F A first epitaxial source or drain structure (e.g., left-side feature 422) is formed at the first vertically arranged end of the nanowire 406'. A second epitaxial source or drain structure (e.g., right-side feature 422) is formed at the second vertically arranged end of the nanowire 406'. Then, an interlayer dielectric (ILD) material 424 is formed on the side of the gate electrode 410 and adjacent to the source or drain structure 422, as shown below. Figure 4G As depicted in the text.

[0105] refer to Figure 4H A replacement gate process is used to form the permanent gate dielectric 428 and the permanent gate electrode 426. In an embodiment, after removing the gate structure 410 and forming the permanent gate dielectric 428 and the permanent gate electrode 426, the recessed silicon-germanium layer 404' is removed to leave the upper active nanowires or nanoribbons 406'. In an embodiment, the recessed silicon-germanium layer 404' is selectively removed using a wet etching process that selectively removes the silicon-germanium without etching the silicon layer. Etching chemicals (such as acid / nitric acid / HF chemicals and citric acid / nitric acid / HF chemicals) can be used, for example, to selectively etch the silicon-germanium. Halide-based dry etching or plasma-enhanced vapor phase etching can also be used to implement the embodiments described herein.

[0106] Refer again Figure 4H One or more of the bottommost nanowires or nanoribbons 406' are then (e.g., by combining) Figures 3A-3D The described method involves oxidation to form one or more oxide nanowires or nanoribbons 499. A permanent gate dielectric 428 and a permanent gate electrode 426 are then formed around the nanowires or nanoribbons 406' and one or more oxide nanowires or nanoribbons 499.

[0107] refer to Figure 4IThe ILD material 424 is then removed. The sacrificial material 420 is then removed from one of the source and drain locations (e.g., the right side) to form the trench 432, but not from the other source and drain location to form the trench 430.

[0108] refer to Figure 4J A first conductive contact structure 434 is formed, coupled to a first epitaxial source or drain structure (e.g., left-side feature 422). A second conductive contact structure 436 is formed, coupled to a second epitaxial source or drain structure (e.g., right-side feature 422). The second conductive contact structure 436 is formed to be deeper along the fin 402 than the first conductive contact structure 434. In an embodiment, although... Figure 4J Not depicted, but the method further includes forming an exposed surface of a second conductive contact structure 436 at the bottom of the fin 402.

[0109] In one embodiment, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as depicted. In another such embodiment, not depicted, the first conductive contact structure 434 is partially along the fin 402.

[0110] In one embodiment, the second conductive contact structure 434 extends along the entire fin 402. In another embodiment, although not depicted, the second conductive contact structure 434 has an exposed surface at the bottom of the fin 402 if the bottom of the fin 402 is exposed via a backside substrate removal process.

[0111] On the other hand, in order to access both conductive contact structures in a pair of asymmetrical source and drain contact structures, the integrated circuit structure described herein can be fabricated using back-side exposure of a front-side fabrication method. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. In contrast to conventional through-silicon via (TSV) technology, back-side exposure of transistors as described herein can be performed at device cell density and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove the entire donor substrate, on which the device layer is disposed during front-side device processing. Thus, micrometer-deep TSVs become unnecessary, as the thickness of the semiconductor in the device cell may be only tens or hundreds of nanometers after back-side exposure of the transistor.

[0112] The exposure techniques described in this paper enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where "center" refers to any layer that is employed in front-side fabrication, exposed from the back side, and reused in back-side fabrication. When relying primarily on front-side processing, processing both the front and exposed back sides of the device structure can address many of the challenges associated with manufacturing 3D ICs.

[0113] For example, a back-side exposure using a transistor approach can be used to remove at least a portion of the carrier layer and intermediate layer of a donor-host substrate assembly. The process flow begins with input to the donor-host substrate assembly. A carrier layer of a certain thickness in the donor-host substrate is polished (e.g., chemical mechanical polishing (CMP)) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the components of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0114] In some embodiments, prior to the above-described process, the carrier layer is peeled off along a fracture plane substantially parallel to the intermediate layer. The peeling or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400 μm–900 μm, 100 μm–700 μm can be peeled off by practicing any known blanket implant that promotes wafer-level fracture. In some exemplary embodiments, a lightweight element (e.g., H, He, or Li) is implanted into the carrier layer at a uniform target depth within the desired fracture plane. After such a peeling process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete removal. Alternatively, in the absence of fracture, grinding, polishing, and / or etching operations can be used to remove larger thickness carrier layers.

[0115] Next, the exposure of the intermediate layer is detected. Detection is used to identify points when the back surface of the donor substrate has approached the device layer. Any endpoint detection technique known to be suitable for detecting transitions between materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on changes in optical absorption or emission detected during the polishing or etching process performed on the back surface of the donor substrate. In some other embodiments, the endpoint criteria are associated with changes in the optical absorption or emission of byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary depending on the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of byproducts from polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the changes in mass can be associated with different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and a polished surface that is in contact with the back surface of the donor substrate.

[0116] When the removal process is selective for the carrier layer relative to the intermediate layer, the detection of the intermediate layer can be enhanced because the inhomogeneities in the carrier removal process can be mitigated by the etch rate increment between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that at which the carrier layer is removed, detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations can be stopped on the intermediate layer material for a predetermined fixed duration if the thickness of the intermediate layer is sufficient for selective etching. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1 to 10:1 or greater.

[0117] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be removed uniformly by polishing. Alternatively, the thickness of the intermediate layer can be removed using a masking etching process or a full-scale etching process. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intermediate layer provides an etching stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more conducive to removing the intermediate layer than removing the device layer. When removing intermediate layer thicknesses of less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, employ a paste that provides very high selectivity (e.g., 100:1-300:1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO), which surrounds the device layer and is embedded within the intermediate layer, for example, as electrical isolation between adjacent device regions.

[0118] In embodiments where the device layer is exposed by completely removing the intermediate layer, the back-side processing can begin on the exposed back side of the device layer or on a specific device region therein. In some embodiments, the back-side device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region (such as a source or drain region) previously fabricated in the device layer.

[0119] In some embodiments where wet and / or plasma etching is used to recess the back side of the carrier layer, intermediate layer, or device layer, such etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back side surface of the device layer. As further described below, patterning can be within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back side device layer. Therefore, the masking etching process can precede the etching of the corresponding masked device layer.

[0120] The above processing scheme can produce a donor-host substrate assembly including an IC device, wherein the back side of the intermediate layer of the IC device, the back side of the device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer are exposed. Additional back-side processing of any of these exposed regions can then be performed during downstream processing.

[0121] It should be understood that the structure generated by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as CMOS, PMOS, and / or NMOS device fabrication. As an example of the completed device, Figure 5 The figure illustrates a cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure. It should be understood that, based on one or more embodiments described herein, in conjunction with... Figure 5 One or more nanowires described can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0122] refer to Figure 5 The semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In one embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires 504A and 504B) above the sub-fin region 505, as indicated by dashed lines. In either case, for ease of description of the non-planar integrated circuit structure 500, the non-planar active region 504 is hereinafter referred to as the protruding fin portion. For example, in one embodiment, the lower nanowire 504B is an oxide nanowire, and the upper nanowire 504A is an active nanowire. In one embodiment, the lower oxide nanowire 504B includes an oxide catalyst layer thereon.

[0123] Gate line 508 is disposed above the protrusion 504 of the non-planar active region (including, if applicable, surrounding nanowires 504A and 504B), and above a portion of the trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric capping layer 554. From this viewpoint, gate contact 514 and overlying gate contact via 516, as well as overlying metal interconnect 560, are also visible, all disposed within an interlayer dielectric stack or layer 570. Also from... Figure 5 From the perspective of the viewpoint, in one embodiment, the gate contact 514 is disposed above the trench isolation region 506, but not above the non-planar active region.

[0124] In this embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such embodiments, the corresponding semiconductor channel region is constituted by or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0125] Similarly, Figure 5 As depicted, in an embodiment, an interface 580 exists between the protruding fin portion 504 and the sub-fin region 505. Interface 580 may be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid-state doped layer at the sub-fin location. In certain such embodiments, the width of each fin is less than 10 nanometers.

[0126] although Figure 5 Not depicted, but to be understood, the source or drain region of the protruding fin portion 504, or the source or drain region adjacent to the protruding fin portion 504, is on either side of the gate line 508, i.e., entering and exiting the page. In one embodiment, the source or drain region is a doped portion of the original material of the protruding fin portion 504. In another embodiment, the material of the protruding fin portion 504 is removed and replaced with another semiconductor material (e.g., by epitaxial deposition) to form a discrete epitaxial blob or a non-discrete epitaxial structure. In either embodiment, the source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 580) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, the source or drain structure is an N-type epitaxial source or drain structure, both comprising phosphorus-doped impurity atoms. According to one or more embodiments of this disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as described above. Figure 4J As described.

[0127] Refer again Figure 5 In one embodiment, fins 504 / 505 (and possible nanowires 504A and 504B) are composed of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof). In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, fins 504 / 505 are composed of group III-V materials, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. Trench isolation region 506 may be composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0128] Gate line 508 may be formed by a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrodes of the gate electrode stack are made of metal gates, and the gate dielectric layer is made of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is made of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a native oxide layer formed by several layers on top of the protruding fin portion 504. In an embodiment, the gate dielectric layer is formed by a top high-k portion and a lower portion made of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is formed by a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, the gate dielectric portion is a "U"-shaped structure, comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0129] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-work function set fill material formed over a metal work function set layer. The gate electrode layer can be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a power function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and excluding the sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of this disclosure, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0130] The spacers associated with the gate electrode stack can be made of materials suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts) or facilitating the isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are made of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0131] The gate contact 514 and the overlying gate contact via 516 may be made of a conductive material. In embodiments, one or more of the contacts or vias may be made of a metallic material. The metallic material may be a pure metal (such as tungsten, nickel, or cobalt) or an alloy (such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0132] In an embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while eliminating the use of photolithography steps with extremely tight registration budgets. In an embodiment, the contact pattern is a vertically asymmetrical contact pattern, such as a combination Figure 4J As described. In other embodiments, all contacts are front-connected and not asymmetrical. In one such embodiment, the self-aligned method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to generate the contact openings. In an embodiment, the contact pattern is formed using existing gate patterns by incorporating contact plugging lithography operations. In one such embodiment, the method enables the elimination of the need for lithography operations critical in other cases to generate the contact pattern, as used in conventional methods. In an embodiment, the trench contact mesh is not patterned separately but formed between the gate lines. For example, in one such embodiment, the trench contact mesh is formed after gate grating patterning but before gate grating dicing.

[0133] In an embodiment, providing structure 500 involves fabricating a gate stack structure 508 using a gate replacement process. In such an embodiment, a dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed during this process, contrary to the use of a previous process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including an aqueous phosphoric acid solution.

[0134] Refer again Figure 5 The arrangement of the semiconductor structure or device 500 places the gate contact above the isolation region. Such an arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above fin 505) and in the same layer as the trench contact via.

[0135] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. Semiconductor devices can be transistors or similar devices. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Furthermore, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate-all-around (GAA) device, a tri-gate device, an independently accessible dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0136] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises, or includes, layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD) or by other deposition methods.

[0137] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and so on. Thus, an interconnect may be a single layer of material or may be formed from several layers including a conductive liner layer and a filler layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0138] In embodiments, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials may be used in different regions to provide different growth or etching selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping, or plug layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping, or plug layers known in the art may be used. The hard mask, capping, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0139] In embodiments, as used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV, and / or EBDW lithography. Positive or negative tone resists may be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a terrain masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the terrain masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0140] On the other hand, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may involve the integration of multi-width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In embodiments, the nanowires / nanoribbons are integrated with multiple Wsi within a portion of the SAGE architecture of a front-end process flow. Such process flows may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next-generation transistors with low power and high performance. The associated epitaxial source or drain regions may be embedded (e.g., a portion of the nanowire is removed, and then source or drain (S / D) growth is performed) or formed by vertical merging (e.g., the epitaxial region is formed around an existing wire), as described below. Figures 9A-9E A more detailed description.

[0141] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, and in particular, scaling of diffusion pitch. For illustrative comparisons, Figure 6The figure illustrates a cross-sectional view of nanowires and fins according to an embodiment of the present disclosure, taken from a non-endcap architecture (left side (a)) relative to a self-aligned gate endcap (SAGE) architecture (right side (b)). It should be understood that, according to one or more embodiments described herein, in conjunction with... Figure 6 One or more nanowires described can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0142] refer to Figure 6 On the left side (a), the integrated circuit structure 600 includes a substrate 602 having sub-fins 604 projecting from it within an isolation structure 608 laterally surrounding sub-fins 604. Corresponding nanowires 649 and 605 are positioned above the sub-fins 604. In one embodiment, the lower nanowire 649 is an oxide nanowire, and the upper nanowire 605 is an active nanowire. In one embodiment, the lower oxide nanowire 649 includes an oxide catalyst layer thereon. A gate structure can be formed on the integrated circuit structure 600 to fabricate a device. However, breaks in such gate structures can be accommodated by increasing the spacing between the sub-fin 604 / nanowire 649 / 605 pairs.

[0143] In comparison, reference Figure 6 On the right side (b), the integrated circuit structure 650 includes a substrate 652 having sub-fins 654 projecting from it within an isolation structure 658 laterally surrounding sub-fins 654. Corresponding nanowires 699 and 655 are positioned above the sub-fins 654. In one embodiment, the lower nanowire 699 is an oxide nanowire, and the upper nanowire 655 is an active nanowire. In one embodiment, the lower oxide nanowire 699 includes an oxide catalyst layer thereon. Isolating SAGE walls 660 are included within the isolation structure 658 and between adjacent sub-fin 654 / nanowire 699 / 655 pairs. The distance between the isolated SAGE walls 660 and the nearest sub-fin 654 / nanowire 699 / 655 pair defines a gate cap spacing 662. Gate structures can be formed between the isolated SAGE walls, above the integrated circuit structure 600, to fabricate devices. Breakages in such gate structures are caused by the isolated SAGE walls. Because the isolated SAGE walls 660 are self-aligned, limitations from conventional methods can be minimized to make diffusion to the diffusion pitch more aggressive. Furthermore, since the gate structure includes breaks at all locations, the individual gate structure portions can be layered via local interconnects formed over the isolated SAGE walls 660. In an embodiment, as depicted, each SAGE wall 660 includes a lower dielectric portion and a dielectric cap on that lower dielectric portion, as depicted.

[0144] The self-aligned gate end cap (SAGE) processing scheme involves the formation of a gate / trench contact end cap that is self-aligned with the fins, without requiring additional length to resolve mask registration errors. Thus, embodiments can be implemented to enable a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0145] In an exemplary processing scheme for a structure with SAGE walls that separate adjacent devices, Figure 7 The figures illustrate cross-sectional views of various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a fully all-around gate device, according to embodiments of the present disclosure. It should be understood that, in conjunction with one or more embodiments described herein... Figure 7 One or more nanowires described can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0146] refer to Figure 7 Part (a) of the initial structure includes a nanowire patterned stack 704 over a substrate 702. A photolithographic patterned stack 706 is formed over the nanowire patterned stack 704. The nanowire patterned stack 704 includes alternating silicon-germanium layers 710 and silicon layers 712. A protective mask 714 is located between the nanowire patterned stack 704 and the photolithographic patterned stack 706. In one embodiment, the photolithographic patterned stack 706 is a three-layer mask consisting of a terrain masking portion 720, an anti-reflective coating (ARC) layer 722, and a photoresist layer 724. In a particular embodiment of this type, the terrain masking portion 720 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 722 is a silicon ARC layer.

[0147] refer to Figure 7 The stack of part (b) and part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 702 and trenches 730.

[0148] refer to Figure 7 Parts (c) and (b) have an isolation layer 740 and a SAGE material 742 formed in the trench 730. The structure is then planarized to leave a patterned terrain masking layer 720' as the exposed upper layer.

[0149] refer to Figure 7In part (d), the isolation layer 740 is recessed below the upper surface of the patterned substrate 702, for example, to define a protruding fin portion and to provide a trench isolation structure 741 below the SAGE wall 742.

[0150] refer to Figure 7 Part (e) involves removing the silicon-germanium layer 710 at least in the channel region to release silicon nanowires 712A and 712B.

[0151] According to embodiments of this disclosure, it is used for communication with Figure 7 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with a removed channel structure. For example, refer to... Figure 7 In part (e), in the embodiments, nanowire 712B and nanoribbon 712A are active nanowire and nanoribbon, respectively. In one such embodiment, nanowire 799B is an oxide nanowire, and nanoribbon 799A is an oxide nanoribbon, as depicted. In another such embodiment, nanowire 799B is an oxide nanowire, and nanoribbon 799A is an active nanoribbon. In yet another such embodiment, nanowire 799B is an active nanowire, and nanoribbon 799A is an oxide nanoribbon. In any case, in the embodiments, the oxide nanowire or oxide nanoribbon includes an oxide catalyst layer thereon.

[0152] In formation Figure 7 Following the structure of part (e), one or more gate stacks may be formed around the active and oxide nanowires and / or nanoribbons, over the protruding fins of the substrate 702, and between the SAGE walls 742. In one embodiment, the remainder of the protective mask 714 is removed before the gate stacks are formed. In another embodiment, the remainder of the protective mask 714 is retained as an insulating fin cap as an artifact of the processing scheme.

[0153] Refer again Figure 7 Section (e) depicts a channel view, wherein the source or drain regions are positioned within and outside the page. In an embodiment, the width of the channel region including nanowire 712B is smaller than the width of the channel region including nanowire 712A. Thus, in an embodiment, the integrated circuit structure includes multi-width (multi-Wsi) nanowires. Although the structures of 712B and 712A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to herein as nanowires. It should also be understood that references or descriptions of fin / nanowire pairs throughout the document can refer to fins and one or more overlay nanowires (e.g., two overlay nanowires in...). Figure 7 The structure shown in the figure has one or more bottom lines that are oxidized for removal.

[0154] Refer again Figure 7 As described in part (e) and subsequently, according to embodiments of the present disclosure, the integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of active nanowires than the second vertical arrangement of nanowires. The first and second vertical arrangements of nanowires have coplanar uppermost nanowires and coplanar lowermost nanowires. The second vertical arrangement of nanowires has a lowermost oxide nanowire. A first gate stack is situated above the first vertical arrangement of nanowires. A second gate stack is situated above the second vertical arrangement of nanowires and surrounds the lowermost oxide nanowire.

[0155] In one embodiment, the horizontal width of the nanowires in the first vertical arrangement is the same as the horizontal width of the nanowires in the second vertical arrangement. In another embodiment, the horizontal width of the nanowires in the first vertical arrangement is greater than the horizontal width of the nanowires in the second vertical arrangement. In yet another embodiment, the horizontal width of the nanowires in the first vertical arrangement is less than the horizontal width of the nanowires in the second vertical arrangement.

[0156] To highlight the exemplary integrated circuit structure with three vertically arranged nanowires, Figure 8A The figure shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Figure 8B The figure shows a section taken along the a-a' axis. Figure 8A A cross-sectional source or drain view of a nanowire-based integrated circuit structure. Figure 8C The figure shows a section taken along the b-b' axis. Figure 8A A cross-sectional channel view of a nanowire-based integrated circuit structure. It should be understood that, based on one or more embodiments described herein, in conjunction with... Figure 8A and Figure 8B One or more nanowires described can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0157] refer to Figure 8AThe integrated circuit structure 800 includes one or more vertically stacked nanowires (groups 804) above a substrate 802. For illustrative purposes, optional fins between the bottommost nanowire and the substrate 802 are not depicted. The embodiments described herein refer to both single-wire and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices having nanowires 804A, 804B, and 804C are shown. For ease of description, nanowire 804A is used as an example, where the description focuses on one of the nanowires. It should be understood that while the properties of one nanowire are described, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire.

[0158] Each nanowire in nanowire 804 includes a channel region 806. The channel region 806 has a length (L). (Reference) Figure 8C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 8A and Figure 8C Gate electrode stack 808 surrounds the entire periphery (Pc) of each channel region in channel region 806. Gate electrode stack 808 includes a gate electrode and a gate dielectric layer (not shown) located between channel region 806 and the gate electrode. In embodiments, the channel region is discrete because it is completely surrounded by gate electrode stack 808 without any intermediate material, such as the underlying substrate material or the upper channel fabrication material. Therefore, in embodiments having multiple nanowires 804, the channel regions 806 of the nanowires are also discrete relative to each other.

[0159] refer to Figure 8A and Figure 8B The integrated circuit structure 800 includes pairs of discrete source or drain regions 810 / 812. The pairs of discrete source or drain regions 810 / 812 are located on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. Furthermore, the pairs of discrete source or drain regions 810 / 812 are adjacent to the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment, although not depicted, the pairs of discrete source or drain regions 810 / 812 are directly vertically adjacent to the channel region 806 because they are epitaxially grown on and between nanowire portions extending beyond the channel region 806, wherein the nanowire ends are shown within the source or drain structure. In another embodiment, as... Figure 8A As depicted, the pairs of non-discrete source or drain regions 810 / 812 are indirectly and vertically adjacent to the channel region 806 because they are formed at the ends of the nanowires, rather than between the nanowires.

[0160] In the embodiments, as depicted, the source or drain regions 810 / 812 are non-discrete because there is no separate and discrete source or drain region for each channel region 806 of the nanowire 804. Accordingly, in embodiments with multiple nanowires 804, the source or drain regions 810 / 812 of the nanowires are global or uniform source or drain regions, rather than discrete regions for each nanowire. In one embodiment, each of the paired non-discrete source or drain regions 810 / 812 is approximately rectangular in shape, having a bottom tapered portion and a top vertex portion, as shown in the figure. Figure 8B As depicted in the text. However, in other embodiments, the source or drain regions 810 / 812 of the nanowire are relatively large but discrete non-vertically merged epitaxial structures, such as those combined with... Figures 4F-4J The small section of the description.

[0161] According to embodiments of this disclosure, and as Figure 8A and Figure 8B As depicted, the integrated circuit structure 800 further includes a pair of contacts 814, each contact 814 situated on one of a pair of discrete source or drain regions 810 / 812. In one such embodiment, vertically, each contact 814 completely surrounds the corresponding discrete source or drain region 810 / 812. On the other hand, the entire periphery of the discrete source or drain region 810 / 812 may not be in contact with the contact 814, and thus the contact 814 only partially surrounds the discrete source or drain region 810 / 812, such as... Figure 8B As depicted in the illustration. In a comparative embodiment not depicted, the entire periphery of the non-discrete source or drain region 810 / 812, truncated along the a-a' axis, is surrounded by contact portions 814. According to embodiments of this disclosure, although not depicted, the paired contact portions 814 are an asymmetrical pair of contact portions, as combined Figure 4J As described.

[0162] refer to Figure 8B and Figure 8CThe non-discrete source or drain regions 810 / 812 are global because a single uniform feature is used for multiple (in this case, three) nanowires 804 and (more specifically) for more than one discrete channel region 806. In one embodiment, the paired non-discrete source or drain regions 810 / 812 are made of a semiconductor material different from the semiconductor material of the discrete channel region 806; for example, the paired non-discrete source or drain regions 810 / 812 are made of silicon-germanium, while the discrete channel region 806 is made of silicon. In another embodiment, the paired non-discrete source or drain regions 810 / 812 are made of the same or substantially the same semiconductor material as the semiconductor material of the discrete channel region 806; for example, both the paired non-discrete source or drain regions 810 / 812 and the discrete channel region 806 are made of silicon.

[0163] Refer again Figure 8A In an embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As depicted, the exterior of the pair of spacers 816 may partially overlap with a portion of the non-discrete source or drain regions 810 / 812, thereby providing an "embedded" portion of the non-discrete source or drain regions 810 / 812 beneath the pair of spacers 816. As also depicted, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend beneath the entirety of the pair of spacers 816.

[0164] Substrate 802 may be made of a material suitable for manufacturing integrated circuit structures. In one embodiment, substrate 802 includes a lower body substrate made of a single-crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, or III-V compound semiconductor materials. An upper insulating layer made of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is situated on the lower body substrate. Thus, structure 800 can be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, structure 800 is formed directly from the body substrate, and localized oxidation is used to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 800 is formed directly from the body substrate, and doping is used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an ΩFET-type structure.

[0165] In embodiments, the nanowire 804 may be a line or strip, as described below, and may have square or more rounded corners. In embodiments, the nanowire 804 is made of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 804, the single-crystal nanowire may be based on (100) global orientation, for example, where… <100> The plane is in the z-direction. Other orientations may also be considered, as described below. In the embodiments, the size of the nanowire 804 is in the nanometer scale from a cross-sectional view. For example, in a specific embodiment, the minimum size of the nanowire 804 is less than about 20 nanometers. In the embodiments, the nanowire 804 is made of a strained material, particularly in the channel region 806.

[0166] refer to Figure 8C In the embodiments, each channel region 806 has a width (Wc) and a height (Hc), with the width (Wc) and height (Hc) being approximately the same. That is, in both cases, the cross-sectional profile of the channel region 806 is approximately square; or, if it is rounded, approximately circular. On the other hand, the width and height of the channel regions do not need to be the same, as in the case of the nanoribbons described throughout.

[0167] On the other hand, methods for fabricating nanowire portions of fin / nanowire integrated circuit structures are provided. For example, Figures 9A-9E The figures illustrate three-dimensional cross-sectional views of various operations in a method for fabricating nanowire portions of a fin / nanowire structure according to embodiments of the present disclosure. It should be understood that, in conjunction with one or more embodiments described herein... Figures 9A-9E One or more nanowires described can be subject to differential release layer processes, such as binding Figure 1A and / or Figure 1B and / or Figures 2A-2D Described.

[0168] Methods for fabricating nanowire integrated circuit structures may include forming nanowires on a substrate. In a specific example illustrating the formation of two silicon nanowires... Figure 9A The figure illustrates a substrate 902 (e.g., composed of a bulk silicon substrate 902A and an insulating silicon dioxide layer 902B thereon), on which a silicon layer 904 / silicon-germanium layer 906 / silicon layer 908 stack is formed. It should be understood that, in another embodiment, the silicon-germanium layer / silicon layer / silicon-germanium layer stack can be used to ultimately form two silicon-germanium nanowires.

[0169] refer to Figure 9B The portion of the stacked silicon layer 904 / silicon-germanium layer 906 / silicon layer 908, and the top of the silicon dioxide layer 902B region (e.g., using a mask and plasma etching process) are patterned into a fin structure 910. It should be understood that, for illustrative purposes, this is intended for... Figure 9BThe etching is shown as forming two silicon nanowire precursor portions. Although for ease of illustration, the etching is shown to end within the bottom isolation layer, more complex stacking is contemplated within the context of embodiments of this disclosure. For example, this process could be applied to nanowire / fin stacks, such as those combined with… Figure 7 As described.

[0170] The method can also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example illustrating the formation of three gate structures on two silicon nanowires, Figure 9C The figure illustrates a fin structure 910 having three sacrificial gates 912A, 912B, and 912C. In one such embodiment, the three sacrificial gates 912A, 912B, and 912C are composed of a sacrificial gate oxide layer 914 and a sacrificial polysilicon gate layer 916, which are blanket-deposited and patterned using a plasma etching process.

[0171] After patterning to form three sacrificial gates 912A, 912B, and 912C, spacers can be formed on the sidewalls of the three sacrificial gates 912A, 912B, and 912C. Doping can be performed (e.g., tip and / or source and drain type doping), and an interlayer dielectric layer can be formed to cover the three sacrificial gates 912A, 912B, and 912C. The interlayer dielectric layer can be polished to expose the three sacrificial gates 912A, 912B, and 912C for replacement gate processes or post-gate processes.

[0172] refer to Figure 9D The three sacrificial gates 912A, 912B, and 912C are removed, leaving spacer 918 and a portion of interlayer dielectric layer 920. Additionally, in the region initially covered by the three sacrificial gates 912A, 912B, and 912C, portions of the silicon-germanium layer 906 and the insulating silicon dioxide layer 902B of fin structure 910 are removed. Thus, discrete portions of silicon layers 904 and 908 are retained, as... Figure 9D As depicted in the text.

[0173] In one embodiment, Figure 9D The discrete portions of silicon layers 904 and 908 shown will ultimately become the channel regions in nanowire-based devices. Thus, in Figure 9D The process stages described herein allow for the design, fabrication, or tuning of the trenches. For example, in one embodiment, oxidation and etching processes are used to thin the trench. Figure 9DThe discrete portions of silicon layers 904 and 908 are shown. This etching process can be performed simultaneously with the separation of the lines by etching the silicon-germanium layer 906. Accordingly, the initial line formed by silicon layers 904 and 908 begins to thicken and is thinned to a size suitable for the channel region in the nanowire device, independent of adjustments to the size of the source and drain regions of the device. Thus, in this embodiment, forming the channel region includes removing portions of the nanowire, and the resulting perimeter of the source and drain regions (described below) is greater than the perimeter of the resulting channel region.

[0174] According to embodiments of this disclosure, a manufacturing process is performed after removing the three sacrificial gates 912A, 912B, and 912C from the region initially covered by the three sacrificial gates 912A, 912B, and 912C, and removing portions of the silicon-germanium layer 906 and the insulating silicon dioxide layer 902B of the fin structure 910, which provides a gate-all-around integrated circuit structure.

[0175] The method may also include forming a stack of gate electrodes around the entire periphery of the channel region. In a specific example illustrating the formation of three gate structures on two silicon nanowires, Figure 9E The diagram illustrates the structure after depositing a gate dielectric layer 922 (such as a high-k gate dielectric layer) and a gate electrode layer 924 (such as a metal gate electrode layer) between spacers 918 and subsequently polishing. That is, the gate structure is... Figure 9D It was formed in trench 921. Additionally, Figure 9E The result of removing the interlayer dielectric layer 920 after the formation of the permanent gate stack is depicted. A portion of the silicon-germanium layer 906 and a portion of the insulating silicon dioxide layer 902B of the fin structure 910 were also initially formed by… Figure 9D The area partially covered by the interlayer dielectric layer 920 depicted in the diagram is removed. Thus, the discrete portions of silicon layers 904 and 908 are retained, as... Figure 9E As depicted in the text.

[0176] The method may also include forming a pair of source and drain regions in the nanowire, on either side of the channel region, wherein the periphery of each of the source and drain regions is orthogonal to the length of the channel region. Specifically, in one embodiment, Figure 9E The discrete portions of silicon layers 904 and 908 shown will ultimately become at least a portion of the source and drain regions in a nanowire-based device. In one such embodiment, the epitaxial source or drain structure is formed by incorporating the epitaxial material surrounding the existing nanowires 904 and 908. In another embodiment, the epitaxial source or drain structure is embedded, for example, portions of nanowires 904 and 908 are removed, and then source or drain electrode (S / D) growth is performed. In the latter case, according to embodiments of this disclosure, such epitaxial source or drain structures can be non-discrete, such as combined with... Figure 8A and Figure 8B As illustrated; or it can be discrete, such as in combination. Figure 4J As illustrated. In any case, in one embodiment, the source or drain structure is an N-type epitaxial source or drain structure, both of which include phosphorus-doped impurity atoms.

[0177] The method may then include forming a pair of contacts, wherein a first contact in the pair completely or almost completely surrounds the periphery of the source region, and a second contact in the pair completely or almost completely surrounds the periphery of the drain region. In embodiments, the pair of contacts is an asymmetrical pair of source and drain contact structures, such as those combined with... Figure 4J As described. In other embodiments, the paired contacts are a symmetrical pair of source and drain contact structures. Specifically, after epitaxial growth, the contacts are... Figure 9E The trench 925 is formed. One trench may initially be recessed further than the other trench. In an embodiment, the contact portion is formed of a metallic material. In one such embodiment, the metallic material is formed by conformally depositing a contact metal and then filling any remaining trench volume. The conformal aspect of the deposition can be performed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow.

[0178] In embodiments, as described throughout, the integrated circuit structure includes non-planar devices, such as, but not limited to, finFETs or tri-gate devices having corresponding one or more overlying nanowire structures. In such embodiments, the corresponding semiconductor channel region is constituted by or formed within a three-dimensional body, wherein one or more discrete nanowire channel portions are overlying the three-dimensional body. In one such embodiment, the gate structure at least surrounds the top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0179] In embodiments, as described throughout, the substrate may be made of a semiconductor material capable of withstanding fabrication processes and in which charge can migrate. In embodiments, the substrate is a bulk substrate composed of crystalline silicon, silicon / germanium, or a germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof) for forming the active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate). The bulk substrate may alternatively be made of a Group III-V material. In embodiments, the bulk substrate is made of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is made of a Group III-V material, and the charge carrier dopant impurity atoms are charge carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0180] In embodiments, as described throughout, the trench isolation layer may be made of a material suitable for ultimately electrically isolating portions of a permanent gate structure from the underlying bulk substrate, or for facilitating the electrical isolation of portions of a permanent gate structure from the underlying bulk substrate, or for isolating active regions (such as isolation fin active regions) formed within the underlying bulk substrate. For example, in one embodiment, the trench isolation layer is made of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0181] In embodiments, as described throughout, the self-aligned gate cap isolation structure may be made of one or more materials suitable for electrically isolating portions of the permanent gate structure from each other, or for contributing to the isolation of portions of the permanent gate structure from each other. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower layer of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper layer of a material with a higher dielectric constant (such as hafnium oxide).

[0182] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art, such as computer systems (e.g., desktop computers, laptops, servers), cellular phones, personal electronic products, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0183] Figure 10 The figure illustrates a computing device 1000 according to one implementation of an embodiment of the present disclosure. The computing device 1000 houses a board 1002. The board 1002 may include multiple components, including but not limited to a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In a further implementation, the communication chip 1006 is part of the processor 1004.

[0184] Depending on its application, computing device 1000 may include other components that may be physically and electrically coupled to board 1002 or may not be physically and electrically coupled to board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0185] Communication chip 1006 implements wireless communication for transmitting data to and from computing device 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that enable data transmission through non-solid media using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, but in some embodiments, the associated device may not contain any wires. Communication chip 1006 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and higher generations. Computing device 1000 may include multiple communication chips 1006. For example, the first communication chip 1006 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0186] The processor 1000 of the computing device 1004 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures, such as an all-around gate integrated circuit structure formed using a differentiated release layer and constructed according to an implementation of embodiments of the present disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert such electronic data into other electronic data that may be stored in registers and / or memory.

[0187] The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. The integrated circuit die of the communication chip 1006 may include one or more structures, such as a gate-all-around integrated circuit structure formed using a differentiated release layer and constructed according to an implementation of embodiments of the present disclosure.

[0188] In a further implementation, another component housed within the computing device 1000 may include an integrated circuit die comprising one or more structures, such as a gate-all-around integrated circuit structure formed using a differentiated release layer and constructed according to an implementation of embodiments of the present disclosure.

[0189] In various implementations, the computing device 1000 can be a laptop, netbook, notebook computer, ultrabook, smartphone, tablet device, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, the computing device 1000 can be any other electronic device that processes data.

[0190] Figure 11 The figure illustrates an interposer 1100 including one or more embodiments of the present disclosure. Interposer 1100 is an intermediate substrate for bridging a first substrate 1102 to a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1100 is to extend connections to wider spacing or to reroute connections to different connections. For example, interposer 1100 may couple an integrated circuit die to a ball grid array (BGA) 1106, which may then be coupled to the second substrate 1104. In some embodiments, the first substrate 1102 and the second substrate 1104 are attached to opposite sides of interposer 1100. In other embodiments, the first substrate 1102 and the second substrate 1104 are attached to the same side of interposer 1100. And in a further embodiment, three or more substrates are interconnected by means of interposer 1100.

[0191] Interposer 1100 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (such as polyimide). In a further embodiment, interposer 1100 may be formed of a rigid or flexible material, which may include the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other group III-V and IV materials).

[0192] Interposer 1100 may include metal interconnects 1108 and vias 1110, including but not limited to through-silicon vias (TSVs) 1112. Interposer 1100 may further include embedded devices 1114, which may include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1100. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used to manufacture interposer 1100 or components included in interposer 1100.

[0193] Therefore, embodiments of this disclosure include a gate-all-around integrated circuit structure formed using a differential release layer, and a method for manufacturing a gate-all-around integrated circuit structure using a differential release layer.

[0194] The above description of the illustrated implementations of this disclosure (including those described in the abstract) is not intended to be exhaustive, nor is it intended to limit this disclosure to the precise forms disclosed. Although specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be appreciated by those skilled in the art. These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific implementations disclosed in the specification and claims.

[0195] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment has been described for a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The foregoing description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art benefiting from this disclosure.

[0196] The scope of this disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. Specifically, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from individual independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0197] Various embodiments or aspects of this disclosure are described herein. In some implementations, different embodiments are practiced separately. However, embodiments are not limited to those practiced separately. For example, two or more different embodiments may be combined together to be practiced as a single device, process, structure, etc. In some instances, the entirety of the embodiments may be combined together. In other instances, portions of a first embodiment may be combined with portions of one or more different embodiments. For example, portions of a first embodiment may be combined with portions of a second embodiment, or portions of a first embodiment may be combined with portions of a second embodiment and portions of a third embodiment. The following examples relate to further embodiments. Various features of different embodiments can be combined in various ways with some included features and other excluded features to suit a variety of different applications.

[0198] Example 1: The integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is located above the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is located above the first set of horizontal nanowires. A second gate structure is located above the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first and second gate structures and are vertically positioned between adjacent nanowires in the first and second sets of horizontal nanowires. Each of the dielectric spacers has a notch at a position vertically positioned between the first and second sets of horizontal nanowires.

[0199] Example 2: The integrated circuit structure as in Example 1, wherein the vertical position between the first group of horizontal nanowires and the second group of horizontal nanowires is the P / N boundary between the first group of horizontal nanowires and the second group of horizontal nanowires.

[0200] Example 3: An integrated circuit structure as in Example 1 or 2, wherein the first gate structure is a P-type gate structure and the second gate structure is an N-type gate structure.

[0201] Example 4: An integrated circuit structure as in Example 1 or 2, wherein the first gate structure is an N-type gate structure and the second gate structure is a P-type gate structure.

[0202] Example 5: A method for manufacturing an integrated circuit structure, comprising: forming a first set of horizontal nanowires and a first release layer over a sub-fin structure. The method further comprises: forming a second set of horizontal nanowires and a second release layer over the first set of horizontal nanowires. The method further comprises: removing the first release layer and the second release layer, wherein the first release layer is removed before the second release layer is removed. The method further comprises: forming a first gate structure over the first set of horizontal nanowires. The method further comprises: forming a second gate structure over the second set of horizontal nanowires.

[0203] Example 6: The method of Example 5, wherein the first release layer has the same components as the second release layer.

[0204] Example 7: The method of Example 5, wherein the first release layer has a different composition from the second release layer.

[0205] Example 8: The method of Example 7, wherein the second release layer is a SiGe release layer, and the germanium-silicon ratio of the SiGe release layer is less than that of the first release layer.

[0206] Example 9: The method of Example 5, 6, 7 or 8 further includes: forming dielectric spacers adjacent to the first gate structure and the second gate structure, each dielectric spacer having a notch at a position vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

[0207] Example 10: The method as in Example 5, 6, 7, 8 or 9, wherein the first gate structure is a P-type gate structure and the second gate structure is an N-type gate structure.

[0208] Example 11: The method as in Example 5, 6, 7, 8 or 9, wherein the first gate structure is an N-type gate structure and the second gate structure is a P-type gate structure.

[0209] Example 12: A computing device includes a board and components coupled to the board. The components include an integrated circuit structure comprising a first set of horizontal nanowires above a sub-fin structure. A first gate structure is situated above the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is situated above the first set of horizontal nanowires. A second gate structure is situated above the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first and second gate structures and are vertically positioned between adjacent nanowires in the first and second sets of horizontal nanowires. Each dielectric spacer has a notch at a position vertically positioned between the first and second sets of horizontal nanowires.

[0210] Example 13: A computing device as in Example 12, wherein the position vertically located between the first group of horizontal nanowires and the second group of horizontal nanowires in the integrated circuit structure is the P / N boundary between the first group of horizontal nanowires and the second group of horizontal nanowires.

[0211] Example 14: A computing device as in Example 12 or 13, wherein the first gate structure of the integrated circuit structure is a P-type gate structure and the second gate structure of the integrated circuit structure is an N-type gate structure.

[0212] Example 15: A computing device as in Example 12 or 13, wherein the first gate structure of the integrated circuit structure is an N-type gate structure and the second gate structure of the integrated circuit structure is a P-type gate structure.

[0213] Example 16: A computing device such as Example 12, 13, 14 or 15, further including a memory coupled to a board.

[0214] Example 17: A computing device such as Example 12, 13, 14, 15 or 16 further includes a communication chip coupled to a board.

[0215] Example 18: A computing device such as Example 12, 13, 14, 15, 16 or 17, further including a camera coupled to the board.

[0216] Example 19: A computing device such as Example 12, 13, 14, 15, 16, 17 or 18, further comprising a battery coupled to a plate.

[0217] Example 20: A computing device as in Example 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: The first set of horizontal nanowires is positioned above the sub-fin structure; A first gate structure is situated above the first set of horizontal nanowires, wherein the first set of horizontal nanowires extends laterally beyond the first gate structure. The second group of horizontal nanowires is positioned above the first group of horizontal nanowires. A second gate structure is situated above the second set of horizontal nanowires, wherein the second set of horizontal nanowires extends laterally beyond the second gate structure; and A dielectric spacer is adjacent to the first gate structure and the second gate structure and is vertically positioned between adjacent nanowires in the first group of horizontal nanowires and the second group of horizontal nanowires. Each dielectric spacer has a notch at a position vertically positioned between the first group of horizontal nanowires and the second group of horizontal nanowires.

2. The integrated circuit structure as described in claim 1, wherein, The position vertically located between the first group of horizontal nanowires and the second group of horizontal nanowires is the P / N boundary between the first group of horizontal nanowires and the second group of horizontal nanowires.

3. The integrated circuit structure as described in claim 1 or 2, wherein, The first gate structure is a P-type gate structure, and the second gate structure is an N-type gate structure.

4. The integrated circuit structure as described in claim 1 or 2, wherein, The first gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure.

5. A method for manufacturing an integrated circuit structure, comprising: A first set of horizontal nanowires and a first release layer are formed above the sub-fin structure; A second set of horizontal nanowires and a second release layer are formed on top of the first set of horizontal nanowires; Remove the first release layer and the second release layer, wherein the first release layer is removed before the second release layer is removed; A first gate structure is formed on the first set of horizontal nanowires; and A second gate structure is formed on the second set of horizontal nanowires.

6. The method of claim 5, wherein, The first release layer has the same components as the second release layer.

7. The method of claim 5, wherein, The first release layer has a different composition than the second release layer.

8. The method of claim 7, wherein, The second release layer is a SiGe release layer, and the germanium-to-silicon ratio of the SiGe release layer is less than that of the first release layer.

9. The method of claim 5, 6, 7 or 8, further comprising: Dielectric spacers are formed adjacent to the first gate structure and the second gate structure, each of the dielectric spacers having a notch at a position vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

10. The method as described in claim 5, 6, 7 or 8, wherein, The first gate structure is a P-type gate structure, and the second gate structure is an N-type gate structure.

11. The method as described in claim 5, 6, 7 or 8, wherein, The first gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure.

12. A computing device, comprising: plate; as well as Components, coupled to the board, the components including an integrated circuit structure, the integrated circuit structure comprising: The first set of horizontal nanowires is positioned above the sub-fin structure; A first gate structure is situated above the first set of horizontal nanowires, wherein the first set of horizontal nanowires extends laterally beyond the first gate structure. The second group of horizontal nanowires is positioned above the first group of horizontal nanowires. A second gate structure is situated above the second set of horizontal nanowires, wherein the second set of horizontal nanowires extends laterally beyond the second gate structure; and A dielectric spacer is adjacent to the first gate structure and the second gate structure and is vertically positioned between adjacent nanowires in the first group of horizontal nanowires and the second group of horizontal nanowires. Each dielectric spacer has a notch at a position vertically positioned between the first group of horizontal nanowires and the second group of horizontal nanowires.

13. The computing device of claim 12, wherein, The position vertically located between the first group of horizontal nanowires and the second group of horizontal nanowires in the integrated circuit structure is the P / N boundary between the first group of horizontal nanowires and the second group of horizontal nanowires.

14. The computing device as claimed in claim 12 or 13, wherein, The first gate structure of the integrated circuit structure is a P-type gate structure, and the second gate structure of the integrated circuit structure is an N-type gate structure.

15. The computing device as claimed in claim 12 or 13, wherein, The first gate structure of the integrated circuit structure is an N-type gate structure, and the second gate structure of the integrated circuit structure is a P-type gate structure.

16. The computing device of claim 12 or 13, further comprising: The memory is coupled to the board.

17. The computing device of claim 12 or 13, further comprising: A communication chip is coupled to the board.

18. The computing device of claim 12 or 13, further comprising: The camera is coupled to the plate.

19. The computing device of claim 12 or 13, further comprising: The battery is coupled to the plate.

20. The computing device of claim 12 or 13, wherein, The component is a packaged integrated circuit die.

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