Power device wafer failure analysis method and device
By performing defect scanning on silicon carbide power device wafers and analyzing the relationship between the substrate, epitaxial layer, and surface, the problem of device performance being affected by defects was solved, resulting in improved device performance and reduced failure rate.
Patent Information
- Application Number
- CN202512033020.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-31
AI Technical Summary
Existing silicon carbide power devices contain various types of defects in the substrate and epitaxial layer, which affect device performance. Although the defect density has been reduced, it still does not reach the level of silicon-based materials, increasing the probability of device failure.
By scanning the surface of the power device wafer, the surface of the epitaxial layer, and the surface of the substrate for defects, the failure point information and defect information of each are obtained. The relationship between the three is analyzed, and then the substrate or epitaxial layer is screened and optimized to reduce the failure probability.
It improves the performance of power devices, reduces the probability of failure, and enhances the accuracy of analysis and optimization results.
Smart Images
Figure CN121762447A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a method and apparatus for analyzing the failure of power device wafers. Background Technology
[0002] Silicon carbide (SiC) materials possess excellent physicochemical properties, such as a large bandgap, high carrier saturation migration velocity, high critical breakdown field strength, high thermal conductivity, and good chemical stability. Based on these properties, silicon carbide materials are considered ideal materials for high-frequency, high-power, high-temperature resistant, and radiation-resistant electronic devices.
[0003] Currently, silicon carbide power devices contain various types of defects in the silicon carbide substrate and epitaxial layer, which are inherited. With the advancement of technology, the defect density has been greatly reduced, but it is still impossible to achieve the defect level of silicon-based materials. These defects have a great impact on device performance. Summary of the Invention
[0004] The technical problem solved by this invention is how to improve the device performance of power devices.
[0005] To address the aforementioned technical problems, this invention provides a method for analyzing the failure of a power device wafer. The power device wafer includes a substrate, an epitaxial layer on the substrate, and a plurality of power devices on the epitaxial layer. The method includes: performing a defect scan on the surface of the power device wafer to obtain failure location information of the power devices on the power device wafer; performing a defect scan on the surface of the epitaxial layer to obtain defect information of the epitaxial layer surface; performing a defect scan on the surface of the substrate to obtain defect information of the substrate surface; obtaining a relationship between the power device failure and the defects on the epitaxial layer surface based on the failure location information of the power devices and the defect information of the epitaxial layer surface; obtaining a relationship between the power device failure and the defects on the substrate surface based on the failure location information of the power devices and the defect information of the substrate surface; and obtaining a relationship between the defects on the epitaxial layer surface and the defects on the substrate surface based on the defect information of the epitaxial layer surface and the defects on the substrate surface.
[0006] Optionally, before performing defect scanning on the surface of the power device wafer, the method further includes: constructing a partitioning grid based on the size of a single power device within the device layer, the partitioning grid comprising arrayed cells; and partitioning the surface of the power device wafer according to the partitioning grid to obtain several test areas.
[0007] Optionally, dividing the surface of the power device wafer includes: aligning the center point of the dividing grid with the center point of the power device wafer, wherein the line connecting the center point of the dividing grid and the center point of the power device wafer is a projection ray; and projecting the power device wafer and the dividing grid to coincide based on the projection ray.
[0008] Optionally, a first defect scan is performed on the surface of the power device wafer to obtain the failure point information of the power device on the power device wafer, including: performing electrical failure tests on the power devices in several test areas based on the location information of several test areas, locating the fault area, and obtaining the location information of the fault point in the fault area; and performing physical failure tests on the fault point in the fault area based on the location information of the fault area to obtain the physical defects of the fault point.
[0009] Optionally, a defect scan is performed on the surface of the epitaxial layer to obtain defect information of the surface of the epitaxial layer, including: using high-precision differential interference optics and photoluminescence imaging to scan the surface of the epitaxial layer to obtain first defect information; and obtaining a first defect region based on the first defect information and the location information of the test area.
[0010] Optionally, based on the failure location information of the power device and the defect information of the epitaxial layer surface, the relationship between the failure of the power device and the defects of the epitaxial layer surface is obtained, including: obtaining the device failure rate in the first defect area according to the location information of the fault area and the location information of the first defect area.
[0011] Optionally, a defect scan is performed on the substrate surface to obtain defect information of the substrate surface, including: thinning the power device wafer to expose the substrate surface and forming a second etch pit on the substrate surface; using high-precision differential interference optics to image and obtain the position information of the test area corresponding to the second etch pit; obtaining a number of second test dislocation regions based on the position information of the test area corresponding to the second etch pit; obtaining the dislocation distribution and region density in each of the second test dislocation regions; and locating the second dislocation region based on the region density in the second test dislocation region.
[0012] Optionally, based on the failure location information of the power device and the defect information of the substrate surface, the relationship between the failure of the power device and the defects of the substrate surface is obtained, including: obtaining the device failure rate in the second dislocation region according to the location information of the fault region and the location information of the second dislocation region.
[0013] Optionally, performing defect scanning on the surface of the epitaxial layer to obtain defect information of the epitaxial layer surface further includes: thinning the power device wafer to expose the surface of the epitaxial layer, forming a first etch pit located on the surface of the epitaxial layer; using high-precision differential interference optics to image and obtain the position information of the test area corresponding to the first etch pit; obtaining a plurality of first test dislocation regions based on the position information of the test area corresponding to the first etch pit; obtaining the dislocation distribution and region density in each of the first test dislocation regions; and locating the first dislocation region based on the region density in the first test dislocation regions.
[0014] Optionally, based on the defect information of the epitaxial layer surface and the defect information of the substrate surface, the relationship between the defects of the epitaxial layer surface and the defects of the substrate surface is obtained, including: obtaining the inheritance probability between the dislocations on the epitaxial layer surface and the dislocations on the substrate surface according to the position information of the first dislocation region and the position information of the second dislocation region.
[0015] Optionally, the analysis method for power device wafer failure further includes: screening and optimizing the substrate and epitaxial layer of the power device wafer based on the relationship between the power device failure and the surface defects of the epitaxial layer, the failure location information of the power device and the defect information of the substrate surface, as well as the defect information of the epitaxial layer surface and the defect information of the substrate surface.
[0016] Accordingly, the present invention also provides an analysis apparatus for power device wafer failure, comprising: a first defect scanning unit for performing defect scanning on the surface of the power device wafer to obtain failure point information of the power device on the power device wafer; a second defect scanning unit for performing defect scanning on the surface of an epitaxial layer to obtain defect information of the surface of the epitaxial layer; a third defect scanning unit for performing defect scanning on the surface of a substrate to obtain defect information of the surface of the substrate; a first analysis unit for obtaining a relationship between the failure of the power device and the defects on the surface of the epitaxial layer based on the failure point information of the power device and the defect information of the surface of the epitaxial layer; a second analysis unit for obtaining a relationship between the failure of the power device and the defects on the surface of the substrate based on the failure point information of the power device and the defect information of the surface of the substrate; and a third analysis unit for obtaining a relationship between the defects on the surface of the epitaxial layer and the defects on the surface of the substrate based on the defect information of the surface of the epitaxial layer.
[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0018] In the technical solution of this invention, defects are sequentially scanned on the surface of the power device wafer, the surface of the epitaxial layer, and the surface of the substrate. Based on the defect information of the power device wafer surface, the surface of the epitaxial layer, and the surface of the substrate, the relationship between the defect information of the three is obtained. This allows analysis of the impact of defects on the substrate surface or the surface of the epitaxial layer on the failure of the power device wafer. Subsequently, the substrate or epitaxial layer can be screened and optimized based on the analyzed relationship, thereby reducing the failure probability of the power device wafer and improving the device performance of the power device.
[0019] Furthermore, the technical solution of the present invention constructs an array of cells based on the size of a single power device within the device layer, and divides the surface of the power device wafer according to the array of cells to obtain a test area. This achieves a precise correspondence between the test area and the size of a single power device within the device layer, thereby improving the accuracy of analyzing the relationship between power device failure and substrate surface defects. Attached Figure Description
[0020] Figure 1 This is a flowchart illustrating the analysis method for power device wafer failure in an embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram of the structure of the power device wafer in an embodiment of the present invention;
[0022] Figure 3 This is a schematic flowchart illustrating the relationship between the failure of the power device and the surface defects of the epitaxial layer in an embodiment of the present invention;
[0023] Figure 4 This is a schematic flowchart illustrating the relationship between the failure of the power device and the defects on the substrate surface in an embodiment of the present invention.
[0024] Figure 5 This is a schematic diagram of the substrate surface structure in an embodiment of the present invention;
[0025] Figure 6 This embodiment of the invention obtains the relationship between defects on the surface of the epitaxial layer and defects on the surface of the substrate;
[0026] Figure 7 This is a schematic diagram of the structure of the epitaxial layer surface in an embodiment of the present invention;
[0027] Figure 8 This is a schematic diagram of the structure of the analysis device for power device wafer failure in an embodiment of the present invention. Detailed Implementation
[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0029] Current silicon carbide power devices suffer from device failure issues. Various types of defects exist in the silicon carbide substrate and epitaxial layer, and these defects have a succession relationship. With the advancement of technology, the defect density has been greatly reduced, but it is still impossible to achieve the defect level of silicon-based materials. These defects have a significant impact on device performance.
[0030] However, the correlation between defects on silicon carbide substrates and epitaxial layers and the failure of silicon carbide power devices is currently unavailable, so the failure probability of silicon carbide power devices continues to increase.
[0031] To address the aforementioned technical problems, this invention provides a method for analyzing the failure of a power device wafer. The power device wafer includes a substrate, an epitaxial layer on the substrate, and a plurality of power devices on the epitaxial layer. The method includes: performing a defect scan on the surface of the power device wafer to obtain failure location information of the power devices on the power device wafer; performing a defect scan on the surface of the epitaxial layer to obtain defect information of the epitaxial layer surface; performing a defect scan on the surface of the substrate to obtain defect information of the substrate surface; obtaining a relationship between the power device failure and the defects on the epitaxial layer surface based on the failure location information of the power devices and the defect information of the epitaxial layer surface; obtaining a relationship between the power device failure and the defects on the substrate surface based on the failure location information of the power devices and the defect information of the substrate surface; and obtaining a relationship between the defects on the epitaxial layer surface and the defects on the substrate surface based on the defect information of the epitaxial layer surface and the defects on the substrate surface.
[0032] By sequentially scanning the surface of the power device wafer, the surface of the epitaxial layer, and the surface of the substrate for defects, and based on the defect information of the power device wafer surface, the surface of the epitaxial layer, and the surface of the substrate, the relationship between the defect information of the three can be obtained. This allows for the analysis of the impact of defects on the substrate surface or the surface of the epitaxial layer on the failure of the power device wafer. Subsequently, the substrate or epitaxial layer can be screened and optimized based on the analyzed relationship, thereby reducing the probability of power device wafer failure and improving the device performance of the power device.
[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0034] refer to Figure 1 The analysis method for power device wafer failure includes:
[0035] S1: Perform a defect scan on the surface of the power device wafer to obtain the failure point information of the power device on the power device wafer.
[0036] In some embodiments, the power device wafer includes a substrate, an epitaxial layer on the substrate, and a power device layer on the epitaxial layer, wherein the power device layer has a plurality of power devices.
[0037] Specifically, the power device wafer is a silicon carbide power device wafer, which includes transistors or diodes.
[0038] The failure point information of the power device on the power device wafer refers to the location of the electrical failure information of the specific power device, such as a short circuit in a transistor or diode, which leads to the failure of the power device.
[0039] S2: Perform a defect scan on the surface of the epitaxial layer to obtain defect information of the surface of the epitaxial layer; perform a defect scan on the surface of the substrate to obtain defect information of the surface of the substrate.
[0040] S3: Perform a defect scan on the substrate surface to obtain defect information on the substrate surface.
[0041] The substrate and the epitaxial layer are both made of silicon carbide.
[0042] Defects on the substrate include scratches, stacking faults, microtubules, particles, pits, bumps, etc.; defects on the epitaxial layer include scratches, triangular stacking faults, volumetric stacking faults, triangles, dropped objects, particles, microtubules, bumps, pits, step lines, etc.
[0043] In some embodiments, high-precision differential interference optics and photoluminescence imaging are used to perform defect scanning on the surface of the power device wafer, the surface of the substrate, and the surface of the epitaxial layer, resulting in two-channel scanning results on the surface of the power device wafer.
[0044] Among them, the high-precision differential interference optics principle is suitable for using beam shearing and interference to obtain the height gradient intensity of the power device wafer surface, the substrate surface and the epitaxial layer surface, and to convert the microscopic height differences of the power device wafer surface, the substrate surface and the epitaxial layer surface into high-contrast bright or dark or color images, thereby clearly showing defects.
[0045] The photoluminescence principle is suitable for using high-power ultraviolet / deep ultraviolet lasers to focus the laser and scan the sample surface, while collecting weak fluorescence signals to obtain information about internal defects in the power device wafer.
[0046] S4: Based on the failure location information of the power device and the defect information of the epitaxial layer surface, the relationship between the failure of the power device and the defects of the epitaxial layer surface is obtained.
[0047] In some embodiments, the relationship between the power device failure and the epitaxial layer surface defect refers to the correspondence between the location of the failed device on the power device and the location of the epitaxial layer surface defect.
[0048] S5: Based on the failure location information of the power device and the defect information of the substrate surface, the relationship between the failure of the power device and the defects of the substrate surface is obtained.
[0049] In some embodiments, the relationship between the power device failure and the substrate surface defect refers to the correspondence between the location of the failed device on the power device and the location of the substrate surface defect.
[0050] The defect information on the substrate surface includes substrate surface defects and substrate surface dislocations.
[0051] S6: Based on the defect information of the epitaxial layer surface and the defect information of the substrate surface, obtain the relationship between the defects of the epitaxial layer surface and the defects of the substrate surface.
[0052] In some embodiments, the relationship between the epitaxial layer surface defects and the substrate surface defects refers to the relationship between the defects on the epitaxial layer surface and the substrate surface defects, as well as the relationship between the epitaxial surface defects and the substrate surface dislocations.
[0053] Before performing defect scanning on the surface of the power device wafer in step S1, the method further includes: constructing a grid based on the size of a single power device within the device layer, the grid comprising arrayed cells; and dividing the surface of the power device wafer according to the grid to obtain several test areas.
[0054] The size of a single power device within the device layer is the same as the size of the cell.
[0055] In an embodiment of the present invention, the cell is a rectangle.
[0056] refer to Figure 2 , Figure 2 This is a schematic diagram of the power device layer on the power device wafer. Based on the grid division, the surface of the power device layer 701 is divided to obtain several test areas 702.
[0057] The process of dividing the surface of the power device wafer 701 includes: aligning the center point of the dividing grid with the center point of the power device wafer 701, wherein the line connecting the center point of the dividing grid and the center point of the power device wafer 701 is a projection ray; and projecting the power device wafer 701 and the dividing grid to coincide based on the projection ray.
[0058] In some embodiments, the array of grids is the same size as the defect scanning region.
[0059] In a specific embodiment, the diameter of the power device chip is 150mm, 200mm or 300mm, and specifically, the size of the cell is 5mm*5mm.
[0060] In the above scheme, cells arranged in an array are constructed according to the size of a single power device in the device layer, and the surface of the power device wafer is divided according to the cells arranged in an array to obtain the test area. This achieves a precise correspondence between the test area and the size of a single power device in the device layer, improving the accuracy of analyzing the relationship between power device failure and substrate surface defects.
[0061] refer to Figure 3 Step S1 involves performing a first defect scan on the surface of the power device wafer to obtain failure point information of the power device on the power device wafer, including:
[0062] S11: Based on the location information of several test areas, perform electrical failure tests on the power devices in the several test areas, locate the fault area, and obtain the location information of the fault point within the fault area.
[0063] Specifically, the electrical failure test characterizes whether the power device is in a normal working state or in a short circuit state. When the power device is in a short circuit state, the power device is a failed power device, and the test area where the failed power device is located is the fault area.
[0064] The location information of the fault point is represented by the center coordinates of the cell corresponding to the fault area.
[0065] Continue to refer to Figure 2 , Figure 2 The power devices within the unfilled test area 702 are in normal operating condition. Figure 2 The power device in the black-filled test area is in a failed state, i.e. Figure 2 The test area filled with black is fault area 703.
[0066] S12: Based on the location information of the fault area, perform physical failure tests on the fault points within the fault area to obtain the physical defects of the fault points.
[0067] In some embodiments, the physical defects include scratches, steps, particles, dents, uneven polishing, film thickness variations, and other defects related to surface flatness. The physical defects of the fault point are obtained by high-precision differential interference optics and photoluminescence imaging.
[0068] Step S2 involves performing a defect scan on the surface of the epitaxial layer to obtain defect information on the surface of the epitaxial layer, including:
[0069] S21: Using the high-precision differential interference optical principle and photoluminescence principle, the surface of the epitaxial layer is scanned for defects to obtain the first defect information.
[0070] In some embodiments, before performing defect scanning on the epitaxial layer surface, the surface of the power device wafer is thinned to remove the power device layer and expose the epitaxial layer surface.
[0071] S22: Based on the first defect information and the location information of the test area, the first defect area is obtained.
[0072] In some embodiments, the epitaxial layer surface is divided according to the grid to obtain several test areas, wherein the wafer area on the epitaxial layer coincides with the projection of the test area on the substrate surface; based on the grid, a defect scan is performed on the epitaxial layer surface to obtain several first defect information on the epitaxial layer surface, and the location information of the first defect information is located, wherein the first defect information is the location information of the test area where the first defect is located; the test area with the first defect information is defined as the first defect area.
[0073] Step S4, based on the failure location information of the power device and the defect information of the epitaxial layer surface, obtains the relationship between the power device failure and the defects on the epitaxial layer surface, including:
[0074] S41: Based on the location information of the fault area and the location information of the first defect area, obtain the device failure rate within the first defect area.
[0075] The location information of the first defect area is represented by the center coordinates of the cell corresponding to the test area where the first defect is located.
[0076] The device failure rate within the first defect area refers to the first number of test areas where the location information of the first defect area and the location information of the fault area are matched, and the first number of test areas where the first defect information and the fault point exist simultaneously at the same location coordinates are obtained; the ratio of the first number to the number of the first defect area is calculated, and the ratio is the device failure rate within the first defect area.
[0077] Specifically, when the device failure rate is greater than a preset threshold, that is, the first defect information on the current epitaxial layer affects the performance of the power device on the power device wafer.
[0078] In some embodiments, the method for analyzing power device wafer failure further includes: screening and optimizing the epitaxial layer of the power device wafer based on the relationship between the power device failure and the surface defects of the epitaxial layer.
[0079] In the above scheme, by analyzing the relationship between the power device failure and the surface defects of the epitaxial layer, the correspondence between the location of the fault region and the location of the first defect region is obtained, thereby obtaining the device failure rate in the first defect region and the relationship between the location of the power device failure and the location of the defect on the epitaxial layer. Subsequently, based on the position correspondence, the epitaxial layer can be accurately screened and optimized to reduce the device failure rate and improve the device performance.
[0080] exist Figure 3 Based on, refer to Figure 4 Step S3 involves performing a defect scan on the substrate surface to obtain defect information, including:
[0081] S31: Thin the power device wafer to expose the substrate surface, forming a second etch pit on the substrate surface.
[0082] The second type of corrosion pit includes threading screw dislocation (TSD), basal plane dislocation (BPD), and threading edge dislocation (TED).
[0083] Specifically, the through-screw dislocation type is the first dislocation type, the base-plane dislocation type is the second dislocation type, and the through-edge dislocation type is the third dislocation type.
[0084] The process for thinning the power device wafer is a wet etching process, the etching solution includes KOH, the etching time is 15 minutes, and the etching temperature is 550 degrees Celsius.
[0085] The second corrosion pit is characterized as a dislocation on the substrate surface.
[0086] S32: Using high-precision differential interference optical principle imaging, obtain the location information of the test area corresponding to the second corrosion pit.
[0087] In some embodiments, the location information of the test area corresponding to different types of the second corrosion pit is obtained.
[0088] S33: Based on the location information of the test area corresponding to the second corrosion pit, several second test dislocation regions are obtained.
[0089] The second test dislocation region is characterized by the center coordinate position of the cell in the test region corresponding to the second corrosion pit.
[0090] In some embodiments, the substrate surface is divided according to the grid to obtain several test areas, wherein the wafer area on the substrate and the projection of the test area on the substrate surface coincide; based on the grid, different types of second etch pits on the substrate surface are scanned for defects to obtain the position information of the test area corresponding to the second etch pit, and the test area corresponding to the second etch pit is defined as the second test dislocation region.
[0091] S34: Obtain the dislocation distribution and region density in each of the second test dislocation regions.
[0092] Specifically, the ratio between the number of second test dislocation regions with the first dislocation type and the total number of test regions on the substrate surface is obtained and calculated. This ratio is the first region density within the second test dislocation region.
[0093] The ratio between the number of second test dislocation regions with the second dislocation type and the total number of test regions on the substrate surface is obtained and calculated. This ratio is the second region density within the second test dislocation region.
[0094] The ratio between the number of second test dislocation regions with the third dislocation type and the total number of test regions on the substrate surface is obtained and calculated. This ratio is the third region density within the second test dislocation region.
[0095] Obtain and calculate the ratio between the total number of all second test dislocation regions and the total number of test regions on the substrate surface. This ratio is the total region density within the second test dislocation regions.
[0096] The dislocation distribution within the second test dislocation region is the location information of the second test dislocation region.
[0097] S35: Locate the second dislocation region based on the region density within the second test dislocation region.
[0098] In a specific embodiment, when the density of the region within the second test dislocation region is greater than a preset threshold, the second test dislocation region is defined as the second dislocation region.
[0099] For example, when the density of the first region is greater than a preset threshold, the second test dislocation region under the density of the first region is defined as the second dislocation region. That is, the first dislocation type under the density of the first region may affect the performance of the power device formed subsequently.
[0100] For example, when the total region density is greater than a preset threshold, the second test dislocation region under the total region density is defined as the second dislocation region. That is, the first dislocation type, the second dislocation type and the third dislocation type under the total region density may affect the performance of the power device formed subsequently.
[0101] refer to Figure 5 , Figure 5 The substrate is 704 surface. Figure 5 No second corrosion pit was found in the unfilled test area 705. Figure 5 A second corrosion pit was found within the black-filled test area, and Figure 5 The density within the black-filled test area (e.g., the density of the first area, the density of the second area, or the total density) is greater than a preset threshold, i.e. Figure 5 The black-filled test area is the second test dislocation region 706.
[0102] Step S5, based on the failure location information of the power device and the defect information of the substrate surface, obtains the relationship between the failure of the power device and the defects on the substrate surface, including:
[0103] S51: Based on the location information of the fault region and the location information of the second dislocation region, obtain the device failure rate within the second dislocation region.
[0104] The device failure rate within the second dislocation region refers to the second number of test areas where the location information of the second dislocation region is matched with the location information of the fault region, and the second number of test areas where the dislocation type and fault point corresponding to the second corrosion pit exist simultaneously at the same location coordinates; the ratio of the second number to the number of the second dislocation region is calculated, and the ratio is the device failure rate within the second dislocation region.
[0105] In some embodiments, a second number of test areas where both the first misalignment type and the fault point exist simultaneously at the same location coordinates is obtained; the ratio of the second number to the number of the second misalignment areas is calculated, and the ratio is the device failure rate in the second misalignment area corresponding to the first misalignment type.
[0106] In other embodiments, a second number of test areas where all dislocation types and fault points exist simultaneously at the same location coordinates is obtained; the ratio of the second number to the number of the second dislocation areas is calculated, and the ratio is the device failure rate in the second dislocation area corresponding to all dislocation types.
[0107] In some embodiments, the method for analyzing the failure of power device wafers further includes: screening and optimizing the substrate of the power device wafer based on the failure location information of the power device and the defect information of the substrate surface.
[0108] In the above scheme, by analyzing the relationship between the failure of the power device and the defects on the substrate surface, the correspondence between the location of the fault region and the location of the second dislocation region is obtained, thereby obtaining the device failure rate in the second dislocation region and the relationship between the location of the power device failure and the location of the defects on the substrate. Subsequently, the substrate can be accurately screened and optimized based on the position correspondence, thereby reducing the device failure rate and improving the device performance.
[0109] exist Figure 4 Based on, refer to Figure 6 Step S2 involves performing a defect scan on the surface of the epitaxial layer to obtain defect information on the surface of the epitaxial layer, and further includes:
[0110] S23: Thin the power device wafer to expose the surface of the epitaxial layer, forming a first etch pit on the surface of the epitaxial layer.
[0111] It should be noted that the process steps for thinning the power device wafer to expose the surface of the epitaxial layer are the same as those in step S31, and will not be repeated here.
[0112] The first corrosion pit includes the following types: threading screw dislocation (TSD), basal plane dislocation (BPD), and threading edge dislocation (TED).
[0113] Specifically, the through-screw dislocation type is the first dislocation type, the base-plane dislocation type is the second dislocation type, and the through-edge dislocation type is the third dislocation type.
[0114] The first corrosion pit is characterized as a dislocation on the surface of the epitaxial layer.
[0115] S24: Using high-precision differential interference optical principle imaging, obtain the location information of the test area corresponding to the first corrosion pit.
[0116] In some embodiments, the location information of the test area corresponding to different types of the first corrosion pit is obtained.
[0117] S25: Based on the location information of the test area corresponding to the first corrosion pit, several first test dislocation regions are obtained.
[0118] The first test dislocation region is characterized by the center coordinate position of the cell in the test region corresponding to the first corrosion pit.
[0119] In some embodiments, the epitaxial layer surface is divided according to the grid to obtain several test areas, wherein the wafer area on the epitaxial layer coincides with the projection of the test area on the substrate surface; based on the grid, different types of first etch pits on the epitaxial layer surface are subjected to defect scanning to obtain the position information of the test area corresponding to the first etch pit, and the test area corresponding to the first etch pit is defined as the first test dislocation region.
[0120] S26: Obtain the dislocation distribution and region density in each of the first test dislocation regions.
[0121] Specifically, the ratio between the number of the first test dislocation regions with the first dislocation type and the total number of test regions on the surface of the epitaxial layer is obtained and calculated. The ratio is the first region density within the first test dislocation region.
[0122] Obtain and calculate the ratio between the number of the first test dislocation regions with the second dislocation type and the total number of test regions on the surface of the epitaxial layer. The ratio is the second region density within the first test dislocation region.
[0123] Obtain and calculate the ratio between the number of first test dislocation regions with the third dislocation type and the total number of test regions on the surface of the epitaxial layer. The ratio is the density of the third region within the first test dislocation region.
[0124] Obtain and calculate the ratio between the total number of all first test dislocation regions and the total number of test regions on the surface of the epitaxial layer. This ratio is the total region density within the first test dislocation regions.
[0125] The dislocation distribution within the first test dislocation region is the location information of the first test dislocation region.
[0126] S27: Locate the first dislocation region based on the regional density within the first test dislocation region.
[0127] In a specific embodiment, when the density of the region within the first test dislocation region is greater than a preset threshold, the first test dislocation region is defined as the first dislocation region.
[0128] For example, when the density of the first region is greater than a preset threshold, the first test dislocation region under the density of the first region is defined as the first dislocation region. That is, the first dislocation type under the density of the first region may affect the performance of the power device formed subsequently.
[0129] For example, when the total region density is greater than a preset threshold, the first test dislocation region under the total region density is defined as the first dislocation region. That is, the first dislocation type, the second dislocation type and the third dislocation type under the total region density may affect the performance of the power device formed subsequently.
[0130] In some embodiments, the preset threshold for density is 60 / cm³. 2 .
[0131] refer to Figure 7 , Figure 7 The surface of the epitaxial layer 707 Figure 7 No second corrosion pit was found in the unfilled test area 708. Figure 7 The first corrosion pit was found within the black-filled test area, and Figure 7 The density within the black-filled test area (e.g., the density of the first area, the density of the second area, or the total density) is greater than a preset threshold, i.e. Figure 7 The black-filled test area is the first test dislocation region 709.
[0132] In some embodiments, dislocation information on the epitaxial layer surface is obtained before obtaining dislocation information on the substrate surface. Step S6, based on the defect information on the epitaxial layer surface and the defect information on the substrate surface, determines the relationship between the defects on the epitaxial layer surface and the defects on the substrate surface, including:
[0133] S61: Based on the position information of the first dislocation region and the position information of the second dislocation region, obtain the inheritance probability between the dislocation on the substrate surface and the dislocation on the epitaxial layer surface.
[0134] The inheritance probability between dislocations on the substrate surface and dislocations on the epitaxial layer surface refers to the third number of test areas where the position information of the second dislocation region is matched with the position information of the first dislocation region, and the dislocation type corresponding to the second etch pit and the dislocation type corresponding to the first etch pit are simultaneously present at the same position coordinate. The ratio of the third number to the number of the second dislocation region is calculated, and the ratio is the inheritance probability between dislocations on the substrate surface and dislocations on the epitaxial layer surface.
[0135] In some embodiments, the method for analyzing the failure of power device wafers further includes: screening and optimizing the substrate and epitaxial layer of the power device wafer based on the defect information on the surface of the epitaxial layer and the defect information on the surface of the substrate.
[0136] In the above scheme, by analyzing the relationship between defects on the surface of the epitaxial layer and the surface of the substrate, the correspondence between the positions of the first dislocation region and the second dislocation region is obtained. This yields the inheritance probability between dislocations on the substrate surface and dislocations on the surface of the epitaxial layer, as well as the relationship between the positions of dislocations on the substrate surface and the positions of dislocations on the surface of the epitaxial layer. Subsequently, based on the positional correspondence, the substrate and epitaxial layer can be accurately screened and optimized, reducing the device failure rate and improving device performance.
[0137] In other embodiments, performing defect scanning on the surface of the epitaxial layer to obtain defect information of the surface of the epitaxial layer includes: performing defect scanning on the surface of the epitaxial layer to obtain second defect information; and obtaining a second defect region based on the second defect information and the location information of the test area.
[0138] Based on the defect information of the epitaxial layer surface and the defect information of the substrate surface, the relationship between the defects of the epitaxial layer surface and the defects of the substrate surface is obtained, which further includes: obtaining the inheritance probability between the defects of the epitaxial layer surface and the defects of the substrate surface according to the location information of the second defect region and the location information of the first defect region.
[0139] Specifically, the inheritance probability between defects on the epitaxial layer surface and defects on the substrate surface refers to the fourth number of test areas where the location information of the second defect area is matched with the location information of the first defect area, and the first and second defect information exist simultaneously at the same location coordinates are obtained; the ratio of the fourth number to the number of first defect areas is calculated, which is the inheritance probability between defects on the epitaxial layer surface and defects on the substrate surface.
[0140] In other embodiments, the relationship between the defects on the epitaxial layer surface and the defects on the substrate surface is obtained based on the defect information on the surface of the epitaxial layer and the defect information on the substrate surface. This further includes obtaining the relationship between the defects on the surface of the epitaxial layer and the defects on the substrate surface, as well as the relationship between the defects on the epitaxial surface and the dislocations on the substrate surface.
[0141] Accordingly, refer to Figure 8 The present invention also provides an analysis apparatus 80 for power device wafer failure, comprising:
[0142] The first defect scanning unit 81 is used to perform defect scanning on the surface of the power device wafer to obtain the failure point information of the power device on the power device wafer;
[0143] The second defect scanning unit 82 is used to perform defect scanning on the surface of the epitaxial layer and obtain defect information of the surface of the epitaxial layer.
[0144] The third defect scanning unit 83 is used to perform defect scanning on the substrate surface and obtain defect information of the substrate surface;
[0145] The first analysis unit 84 is used to obtain the relationship between the failure of the power device and the defects on the surface of the epitaxial layer based on the failure point information of the power device and the defect information on the surface of the epitaxial layer.
[0146] The second analysis unit 85 is used to obtain the relationship between the failure of the power device and the defects on the substrate surface based on the failure location information of the power device and the defect information on the substrate surface.
[0147] The third analysis unit 86 is used to obtain the relationship between the defects on the surface of the epitaxial layer and the defects on the surface of the substrate based on the defect information on the surface of the epitaxial layer and the defect information on the surface of the substrate.
[0148] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method of analyzing a power device wafer failure, wherein, The power device wafer comprises a substrate, an epitaxial layer on the substrate, and a power device layer on the epitaxial layer, wherein the power device layer has a plurality of power devices, and the power device wafer comprises: a defect scanning is performed on the surface of the power device wafer to obtain failure point information of the power devices on the power device wafer; a defect scanning is performed on the surface of the epitaxial layer to obtain defect information of the surface of the epitaxial layer; a defect scanning is performed on the surface of the substrate to obtain defect information of the surface of the substrate; a relationship between the failure of the power device and the defect of the surface of the epitaxial layer is obtained based on the failure point information of the power device and the defect information of the surface of the epitaxial layer; a relationship between the failure of the power device and the defect of the surface of the substrate is obtained based on the failure point information of the power device and the defect information of the surface of the substrate; a relationship between the defect of the surface of the epitaxial layer and the defect of the surface of the substrate is obtained based on the defect information of the surface of the epitaxial layer and the defect information of the surface of the substrate.
2. The method of claim 1, wherein the power device wafer failure analysis method is characterized by, Before the defect scanning is performed on the surface of the power device wafer, the method further comprises: a division grid is constructed based on the size of a single power device in the device layer, and the division grid comprises a plurality of unit cells arranged in an array; the surface of the power device wafer is divided according to the division grid to obtain a plurality of test regions.
3. The method of claim 2, wherein the power device wafer failure analysis method is characterized by: The division of the surface of the power device wafer comprises: aligning a center point of the division grid with a center point of the power device wafer, and a line connecting the center point of the division grid and the center point of the power device wafer is a projection ray; the power device wafer is projected and overlapped with the division grid based on the projection ray.
4. The method of claim 2, wherein the power device wafer failure analysis method is characterized by, The first defect scanning performed on the surface of the power device wafer to obtain the failure point information of the power devices on the power device wafer comprises: electrical failure tests are performed on the power devices in the plurality of test regions based on position information of the plurality of test regions to locate a fault region and obtain position information of fault points in the fault region; physical failure tests are performed on the fault points in the fault region based on the position information of the fault region to obtain physical defects of the fault points.
5. The method of claim 4, wherein the step of determining the failure mode of the power device wafer comprises the steps of: determining the failure mode of the power device wafer based on the step of determining the failure mode of the power device wafer. The defect scanning performed on the surface of the epitaxial layer to obtain the defect information of the surface of the epitaxial layer comprises: a defect scanning is performed on the surface of the epitaxial layer by using high-precision differential interference optical imaging and light-induced luminescence imaging to obtain first defect information; a first defect region is obtained according to the first defect information and the position information of the test regions.
6. The method of claim 5, wherein the step of determining the failure mode of the power device wafer comprises the steps of: determining the failure mode of the power device wafer based on the step of determining the failure mode of the power device wafer. The relationship between the failure of the power device and the defect of the surface of the epitaxial layer is obtained based on the failure point information of the power device and the defect information of the surface of the epitaxial layer, and the relationship comprises: a device failure rate in the first defect region is obtained according to the position information of the fault region and the position information of the first defect region.
7. The method of claim 4, wherein the step of analyzing the power device wafer failure is performed by a computer system. The defect scanning performed on the surface of the substrate to obtain the defect information of the surface of the substrate comprises: the power device wafer is thinned to expose the surface of the substrate to form a second etching pit on the surface of the substrate; Position information of a test region corresponding to the second etching pit is obtained by using high-precision differential interference optical principle; Second test dislocation regions are obtained according to the position information of the test region corresponding to the second etching pit; Dislocation distribution and area density in each second test dislocation region are obtained; Second dislocation regions are located according to the area density in the second test dislocation region.
8. The method of claim 7, wherein the power device wafer failure analysis method is characterized by, Based on the failure point information of the power device and the defect information of the substrate surface, a relationship between the power device failure and the substrate surface defect is obtained, including: According to the position information of the fault region and the position information of the second dislocation region, a device failure rate in the second dislocation region is obtained.
9. The method of claim 7, wherein the power device wafer failure analysis method is characterized by, Defect scanning is performed on the epitaxial layer surface to obtain defect information of the epitaxial layer surface, and the method further includes: The power device wafer is thinned to expose the epitaxial layer surface, and a first etching pit located on the epitaxial layer surface is formed; Position information of a test region corresponding to the first etching pit is obtained by using high-precision differential interference optical principle; Second test dislocation regions are obtained according to the position information of the test region corresponding to the second etching pit; Dislocation distribution and area density in each second test dislocation region are obtained; Second dislocation regions are located according to the area density in the second test dislocation region.
10. The method of claim 9, wherein the power device wafer failure analysis method is characterized by, Based on the defect information of the epitaxial layer surface and the defect information of the substrate surface, a relationship between the defect of the epitaxial layer surface and the defect of the substrate surface is obtained, including: According to the position information of the first dislocation region and the position information of the second dislocation region, an inheritance probability between dislocations on the epitaxial layer surface and dislocations on the substrate surface is obtained.
11. The method of claim 1, wherein the power device wafer failure analysis method is characterized by, Further including: According to the relationship between the power device failure and the defect of the epitaxial layer surface, the failure point information of the power device and the defect information of the substrate surface, and the defect information of the epitaxial layer surface and the defect information of the substrate surface, the substrate and the epitaxial layer of the power device wafer are screened and optimized.
12. An analysis apparatus for power device wafer failure, characterized in that, Including: A first defect scanning unit is configured to perform defect scanning on the surface of the power device wafer to obtain failure point information of a power device on the power device wafer; A second defect scanning unit is configured to perform defect scanning on the surface of the epitaxial layer to obtain defect information of the surface of the epitaxial layer; A third defect scanning unit is configured to perform defect scanning on the surface of the substrate to obtain defect information of the surface of the substrate; A first analysis unit is configured to obtain a relationship between the power device failure and the defect of the epitaxial layer surface based on the failure point information of the power device and the defect information of the epitaxial layer surface; A second analysis unit is configured to obtain a relationship between the power device failure and the defect of the substrate surface based on the failure point information of the power device and the defect information of the substrate surface; A third analysis unit is configured to obtain a relationship between the defect of the epitaxial layer surface and the defect of the substrate surface based on the defect information of the epitaxial layer surface and the defect information of the substrate surface.